A method and system for testing the real-time computing power and power consumption of a domain controller chip

Abstract

This invention relates to the field of automotive chip testing technology, and discloses a method and system for testing the real-time computing power and power consumption of a domain controller chip. The system includes: a system under test (SUT), comprising a chip under test, a supporting circuit board, and peripheral components; the chip under test is configured to execute a preset algorithm and generate computational characteristic signals; a power analyzer module for real-time monitoring and recording of dynamic power consumption data of the SUT during operation; a signal input device including multiple cameras and a signal generator for inputting test signals to the chip under test via wiring harnesses; a temperature control accessory system including a water-cooling circulation device and an air-cooling heat dissipation component for maintaining the operating temperature of the chip under test within a preset threshold range; and a test host computer configured with a computing power parameter test scheduling system. This invention provides a reliable, accurate, and efficient path for testing and evaluating the computing power of automotive domain controllers, helping to accelerate the iterative development process of high-efficiency, high-reliability automotive chips.

Description

Technical Field

[0001] This invention relates to the field of automotive chip testing technology, specifically to a method and system for testing the real-time computing power and power consumption of a domain controller chip. Background Technology

[0002] As automotive electronic and electrical architectures evolve towards domain-centralized and even centralized computing, domain controllers have become the core computing platform for realizing vehicle intelligence (such as autonomous driving and smart cockpits) and connectivity. As the core of the domain controller, the chip undertakes the task of integrating and processing key functions such as power control, body electronics, infotainment, and advanced driver assistance systems (ADAS). It needs to process large amounts of heterogeneous data from various sensors such as cameras, radar, and lidar in real time, executing complex perception, decision-making, and control algorithms, which places extremely high demands on the chip's computing power. At the same time, given the stringent space and heat dissipation constraints of the in-vehicle environment, and the pursuit of longer driving range in new energy vehicles, the chip's power efficiency has also become a crucial performance indicator. Therefore, high computing power and low power consumption have become the core design goals and competitive focus of automotive domain controller chips.

[0003] However, conducting accurate and efficient collaborative testing of computing power and power consumption of automotive domain controller chips, especially evaluating their real-time computing performance and power consumption in real-world application scenarios, still faces a series of severe technical challenges:

[0004] (1) The application scenarios of in-vehicle systems are complex and varied, and the test scenarios cannot fully cover all application scenarios: Automotive domain controllers need to cope with highly diverse operating scenarios (such as urban congestion, highway cruising, and parking) and dynamically changing load demands. Their core functions often rely on the tight coupling and collaborative work of multiple algorithms (such as perception fusion, path planning, and control execution). Existing test methods are difficult to effectively simulate such complex working conditions of multi-algorithm coupling and dynamic load, resulting in incomplete coverage of test scenarios and test results that cannot truly reflect the comprehensive performance of the chip in the in-vehicle environment.

[0005] (2) Chip computing has extremely high real-time requirements and strict requirements on system response speed, making testing difficult: Vehicle control (especially autonomous driving-related functions) has extremely strict real-time requirements for computational latency and determinism (low jitter). Traditional performance testing methods often focus on average throughput or peak computing power, making it difficult to accurately quantify the worst-case execution time (WCET) and response latency of the chip under extreme load, task changes, and other conditions, and thus failing to fully verify its ability to meet the real-time constraints of vehicle safety-critical systems.

[0006] (3) The testing coverage of computing power management is limited, making it difficult to comprehensively evaluate the chip's performance in real-world environments: Existing computing power testing methods are often limited to average index measurements under static or simple cyclic loads, lacking a comprehensive assessment of the chip's instantaneous power consumption and power consumption rate under dynamic load changes, switching between different operating modes (such as DVFS state), and multi-core / multi-IP collaborative operation. It is difficult to capture the chip's energy efficiency characteristics and potential problems under real, complex, and long-term operating conditions.

[0007] In summary, during the testing and evaluation of the computing power of automotive domain controllers, there is an urgent need to design a unified and efficient real-time computing power and power consumption collaborative testing method and system for automotive domain controller chips, so as to be suitable for testing and verification of the multi-algorithm coupling characteristics and complex and variable operating conditions of automotive domain controllers. Summary of the Invention

[0008] This invention aims to provide a testing method and system for real-time computing power and power consumption of domain controller chips, providing a reliable, accurate and efficient path for testing and evaluating the computing power of automotive domain controllers. This helps to accelerate the iterative development process of high-energy-efficiency and high-reliability automotive chips and can provide a solid hardware foundation for the intelligent upgrade of automobiles.

[0009] To achieve the above objectives, the present invention provides the following basic solution.

[0010] Option 1

[0011] A testing system for real-time computing power and power consumption of a domain controller chip, comprising:

[0012] The system under test includes a chip under test, a supporting circuit board, and peripheral components. The chip under test is configured to execute a preset algorithm and generate computational feature signals.

[0013] The power analyzer module is used to monitor and record the dynamic power consumption data of the system under test in real time during operation.

[0014] The signal input device includes a multi-channel camera and a signal generator, used to input test signals to the chip under test via a wiring harness;

[0015] The temperature control accessory system includes a water-cooling circulation device and an air-cooling heat dissipation component, used to maintain the operating temperature of the chip under test within a preset threshold range;

[0016] The host computer is configured with a computing power parameter test scheduling system to perform the following operations: send algorithm configuration commands to the chip under test via the LINX architecture Ubuntu operating system; receive voltage / current time-domain data transmitted by the power analyzer module and frame rate parameters output by the chip under test in real time; calculate the computing power index per unit power consumption based on dynamically captured frame rate and power consumption data; and generate a multi-dimensional performance analysis report including power consumption curves and computing power distribution maps.

[0017] Option 2

[0018] A method for testing the real-time computing power and power consumption of a domain controller chip, used in a testing system for the real-time computing power and power consumption of a domain controller chip as described in Scheme 1; comprising the following steps:

[0019] Step S1, System initialization;

[0020] Power the domain controller via an external DC power supply, configure the supply voltage and maximum current limit; reset the test system and activate the water cooling module to stabilize the chip temperature within the preset threshold range;

[0021] Configure multiple camera input signals and verify the split-screen display function;

[0022] Step S2, test dynamic configuration;

[0023] Start the preset chip-test test software to create a new project, and select the neural network model according to the test requirements; set the voltage / current threshold in the power analyzer module; when the test system self-tests without faults, perform global configuration of the test system through the system scheduling module of the chip-test software; if a fault code is detected, trigger an alarm and terminate the test process.

[0024] Step S3: Test execution and monitoring;

[0025] Run the selected neural network model and perform a steady-state test for 3 minutes; periodically collect chip terminal voltage and current data via CAN bus; record chip characteristic parameters in real time; automatically proceed to the next stage when a single test times out by 5 minutes;

[0026] Step S4: Data generation and iteration;

[0027] Trigger a data acquisition termination command to automatically save test data to the specified path;

[0028] Calculate the computing power per unit power consumption; and reconfigure the test parameters based on the calculation results for iterative verification.

[0029] The working principle and advantages of this invention are as follows:

[0030] This invention provides a method and system for testing the real-time computing power and power consumption of domain controller chips. It offers a reliable, accurate, and efficient path for testing and evaluating the computing power of automotive domain controllers, helping to accelerate the iterative development of high-energy-efficiency and high-reliability automotive chips and providing a solid hardware foundation for the intelligent upgrade of automobiles. The key points are:

[0031] First, this solution constructs a closed-loop testing system encompassing "algorithm execution - power consumption acquisition - parameter feedback," overcoming the limitations of traditional separate testing methods. Based on the working principle of the "algorithm execution - power consumption acquisition - monitoring loop," the testing system promptly transmits the current chip calculation parameters to the host computer after the controller executes the computational instructions. Simultaneously, the transmission of electrical performance information via a power analyzer allows testers to record and extract typical electrical performance parameters (such as voltage and current) based on instantaneous peak and average values ​​as required.

[0032] Secondly, the computing power calculation formula used in this solution is simple and clear, and has universal applicability. Compared with the traditional calculation method based on the inherent characteristics of the system, this solution uses real-time extraction of characteristic parameters during the chip's calculation process. The formula derivation process incorporates the chip frame rate, ensuring the rigor of the theoretical basis, helping users understand the underlying principles and guaranteeing the effectiveness of the indicator calculation.

[0033] Third, this testing solution closely integrates with real-world application scenarios and the core needs of chip manufacturers, meeting their requirements for real-time performance and scenario reproducibility. The testing system operates through efficient algorithms, rapidly processing input data and outputting analysis results, providing users with immediate feedback. More importantly, this method effectively simulates the complex, low-probability "long-tail" operating conditions that domain controllers may encounter during the computing power testing phase, assisting testers in identifying potential defects in software computing mechanisms early on, thus improving testing efficiency. This is particularly valuable in development environments requiring rapid iteration. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the system structure of a method and system for testing the real-time computing power and power consumption of a domain controller chip according to the present invention.

[0035] Figure 2 This is a schematic flowchart of a method and system embodiment 1 for testing the real-time computing power and power consumption of a domain controller chip according to the present invention;

[0036] Figure 3 This is a mixed bar and line graph of the computing power distribution of a tested chip, obtained by the system of the test method and system embodiment one of the present invention for testing the real-time computing power and power consumption of a domain controller chip.

[0037] Figure 4The radar image of the computing power distribution of a chip under test obtained by the system in Embodiment 1 of the present invention, which is a method and system for testing the real-time computing power and power consumption of a domain controller chip.

[0038] Figure 5 This is a power change curve of a tested chip obtained by the system in Embodiment 1 of the test method and system for real-time computing power consumption of a domain controller chip according to the present invention. Detailed Implementation

[0039] The following detailed explanation illustrates the specific implementation methods:

[0040] Example 1

[0041] The basic implementation examples are as follows: Figure 1 As shown: A test system for real-time computing power and power consumption of a domain controller chip, comprising:

[0042] The system under test includes a chip under test, a supporting circuit board, and peripheral components. The chip under test is configured to execute a preset algorithm and generate computational feature signals, which helps to simulate its working state in practical applications. The preset algorithm includes YOLOv5, RCNN, FAST12, etc.; the feature signals include frame rate, computational constant, and computing power.

[0043] During testing, the system under test (SUT) responds to instructions from the host computer in real time, executing various computational tasks. This process allows for the acquisition of key performance indicators such as computing power, latency, and power consumption under different loads. To ensure the accuracy of the test results, the SUT is typically operated under various conditions, and its design and configuration are directly related to the effectiveness of the entire testing process.

[0044] The power analyzer module is used to monitor and record the dynamic power consumption data of the system under test in real time during operation.

[0045] Specifically, the power analyzer module includes: a high-precision sensor for real-time measurement of the current and voltage flowing through the chip under test; a calculation unit connected to the high-precision sensor for calculating the energy consumption of the chip under test based on the measured current and voltage; and a communication module connected to the calculation unit for transmitting at least one of the energy consumption data, power curve data, and statistical data to a test host computer. The power analyzer is configured to monitor the power consumption characteristics of the chip under test in real-time during operation and transmit the data to the test host computer for display and analysis, thereby identifying the chip's energy efficiency characteristics.

[0046] The signal input device includes multiple cameras and a signal generator, used to input test signals to the chip under test via a wiring harness.

[0047] Specifically, the multi-camera setup is configured to input visual signals (ranging from 10-120fps with a maximum resolution of 1024x2048) to the chip under test (DUT) to test its image processing capabilities. The signal generator is a programmable signal generator configured to generate CAN bus signals simulating sensor input (with a baud rate of 250KB or 500KB) to simulate the real-world application scenarios of the DUT, providing fundamental support for the acquisition of output data and computational analysis of the DUT. The signal input device also includes a multiplexing and switching module for controlling the dynamic switching test between camera input signals and analog signals.

[0048] The switching logic of the multiplexing switching module includes: (1) timing mode; alternating input between camera and bus signals according to a preset cycle; (2) event trigger mode; switching signal source in response to the computing power load threshold of the chip under test (such as CPU utilization > 80%); (3) hybrid mode; parallel input of visual signals and bus signals to simulate multi-sensor fusion scenario.

[0049] The temperature control accessory system includes a water-cooling circulation device and an air-cooling heat dissipation component, which is used to maintain the operating temperature of the chip under test within a preset threshold range.

[0050] In this embodiment, the water-cooling circulation device employs circulating cooling technology, effectively transferring heat to the heat sink through the flow of coolant to reduce the chip temperature and prevent overheating that could lead to performance degradation or damage. The air-cooling component assists in heat dissipation by accelerating airflow, ensuring the test environment temperature is controlled within a reasonable range. Under high-load testing, especially when the chip performs frequent computational operations, the reliability of the accessory system is crucial. This solution, through proper configuration of the accessory system, can reduce test failures caused by overheating, ensuring the accuracy and reliability of the acquired data. Simultaneously, good temperature control also helps extend the chip's lifespan, providing strong support for subsequent performance evaluation and design improvements.

[0051] The host computer for testing is equipped with a computing power parameter testing scheduling system and interacts in real time with the system under test, the power analyzer, and the signal input device. It performs the following operations: issuing algorithm configuration commands to the chip under test via the LINX-based Ubuntu operating system; receiving voltage / current time-domain data transmitted from the power analyzer module and frame rate parameters output by the chip under test in real time; calculating the computing power per unit power consumption index based on dynamically captured frame rate and power consumption data; and generating a multi-dimensional performance analysis report including power consumption curves and computing power distribution maps. A visual interface is provided to display the multi-dimensional performance analysis report and test process information.

[0052] Specifically, when issuing algorithm configuration instructions, the computing power parameter test scheduling system includes: single algorithm configuration—configuring a single algorithm, including the classification algorithm ResNet18, the perception algorithm YOLOv5, the rule-control algorithm Unet_MobileNet, RCNN, and executing FAST12, etc.; and combined algorithm configuration—combining multiple single algorithms in the order of classification-perception-rule-control-execution to reproduce the long-tail scenario encountered by the domain controller during the chip computing power testing phase. In this embodiment, the computing power parameter test scheduling system is integrated into or operates based on the preset chip-test test software.

[0053] The preset chip-test testing software is equipped with a hierarchical dynamic scheduling engine and a preemptive task scheduling mechanism.

[0054] The execution mechanism of the hierarchical dynamic scheduling engine includes: a top-level flow chart-based ( Figure 2 The test phases are divided (initialization → load injection → result acquisition), and the chip resources (synapse utilization / power consumption / temperature) are monitored in real time at the underlying level, and the task granularity is dynamically adjusted.

[0055] The preemptive task scheduling mechanism includes: allowing high-priority tasks (such as fault detection) to interrupt low-priority tasks (such as batch inference);

[0056] The preset chip-test test software is configured with a multi-platform compatible architecture and open API interfaces. The multi-platform compatible architecture provides a unified device interface through a modular hardware abstraction layer and uses a custom protocol parser to be compatible with private communication specifications.

[0057] Preferably, the preset chip-test testing software is further configured with a front-end and back-end separation architecture and a hardware abstraction layer (HAL) modification unit; the front-end and back-end separation architecture includes: decoupling the front-end interactive interface from the back-end service, and the back-end using Python to encapsulate Shell commands to build a real-time test information calling module to dynamically parse the raw data stream returned by the chip.

[0058] The execution process of the real-time test information calling module includes: directly accessing the chip registers through Shell commands; extracting key parameters (such as synaptic utilization / power consumption values) using the Python regular expression engine; and converting the raw hexadecimal data into floating-point physical quantities.

[0059] The Hardware Abstraction Layer (HAL) modification unit is used to deploy a unified device interface protocol, abstracting the physical layer differences between chips from multiple vendors; and to provide a standardized device driver registration interface, supporting plug-and-play functionality for heterogeneous chips. The unified device interface protocol includes: a device discovery mechanism that automatically identifies the vendor ID of the access chip; and a protocol adaptation layer that maps private communication commands to standard commands (set according to actual application requirements).

[0060] The pre-built chip-test software based on this solution supports flexible and accurate dynamic scheduling of the computing power parameter test scheduling system. Furthermore, compared to existing tools (such as NeuChipTest), which often only support static task allocation and cannot adjust based on real-time chip status (synapse utilization / temperature), only support standard communication protocols (such as CANFD), and require waiting for the current test cycle to end before handling faults, this solution features a dynamic resource scheduling mechanism. It can dynamically compress task granularity through underlying monitoring feedback (e.g., reducing load injection units during sudden high temperatures), and configure byte order / verification rules through a protocol parser to adapt to vehicle manufacturer-specific encryption protocols. It also incorporates a preemptive scheduling mechanism that can immediately interrupt batch inference tasks to perform ECU fault diagnosis, ensuring timely fault response with minimal latency.

[0061] The unit power consumption computing power index is calculated using the following formula: Where C is the computational constant, FPS is the computational frame rate, U is the voltage, and I is the current. CAL is the bit power consumption computing power index.

[0062] The host computer for testing also integrates a fault diagnosis module, which triggers an alarm and terminates the test when any of the following is detected:

[0063] The instantaneous current collected by the power analyzer exceeds a% of the rated value and the duration exceeds the corresponding threshold.

[0064] The temperature of the tested chip rises at a rate exceeding c℃ / s within b seconds;

[0065] The calculated frame rate consistently deviates from the preset theoretical value by more than d%.

[0066] In this embodiment, the values ​​of a, b, c, and d are set to 25, 3, 8, and 40, respectively.

[0067] like Figure 2 As shown, this embodiment also provides a method for testing the real-time computing power consumption of a domain controller chip, used in the testing system for real-time computing power consumption of a domain controller chip as described in Scheme 1; including the following steps:

[0068] Step S1, System initialization;

[0069] Power the domain controller via an external DC power supply, configure the supply voltage and maximum current limit; reset the test system and activate the water cooling module to stabilize the chip temperature within the preset threshold range;

[0070] Configure multiple camera input signals and verify the split-screen display function;

[0071] Step S2, test dynamic configuration;

[0072] Start the preset chip-test test software to create a new project, and select a neural network model (such as YOLOv 5, Faster R-CNN, etc.) according to the test requirements; set the voltage / current threshold in the power analyzer module; when the test system self-tests without faults, perform global configuration of the test system through the system scheduling module of the chip-test software (in this embodiment, it refers to the computing power parameter test scheduling system); if a fault code is detected, trigger an alarm and terminate the test process;

[0073] Step S3: Test execution and monitoring;

[0074] Run the selected neural network model and perform a steady-state test for 3 minutes; collect chip terminal voltage and current data periodically via CAN bus to facilitate the introduction of power consumption and computing power indicators; record chip characteristic parameters (including computational constants and operation frame rate) in real time; when a single test times out by 5 minutes, automatically proceed to the next stage.

[0075] This step also includes:

[0076] Case 1 – Chip Feature Parameter Testing Sub-process:

[0077] Real-time monitoring of the CPU and BPU operating information of the chip under test;

[0078] When the chip's computing load stability fluctuates less than the corresponding threshold for 30 consecutive seconds, it is determined to have entered a steady state.

[0079] Automatically generate and calculate characteristic signals and trigger data saving operations.

[0080] Scenario 2 – Power Consumption Performance Comparison Test Sub-process:

[0081] Idle power consumption test: Stop task scheduling and collect the voltage and current values ​​of the chip under test in standby mode;

[0082] Peak power consumption test: Start and configure the model, continuously send high-power computing tasks to the domain controller, and read the voltage and current values ​​of the chip under test during inference.

[0083] Dynamic power consumption tracking: Records current waveforms at a 1ms resolution during inference.

[0084] Step S4, Data Generation and Iteration;

[0085] Trigger a data acquisition termination command to automatically save test data to the specified path;

[0086] Calculate the computing power per unit power consumption; and reconfigure the test parameters based on the calculation results for iterative verification.

[0087] In this embodiment, the test data will be further output as a computing power distribution map and a power change curve for intuitive analysis of the computing power of the chip under test.

[0088] like Figure 3 , Figure 4 The computing power distribution of a chip under test, measured using this test method and system, is shown respectively.

[0089] against Figure 3 The horizontal axis represents the task scenario, including "classification, detection, and multi-task," representing different application scenarios for chip testing; the vertical axis represents the computing power value, used to measure the chip's processing capability. Phase 1 and Phase 2 correspond to the chip's computing power performance under different phases or test conditions.

[0090] In the classification scenario (around the horizontal axis 2-4): the computing power of both stage 1 and stage 2 is low and the fluctuation is small, indicating that the chip's processing power is stable but not high overall in the basic scenario of classification tasks, and its adaptability to simple classification tasks is average.

[0091] In the detection scenario (around the horizontal axis 6-8): the computing power of stage 2 is significantly higher than that of stage 1. This indicates that in the detection scenario, the stage 2 configuration is the scenario where chip computing power is superior; stage 1 fluctuates in the detection scenario, but is generally lower than stage 2.

[0092] In a multi-tasking scenario (around 10-16 on the horizontal axis): the computing power of both stage 1 and stage 2 is low and similar, indicating that the chip's computing power is limited when multiple tasks are running in parallel, and it is difficult to improve the computing power of different stages. Multi-tasking may be the bottleneck scenario for the chip's computing power.

[0093] In summary, based on this computing power distribution map, we can analyze that: Stage 2 performs well in targeted optimization scenarios, while Stage 1 is more balanced but has lower peak performance; both are weak in multi-task scenarios, requiring optimization of the architecture or algorithm. If detection tasks are required, Stage 2 configuration should be prioritized; for multi-task scenarios, it is necessary to assess whether the chip's computing power is sufficient, or optimize task scheduling and upgrade the chip.

[0094] against Figure 4 It is a radar chart of the computing power distribution of the chip under test under different model tasks, covering 15 types of models such as MobileNetV1, GoogleNet, and ResNet18 (such as object detection and classification models). The vertical axis (concentric circles) represents the computing power intensity, and the computing power is higher as it is further out.

[0095] In most model tasks, the orange polygons are positioned further out (such as in object detection models like yolov3_darknet53 / yolov2_darknet19), indicating that having 2 cores provides stronger computational support for the model tasks and is suitable for deploying highly complex detection tasks.

[0096] The overall polygons of core 1 are more inward, and only a few models (such as model_info) are close to those of core 2, indicating that the computing power of core 1 is generally weaker than that of core 2, and core 1 is more suitable for lightweight tasks.

[0097] like Figure 5 The figure shows the power variation curve of a chip under test obtained by applying this test method and system. The figure shows the power variation of the chip in different task stages (detection, classification, and multi-task), reflecting the differences in chip load of different tasks (the detection task has a balanced load and the chip power consumption is stable; the classification task has a higher demand on chip computing power and triggers a significant increase in power consumption; when multiple tasks are in parallel, the chip power consumption is lower than that in the classification stage, but still higher than that in the detection stage, reflecting that the task load has been adjusted). It can be used to guide power consumption optimization and task scheduling design.

[0098] This embodiment provides a method and system for testing the real-time computing power and power consumption of a domain controller chip, offering a reliable, accurate, and efficient path for testing and evaluating the computing power of automotive domain controllers. This helps accelerate the iterative development of high-energy-efficiency and high-reliability automotive chips and provides a solid hardware foundation for the intelligent upgrade of automobiles.

[0099] Example 2

[0100] A test system for real-time computing power and power consumption of a domain controller chip, based on Embodiment 1, has been modified as follows.

[0101] When issuing algorithm configuration instructions, the computing power parameter test scheduling system issues algorithm configuration instructions through a preset configuration method to reproduce the long-tail scenario encountered by the domain controller during the chip computing power test phase.

[0102] The preset configuration method includes:

[0103] Key parameters leading to chip failure / frequency reduction in real long-tail scenarios were extracted from historical test logs, vehicle black boxes, and production line fault records. These parameters included: bus anomalies—CAN bus error rate or LIN signal delay time exceeding the corresponding threshold; peak computing power exceeding the corresponding threshold; drastic temperature changes; and voltage disturbances. These parameters were then used to construct a long-tail scenario feature library.

[0104] Scene association modeling is performed based on a predefined long-tail scene feature library. In this embodiment, a scene transition probability matrix is ​​established based on a Markov chain to associate various key parameters. For example, if a bus anomaly occurs, there is a certain probability that a data conflict will be triggered in the next time sequence (such as the absence of visual signals or bus signals). If a computing power peak is detected, there is a certain probability that a temperature rise will occur within a preset time.

[0105] The system applies load to the chip, monitors the chip resource status in real time, and triggers multi-level chain-like hardware anomalies and software failures based on correlation modeling when a threshold is reached, in order to reproduce the long-tail scenario conditions encountered by the domain controller during the computing power testing phase.

[0106] In this embodiment, key parameters are injected step by step according to the chain triggering from hardware failure (level 1) → system interruption (level 2) → software crash (level 3) to reproduce the working condition.

[0107] This embodiment provides a method and system for testing the real-time computing power and power consumption of a domain controller chip. By converting discrete abnormal events into a probabilistic chain of fault sequences, it can accurately reproduce the long-tail evolution process from quantitative change (load accumulation) to qualitative change (system collapse) in a real system, which helps to improve the realism of chip testing.

[0108] The above descriptions are merely embodiments of the present invention. Commonly known structures and characteristics of the solutions are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, under the guidance of this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent.

Claims

1. A testing system for real-time computing power and power consumption of a domain controller chip, characterized in that, include: The system under test includes a chip under test, a supporting circuit board, and peripheral components. The chip under test is configured to execute a preset algorithm and generate computational feature signals. The power analyzer module is used to monitor and record the dynamic power consumption data of the system under test in real time during operation. The signal input device includes a multi-channel camera and a signal generator, used to input test signals to the chip under test via a wiring harness; The temperature control accessory system includes a water-cooling circulation device and an air-cooling heat dissipation component, used to maintain the operating temperature of the chip under test within a preset threshold range; The host computer is configured with a computing power parameter test scheduling system to perform the following operations: send algorithm configuration commands to the chip under test via the LINX architecture Ubuntu operating system; receive voltage / current time-domain data transmitted by the power analyzer module and frame rate parameters output by the chip under test in real time; calculate the computing power index per unit power consumption based on dynamically captured calculation frame rate and power consumption data; and generate a multi-dimensional performance analysis report including power consumption curves and computing power distribution maps. The unit power consumption computing power index is calculated using the following formula: Where C is a calculation constant, FPS is the calculation frame rate, U is the voltage, and I is the current; This refers to the computing power per unit of power consumption. The host computer for testing also integrates a fault diagnosis module, which triggers an alarm and terminates the test when any of the following is detected: The instantaneous current collected by the power analyzer exceeds 25% of the rated value and the duration exceeds the corresponding threshold; The temperature of the tested chip rose at a rate exceeding 8°C / s within 3 seconds. The calculated frame rate consistently deviates from the preset theoretical value by more than 40%. The computing power parameter test scheduling system is integrated into the preset chip-test test software, or operates based on the preset chip-test test software; The preset chip-test testing software is equipped with a hierarchical dynamic scheduling engine and a preemptive task scheduling mechanism. The execution mechanism of the hierarchical dynamic scheduling engine includes: the top layer divides the test phase based on the flowchart, the bottom layer monitors chip resources in real time, and dynamically adjusts the task granularity. The preemptive task scheduling mechanism includes: allowing high-priority tasks to interrupt low-priority tasks; The preset chip-test test software is configured with a multi-platform compatible architecture and open API interfaces. The multi-platform compatible architecture provides a unified device interface through a modular hardware abstraction layer and uses a custom protocol parser to be compatible with private communication specifications.

2. The test system for real-time computing power and power consumption of a domain controller chip according to claim 1, characterized in that, The signal generator is a programmable signal generator and is configured to generate CAN / LIN bus signals that are analog sensor inputs.

3. The test system for real-time computing power and power consumption of a domain controller chip according to claim 1, characterized in that, The signal input device is also equipped with a multiplexing and switching module, which is used to control the dynamic switching test scenario between the camera input signal and the analog signal.

4. The test system for real-time computing power and power consumption of a domain controller chip according to claim 1, characterized in that, When issuing algorithm configuration instructions, the computing power parameter test scheduling system includes: single algorithm configuration—configuring a single algorithm, including the classification algorithm ResNet18, the perception algorithm YOLOv5, the regulation and control algorithm Unet_MobileNet, and the execution algorithm FAST12; combined algorithm configuration—combining multiple single algorithms in the order of classification-perception-regulation and control-execution to reproduce the long-tail scenario encountered by the domain controller during the chip computing power test phase.

5. A method for testing the real-time computing power and power consumption of a domain controller chip, characterized in that, The test system is used to test the real-time computing power and power consumption of a domain controller chip as described in any one of claims 1-4; the test includes the following steps: Step S1, system initialization; Power the domain controller via an external DC power supply, configure the supply voltage and maximum current limit; reset the test system and activate the water cooling module to stabilize the chip temperature within the preset threshold range; Configure multiple camera input signals and verify the split-screen display function; Step S2, test dynamic configuration; Start the preset chip-test test software to create a new project, and select the neural network model according to the test requirements; set the voltage / current threshold in the power analyzer module; when the test system self-tests without faults, perform global configuration of the test system through the system scheduling module of the chip-test software; if a fault code is detected, trigger an alarm and terminate the test process. Step S3: Test execution and monitoring; Run the selected neural network model and perform a steady-state test for 3 minutes; periodically collect chip terminal voltage and current data via CAN bus; record chip characteristic parameters in real time; automatically proceed to the next stage when a single test times out by 5 minutes; Step S4: Data generation and iteration; Trigger a data acquisition termination command to automatically save test data to the specified path; Calculate the computing power per unit power consumption; and reconfigure the test parameters based on the calculation results for iterative verification.

6. The method for testing the real-time computing power and power consumption of a domain controller chip according to claim 5, characterized in that, Step S3 includes a chip feature parameter testing sub-process: Real-time monitoring of the CPU and BPU operating information of the chip under test; When the chip's computing load stability fluctuates less than the corresponding threshold for 30 consecutive seconds, it is determined to have entered a steady state. Automatically generate and calculate characteristic signals and trigger data saving operations.

7. The method for testing the real-time computing power and power consumption of a domain controller chip according to claim 5, characterized in that, Step S3 includes a power consumption performance comparison test sub-process: Idle power consumption test: Stop task scheduling and collect the voltage and current values ​​of the chip under test in standby mode; Peak power consumption test: Start and configure the model, continuously send high-power computing tasks to the domain controller, and read the voltage and current values ​​of the chip under test during inference. Dynamic power consumption tracking: Records current waveforms at a 1ms resolution during inference.

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