Universal signal processor of software defined bus and interface protocol
The general-purpose signal processor, which uses software-defined bus and interface protocols, solves the problem of fixed interfaces and buses in existing signal processors, realizes a flexible, multi-functional integrated platform, supports multiple protocol conversions and device interoperability, and improves the system's flexibility and adaptability.
Patent Information
- Application Number
- CN202511006539.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-10-28
AI Technical Summary
The fixed interfaces and buses of existing signal processors cannot be flexibly adjusted, resulting in limited hardware functions, poor system scalability, difficulty in quickly integrating new technological achievements, and inability to meet the demands of modern applications for high-performance radar.
Design a general-purpose signal processor with software-defined bus and interface protocols. Employ software-defined interconnect (SDI) technology to support system interconnection through software-defined hardware, enabling bridging and hybrid interconnection between different protocols. Use OpenVPX bus and 100Gbps fiber optic bus, combined with various protocol conversion chips and modules, to achieve flexible interconnection between modules.
It achieves high flexibility and interoperability of a multi-functional integrated platform, reduces system complexity and maintenance support pressure, supports algorithm upgrades and equipment reconfiguration, is suitable for new deployments and life extension, and promotes the integrated development of military and civilian sectors.
Smart Images
Figure CN120848848A_ABST
Abstract
Description
Technical Field
[0001] This invention mainly relates to the field of sensor open system architecture (SOSA) technology, and in particular to a general-purpose signal processor with software-defined bus and interface protocols. Background Technology
[0002] Modern warfare heavily relies on the acquisition, interaction, and utilization of information via the electromagnetic spectrum. As warfare transforms towards informatization and intelligence, victory in electromagnetic spectrum warfare has become a prerequisite for gaining battlefield advantage. It spans multiple operational domains and permeates the entire course of warfare. Modern warfare has presented a new landscape: single equipment can hardly survive independently. Joint multi-domain operational postures are becoming an urgent need. It's no longer about a single piece of equipment countering a single threat, but rather using multiple electronic warfare technologies and platforms across a broader area to achieve common objectives. Only through effective coordination among various devices can the normal operation of different electronic equipment be guaranteed, enabling them to form a powerful combat capability. From the perspective of equipment composition, such as... Figure 1 As shown, each platform in each domain is essentially a siloed territory, establishing its own distinct standards and developing technologies accordingly to meet the unique needs of its respective domain. These standards themselves may even be based on similar, identical architectures designed with similar underlying principles. This leads to redundant development to create the same functionality, but ultimately, it may fail to interoperate with external devices because their interfaces are developed for specific purposes and uses, and the interfaces and buses of their signal processors are also fixed. The complex electronic warfare environment has given rise to new requirements for multi-functional integration. An integrated concept and architecture helps overcome the gaps between multiple platforms and devices, significantly enhancing system capabilities.
[0003] Since radar and communication equipment use electromagnetic waves or electrical signals as their processing medium, the electronic components, processing methods, software processes, and structural technologies employed in their research and production are often similar or identical. They all consist of array antennas, transmitters, receivers, signal processing units, display and control units, servo systems, and power supply systems. Therefore, these common characteristics can be utilized to integrate electronic devices and technologies with different functions into a single unit. Among these, a common requirement is for a signal processor, such as... Figure 2 As shown, however, it is necessary to solve the problem of interfacing with different devices such as reconnaissance, jamming, detection, and communication. Due to the professional requirements and the inheritance of technical history, they use different interfaces from the back-end processing. Moreover, previous signal processors could only provide one fixed interface, such as the SRIO interface. If multiple interfaces are required, such as Ethernet (ETH) or fiber optic (FC) interfaces, different interface conversion modules need to be installed. In particular, the internal bus of the signal processor cannot be changed once it has been designed and manufactured.
[0004] Not only do signal processors in reconnaissance and communication equipment vary, but radars in the detection field also come in a wide variety of types. From early simple target detection to today's widespread application in complex scenarios such as aerospace, navigation, meteorological monitoring, and traffic control, radar technology has continuously evolved. Traditional radars, due to limitations in their hardware architecture and signal processing methods, have gradually revealed their shortcomings, mainly in the following aspects: First, the fixed hardware leads to limited functionality. Signal generation, transmission, reception, and processing are typically achieved through hardware circuits. Once the hardware design is complete, its functions are essentially fixed, making it difficult to flexibly adjust to new mission requirements later. Second, the system has poor scalability. When new functional modules need to be added, large-scale modifications or even redesigns of the hardware are required. Third, technological updates are difficult, hindering the rapid integration of new technological achievements, resulting in lagging technological advancements and an inability to meet the demands of modern applications for high-performance radar. Different types of radar operate at different frequencies. Their antennas are closely related to the frequency, and their transmitters and receivers are also related to the operating frequency. In other words, their front-ends are different, but the processing flow after digitization is basically the same, and the hardware functions of the back-end signal processors are also basically the same. The only difference is that the computing power requirements are different due to the different scale of the radar, which means that the configuration requirements of the signal processors are different. Everything else is basically the same.
[0005] Therefore, if a signal processor with a variable interface and bus, namely software-defined interconnect (SDI), can be developed, it can provide a truly universal signal processor for radar. By loading different software algorithms, it can realize a variety of radar functions. When new functions need to be added or existing functions need to be improved, only the software needs to be upgraded and updated to continuously improve the performance and functions of the radar. Summary of the Invention
[0006] The purpose of this invention is to provide a general-purpose signal processor with a software-defined bus and interface protocol. The signal processor's interface and bus feature software-definable interconnectivity, not limited to a fixed interface or bus, and applicable to various purposes and uses. By supporting system interconnectivity through software-defined hardware, it can both define a single protocol required for a specific piece of equipment and, based on software-defined interconnect technology, enable bridging between different protocols and generate multiple protocols. It supports hybrid interconnectivity of heterogeneous and custom protocols, creating a new, flexible, and adaptable software-defined interconnect device system, providing technical support for multi-functional integrated back-end processing.
[0007] To achieve the above objectives, the present invention provides a general signal processor with software-defined bus and interface protocol, including a functional module, a rear interface module, a power supply module, a backplane, a chassis, and a fan unit; The backplane is the physical carrier for realizing module interconnection, including 3 power supply slots and 10 function slots; The functional modules include two data exchange modules and a load module; A chassis can accommodate 2 data exchange modules, no more than 8 load modules, and no more than 3 power supply modules. The two data exchange modules are of the same type, and a 1+1 redundancy design is implemented for the two data exchange modules to achieve 1:1 online backup; The 12 Gigabit Ethernet signals on the VPX P1 connector of the data exchange module complete the exchange of Gigabit Ethernet signals from all load modules VPX P4 connectors gathered from the backplane. The 12 ETH / SRIO / FC / PCIe multi-protocol signals on the VPX P2, P3, P4, and P5 connectors of the data exchange module complete the data exchange of ETH / SRIO / FC / PCIe multi-protocol signals from all load modules VPX P1 gathered from the backplane. The rear interface module can be plugged into the rear of the data exchange module or the load module; The power module provides dual IPMB management interfaces based on the I2C protocol. The power module is used to supply power to the load module, data exchange module and fan unit. The +12V is the main power supply for the functional modules, the +3.3V is the auxiliary power supply for management, and the +48V is the power supply for the cooling DC fan in the fan unit.
[0008] Furthermore, it also includes the OpenVPX bus and a 100Gbps fiber optic bus; The OpenVPX bus is the standard VITA 65-2010 OpenVPX bus, which includes the Intelligent Platform Management Bus (IPMB), the Task Control Bus (1GbE Gigabit Ethernet), and the Data Bus (40Gbps serial bus); the OpenVPX bus transmits electrical signals from the backplane. The 100Gbps fiber optic bus transmits electrical signals from the front panel of the load board, not from the back panel.
[0009] Furthermore, the 10 functional slots on the back panel include 8 processing slots and 2 exchange slots; Each of the eight processing slots has two 10G×4 high-speed buses that are connected to two switching slots respectively, with a single channel rate of 10Gbps. Each of the eight processing slots has two SGMII gigabit network lines, which are interconnected with two switching slots respectively; The eight processing slots are interconnected by two PCIe 3.0×4 buses between each pair of adjacent slots, with a single-channel rate of 8Gbps; The dual-channel IPMB management interface based on the I2C protocol is associated with 3 power supply slots and 10 function slots; the external power supply is 220V DC input, and the power supply slots lead out DC +12V, 3.3V and 48V power supplies, of which +12V and 3.3V are used to power the function modules and +48V is used to power the fan unit.
[0010] Furthermore, if the back interface module is inserted after the data exchange module, the data transmitted from the outside will be converted in the back interface module. The steps include: S1: Data is transmitted directly to the data exchange module on the front board in sequence via RP6, RJ6, P6, and J6; S2: Then distribute the task allocation data to the load module.
[0011] Furthermore, if the rear interface module is plugged after the load module, the data conversion steps include: S3: Data is transmitted directly to the load module in the front panel for processing via RP3, RJ3, J3, and P3 in sequence; S4: Then pass the data sequentially through load modules P3, J3, backplane, data exchange modules RJ2~RJ5, and P2~P5; S5: The data exchange module distributes data to the load module according to the task allocation.
[0012] Furthermore, the load module includes the SDI4820 software-defined interconnect switching chip, which supports multiple protocol conversions. The software configuration steps for multiple protocol conversions in the load module include: K1: Configure the function block Bank, set the BCFG and SPD pins, power on the SDI switching module, perform a hardware reset on the SDI4820 chip, and make the configuration path ready. K2: PLL locks the core phase-locked loop, loads BCFG and SPD into registers, resets and releases serdes, loads configuration, outputs Ethernet IP clock xsbi_clk, enters configuration controller mode, and configures port rate / mode to the relevant registers. K3: After configuration, establish a communication link and send and receive data packets.
[0013] Furthermore, the data exchange module includes two SDI4820 software-defined interconnect switching chips that support multiple protocol conversions, enabling mixed protocol switching. Specific steps include: K4: When switching port speed or mode during operation, first disable the enable of all ports in the function block Bank and stop receiving packets; K5: Configure global routing, disallow packet forwarding to function blocks (Bank), and modify the port type to the required rate mode; K6: If the channel rate changes, reset the corresponding SERDES channel, enter the configuration controller mode, and reconfigure the rate, mode, and control registers in the Ethernet physical layer. K7: After configuration, establish a communication link and send and receive data packets.
[0014] Furthermore, the back-end interface module includes an FPGA, which transmits and receives data, completing the protocol conversion from RocketIO or Aurora to ETH, SRIO, FC, and PCIe. The general-purpose signal processor can interface with these six interface protocols. The specific steps include: T1: On the RocketIO side, within the FPGA, logic programming is used to receive the serial data stream and perform physical layer processing, which includes word alignment, 8b or 10b decoding, and comma detection. T2: Package the logic layer data into RapidIO protocol format, and generate packet headers and CRC checksums; T3: Store in FIFO buffer, perform transaction processing and flow control logic layer processing, and send data through RapidIO port; T4: On the RapidIO side, within the FPGA, logic programming is used to parse the RapidIO packet header protocol and extract information, including transaction type, address, and length. T5: Insert control characters, including Idle, Start, and End of Packet; T6: Perform 8b / 10b encoding, parallel-to-serial conversion, put the data into the Playload buffer, and send the data through the RocketIO port.
[0015] Furthermore, if the power consumption of a module in a general-purpose signal processor is greater than the power that two power supply modules can provide, then the number of power supply modules is three, without a 2+1 redundancy design, and the three power supply modules are connected in parallel for power supply. If the power provided by one power module is less than the power consumption of the modules in the general signal processor and less than the power provided by two power modules, then the number of power modules is two or three. If there are two power modules, then the two power modules are connected in parallel to supply power. If there are 3 power modules, then the power modules are designed with 2+1 redundancy to achieve 2:1 online backup; If the power consumption of a module in a general-purpose signal processor is less than or equal to the power that one power supply module can provide, then the number of power supply modules is one or two. If there is only one power module, then one power module will provide power. If there are two power modules, then a 1+1 redundancy design is implemented for the power modules to achieve 1:1 online backup.
[0016] Furthermore, the interconnection between general signal processing modules adopts a star interconnection architecture based on the OpenVPX specification. The architecture consists of multiple planes, which are the physical and logical channels for interconnection between devices, including the base plane, management plane, control plane, data plane, extension plane, and extended data plane. The base plane provides basic services, including system power supply, system reference clock, system reset, and system test signals; The management plane is used to organize and manage hardware resources based on the IPMI standard; The control plane adopts a dual-star gigabit Ethernet topology to carry business application management and control data; The data plane uses a ×4 high-speed serial bus data plane to transmit service data between modules. The ×4 high-speed serial bus data plane can be different interface protocols, including 40GbE network interface protocol, 40Gbps SRIO 3.0 interface protocol, and single-channel 8.5Gbps FC interface protocol. The service data includes echo data and intermediate processing data. The extended plane enables interconnection between the module and two adjacent modules. Functional modules are interconnected point-to-point with adjacent modules via PCIe bus. A single functional module supports three output modes: 1 set of PCIe×16, 2 sets of PCIe×8, or 4 sets of PCIe×4. Expand the data plane to enable point-to-point transmission from the load module to the switching module by adding a ×4 100Gbps high-speed serial bus to transmit service data from the data plane.
[0017] Beneficial Effects: This invention provides a general-purpose signal processor based on a software-defined bus and interface protocol, providing technical support for the integration of various weapon systems. This multi-functional integrated platform has the following advantages in weapon systems: (1) First, the ability of a single multi-functional integrated device to handle multiple functions reduces the overall complexity of the weapon system. Furthermore, the general-purpose signal processor platform based on a software-defined bus and interface protocol is highly flexible and versatile because its interconnection method can be reconfigured by software, making these devices highly interoperable and capable of being integrated into traditional and newer equipment; (2) In addition, the flexibility of these platforms makes them suitable for new deployments and service life extension plans. The reconfigurability of the digital backend of the general-purpose signal processor using a software-defined bus and interface protocol is based on software configuration operation. Since no hardware modification is required, this reconfigurability allows for easy testing and implementation of algorithm upgrades at low cost. The reconfigurability of the software-defined bus and interface protocol processor means that a single device can be reconfigured to perform different functions. Since it does not require the purchase of multiple modules, compared with traditional single-protocol signal processors, it can unify the signal processing platform, reduce the pressure of system maintenance and support and reduce personnel configuration. The software-defined connection processing platform SDI is more cost-effective; (3) From the perspective of accelerating the construction of a world-class army and accelerating the development of military-civilian integration, in-depth research on the application of SDI in the military and civilian computing fields is conducive to shortening the gap between our army and the world-class army in terms of equipment, and is conducive to generating huge economic and social benefits, and promoting the progress of multi-functional integrated equipment, signal processors and other technologies. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of multi-functional joint operations involving existing technologies; Figure 2 This is a schematic diagram of a multi-functional integrated device involved in existing technology; Figure 3 This is a rear view of a general-purpose signal processor according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a general signal processor according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the VPX front and rear insertion modules of the general signal processor involved in the embodiments of the present invention; Figure 6 This is a diagram of a general signal processor dual-switching interconnect topology according to an embodiment of the present invention; Figure 7 This is a diagram of a general signal processor system architecture according to an embodiment of the present invention; Figure 8 This is a diagram showing the interconnection relationship of a general signal processor backplane according to an embodiment of the present invention; Figure 9This is a flowchart of the Ethernet configuration method according to an embodiment of the present invention; Figure 10 This is a flowchart of the Ethernet switching reconfiguration process according to an embodiment of the present invention; Figure 11 This is a flowchart illustrating the data transmission and reception process using the RocketIO-RapidIO interface module, as described in an embodiment of the present invention. Figure 12 This is a front view of a general-purpose signal processor according to an embodiment of the present invention. Figure 13 This is a rear view of a general-purpose signal processor according to an embodiment of the present invention; Figure 14 This is a front view of a general signal processing chassis according to an embodiment of the present invention; Figure 15 This is a rear front view of the general signal processing chassis involved in the embodiments of the present invention. Detailed Implementation Example 1
[0020] The purpose of this invention is to provide a general-purpose signal processor with an external interface and an internal bus protocol that can be defined by software. This embodiment uses the SDI4820 software-defined interconnect switching chip, which supports multiple protocol conversions, as its core to construct a general-purpose signal processor supporting multiple protocols. By sending protocol reconfiguration commands, a signal processor that could previously only be designed for one data communication and exchange protocol can become one or more of four protocols with a single-channel maximum rate: SRIO protocol 25.78125Gbps, FC protocol 28.05Gbps, PCIes protocol 16Gbps, and ETH protocol 26.5625Gbps (NRZ) / 53.125Gbps (PAM4). Multiple channels can be bundled into ports, such as a general-purpose signal processor supporting ×4 100G / 200G Ethernet. Data can be input / output to the signal processor from the bus of the data exchange module, or from the back-end interface module in the load module or the back-end interface module in the data exchange module. The interface can be an Aurora or RocketIO custom protocol or other protocols, which are also software-selectable.
[0021] Figure 1 This is a schematic diagram of multi-functional joint operations involving existing technologies; Figure 2 This is a schematic diagram of a multi-functional integrated device involved in existing technology; Figure 3 This is a rear view of a general signal processor involved in an embodiment of the present invention.
[0022] The general-purpose signal processor in this embodiment consists of a load module, a data exchange module, a rear interface module, a power supply module, a backplane, and a chassis, etc., for details. Figure 4The load modules can be general-purpose CPU computing modules, DSP computing modules, GPU computing modules, FPGA computing modules, record storage modules, and other modules conforming to the OpenVPX specification. Up to eight load modules can be inserted; these modules can be of the same type or different types, and the type and quantity are configured according to actual needs.
[0023] The two data exchange modules can be software-defined as commonly used high-speed serial buses such as ETH, SRIO, FC, and PCIe exchange modules. These two exchange modules can be of the same or different types, but are generally of the same type because in critical equipment, mission reliability is paramount. The purpose of having two exchange modules is to implement a 1+1 redundancy design, i.e., 1:1 online backup. When one exchange module fails, it automatically switches to the other. Redundancy is not always necessary; in applications with low requirements, only one data exchange module can be used. This invention is based on a 1+1 redundancy design. Eight general-purpose computing modules, each with one Gigabit Ethernet signal on its VPX P4 connector, are aggregated via the backplane to the corresponding eight Gigabit Ethernet signals on the VPX P1 connector of a data switching module (12 channels on P1, the rest used for other purposes), completing the Gigabit Ethernet signal switching. Similarly, each of the eight general-purpose computing modules has one ETH / SRIO / FC / PCIe multi-protocol signal on its VPX P1 connector, which is aggregated via the backplane to the corresponding eight ETH / SRIO / FC / PCIe multi-protocol signals on the VPX P2, P3, P4, and P5 connectors of the data switching module (16 channels on P2, P3, P4, and P5, the rest used for other purposes), completing the ETH / SRIO / FC / PCIe multi-protocol signal switching. Figure 5 As shown, the middle part is the back plate, which is also called the bottom plate or middle plate.
[0024] The back-end interface module is typically plugged after the data exchange module and belongs to the back-end I / O (input / output) module category. Data from external sources is converted in the back-end interface module, for example, after RCockIO is converted to SRIO, it is then transmitted through... Figure 5 As shown, RP6 → RJ6 → P6 → J6 directly transmits data to the front-panel data exchange module, and then distributes the data to the general computing module (a type of load module) according to the task allocation.
[0025] The rear interface module can also be plugged into, for example Figure 4 Following the general computing module shown, by Figure 5As shown, RP3 → RJ3 → J3 → P3 directly transmits data to the general computing module on the front panel for processing. Then, through the general computing module P3 → J3 → back panel → data exchange module RJ(2~5) → P(2~5), the data exchange module distributes the data to the general computing module according to the task allocation.
[0026] In the signal processor, the power supply module is mainly used to power the computing, switching, and fan units. The +12V supply is the main power supply for module operation, the +3.3V supply is the auxiliary power supply for management, and the +48V supply is the power supply for the DC cooling fans in the fan unit. The power supply module provides dual IPMB (I2C) management interfaces. A maximum of three power supply modules can be inserted into a single chassis; a 2+1 redundancy design is implemented to improve task reliability. When the power consumption of the modules inserted into the signal processor exceeds the power provided by two power supplies, the 2+1 redundancy design can be eliminated, and the three power supply modules can be connected in parallel, with current sharing functionality. When the power consumption of the modules inserted into the signal processor is relatively low or the number of modules is small, and one power supply module is sufficient to provide the required power, two power supply modules can be inserted, implementing a 1+1 redundancy design.
[0027] In the general-purpose signal processor of this embodiment, the modules adopt a star interconnection mode, with each module having equal status, consistent communication mode, and basically consistent communication latency, making it very easy to achieve expansion and contraction within the chassis; for higher performance application system requirements, system expansion can be achieved based on the interconnection of switching modules between chassis. Figure 6 This is a dual-switching interconnection topology diagram of a general signal processor involved in this embodiment. In the diagram, data bus 1 and data bus 2 are point-to-point serial buses. The two buses are completely identical and of equal status. They include gigabit network electrical signals 1GbE SerDes, 40GbE or 40Gbps SRIO 3.0 or other 40Gbps SerDes serial bus electrical signals, as well as the 100Gbps fiber optic signal extended in this embodiment.
[0028] Figure 7 This is a general signal processor system architecture diagram involved in this embodiment. The three buses below are the Intelligent Platform Management Bus (IPMB), the Task Control Bus (1GbE Gigabit Ethernet), and the Data Bus (40Gbps). The Data Bus is a standard VITA65-2010 OpenVPX bus, which is an electrical signal route from the backplane. This embodiment adds a 100Gbps fiber optic bus route from the front panel. Figure 7 The expansion bus at the top.
[0029] Depend on Figure 6As we know, the module interconnection adopts a star interconnection architecture based on the OpenVPX specification. According to power supply, management, and application requirements, and referring to the design principles of OpenVPX, the system logical architecture is divided into a base plane (Utility Plane), a management plane (Management Plane), a control plane (Control Plane), a data plane (Data Plane), and an expansion plane (Expansion Plane). (Plane refers to the physical and logical channels for interconnection between devices.) The backplane is the physical carrier for realizing module interconnection; its logical interconnection relationships are described in [link to backplane]. Figure 8 The backplane contains 3 power supply slots (XSP1~XSP3) and 10 function slots (including 8 processing slots + 2 switching slots, XS1~XS10). Each of the processing slots 1-8 has 2 10G×4 high-speed buses connected to switching slots 1 and 2 respectively, with a single lane speed of 10Gbps. Each of the processing slots 1-8 also has 2 SGMII gigabit network connections, connected to switching slots 1 and 2 respectively. Two PCIe 3.0×4 buses are provided between adjacent slots in each of the processing slots 1-8, with a single lane speed of 8Gbps. There are 2 system I2C buses connecting the 3 power supply slots and 10 function slots. External power supply is 220V DC input, with the power supply slots providing +12V, 3.3V, and 48V DC power. The +12V and 3.3V power supplies the function modules, and the +48V power supplies the plug-in fan. Figure 8 The interconnection diagram of the general signal processor baseboard involved in this embodiment is explained as follows: (1) Basic plane: The basic plane provides the most basic services for the system, including system power supply, system reference clock, system reset, system test signals, etc.
[0030] (2) Management plane: The management plane is used to organize and manage hardware resources based on the IPMI standard, and mainly consists of ChMC (Chassis Management Controller) and IPMC.
[0031] (3) Control plane: The control plane of the signal processor is a gigabit Ethernet used to carry business application management and control data, and adopts a dual-star gigabit Ethernet topology.
[0032] (4) Data plane: The data plane is responsible for building a high-bandwidth, low-latency data path between boards and on the backplane to carry business data for information processing (such as echo data, intermediate processing data, etc.). Communication protocols of the physical layer, logical layer, and network layer will be applied to the data plane.
[0033] In this embodiment, a ×4 high-speed serial bus data plane is reserved to transmit service data between modules. This ×4 high-speed serial bus data plane can be different interface protocols such as 40GbE network, 40Gbps SRIO 3.0, and single-channel 8.5Gbps FC.
[0034] (5) Extended Plane: The extended plane enables interconnection between modules and adjacent modules. Similar to the data plane, the extended plane requires low-latency, high-bandwidth channels to support its communication. Each functional module of the signal processor supports three output modes: 1 set of PCIe (4.0 and above, backward compatible with 3.0 / 2.0 / 1.0, the same below) × 16, 2 sets of PCIe × 8, or 4 sets of PCIe × 4. Functional modules are interconnected point-to-point with adjacent modules via a PCIe bus.
[0035] (6) Expanding the data plane: In this embodiment, based on the previous types of planes, the data between modules is interconnected through the MT fiber of the VPX front-end module. Like the SerDes electrical signal on the backplane, it is still a point-to-point transmission from the load module to the switching module, and still satisfies the requirements. Figure 6 The dual-star switching architecture is used, except that the physical medium for transmission is changed to optical fiber, with a single-channel rate of 25Gbps. For the signal processor, an additional 4×100Gbps high-speed serial bus is added to transmit service data in the data plane.
[0036] In the general-purpose processing module (a type of load module), the SDI4820 is the core chip for multi-protocol conversion. It's equivalent to the older PCIe bridge chips, which previously only had single-protocol conversion capabilities. The SDI4820, however, incorporates all of these functions. Taking ETH as an example, the software configuration method for protocol conversion is as follows: Figure 9 As shown: The software configuration steps for multiple protocol conversions in the load module include: K1: Configure the function block Bank, set the BCFG and SPD pins, power on the SDI switching module, perform a hardware reset on the SDI4820 chip, and make the configuration path ready. K2: PLL locks the core phase-locked loop, loads BCFG and SPD into registers, resets and releases serdes, loads configuration, outputs Ethernet IP clock xsbi_clk, enters configuration controller mode, and configures port rate / mode to the relevant registers. K3: After configuration, establish a communication link and send and receive data packets.
[0037] In the data exchange module, the core of the entire board is two SDI4820 chips. These are equivalent to previous switching chips, which only had single-protocol switching capabilities. The SDI4820 not only includes these functions but can also perform mixed-protocol switching, such as ETH, SRIO, and FC. Furthermore, the speed has been improved generationally; for example, SRIO 3.0's speed has increased from 10.3125Gbps to SRIO 4.0's 25.78125Gbps. Taking ETH as an example, the software configuration method for the switching protocol is as follows... Figure 10 As shown: The specific steps include: K4: When switching port speed or mode during operation, first disable the enable of all ports in the function block Bank and stop receiving packets; K5: Configure global routing, disallow packet forwarding to function blocks (Bank), and modify the port type to the required rate mode; K6: If the channel rate changes, reset the corresponding SERDES channel, enter the configuration controller mode, and reconfigure the rate, mode, and control registers in the Ethernet physical layer. K7: After configuration, establish a communication link and send and receive data packets.
[0038] In the back-end interface module, the FPGA is the core of the entire board, responsible for sending and receiving data and performing protocol conversion from RocketIO / Aurora to ETH / SRIO / FC / PCIe. Taking RocketIO to SRIO as an example, the conversion process is as follows: Figure 11 As shown, the conversion to the FC protocol is similar. The back-end interface module includes an FPGA, which transmits and receives data, completing the protocol conversion from RocketIO or Aurora to ETH, SRIO, FC, and PCIe. The specific steps include: T1: On the RocketIO side, within the FPGA, logic programming is used to receive the serial data stream and perform physical layer processing, which includes word alignment, 8b or 10b decoding, and comma detection. T2: Package the logic layer data into RapidIO protocol format, and generate packet headers and CRC checksums; T3: Store in FIFO buffer, perform transaction processing and flow control logic layer processing, and send data through RapidIO port; T4: On the RapidIO side, within the FPGA, logic programming is used to parse the RapidIO packet header protocol and extract information, including transaction type, address, and length. T5: Insert control characters, including Idle, Start, and End of Packet; T6: Perform 8b / 10b encoding, parallel-to-serial conversion, put the data into the Playload buffer, and send the data through the RocketIO port.
[0039] Data from ETH / SRIO / FC / PCIe protocols does not require conversion and can be directly passed to the data exchange module. Therefore, the signal processor of this invention can interface with six interface protocols.
[0040] Figure 12 This is a front view of a general-purpose signal processor according to an embodiment of the present invention; Figure 13 This is a rear view of a general-purpose signal processor according to an embodiment of the present invention; Figure 14 This is a front view of a general signal processing chassis according to an embodiment of the present invention; Figure 15 This is a rear front view of the general signal processing chassis involved in the embodiments of the present invention.
[0041] This invention provides a general-purpose signal processor with a software-defined bus and interface protocol. The signal processor's interface and bus feature software-definable interconnectivity, not limited to a fixed interface or bus, and applicable to various purposes and uses. By supporting system interconnectivity through software-defined hardware, it can both define a single protocol required for a specific piece of equipment and, based on software-defined interconnect technology, enable bridging between different protocols and generate multiple protocols. It supports hybrid interconnection of heterogeneous and custom protocols, creating a new, flexible, and adaptable software-defined interconnect device system, providing technical support for multi-functional integrated back-end processing.
[0042] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. However, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A general-purpose signal processor with a software-defined bus and interface protocol, characterized in that, Includes functional modules, rear interface modules, power supply modules, backplane, chassis, and fan units; The backplane is the physical carrier for realizing module interconnection, including 3 power supply slots and 10 function slots; The functional modules include two data exchange modules and a load module; A chassis can accommodate 2 data exchange modules, no more than 8 load modules, and no more than 3 power supply modules. The two data exchange modules are of the same type, and a 1+1 redundancy design is implemented for the two data exchange modules to achieve 1:1 online backup; The 12 Gigabit Ethernet signals on the VPX P1 connector of the data exchange module complete the exchange of Gigabit Ethernet signals from all load modules VPX P4 connectors gathered from the backplane. The 12 ETH / SRIO / FC / PCIe multi-protocol signals on the VPX P2, P3, P4, and P5 connectors of the data exchange module complete the data exchange of ETH / SRIO / FC / PCIe multi-protocol signals from all load modules VPX P1 gathered from the backplane. The rear interface module can be plugged into the rear of the data exchange module or the load module; The power module provides dual IPMB management interfaces based on the I2C protocol. The power module is used to supply power to the load module, data exchange module and fan unit. The +12V is the main power supply for the functional modules, the +3.3V is the auxiliary power supply for management, and the +48V is the power supply for the cooling DC fan in the fan unit.
2. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, It also includes the OpenVPX bus and a 100Gbps fiber bus; The OpenVPX bus is the standard VITA 65-2010 OpenVPX bus, which includes the Intelligent Platform Management Bus (IPMB), the Task Control Bus (1GbE Gigabit Ethernet), and the Data Bus (40Gbps Serial Bus). The OpenVPX bus transmits electrical signals from the backplane. The 100Gbps fiber optic bus transmits electrical signals from the front panel of the load board, not from the back panel.
3. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, The back panel has 10 functional slots, including 8 processing slots and 2 exchange slots; Each of the eight processing slots has two 10G×4 high-speed buses that are connected to two switching slots respectively, with a single channel rate of 10Gbps. Each of the eight processing slots has two SGMII gigabit network lines, which are interconnected with two switching slots respectively; The eight processing slots are interconnected by two PCIe 3.0×4 buses between each pair of adjacent slots, with a single-channel rate of 8Gbps; The dual-channel IPMB management interface based on the I2C protocol is associated with 3 power supply slots and 10 function slots; the external power supply is 220V DC input, and the power supply slots lead out DC +12V, 3.3V and 48V power supplies, of which +12V and 3.3V are used to power the function modules and +48V is used to power the fan unit.
4. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, If the back interface module is plugged after the data exchange module, the data transmitted from the outside will be converted in the back interface module. The steps include: S1: Data is transmitted directly to the data exchange module on the front board in sequence via RP6, RJ6, P6, and J6; S2: Then distribute the task allocation data to the load module.
5. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, If the rear interface module is plugged after the load module, the data conversion steps include: S3: Data is transmitted directly to the load module in the front panel for processing via RP3, RJ3, J3, and P3 in sequence; S4: Then pass the data sequentially through load modules P3, J3, backplane, data exchange modules RJ2~RJ5, and P2~P5; S5: The data exchange module distributes data to the load module according to the task allocation.
6. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, The load module includes the SDI4820 software-defined interconnect switching chip, which supports multiple protocol conversions. The software configuration steps for multiple protocol conversions in the load module include: K1: Configure the function block Bank, set the BCFG and SPD pins, power on the SDI switching module, perform a hardware reset on the SDI4820 chip, and make the configuration path ready. K2: PLL locks the core phase-locked loop, loads BCFG and SPD into registers, resets and releases serdes, loads configuration, outputs Ethernet IP clock xsbi_clk, enters configuration controller mode, and configures port rate / mode to the relevant registers. K3: After configuration, establish a communication link and send and receive data packets.
7. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, The data exchange module includes two SDI4820 software-defined interconnect switching chips that support multiple protocol conversions, enabling mixed protocol switching. The specific steps include: K4: When switching port speed or mode during operation, first disable the enable of all ports in the function block Bank and stop receiving packets; K5: Configure global routing, disallow packet forwarding to function blocks (Bank), and modify the port type to the required rate mode; K6: If the channel rate changes, reset the corresponding SERDES channel, enter the configuration controller mode, and reconfigure the rate, mode, and control registers in the Ethernet physical layer. K7: After configuration, establish a communication link and send and receive data packets.
8. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, The back-end interface module includes an FPGA, which transmits and receives data and performs protocol conversion from RocketIO or Aurora to ETH, SRIO, FC, and PCIe. The general-purpose signal processor can interface with six interface protocols. The specific steps include: T1: On the RocketIO side, within the FPGA, logic programming is used to receive the serial data stream and perform physical layer processing, which includes word alignment, 8b or 10b decoding, and comma detection. T2: Package the logic layer data into RapidIO protocol format, and generate packet headers and CRC checksums; T3: Store in FIFO buffer, perform transaction processing and flow control logic layer processing, and send data through RapidIO port; T4: On the RapidIO side, within the FPGA, logic programming is used to parse the RapidIO packet header protocol and extract information, including transaction type, address, and length. T5: Insert control characters, including Idle, Start, and End of Packet; T6: Perform 8b / 10b encoding, parallel-to-serial conversion, put the data into the Playload buffer, and send the data through the RocketIO port.
9. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, If the power consumption of a module in a general-purpose signal processor is greater than the power that two power supply modules can provide, then the number of power supply modules is three, without 2+1 redundancy design, and the three power supply modules are connected in parallel to provide power. If the power provided by one power module is less than the power consumption of the modules in the general signal processor and less than the power provided by two power modules, then the number of power modules is two or three. If there are two power modules, then the two power modules are connected in parallel to supply power. If there are 3 power modules, then the power modules are designed with 2+1 redundancy to achieve 2:1 online backup; If the power consumption of a module in a general-purpose signal processor is less than or equal to the power that one power supply module can provide, then the number of power supply modules is one or two. If there is only one power module, then one power module will provide power. If there are two power modules, then a 1+1 redundancy design is implemented for the power modules to achieve 1:1 online backup.
10. The general-purpose signal processor with software-defined bus and interface protocol according to claim 1, characterized in that, The interconnection between general signal processing modules adopts a star interconnection architecture based on the OpenVPX specification. The architecture consists of multiple planes, which are the physical and logical channels for interconnection between devices, including a base plane, management plane, control plane, data plane, extension plane, and extended data plane. The base plane provides basic services, including system power supply, system reference clock, system reset, and system test signals; The management plane is used to organize and manage hardware resources based on the IPMI standard; The control plane adopts a dual-star gigabit Ethernet topology to carry business application management and control data; The data plane uses a ×4 high-speed serial bus data plane to transmit service data between modules. The ×4 high-speed serial bus data plane can be different interface protocols, including 40GbE network interface protocol, 40Gbps SRIO 3.0 interface protocol, and single-channel 8.5Gbps FC interface protocol. The service data includes echo data and intermediate processing data. The extended plane enables interconnection between the module and two adjacent modules. Functional modules are interconnected point-to-point with adjacent modules via PCIe bus. A single functional module supports three output modes: 1 set of PCIe×16, 2 sets of PCIe×8, or 4 sets of PCIe×4. Expand the data plane to enable point-to-point transmission from the load module to the switching module by adding a ×4 100Gbps high-speed serial bus to transmit service data from the data plane.