FPGA software online updating method and system
Through the synergy of the external DDR chip of the DSP chip and the receiving-end FLASH chip, efficient online updating of FPGA software is achieved, solving the problems of long update time and high hardware cost in the existing technology, and is suitable for the synchronous update of multiple FPGA chips.
Patent Information
- Application Number
- CN202510903105.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-01
- Publication Date
- 2025-10-28
AI Technical Summary
Existing online FPGA software update methods suffer from problems such as long update times, high hardware costs, or the need for manual operation, and are particularly difficult to update efficiently when there is no debugging interface.
Binary file data is sent to the FPGA chip via an external DDR chip connected to the DSP chip, and flow control is performed using the receiving FLASH chip. The FPGA chip only caches a small amount of data. By combining the FPGA chip with the FLASH chip's operation process, efficient updates can be achieved.
It shortens software update time, improves update efficiency, reduces FLASH chip operation waiting time, and is suitable for synchronous updates of multiple FPGA chips.
Smart Images
Figure CN120848916A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of data update technology, and in particular to an online update method and system for FPGA software. Background Technology
[0002] FPGA chips are widely used in high-speed signal processing systems. Generally, the firmware binary file for an FPGA chip is several MB to tens of MB in size and needs to be stored in an external FLASH chip. Software flashing can be done by using an FPGA emulator to download and program the FLASH chip, or by designing dedicated software. Currently, FPGA emulators commonly use USB interfaces, resulting in slow download speeds, and software updates require manual intervention. This is especially problematic for electronic systems that, after debugging, lack a dedicated FPGA debugging interface, necessitating opening the device casing for software updates.
[0003] Existing online FPGA software updates either rely on an off-chip FPGA controller (such as a DSP chip) as the main control device or require external DDR memory on the FPGA. Using an off-chip controller results in frequent external interactions and significant latency, leading to long update times. Using external memory can increase hardware costs; in some cases, the FPGA chip lacks external DDR memory, and the on-chip memory cannot hold the entire configuration binary file. All these approaches impose various limitations on online FPGA software updates.
[0004] Therefore, it is necessary to improve one or more of the problems existing in the above-mentioned related technical solutions.
[0005] It should be noted that this section is intended to provide background or context for the technical solutions of this disclosure as set forth in the claims. The description herein does not constitute an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0006] The purpose of this disclosure is to provide an online FPGA software update method and system, thereby overcoming at least to some extent one or more problems caused by the limitations and defects of related technologies.
[0007] This disclosure first provides a method for online FPGA software updates, including: Receive a data update start command sent by the DSP chip, the data update start command including multiple command parameters; In response to the data update start command, the device receives binary file data sent by the DSP chip and stores the binary file data in the receive buffer of the FPGA chip. The binary file data is initially stored in the external DDR chip of the DSP chip. The FLASH control command is generated according to the data update start command and sent to the FLASH chip. The area to be updated in the FLASH chip is erased according to multiple command parameters in the control command. The binary file data in the receiving buffer is read and written to the area to be updated to complete the data update.
[0008] In one embodiment of this disclosure, the plurality of command parameters include: command type, software update start address, data packet length, and verification information.
[0009] This disclosure further provides an online FPGA software update system, the update system comprising: The DSP chip is used to send a data update start command and binary file data to the FPGA chip. The data update start command includes multiple command parameters. The DDR chip is used to store binary file data and is an external chip of the DSP chip. An FPGA chip is used to respond to the data update start command, receive binary file data sent by the DSP chip, and store the binary file data in the receive buffer of the FPGA chip; and generate FLASH control instructions according to the data update start command and send control instructions to the FLASH chip. The FLASH chip is an external chip of the FPGA chip. The FLASH chip is used to respond to the control command, erase the area to be updated in the FLASH chip according to multiple command parameters in the control command, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
[0010] In one embodiment of this disclosure, the plurality of command parameters include: command type, software update start address, data packet length, and verification information.
[0011] In one embodiment of this disclosure, the FPGA chip includes: The high-speed serial interface module is used to send receive status signals to the DSP chip and receive data update startup commands and binary file data sent by the DSP chip. The FLASH control module is used to generate FLASH control instructions based on the data update start command and send the FLASH control instructions to the FLASH interface module. It generates a receiving status signal based on the remaining space of the receiving buffer in the FLASH control module and sends it to the high-speed serial interface module. It receives the binary file data and stores it in the receiving buffer. It reads the binary file data in the receiving buffer and writes the binary file data into the area to be updated in the FLASH chip. The FLASH interface module is used to receive FLASH control commands sent by the FLASH control module, convert them into FLASH chip interface signals, and send the FLASH chip interface signals to the FLASH chip.
[0012] In one embodiment of this disclosure, when the remaining space in the receiving buffer is greater than the length of one data packet, the receiving status signal is valid. When the receiving status signal is valid, the DSP chip sends binary file data to the FPGA chip.
[0013] In one embodiment of this disclosure, the FLASH control instructions include: erase, program, and read operation instructions; When the FLASH interface module receives the erase operation command, it continuously sends the FLASH status register to read the status signal to query the status until the erase command signal is marked in the FLASH status register. When the FLASH interface module receives a programming operation instruction, it continuously sends FLASH status register read status signals to query the status until the FLASH status register marks the end of the editing instruction signal. When the FLASH interface module receives a read operation command, it continuously reads data from the specified area, calculates the verification information of the read data during the data reading process, and compares the calculated verification information of the read data with the verification information in the command parameters to determine whether the update is successful.
[0014] This disclosure also provides an online FPGA software update method, which enables simultaneous data updates for multiple FPGA chips to be updated by performing the following operations through a control-end FPGA chip: Receive a data update start command sent by the DSP chip, the data update start command including multiple command parameters; The data update start command is sent to multiple FPGA chips that need to be updated. The system receives multiple receive status signals sent by the multiple FPGA chips to be updated after responding to the data update start command, and summarizes the multiple receive status signals to obtain a composite receive status signal, which is then sent to the DSP chip. The FPGA chip receives binary file data sent by the DSP chip and stores the binary file data in the receive buffer of the FPGA chip, wherein the binary file data is stored in the external DDR chip of the DSP chip; The binary file data is sent to the plurality of FPGA chips to be updated, so that the plurality of FPGA chips to be updated can erase the area to be updated in the plurality of FPGA chips to be updated according to the plurality of command parameters in the data update start command, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
[0015] In one embodiment of this disclosure, the control terminal FPGA chip, the DSP chip, and the DDR chip are located on the same control board, and the plurality of FPGA chips to be updated are located one-to-one on a plurality of circuit boards.
[0016] In one embodiment of this disclosure, each of the plurality of FPGA chips to be updated has a corresponding FLASH chip.
[0017] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: This disclosure discloses an online software update method and system for FPGAs. The configuration binary file data is sent to the FPGA chip via an external DDR chip connected to the external DSP chip. The receiving FLASH chip is used for flow control. During the software update process, the FPGA chip only needs to cache a small amount of data. At the same time, the FPGA chip controls the operation process of the FLASH chip, reducing the FLASH chip operation waiting time and improving the software update efficiency. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0019] Figure 1 A flowchart illustrating an exemplary embodiment of the present disclosure of an FPGA software online update method is shown. Figure 2This diagram illustrates a block diagram of an FPGA software online update system in an exemplary embodiment of this disclosure. Figure 3 This diagram illustrates a DSP software processing flowchart in an exemplary embodiment of this disclosure. Figure 4 This diagram illustrates the internal functional module structure of the FPGA software in an exemplary embodiment of this disclosure. Figure 5 This diagram illustrates the processing flowchart of the FLASH control module in an exemplary embodiment of this disclosure. Figure 6 This diagram illustrates the erase / programming process of the FLASH interface module in an exemplary embodiment of this disclosure. Figure 7 This diagram illustrates the FLASH interface module reading process in an exemplary embodiment of this disclosure. Figure 8 A flowchart illustrating an online FPGA software update method in yet another exemplary embodiment of this disclosure is shown. Figure 9 This diagram illustrates a system block diagram of simultaneous software updates for multiple FPGA chips in an exemplary embodiment of this disclosure. Figure 10 A block diagram of the software functions of the FPGA chip on the control board in an exemplary embodiment of this disclosure is shown. Detailed Implementation
[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0021] Furthermore, the accompanying drawings are merely illustrative diagrams of embodiments of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.
[0022] This example implementation first provides a method for online FPGA software updates. Please refer to [link / reference]. Figure 1 The update method is described from the FPGA chip side, and the method may include: S101-S103, as follows: S101, Receive a data update start command sent by the DSP chip. The data update start command includes multiple command parameters. The multiple command parameters include: command type, software update start address, data packet length, and verification information.
[0023] The command types can be divided into two categories: Command Type 1, which sends binary file data while initiating the online update, only needs to be sent once during the online update process; and Command Type 2, which typically needs to be sent multiple times to send the binary file data. The software update start address and data packet length are 32-bit variables, representing the start address and length of the space to be updated within the FLASH chip, respectively, and only need to be sent once during the online update process. The verification information is a 32-bit variable, representing the checksum of the entire FPGA software binary file data, and only needs to be sent once during the online update process. The binary file data sent by the DSP chip to the FPGA chip in the online update start command only includes a portion of the entire FPGA software binary file. During the update process, the DSP chip needs to send the entire FPGA software binary file data multiple times to complete the update. Preferably, the amount of binary file data sent by the DSP chip each time should be an integer multiple of 256 bytes; the amount of data sent each time should not be too large to avoid consuming too much of the FPGA's internal storage resources.
[0024] S102, in response to the data update start command, receive binary file data sent by the DSP chip, and store the binary file data in the receive buffer of the FPGA chip, wherein the binary file data is initially stored in the external DDR chip of the DSP chip.
[0025] When the remaining space in the receive buffer is greater than the length of one data packet, the receive status signal is valid. In this case, the DSP chip can send binary file data, and the FPGA chip can receive it. When the space in the receive buffer is less than or equal to the length of the data packet, the receive status signal is invalid. In this case, the DSP chip cannot send binary file data, and the FPGA chip will not receive it. This achieves flow control at the receiving end. That is, before sending data to the FPGA chip, the DSP chip should check the receive status signal in the FPGA software; the DSP chip can only send data if there is sufficient remaining space in the FPGA chip's receive buffer.
[0026] S103, generate FLASH control instructions according to the data update start command, send control instructions to the FLASH chip, erase the area to be updated in the FLASH chip according to multiple command parameters in the control instructions, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
[0027] In this embodiment, the configuration binary file data is sent to the FPGA chip via the external DDR chip of the external DSP chip, and the receiving end FLASH chip is used for flow control. During the software update process, the FPGA chip only needs to cache a small amount of data. At the same time, the FPGA chip uses a loop to query the working status of the FLASH chip to shorten the idle time and improve the efficiency of software update.
[0028] This example implementation also provides an online FPGA software update system, please refer to... Figure 2 The update system includes: The DSP chip is used to send a data update start command and binary file data to the FPGA chip. The data update start command includes multiple command parameters. The DDR chip is used to store binary file data and is an external chip of the DSP chip. An FPGA chip is used to respond to the data update start command, receive binary file data sent by the DSP chip, and store the binary file data in the receive buffer of the FPGA chip; and generate FLASH control instructions according to the data update start command and send control instructions to the FLASH chip. The FLASH chip is an external chip of the FPGA chip. The FLASH chip is used to respond to the control command, erase the area to be updated in the FLASH chip according to multiple command parameters in the control command, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
[0029] In this embodiment, binary file data is sent to the FPGA chip via an external DDR chip connected to the external DSP chip, and flow control is performed using a receiving FLASH chip. During the software update process, the FPGA chip only needs to cache a small amount of data. At the same time, by cyclically querying the working status of the FLASH chip, the idle time is shortened and the software update efficiency is improved.
[0030] The specific functions and interaction processes of each chip in the above embodiments are described below.
[0031] Combination Figure 2This section explains the interconnections between the chips. In this embodiment, a DSP chip, DDR chip, FPGA chip, and FLASH chip are arranged on the same circuit board. The FPGA software configuration information is stored in an off-chip FLASH chip. The software development computer is connected to the DSP chip, the DSP chip is connected to the DDR chip and the FPGA chip respectively, and the FPGA chip is connected to the FLASH chip. The software interface modules, such as the high-speed serial interface between the FPGA chip and the DSP chip, the interface between the DSP chip and the DDR chip, and the network interface of the DSP chip, can all adopt common designs in this field and are not specifically limited in this application.
[0032] First, the FPGA software binary file stored on the software development computer is sent to the DDR chip memory on the circuit board. The software development computer can connect to the DSP chip on the circuit board via a network interface or a USB interface emulator. Using a network connection, the software development computer needs to run a network sending application, and the DSP chip needs to run a network receiving program. The DSP chip receives the FPGA software binary file data and stores it inside the DDR chip. Using a USB interface emulator connection requires manual operation of the DSP software development tools on the software development computer to load the FPGA software binary file data into the external DDR chip of the DSP chip. This method is relatively simple and can be used for initial debugging.
[0033] Then, the DSP chip sends a data update start command and binary file data to the FPGA chip. The data update start command includes multiple command parameters, including command type, software update start address, data packet length, and verification information.
[0034] During the FPGA software online update process, please refer to... Figure 3 The DSP chip control flow is as follows: First, the DSP chip sends a data update start command, and then it continuously queries the receive status signal returned by the FPGA chip. If the receive status signal is valid (meaning that the FPGA chip can receive binary file data), then it sends the binary file data; otherwise, it waits.
[0035] After the binary file data has been sent, wait for a period of time to check the FPGA verification information status to determine whether the software update was successful. The waiting time depends on the file size, the FLASH interface operating frequency, and the data width, and can be determined based on the actual situation. Generally, FLASH chips have a slow write speed but a fast read speed, and the entire chip data can be read in a few seconds. The FPGA verification status check here can be omitted; the success of the online update can be determined based on the FPGA software's operating status after the circuit board is powered on again.
[0036] After receiving the data update startup command and binary file data from the DSP chip, the FPGA chip sends control commands to the FLASH chip to complete the online software update. Please refer to [link / reference needed]. Figure 4 The FPGA chip includes a high-speed serial interface module, a FLASH control module, and a FLASH interface module. The FPGA chip completes online updates through these three modules, as detailed below: (1) High-speed serial interface module The high-speed serial interface module facilitates communication between the FPGA chip and the DSP chip. It receives data updates, startup commands, and binary file data from the DSP chip and continuously sends receive status signals to the DSP chip. When the FPGA chip communicates directly with the DSP chip, the SRIO interface protocol can be used; when the FPGA chip sends receive status signals to the DSP chip, the GPIO interface signals can be used. The high-speed serial interface module in the FPGA software can refer to general designs in this field and will not be described in detail here.
[0037] (2) FLASH control module The FLASH control module translates the data update start commands sent by the DSP chip into FLASH control instructions. The control instructions sent by the FLASH control module to the FLASH interface module are divided into three types: erase, program, and read. Specifically, these are sector (64KB) erase, page (256 bytes) programming, and read. Since FPGA software binary file data is typically in the MB range, the FLASH control module needs to send multiple erase and program commands. However, the read operation can read the entire chip's data at once, so the FLASH control module only needs to send a single read command. The FLASH control module within the FPGA chip has a built-in receive buffer and control logic. The control logic maintains the read / write status of the receive buffer, generates receive status signals, and translates the DSP data update start commands into FLASH interface module control commands. The receive buffer capacity is no less than twice the amount of binary data in the DSP data packet.
[0038] Please refer to Figure 5 The FLASH control module processing flow is as follows: ① After the circuit board is powered on, the receive buffer and receive status signal are reset, ready to receive data, and waiting for the DSP chip to send a data update start command.
[0039] ② Upon receiving the DSP chip's data update start command, the starting address and length of the FLASH storage space are determined based on the command parameters in the data update start command. Multiple erase operation commands are then sent to the FLASH interface function module until the area to be updated is completely erased. After each erase operation command is sent, the system waits for the FLASH interface function module to return an interface status signal before sending the next erase operation command.
[0040] ③ Receive binary file data sent by the DSP chip and store it in the receive buffer. If the space of the receive buffer is greater than the length of a data packet sent by the DSP, the receive status signal is valid; otherwise, it is invalid.
[0041] ④ Read binary file data from the receive buffer and send programming operation commands to the FLASH interface module until the area to be updated is programmed. After each programming operation command is sent, wait for the FLASH interface module to return an interface status signal before sending the next programming operation command.
[0042] ⑤ Send a read operation command to the FLASH interface function module.
[0043] (3) FLASH interface module Please refer to Figure 6 and Figure 7 The FLASH interface module processing flow is as follows: ① Upon receiving an erase operation command, the reset interface status signal is set to idle. A corresponding FLASH interface status signal is generated after each erase operation command signal ends. A FLASH status register read command is sent after each erase operation command signal is received. This process is repeated cyclically until the FLASH status register indicates the end of the erase operation command. The interface status signal is then set to allow the next erase operation.
[0044] ② Upon receiving a programming operation instruction, reset the interface status signal, generate the corresponding FLASH interface signal for the programming operation instruction, and send a FLASH status register read instruction after each programming operation instruction signal ends, until the FLASH status register marks the end of the programming operation instruction. Set the interface status signal to allow the next programming operation.
[0045] ③ Upon receiving a read operation command, a corresponding FLASH interface status signal is generated, and data in the specified area is continuously read. During the data reading process, the verification information of the read data is calculated and compared with the verification information in the received command parameters to determine whether the update was successful.
[0046] This example implementation also provides an online FPGA software update method. The following operations are performed by the control-side FPGA chip to simultaneously update the data of multiple FPGA chips to be updated. Please refer to [reference needed]. Figure 8 The update method includes steps S201 to S205, as follows: S201, Receive a data update start command sent by the DSP chip, the data update start command includes multiple command parameters; S202, the data update start command is sent to multiple FPGA chips to be updated, each of which has a corresponding FLASH chip.
[0047] S203, receive multiple receive status signals sent by the multiple FPGA chips to be updated after responding to the data update start command, summarize the multiple receive status signals to obtain a combined receive status signal, and send the combined receive status signal to the DSP chip. S204, receive binary file data sent by the DSP chip, and store the binary file data in the receive buffer of the FPGA chip, wherein the binary file data is stored in the external DDR chip of the DSP chip; S205, the binary file data is sent to the plurality of FPGA chips to be updated, so that the plurality of FPGA chips to be updated erase the area to be updated in the plurality of FPGA chips to be updated according to the plurality of command parameters in the data update start command, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
[0048] Please refer to Figure 9 This embodiment is applicable when the FPGA chip to be updated does not have a DSP chip, or when multiple FPGA chips to be updated are running the same software program. The software development computer is connected to the control board via a network cable or USB interface. The main chips on the control board include a DSP chip, a DDR chip, and a control-end FPGA chip. The control-end FPGA chip on the control board is connected to multiple circuit boards to be updated (referred to as circuit board 1, circuit board 2, and circuit board 3) via a high-speed serial interface. The FPGA chips on these circuit boards run the same program. Using this method, multiple FPGA chips to be updated can be updated online simultaneously, improving software maintenance efficiency.
[0049] Compared to embodiments where the FPGA chip and DSP chip are on the same circuit board, this embodiment provides more functions for the control-side FPGA chip. Please refer to... Figure 10The main new functions of the FPGA chip at the control end include: sending the DSP chip data update start command to multiple circuit boards at the same time, and summarizing the received status signals of multiple circuit boards and sending them to the DSP chip.
[0050] Please refer to Figure 10 The receive status signal indicates whether the FPGA chip on the circuit board to be updated can receive data. A receive status aggregation module can be used to combine the receive status signals from multiple FPGA chips on the circuit board into a single signal for the DSP chip. The verification status indicates the verification status of the FPGA chip on the circuit board to be updated. A verification status aggregation module can be used to combine the verification status signals from multiple FPGA chips on the circuit board into a single signal for the DSP chip. Similar to single-chip FPGA software updates, the FPGA verification status query operation can be omitted here; the success of the online update can be determined based on the FPGA software's operating status after the circuit board is powered on again.
[0051] In summary, the efficient online FPGA software update method provided in this application sends configuration binary file data to the FPGA chip via the FPGA's external data communication interface and employs receiver flow control. During the software update process, the FPGA chip only needs to cache a small amount of data. Simultaneously, the FPGA chip controls the FLASH chip's operation flow, efficiently completing the online update of the FPGA software to the FLASH chip, reducing FLASH chip operation waiting time, and improving software update efficiency. Furthermore, this method can be extended to scenarios where multiple FPGAs are updated simultaneously, allowing multiple FPGAs running the same program to perform synchronous software updates, making it particularly suitable for FPGA software updates in distributed sampling systems for array antennas.
[0052] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A method for online FPGA software updates, characterized in that, include: Receive a data update start command sent by the DSP chip, the data update start command including multiple command parameters; In response to the data update start command, the device receives binary file data sent by the DSP chip and stores the binary file data in the receive buffer of the FPGA chip. The binary file data is initially stored in the external DDR chip of the DSP chip. The FLASH control command is generated according to the data update start command and sent to the FLASH chip. The area to be updated in the FLASH chip is erased according to multiple command parameters in the control command. The binary file data in the receiving buffer is read and written to the area to be updated to complete the data update.
2. The FPGA software online update method according to claim 1, characterized in that, The multiple command parameters include: command type, software update start address, data packet length, and verification information.
3. An FPGA software online update system, characterized in that, The update system includes: The DSP chip is used to send a data update start command and binary file data to the FPGA chip. The data update start command includes multiple command parameters. The DDR chip is used to store binary file data and is an external chip of the DSP chip. An FPGA chip is used to respond to the data update start command, receive binary file data sent by the DSP chip, and store the binary file data in the receive buffer of the FPGA chip; and generate FLASH control instructions according to the data update start command and send control instructions to the FLASH chip. The FLASH chip is an external chip of the FPGA chip. The FLASH chip is used to respond to the control command, erase the area to be updated in the FLASH chip according to multiple command parameters in the control command, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
4. The FPGA software online update system according to claim 3, characterized in that, The multiple command parameters include: command type, software update start address, data packet length, and verification information.
5. The FPGA software online update system according to claim 4, characterized in that, The FPGA chip includes: The high-speed serial interface module is used to send receive status signals to the DSP chip and receive data update startup commands and binary file data sent by the DSP chip. The FLASH control module is used to generate FLASH control instructions based on the data update start command and send the FLASH control instructions to the FLASH interface module. It generates a receiving status signal based on the remaining space of the receiving buffer in the FLASH control module and sends it to the high-speed serial interface module. It receives the binary file data and stores it in the receiving buffer. It reads the binary file data in the receiving buffer and writes the binary file data into the area to be updated in the FLASH chip. The FLASH interface module is used to receive FLASH control commands sent by the FLASH control module, convert them into FLASH chip interface signals, and send the FLASH chip interface signals to the FLASH chip.
6. The FPGA software online update system according to claim 5, characterized in that, When the remaining space in the receiving buffer is greater than the length of one data packet, the receiving status signal is valid. When the receiving status signal is valid, the DSP chip sends binary file data to the FPGA chip.
7. The FPGA software online update system according to claim 5, characterized in that, The FLASH control instructions include: erase, program, and read operation instructions; When the FLASH interface module receives the erase operation command, it continuously sends the FLASH status register to read the status signal to query the status until the erase command signal is marked in the FLASH status register. When the FLASH interface module receives a programming operation instruction, it continuously sends FLASH status register read status signals to query the status until the FLASH status register marks the end of the editing instruction signal. When the FLASH interface module receives a read operation command, it continuously reads data from the specified area, calculates the verification information of the read data during the data reading process, and compares the calculated verification information of the read data with the verification information in the command parameters to determine whether the update is successful.
8. A method for online FPGA software updates, characterized in that, The following operations are performed using the control-end FPGA chip to simultaneously update the data of multiple FPGA chips to be updated: The update method includes: Receive a data update start command sent by the DSP chip, the data update start command including multiple command parameters; The data update start command is sent to multiple FPGA chips that need to be updated. The system receives multiple receive status signals sent by the multiple FPGA chips to be updated after responding to the data update start command, and summarizes the multiple receive status signals to obtain a composite receive status signal, which is then sent to the DSP chip. The FPGA chip receives binary file data sent by the DSP chip and stores the binary file data in the receive buffer of the FPGA chip, wherein the binary file data is stored in the external DDR chip of the DSP chip; The binary file data is sent to the plurality of FPGA chips to be updated, so that the plurality of FPGA chips to be updated can erase the area to be updated in the plurality of FPGA chips to be updated according to the plurality of command parameters in the data update start command, read the binary file data in the receiving buffer, and write the binary file data into the area to be updated to complete the data update.
9. The FPGA software online update method according to claim 8, characterized in that, The control terminal FPGA chip, the DSP chip, and the DDR chip are located on the same control board, and the multiple FPGA chips to be updated are located on multiple circuit boards in a one-to-one correspondence.
10. The FPGA software online update method according to claim 9, characterized in that, Each of the multiple FPGA chips to be updated has a corresponding FLASH chip.