Chip resource dynamic configuration method

Abstract

The present application relates to chip resource management and scheduling technical field, specifically to a kind of chip resource dynamic configuration method, including steps S1: event sensor detects and obtains the computing event, storage event, communication event of chip in task processing process;Step S2: event analysis unit is parsed to computing event, storage event, communication event in step 1 with event demand prediction, and generates resource configuration instruction;Step S3: according to the resource configuration instruction in step S2, chip resource is allocated immediately;Step S4: after chip resource is allocated immediately, the dynamic allocation of chip resource is cancelled.The present application solves the technical problems that the unit of chip resource allocation adjustment in prior art is large, which leads to the surge or sharp drop of calculation amount and data flow, and the chip resource cannot be configured more flexibly, efficiently and quickly when resource demand conflicts.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip resource management and scheduling, in particular to a chip resource dynamic configuration method. BACKGROUND

[0002] In the field of modern electronic systems and chip technology, the reasonable configuration of chip resources is crucial. As the core driving force of various intelligent devices and computing systems, chips contain a variety of key resources such as computing units, storage resources, and communication bandwidth. Effective resource configuration can maximize the performance potential of the chip, ensuring that it can provide services in the optimal state when running various complex tasks and applications, thereby improving the overall system's running efficiency and response speed. Reasonable resource configuration helps to balance the workload between different modules of the chip, avoiding some resources from being excessively idle while others are overloaded, thereby prolonging the service life of the chip and reducing energy consumption. In the context of rapid development of current technology and explosive growth of data processing demand, optimizing chip resource configuration has far-reaching significance.

[0003] In the prior art, the commonly used chip resource configuration method is static configuration, which fixes the allocation of various resources at the chip design stage. According to the pre-defined task model and expected running scenario, computing, storage, and other resources are allocated to different functional modules. This method basically does not change the resource allocation after the chip is manufactured. In addition, there is a dynamic configuration method based on simple rules. This method usually allocates chip resources according to the priority order of tasks. When a high-priority task arrives, a certain amount of resources is allocated to it according to the established rules. This method often relies on a series of pre-set logical rules to drive the allocation and adjustment of resources.

[0004] However, existing resource allocation methods have many flaws and limitations. Firstly, static allocation methods, once determined, are difficult to change. When faced with complex situations where task types and load intensities frequently change in actual operation, resource allocation is prone to severe disconnect from actual needs. This leads to some modules being under resource strain and unable to function properly, while others have significant idle resources, resulting in waste and hindering the full realization of the chip's overall performance advantages. Dynamic allocation methods based on simple rules, while offering some flexibility, often have relatively fixed and one-sided rules, making it difficult to cope with diverse and complex real-world application scenarios. When edge AI devices (smart cameras, AR glasses, etc.) run multimodal AI tasks (such as object detection, speech recognition, sensor fusion, etc.) in real time, their loads are characterized by sudden changes, heterogeneity, and conflicting resource demands. Existing chip resource allocation methods adjust resource allocation in large units, failing to provide more flexible, efficient, and rapid resource allocation when single tasks suddenly increase or decrease, or task combinations change, leading to sudden surges or drops in computational load and data flow, and conflicting resource demands. Summary of the Invention

[0005] The purpose of this application is to provide a method for dynamic configuration of chip resources, which solves the technical problems in the prior art, such as the large unit of chip resource allocation adjustment leading to a surge or drop in computing power and data traffic, and the inability to configure chip resources more flexibly, efficiently and quickly when resource demand conflicts exist.

[0006] To solve the above-mentioned technical problems, the solution adopted in this application is as follows:

[0007] A method for dynamic allocation of chip resources, the implementation process of which is as follows:

[0008] Step S1: The event sensor detects and acquires computational events, storage events, and communication events of the chip during task processing;

[0009] The computation events include three subcategories: multiply-accumulate instruction burst signals, instantaneous saturation / idle signals of NPU / DSP computing unit utilization, and specific operator activation signals; the storage events include three subcategories: cache miss storm signals, DRAM bank conflict signals, and specific data stream access pattern recognition signals; the communication events include two subcategories: NoC link congestion / idle signals and critical path delay exceeding threshold signals; the computation events, storage events, and communication events are referred to as the raw event stream.

[0010] Step S2: The event parsing unit parses the computation events, storage events, and communication events in Step 1 and predicts event requirements, and generates resource configuration instructions;

[0011] The event analysis unit is composed of a state machine and a lookup table, and is deployed in an NPU computing cluster, a memory controller, and a Noc node in a chip.

[0012] The event analysis unit performs resource scheduling demand mode identification on the original event and predicts the resource demand of the original event according to the resource scheduling demand mode; the resource scheduling demand mode includes a convolution calculation burst mode, a matrix multiplication bottleneck mode, a NoC congestion delay mode, a DMA data flow optimization mode, a high-priority preemption mode, and a task chain trigger mode.

[0013] Step S3: According to the resource configuration instruction in step S2, the chip resources are allocated in real time.

[0014] In this step, the computing resources, storage resources, and communication resources of the chip are finely decomposed into independent computing units, independent storage units, and independent communication units, and the chip resources are allocated and adjusted according to the resource configuration instruction in step S2.

[0015] Step S4: After the chip resources are allocated in real time, the dynamic allocation of the chip resources is revoked.

[0016] In this step, the event analysis unit continuously monitors the real-time state of the original event stream, and when a dynamic allocation revocation trigger condition is detected, a dynamic allocation revocation instruction is generated and executed to release the chip resources allocated in step S3.

[0017] Preferably, the event analysis unit analyzes the original event stream and predicts the event demand, and the implementation process is as follows:

[0018] Step S2.1: The WLU unit receives the original event and performs space-time alignment and filtering processing on the original event.

[0019] The WLU unit receives the original event stream in step S1, and the original event stream is in 64-bit format and includes event type, intensity, timestamp, and spatial coordinates. After the WLU unit receives the original event stream from different parts of the chip, the global clock offset of the chip is eliminated according to the timestamp, the synchronization accuracy is ±200ps, and the original event stream is filtered according to the spatial coordinates. Only the original events matching the location of the chip hardware resources directly managed by the current WLU unit are received, which are referred to as local events, and then a local event stream with a unified time reference is output.

[0020] Step S2.2: The event window buffers the local events in the recent period of time.

[0021] An event window is used to buffer the local events in the recent period of time, and the depth of the event window is determined according to the maximum event rate and the window time. The event window is a hardware queue with storage function.

[0022] Step S2.3: The WLU unit matches the cached local event with the predefined pattern rule, and identifies the specific resource scheduling requirement pattern of the local event;

[0023] Step S2.4: According to the resource scheduling requirement pattern of the local event in step S2.3, the resources required for the execution of the local event are predicted;

[0024] Step S2.5: Resource configuration instructions are generated according to the predicted resource requirements in step S2.4;

[0025] Step S2.6: The resource configuration instructions are distributed to the local resource controller.

[0026] Preferably, the chip resources are allocated in real time according to the resource configuration instructions in step S2, and the implementation process is as follows:

[0027] Step S3.1: The computing resources, storage resources, and communication resources of the chip are decomposed;

[0028] The computing resources are decomposed into independent computing units, the storage resources are decomposed into independent storage units, and the communication resources are decomposed into independent communication units;

[0029] Step S3.2: Chip resource dynamic allocation;

[0030] According to the real-time event resource requirements and system state, the configuration of the hardware resources is adjusted in real time by executing the resource configuration instructions.

[0031] Preferably, the dynamic allocation of the chip resources is revoked, and the implementation process is as follows:

[0032] Step S4.1: Revoking dynamic allocation trigger condition monitoring;

[0033] The dynamic allocation trigger condition includes the end of the burst instruction stream, the decrease of the cache miss rate, the completion of the high-priority task, and the relief of the communication path congestion;

[0034] Step S4.2: Generating a dynamic allocation revocation instruction;

[0035] The dynamic allocation revocation instruction includes a computing resource configuration revocation instruction, a storage resource configuration revocation instruction, and a communication resource configuration revocation instruction;

[0036] Step S4.3: Executing the dynamic allocation revocation instruction operation;

[0037] After the local resource controller receives the dynamic allocation revocation instruction in step S4.2, the local resource controller executes the corresponding dynamic allocation revocation operation

[0038] Step S4.4: Chip resource state feedback.

[0039] The local resource controller feeds back the current state of the chip resources to the WLU unit in real time after executing the undo dynamic allocation instruction operation

[0040] Preferably, the chip resources are abstracted, and the implementation process is as follows:

[0041] Step S3.1.1: The computing resources in the chip are finely granularly disassembled into independent computing units.

[0042] The computing units can be independently used to start, stop, and allocate resources, and after fine-granular disassembly, the computing resources can be dynamically combined at runtime.

[0043] Step S3.1.2: The storage resources in the chip are finely granularly disassembled into independent storage units.

[0044] The storage units can independently perform storage tasks, and each storage unit is configured with an independent priority control and bandwidth management module, and the storage resources in the chip can be flexibly allocated priority and bandwidth according to different task requirements.

[0045] Step S3.1.3: The communication resources in the chip are finely granularly disassembled into independent communication units.

[0046] The independent communication units can independently perform communication tasks, and each communication unit is provided with a dynamically configurable routing and bandwidth control module, and the communication resources in the chip can dynamically adjust their connection weights and bandwidth allocation according to the communication requirements of different tasks.

[0047] Preferably, the chip resources are dynamically allocated, and the implementation process is as follows:

[0048] Step S3.2.1: The local resource controller receives a resource configuration instruction.

[0049] The local resource controller receives the resource configuration instruction generated by the WLU unit in step S2, and the local resource controller adjusts and allocates the chip resources according to the specific resource configuration instruction.

[0050] Step S3.2.2: Chip resource allocation and adjustment.

[0051] When the computing resources required by the computing event increase, the computing resource increase instruction is executed, and the local resource controller allocates the computing units to the current computing event; when the computing resources required by the computing event decrease or are excessive, the computing resource decrease instruction is executed, and the local resource controller undoes the computing units from the current task and allocates them to other computing events or places them in an idle state.

[0052] When the storage resource required by the storage event increases, the storage bandwidth increase instruction is executed, and the local resource controller allocates the storage unit to the current storage event; when the storage resource required by the storage event decreases or is excessive, the storage bandwidth decrease instruction is executed, and the local resource controller allocates the storage unit occupied by the current storage event to other storage events or releases it;

[0053] When the communication resource required by the communication event increases, the interconnection communication unit bandwidth increase instruction is executed, and the local resource controller increases the interconnection communication unit bandwidth of the current storage event; when the communication resource required by the communication event decreases, the interconnection communication unit bandwidth decrease instruction is executed, and the local resource controller decreases the interconnection communication unit bandwidth of the current communication event.

[0054] Preferably, the WLU unit performs pattern recognition on the buffered local event, and the specific implementation process is as follows:

[0055] The WLU unit matches the event sequence in the event window with the pattern rule according to the predefined pattern rule; the parameters compared in the pattern matching process include the event type, the intensity, the time relationship, and the space relationship;

[0056] The predefined pattern rule includes a convolution calculation burst mode rule, a matrix multiplication bottleneck mode rule, a NoC congestion delay mode rule, a DMA data stream optimization mode rule, a high-priority preemption mode rule, and a task chain trigger mode rule.

[0057] Preferably, the resource requirement is predicted and output, and the specific implementation process is as follows:

[0058] After the local event and the pattern are matched successfully, the resource requirement of the local event is predicted and output according to the predefined resource prediction rule;

[0059] The predefined resource prediction rule includes a convolution calculation burst prediction rule, a matrix multiplication bottleneck prediction rule, a NoC congestion delay prediction rule, a DMA data stream optimization prediction rule, a high-priority preemption prediction rule, and a task chain trigger prediction rule.

[0060] Preferably, the resource configuration instruction includes a computing resource configuration instruction, a storage resource configuration instruction, and a communication resource configuration instruction.

[0061] The computing resource configuration instruction is used to execute the computing resource adjustment action of the chip; and the computing resource configuration instruction includes a computing resource increase instruction and a computing resource decrease instruction.

[0062] The storage resource configuration instruction is used to execute the storage resource adjustment action of the chip; and the storage resource configuration instruction includes a storage bandwidth increase instruction, a storage bandwidth decrease instruction, a storage unit access priority improvement instruction, and a storage unit access priority decrease instruction.

[0063] The communication resource configuration instruction is used to execute a communication resource adjustment action of the chip; the communication resource configuration instruction comprises an interconnection communication unit bandwidth increase instruction, an interconnection communication unit bandwidth decrease instruction, an interconnection communication unit priority improvement instruction, an interconnection communication unit priority decrease instruction, and a high-priority data stream channel establishment instruction.

[0064] Preferably, the revocation dynamic allocation instruction comprises a revocation computing resource configuration instruction, a revocation storage resource configuration instruction, and a revocation communication resource configuration instruction.

[0065] The revocation computing resource configuration instruction is used to execute a revocation computing resource adjustment action of the chip; the revocation computing resource configuration instruction comprises a revocation computing resource increase instruction and a revocation computing resource decrease instruction.

[0066] The revocation storage resource configuration instruction is used to execute a revocation storage resource adjustment action; the revocation storage resource configuration instruction comprises a revocation storage bandwidth increase instruction, a revocation storage bandwidth decrease instruction, a revocation storage unit access priority improvement instruction, and a revocation storage unit access priority decrease instruction.

[0067] The revocation communication resource configuration instruction is used to execute a revocation communication resource adjustment action; the revocation communication resource configuration instruction comprises a revocation interconnection communication unit bandwidth increase instruction, a revocation interconnection communication unit bandwidth decrease instruction, a revocation interconnection communication unit priority improvement instruction, a revocation interconnection communication unit priority decrease instruction, and a revocation high-priority data stream channel establishment instruction.

[0068] The technical solution of the present application has at least the following advantages and beneficial effects:

[0069] 1.The chip resource dynamic configuration method is disclosed for the real-time running of multi-modal AI tasks (such as target detection, speech recognition) on edge AI devices, which have the characteristics of burstiness, heterogeneity and conflicting resource requirements.

[0070] 2.The chip dynamic configuration operation in the present application is designed as short-acting (microsecond to millisecond level), and after the task load changes, the chip resources are quickly released or reallocated to avoid resource waste and reduce system power consumption, and maximize the use of chip resources. BRIEF DESCRIPTION OF DRAWINGS

[0071] Fig. 1 The chip resource dynamic configuration method of the present application is a general flowchart.

[0072] Fig. 2 The flowchart of the present application for analyzing the original event stream and predicting event requirements and generating resource configuration instructions.

[0073] Fig. 3 The chip resource dynamic allocation processing process flowchart of the present application is revoked. DETAILED DESCRIPTION

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the present application will be briefly introduced with reference to the drawings and embodiments or prior art descriptions. Obviously, the following description of the drawings structure is only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor. It should be noted that the description of these embodiments is used to help understand the present application, but does not constitute a limitation on the present application.

[0075] It should be understood that although the terms first, second, etc. can be used herein to describe various modules, these modules should not be limited by these terms. These terms are only used to distinguish one module from another. For example, a first module could be termed a second module, and, similarly, a second module could be termed a first module, without departing from the scope of example embodiments of the present application.

[0076] It should be understood that, for the term "and / or" which can occur in the present document, it only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, B alone, and A and B together; for the term " / " which can occur in the present document, it is used to describe another association object relationship, which means that there can be two relationships, for example, A / and B, which means that there are two cases of A alone and A and B together; in addition, for the character " / " which can occur in the present document, it generally means that the associated objects before and after are an "or" relationship.

[0077] Embodiment:

[0078] Please refer to Figs. 1-3 The present application provides a chip resource dynamic configuration method, which is applied to a chip with the following resource architecture:

[0079] The chip hardware bottom layer includes an instruction pipeline, a cache controller, a NoC router, and a task queue manager.

[0080] The instruction pipeline is used to divide the execution process of instructions into multiple continuous steps; the cache controller is used to manage data exchange between the cache and the main memory; the NoC router is used to process data transmission between the processor core and other modules in the chip system; and the task queue manager is used to manage the scheduling and execution sequence of tasks.

[0081] The event sensor in the present application is a hardware logic module, which is deployed in the chip hardware bottom layer, monitors and captures the occurrence of specific events in real time, and transmits the related information of these events to subsequent analysis and decision modules, thereby realizing resource dynamic configuration.

[0082] In the instruction pipeline, the event sensor is integrated at the operation unit interface of the instruction pipeline; in the cache controller, the event sensor is integrated on the address mapping circuit and the data exchange path; in the NoC router, the event sensor is integrated in the data buffer and the routing decision circuit of the NoC router; in the task queue manager, the event sensor is integrated in the scheduling control circuit and the queue state detection point, and collects task scheduling related events through read-only connection, and then transmits them to the WLU unit.

[0083] The internal structure of the chip hardware bottom layer instruction pipeline, the cache controller, the NoC router and the task queue manager is prior art, and the internal detailed circuit structure and principle of each resource module of the chip will not be described in the application.

[0084] The implementation includes the following steps:

[0085] Step S1: An event sensor detects and acquires a computing event, a storage event and a communication event of the chip in a task processing process.

[0086] Specifically, the computing event includes three event sub-classes of a multiply-add instruction burst signal, an NPU / DSP computing unit utilization rate instantaneous saturation / idle signal and a specific operator activation signal; the storage event includes three event sub-classes of a cache miss storm signal, a DRAM Bank conflict signal and a specific data stream access mode recognition signal; and the communication event includes two event sub-classes of a NoC link congestion / idle signal and a critical path delay threshold value signal. The computing event, the storage event and the communication event are collectively referred to as an original event stream.

[0087] Specifically, the acquisition of the original event stream is achieved by implanting an event sensor in the chip hardware bottom layer. The event sensor monitors the chip hardware bottom layer, and captures the computing event, the storage event and the communication event when they occur.

[0088] Specifically, the event sensor is deployed in the instruction pipeline of the chip to monitor the computing event such as the multiply-add instruction burst signal, the NPU / DSP computing unit utilization rate instantaneous saturation / idle signal and the specific operator activation signal; the event sensor is deployed in the cache controller to monitor the storage event such as the cache miss storm signal, the DRAM Bank conflict signal and the specific data stream access mode recognition signal; and the event sensor is deployed in the Noc router to monitor the communication event such as the NoC link congestion / idle signal and the critical path delay threshold value signal.

[0089] It should be noted that the event sensor is a hardware logic module for monitoring and capturing the occurrence of specific events in real time at the hardware bottom layer, and transmitting the related information of the events to a subsequent analysis and decision module, which is prior art. The operation of the event sensor does not affect the normal function of the hardware unit. The main focus of the application is to monitor and capture the computing event, the storage event and the communication event of the chip by using the event sensor, and then to dynamically configure the computing resource, the storage resource and the communication resource of the chip. The detailed working principle and the hardware design method of the chip bottom layer hardware are not described in detail here, which can be understood by those skilled in the art.

[0090] Specifically, a timestamp and spatial position information are added to each event to form an original event stream with space-time characteristics.

[0091] Specifically, the detection source of the computing event is an instruction pipeline, and the spatiotemporal coding mode is (x, y, t, intensity); the detection source of the storage event is a cache controller, and the spatiotemporal coding mode is (bank_id, t); and the detection source of the communication event is a NoC router, and the spatiotemporal coding mode is (routing coordinates, t).

[0092] Step S2: The event analysis unit analyzes and event demand predicts the computing event, the storage event and the communication event in step 1, and generates a resource configuration instruction.

[0093] In this step, the event analysis unit is deployed in the NPU computing cluster, the memory controller and the NoC node in the chip. The event analysis unit is deployed to quickly obtain and analyze the original event stream in step S1, reduce communication delay and ensure the real-time performance of analysis and decision-making. The event analysis unit is hereinafter referred to as a WLU unit.

[0094] It should be noted that the WLU unit is composed of a state machine and a lookup table, and does not depend on complex processors or software algorithms, thereby ensuring low power consumption and high efficiency. The state machine and the lookup table are prior art, and their design and working principle are not described here. The WLU unit is used for event stream analysis in the chip resource configuration method in the present application, and those skilled in the art can understand it.

[0095] Specifically, in the NPU computing cluster, the WLU unit is deployed in the inter-array routing channel, connected to the local MAC unit and the adjacent L2 Bank; for the memory controller, the WLU unit is deployed beside the Bank arbiter, connected to the local DRAM and the adjacent NoC node; and for the NoC router, the WLU unit is deployed in the crossbar control module, connected to the local VC queue and the adjacent computing cluster.

[0096] Specifically, the WLU unit is used to identify the types of original events and the resource scheduling demand mode corresponding to the demand from the input original event stream, and to generate a resource configuration instruction according to these modes.

[0097] It should be noted that the resource scheduling demand mode is proposed by analyzing the types of original event stream and resource demand, including a convolution computation burst mode, a matrix multiplication bottleneck mode, a NoC congestion delay mode, a DMA data stream optimization mode, a high-priority preemption mode and a task chain trigger mode.

[0098] Specifically, in step S2, the event analysis unit analyzes and event demand predicts the computing event, the storage event and the communication event in step 1 according to the following steps.

[0099] Step S2.1: The WLU unit receives the original event and performs spatiotemporal alignment and filtering processing on the original event.

[0100] Specifically, the WLU unit receives the original event stream in step S1, which is in 64-bit format and contains event type, intensity, timestamp, and spatial coordinates. After receiving the original event stream from different parts of the chip, the WLU unit eliminates the global clock offset of the chip according to the timestamp, with a synchronization accuracy of ±200 ps, and filters the original event stream according to the spatial coordinates, only receiving original events that match the location of the chip hardware resources directly managed by the current WLU unit. These original events are referred to as local events, and the WLU unit then outputs a local event stream with a unified time reference.

[0101] More specifically, WLU units deployed in different parts of the chip will filter out local events related to them from the original event stream based on their location and the resources they are responsible for. For example, WLU units deployed in NPU computing clusters filter events related to NPU computing clusters; WLU units deployed in memory controllers filter events related to memory controllers; and WLU units deployed in NoC routers filter local events related to memory controllers.

[0102] More specifically, if events in different domains of the chip use different clock domains, after the WLU unit filters out local events related to local resources, the WLU unit will align the events using different clock domains in time according to the event timestamps, ensuring that the local event stream has a unified time reference, facilitating subsequent event analysis and demand prediction.

[0103] Step S2.2: Cache local events in the recent time window.

[0104] Specifically, a recent time window is used to cache local events in the recent time window. The depth of the event window is determined by the maximum event rate and the window time. The event window is a hardware queue with storage function.

[0105] Specifically, the "recent time window" is a sliding time window, the length of which is set according to the running characteristics of the chip and actual demand, and as time goes on, the time window moves forward, new events enter the time window, and the earliest events gradually move out of the window. More specifically, when the size of the time window is set to 10 milliseconds, at any time, the time window contains events occurring in the past 10 milliseconds.

[0106] Step S2.3: The WLU unit matches the cached local events with pre-defined pattern rules to identify the specific resource scheduling demand pattern of the local events.

[0107] Specifically, the WLU unit matches the event sequence in the event window with the pattern rules according to the pre-defined pattern rules. The parameters compared in the pattern matching process include event type, intensity, time relationship, and spatial relationship.

[0108] Specifically, the predefined pattern rules include a convolution burst pattern rule, a matrix multiplication bottleneck pattern rule, a NoC congestion delay pattern rule, a DMA data flow optimization pattern rule, a high priority preemption pattern rule, and a task chain trigger pattern rule.

[0109] Step S2.4: predicting resources required by the local event according to the resource scheduling requirement pattern of the local event in step S2.3.

[0110] Specifically, after the local event and the pattern are matched successfully, the resource requirement of the local event is predicted according to the predefined resource prediction rule and output.

[0111] Specifically, the predefined resource prediction rule includes a convolution burst prediction rule, a matrix multiplication bottleneck prediction rule, a NoC congestion delay prediction rule, a DMA data flow optimization prediction rule, a high priority preemption prediction rule, and a task chain trigger prediction rule.

[0112] More specifically, when the local event matches the convolution burst pattern, the number of MAC units in the NPU calculation array needs to be increased based on the convolution burst prediction rule, and the access priority of the related cache Bank needs to be improved.

[0113] It should be noted that when the current task is a convolution layer calculation of a convolutional neural network, the task needs to perform a large number of matrix multiplication calculations. According to the size of the input feature map, the size and number of convolution kernels, the required calculation amount is estimated. Specifically, if the input feature map size is 28*28, the convolution kernel size is 3*3, and the number is 16, each MAC unit performs a multiplication and addition operation once per cycle, and the task needs to be completed within 100 cycles, 1204.8 MAC units are required, and after rounding up, it is predicted that 1205 MAC units need to be increased.

[0114] It should be noted that the resource prediction rule and the prediction process in the present application are based on the existing XGBoost machine learning model. The XGBoost machine learning model integrates multiple learners, has high accuracy and stability, can process large-scale data, and can mine the relationship between specific task features and resource requirements. The specific data input and model training process are prior art, which will not be described here.

[0115] More specifically, when the local event matches the matrix multiplication bottleneck pattern, the calculation resources allocated to the task need to be reduced based on the matrix multiplication bottleneck prediction rule, and the bandwidth of the cache Bank corresponding to the task needs to be reduced.

[0116] More specifically, when the local event matches the NoC congestion delay pattern, based on the NoC congestion delay prediction rule, it is predicted that additional NoC link bandwidth needs to be allocated for the high-priority data flow, and it is predicted that the weight of the crossbar connection on the communication path needs to be adjusted.

[0117] More specifically, when the local event matches the DMA data flow optimization pattern, based on the DMA data flow optimization prediction rule, it is predicted that the bandwidth allocation of the DMA channel needs to be adjusted, and for the continuous block access data flow, the bandwidth of the corresponding DMA channel needs to be increased.

[0118] More specifically, when the local event matches the high-priority preemption pattern, based on the high-priority preemption prediction rule, it is predicted that the computing resource needs to be preempted quickly, and it is predicted that the access priority of the storage resource related to the task needs to be improved.

[0119] More specifically, when the local event matches the task chain trigger pattern, based on the task chain trigger prediction rule, it is predicted that the computing resource needs to be reserved for the subsequent task, and it is predicted that the storage resource allocation needs to be adjusted.

[0120] Step S2.5: generating resource configuration instructions according to the resource requirements predicted in step S2.4.

[0121] It should be noted that the specific resource configuration instructions are described in detail in step S3, which will not be repeated here.

[0122] Step S2.6: distributing the resource configuration instructions to the local resource controller.

[0123] Specifically, the resource configuration instructions in step S2.5 are sent to the local resource controller.

[0124] Step S3: allocating the chip resources according to the resource configuration instructions in step S2.

[0125] In the present application, step S3 is implemented as follows:

[0126] Step S3.1: decomposing the computing resources, storage resources, and communication resources of the chip.

[0127] Specifically, in the present application, the resource decomposition processing is to decompose the chip hardware resources into more fine-grained and more flexible configurable units. After the chip resource decomposition processing, the chip is allowed to reconfigure and combine resources in a more flexible manner, so as to better adapt to the sudden task requirements.

[0128] Step S3.2: dynamic allocation of chip resources.

[0129] Specifically, the chip resource dynamic allocation is a process of instantaneously adjusting the configuration of hardware resources according to real-time event task requirements and system states by executing resource configuration instructions. The chip resource dynamic configuration is a dynamic and fine-grained resource management mechanism, which can quickly respond to changes in task load by dynamically allocating chip resources, and ensure efficient use of resources and smooth execution of tasks.

[0130] In the present application, the decomposition processing of the computing resources, storage resources and communication resources of the chip in step S3.1 is implemented according to the following steps:

[0131] Step S3.1.1: Fine-grained disassembly of computing resources in the chip into independent computing units.

[0132] Specifically, the computing units disassembled in step S3.1.1 can be independently used for starting, stopping and resource allocation. After fine-grained disassembly, the computing resources can be dynamically combined at runtime.

[0133] More specifically, in the hardware design phase, the computing resources in the chip, including the NPU computing array, are designed as a combination of multiple independent MAC units, each independent MAC unit has its independent control logic and data path, and can independently perform computing tasks, and each MAC unit can be combined, two MAC units form a computing unit with greater computing power, thereby realizing flexible deployment of computing resources.

[0134] More specifically, when a task needs more computing power, multiple idle MAC units can be temporarily deployed to the computing array of the task, and after the task is completed, these MAC units are released or reallocated to other tasks.

[0135] More specifically, the computing resources in the chip include each CPU core, NPU computing array, DSP processing module, etc.

[0136] Step S3.1.2: Fine-grained disassembly of storage resources in the chip into independent storage units.

[0137] Specifically, the storage units disassembled in step S3.1.2 can independently perform storage tasks, and each storage unit is configured with an independent priority control and bandwidth management module, so that the storage resources in the chip can be flexibly allocated priority and bandwidth according to different task requirements.

[0138] More specifically, when a task frequently causes cache misses, the priority of the cache Bank corresponding to the task can be temporarily increased, or a part of the storage area is reallocated to other tasks.

[0139] More specifically, the storage resources in the chip include SRAM, DRAM controller channels, on-chip network buffers, etc.

[0140] Step S3.1.3: Fine-grained decomposition of communication resources in the chip into independent communication units.

[0141] Specifically, the independent communication units decomposed in step S3.1.3 can independently perform communication tasks, and each communication unit is provided with a dynamically configurable routing and bandwidth control module, so that the communication resources in the chip can dynamically adjust their connection weights and bandwidth allocation according to the communication requirements of different tasks.

[0142] More specifically, when the communication path of a task is congested, the bandwidth of the path can be temporarily adjusted, or the connection weight between the communication units is adjusted to establish a direct channel for high-priority data flow.

[0143] More specifically, the communication resources in the chip include the routing paths of NoC, crossbar connections, and DMA channels.

[0144] In the present application, the step S3.2 of dynamic allocation of chip resources is implemented according to the following steps:

[0145] Step S3.2.1: The local resource controller receives resource configuration instructions;

[0146] Specifically, the local resource controller receives the resource configuration instructions generated by the WLU unit in step S2. The local resource controller adjusts and allocates the chip resources according to the specific resource configuration instructions. The local resource controller includes NPU cluster controllers, Cache Bank controllers, and NoC routers.

[0147] Specifically, the resource configuration instructions include computing resource configuration instructions, storage resource configuration instructions, and communication resource configuration instructions.

[0148] More specifically, the computing resource configuration instructions are used to perform the computing resource adjustment action of the chip. After receiving the computing resource configuration instructions, the local resource controller increases or decreases the computing units allocated to a specific task. The computing resource configuration instructions include computing resource increase instructions and computing resource decrease instructions.

[0149] More specifically, the storage resource configuration instructions are used to perform the storage resource adjustment action of the chip. After receiving the storage resource configuration instructions, the local resource controller increases or decreases the storage bandwidth allocated to a specific task, and increases or decreases the access priority of the storage unit of the storage event. The storage resource configuration instructions include storage bandwidth increase instructions, storage bandwidth decrease instructions, storage unit access priority increase instructions, and storage unit access priority decrease instructions.

[0150] More specifically, the communication resource configuration instruction is used to execute the communication resource adjustment action of the chip. After receiving the communication resource configuration instruction, the local resource controller adjusts the bandwidth allocation and priority of the interconnection communication unit, and establishes a direct communication channel for the high-priority data stream to bypass the congested general communication path. The communication resource configuration instruction includes an interconnection communication unit bandwidth increase instruction, an interconnection communication unit bandwidth decrease instruction, an interconnection communication unit priority increase instruction, an interconnection communication unit priority decrease instruction, and a high-priority data stream channel establishment instruction.

[0151] Step S3.2.2: Chip resource allocation and adjustment.

[0152] Specifically, when the required computing resource of a computing event increases, the computing resource increase instruction is executed, and the local resource controller allocates a computing unit to the current computing event; when the required computing resource of a computing event decreases or is excessive, the computing resource decrease instruction is executed, and the local resource controller removes the computing unit from the current task and allocates it to other computing events or places it in an idle state.

[0153] More specifically, the computing unit includes a MAC unit in an NPU computing array and part of the ALU resource of a CPU core; and the computing event with a change in required computing resource includes a burst convolution and a burst filtering computation.

[0154] Specifically, when the required storage resource of a storage event increases, the storage bandwidth increase instruction is executed, and the local resource controller allocates a storage unit to the current storage event; when the required storage resource of a storage event decreases or is excessive, the storage bandwidth decrease instruction is executed, and the local resource controller allocates the storage unit occupied by the current storage event to other storage events or releases it; when the execution priority of a storage event is increased, the local resource controller executes the storage unit access priority increase instruction to increase the storage unit access priority of the event; and when the execution priority of a storage event is decreased, the local resource controller executes the storage unit access priority decrease instruction to decrease the storage unit access priority of the event.

[0155] More specifically, the storage unit includes a cache unit, an on-chip storage unit, a DRAM unit, and a network buffer unit; and the storage event with a change in required storage resource includes a cache miss event, a DRAM access conflict event, a data stream access mode change event, a high-priority task storage demand event, an on-chip network congestion relief event, and a storage resource utilization rate too low event.

[0156] Specifically, when the required communication resource of a communication event increases, the interconnect communication unit bandwidth increase instruction is executed, and the local resource controller increases the interconnect communication unit bandwidth of the current communication event; when the required communication resource of a communication event decreases, the interconnect communication unit bandwidth decrease instruction is executed, and the local resource controller decreases the interconnect communication unit bandwidth of the current communication event; when the execution priority of a communication event increases, the interconnect communication unit priority increase instruction is executed, and the local resource controller increases the interconnect communication unit priority of the current communication event; when the execution priority of a communication event decreases, the interconnect communication unit priority decrease instruction is executed, and the local resource controller decreases the interconnect communication unit priority of the current communication event.

[0157] More specifically, the communication resource includes a network-on-chip unit, a direct memory access unit, a DMA channel, and a crossbar connection unit; and the communication event in which the required communication resource changes includes a NoC link congestion event, a critical communication path delay event, a communication bandwidth demand surge event, a DMA transmission queue congestion event, an inter-task communication priority change event, and a sensor data stream surge event.

[0158] Step S4: After the chip resources are allocated in real time, the dynamic allocation of the chip resources is revoked.

[0159] In the present application, the chip resource dynamic allocation operation is designed to be short-acting (microsecond to millisecond level), aiming to correspond to burst load. The purpose of the dynamic allocation revocation operation is to quickly release or reallocate the chip resources after the task load changes, so as to avoid resource waste and reduce system power consumption. The specific execution steps are as follows:

[0160] Step S4.1: Revoking the dynamic allocation trigger condition monitoring.

[0161] Specifically, the WLU unit continuously monitors the original event stream from the hardware bottom layer, including the real-time state of the computing event, the storage event and the communication event.

[0162] Specifically, the dynamic allocation revocation trigger condition includes the end of a burst instruction stream, a decrease in cache miss rate, completion of a high-priority task, and relief of communication path congestion.

[0163] Step S4.2: Generating a dynamic allocation revocation instruction.

[0164] Specifically, the dynamic allocation revocation instruction includes a computing resource configuration revocation instruction, a storage resource configuration revocation instruction, and a communication resource configuration revocation instruction.

[0165] More specifically, the undo computing resource configuration instruction is used to execute the undo computing resource adjustment action of the chip. After the local resource controller receives the undo computing resource configuration instruction, the operation of increasing or decreasing the computing resource allocated to the specific task computing unit is undone. The undo computing resource configuration instruction includes an undo computing resource increase instruction, an undo computing resource decrease instruction.

[0166] More specifically, the undo storage resource configuration instruction is used to undo the storage resource adjustment operation. After the local resource controller receives the undo storage resource configuration instruction, the operation of increasing or decreasing the storage bandwidth allocated to the specific task is undone. The undo storage resource configuration instruction includes an undo storage bandwidth increase instruction, an undo storage bandwidth decrease instruction, an undo storage unit access priority increase instruction, and an undo storage unit access priority decrease instruction.

[0167] More specifically, the undo communication resource configuration instruction is used to undo the communication resource adjustment operation. After the local resource controller receives the undo communication resource configuration instruction, the operation of adjusting the bandwidth allocation and priority of the interconnection communication unit is undone, and the operation of establishing a direct communication channel for a high-priority data stream is undone. The undo communication resource configuration instruction includes an undo interconnection communication unit bandwidth increase instruction, an undo interconnection communication unit bandwidth decrease instruction, an undo interconnection communication unit priority increase instruction, an undo interconnection communication unit priority decrease instruction, and an undo high-priority data stream channel establishment instruction.

[0168] Step S4.3: Execute the undo dynamic allocation instruction operation.

[0169] Specifically, after the local resource controller receives the undo dynamic allocation instruction in step S4.2, the local resource controller executes the corresponding undo dynamic allocation operation.

[0170] Specifically, when the computing resource required by the computing event is decreased or excessive, the undo computing resource increase instruction is executed; when the computing resource required by the computing event is increased, the undo computing resource decrease instruction is executed.

[0171] Specifically, when the storage resource required by the storage event is decreased or excessive, the undo storage bandwidth increase instruction is executed; when the storage resource required by the storage event is increased, the undo storage bandwidth decrease instruction is executed; when the execution priority of a certain storage event is decreased, the local resource controller executes the undo storage unit access priority increase instruction; when the execution priority of a certain storage event is increased, the local resource controller executes the undo storage unit access priority decrease instruction.

[0172] Specifically, when the communication resource required by the communication event is reduced or excessive, the interconnection communication unit bandwidth increase instruction is executed; when the communication resource required by the communication event is increased, the interconnection communication unit bandwidth decrease instruction is executed; when the execution priority of a certain communication event is reduced, the interconnection communication unit priority increase instruction is executed; when the execution priority of a certain communication event is increased, the interconnection communication unit priority decrease instruction is executed.

[0173] Step S4.4: chip resource state feedback

[0174] Specifically, the local resource controller feeds back the current state of the chip resource to the WLU unit in real time after executing the dynamic allocation cancellation instruction operation.

[0175] Finally, it should be noted that: the above only for the preferred embodiments of the present application, and not for limiting the scope of protection of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application, should be included within the scope of protection of the present application.

Claims

1. A method for dynamic allocation of chip resources, characterized in that, The implementation process is as follows: Step S1: The event sensor detects and acquires computational events, storage events, and communication events of the chip during task processing; The computation events include three subcategories: multiply-accumulate instruction burst signals, instantaneous saturation / idle signals of NPU / DSP computing unit utilization, and specific operator activation signals; the storage events include three subcategories: cache miss storm signals, DRAM bank conflict signals, and specific data stream access pattern recognition signals; the communication events include two subcategories: NoC link congestion / idle signals and critical path delay exceeding threshold signals; the computation events, storage events, and communication events are referred to as the raw event stream; Step S2: The event parsing unit parses the computation events, storage events, and communication events in Step 1 and predicts event requirements, and generates resource configuration instructions; The event parsing unit consists of a state machine and a lookup table, and the event parsing unit is deployed in the NPU computing cluster, memory controller, and Noc node in the chip. The event parsing unit identifies the resource scheduling demand pattern of the original event and predicts the resource demand of the original event based on the resource scheduling demand pattern; the resource scheduling demand pattern includes convolution calculation burst mode, matrix multiplication bottleneck mode, NoC congestion delay mode, DMA data flow optimization mode, high priority preemption mode, and task chain triggering mode. Step S3: Allocate chip resources in real time according to the resource configuration instructions in step S2; In this step, the chip's computing, storage, and communication resources are broken down into independent computing units, independent storage units, and independent communication units, and the chip resources are allocated and adjusted according to the resource configuration instructions in step S2; specifically: Step S3.1.1: Decompose the computing resources in the chip into independent computing units with fine granularity; Computing units can be used independently for startup, shutdown, and resource allocation. Through fine-grained decomposition, computing resources can be dynamically combined at runtime. Step S3.1.2: Decompose the storage resources in the chip into independent storage units in a fine-grained manner; The storage unit can independently perform storage tasks. Each storage unit is equipped with an independent priority control and bandwidth management module. The storage resources in the chip can be flexibly allocated in terms of priority and bandwidth according to different task requirements. Step S3.1.3: Decompose the communication resources in the chip into independent communication units in a fine-grained manner; Independent communication units can perform communication tasks independently. Each communication unit is provided with a dynamically configurable routing and bandwidth control module. The communication resources in the chip can dynamically adjust their connection weights and bandwidth allocation according to the communication requirements of different tasks. Step S4: After real-time allocation of chip resources, cancel the dynamic allocation of chip resources; In this step, the event parsing unit continuously monitors the real-time status of the original event stream. When the trigger condition for canceling dynamic allocation is detected, a cancel dynamic allocation instruction is generated and executed to release the chip resources allocated in step S3.

2. The method for dynamic allocation of chip resources according to claim 1, characterized in that, The event parsing unit parses the raw event stream and predicts event demand. Its implementation process is as follows: Step S2.1: The WLU unit receives the raw event and performs spatiotemporal alignment and filtering on the raw event; The WLU unit receives the raw event stream from step S1. The raw event stream is in 64-bit format and includes event type, intensity, timestamp, and spatial coordinates. After receiving the raw event streams from different parts of the chip, the WLU unit eliminates the chip's global clock offset based on the timestamp, achieving a synchronization accuracy of ±200ps. It also filters the raw event streams based on the spatial coordinates, only receiving raw events that match the location of the chip hardware resources directly managed by the current WLU unit. These raw events are called local events, and the WLU unit then outputs a local event stream with a unified time base. Step S2.2: The event window caches local events from the most recent period; A local event window is used to cache events within a recent period. The depth of the event window is determined by the maximum event rate and the window time. The event window is a hardware queue with storage capabilities. Step S2.3: The WLU unit matches the cached local events with predefined pattern rules to identify the specific resource scheduling requirement pattern of the local events; Step S2.4: Based on the resource scheduling requirement pattern of the local event in step S2.3, predict the resources required for the execution of the local event; Step S2.5: Generate resource configuration instructions based on the resource requirements predicted in step S2.4; Step S2.6: Distribute the resource configuration instructions to the local resource controller.

3. The method for dynamic allocation of chip resources according to claim 1, characterized in that, According to the resource configuration instructions in step S2, chip resources are allocated in real time. The implementation process is as follows: Step S3.1: Decompose the chip's computing resources, storage resources, and communication resources; Decompose computing resources into independent computing units; decompose storage resources into independent storage units; decompose communication resources into independent communication units; Step S3.2: Dynamic allocation of chip resources; Based on real-time event resource requirements and system status, the configuration of hardware resources is adjusted in real time by executing resource configuration commands.

4. The method for dynamic allocation of chip resources according to claim 1, characterized in that, The process of revoking the dynamic allocation of chip resources is as follows: Step S4.1: Cancel dynamic allocation trigger condition monitoring; The conditions for revoking dynamic allocation include the end of a sudden instruction stream, a decrease in cache miss rate, completion of high-priority tasks, and relief of communication path congestion; Step S4.2: Generate a command to cancel dynamic allocation; Revoking dynamic allocation instructions includes revoking computing resource configuration instructions, revoking storage resource configuration instructions, and revoking communication resource configuration instructions. Step S4.3: Execute the operation to cancel the dynamic allocation instruction; After receiving the revoked dynamic allocation instruction in step S4.2, the local resource controller executes the corresponding revoked dynamic allocation operation. Step S4.4: Chip resource status feedback; After executing the command to revoke dynamic allocation, the local resource controller feeds back the current status of chip resources to the WLU unit in real time.

5. The method for dynamic allocation of chip resources according to claim 3, characterized in that, The dynamic allocation of chip resources is implemented as follows: Step S3.2.1: The local resource controller receives the resource configuration instruction; The local resource controller receives the resource configuration instruction generated by the WLU unit in step S2, and performs chip resource adjustment and allocation actions according to the specific resource configuration instruction. Step S3.2.2: Chip resource allocation and adjustment; When the computing resources required for a computing event increase, a computing resource increase instruction is executed, and the local resource controller allocates computing units to the current computing event; when the computing resources required for a computing event decrease or become excessive, a computing resource decrease instruction is executed, and the local resource controller removes the computing units from the current task and allocates them to other computing events or sets them to an idle state. When the storage resources required by a storage event increase, a storage bandwidth increase instruction is executed, and the local resource controller allocates storage units to the current storage event; when the storage resources required by a storage event decrease or become excessive, a storage bandwidth decrease instruction is executed, and the local resource controller allocates the storage units occupied by the current storage event to other storage events or releases them. When the communication resources required for a communication event increase, an instruction to increase the bandwidth of the interconnect communication unit is executed, and the local resource controller increases the bandwidth of the interconnect communication unit for the current stored event; when the communication resources required for a communication event decrease, an instruction to decrease the bandwidth of the interconnect communication unit is executed, and the local resource controller decreases the bandwidth of the interconnect communication unit for the current communication event.

6. The method for dynamic allocation of chip resources according to claim 2, characterized in that, The WLU unit performs pattern recognition on cached local events, and its specific implementation process is as follows: The WLU unit matches the event sequence in the event window with the predefined pattern rules; the parameters compared during the pattern matching process include event type, intensity, temporal relationship, and spatial relationship. The predefined pattern rules include convolution calculation burst pattern rules, matrix multiplication bottleneck pattern rules, NoC congestion delay pattern rules, DMA data flow optimization pattern rules, high priority preemption pattern rules, and task chain triggering pattern rules.

7. The method for dynamic allocation of chip resources according to claim 2, characterized in that, The specific implementation process of predicting and outputting resource requirements is as follows: After a local event and pattern match is successful, the resource requirements of the local event are predicted and output according to the predefined resource prediction rules. The predefined resource prediction rules include convolution calculation burst prediction rules, matrix multiplication bottleneck prediction rules, NoC congestion delay prediction rules, DMA data flow optimization prediction rules, high-priority preemption prediction rules, and task chain triggering prediction rules.

8. The method for dynamic allocation of chip resources according to claim 2, characterized in that, The resource configuration instructions include computing resource configuration instructions, storage resource configuration instructions, and communication resource configuration instructions. The computing resource configuration instructions are used to perform computing resource adjustment actions on the chip; the computing resource configuration instructions include computing resource increase instructions and computing resource decrease instructions; The storage resource configuration instructions are used to perform storage resource adjustment actions on the chip; the storage resource configuration instructions include storage bandwidth increase instructions, storage bandwidth decrease instructions, storage cell access priority increase instructions, and storage cell access priority decrease instructions; The communication resource configuration instructions are used to perform communication resource adjustment actions of the chip; the communication resource configuration instructions include instructions to increase the bandwidth of interconnect communication units, instructions to decrease the bandwidth of interconnect communication units, instructions to increase the priority of interconnect communication units, instructions to decrease the priority of interconnect communication units, and instructions to establish a high-priority data flow channel.

9. A method for dynamic allocation of chip resources according to claim 4, characterized in that, The revocation dynamic allocation instruction includes the revocation of computing resource configuration instruction, the revocation of storage resource configuration instruction, and the revocation of communication resource configuration instruction; The command to cancel the configuration of computing resources is used to execute the action of canceling the adjustment of computing resources in the chip; The command to cancel the configuration of computing resources includes commands to cancel the addition of computing resources and commands to cancel the reduction of computing resources. The command to cancel storage resource configuration is used to cancel storage resource adjustment operations; the command to cancel storage resource configuration includes commands to cancel storage bandwidth increase, storage bandwidth decrease, storage unit access priority increase, and storage unit access priority decrease. The command to cancel communication resource configuration is used to cancel communication resource adjustment operations; the command to cancel communication resource configuration includes canceling the command to increase the bandwidth of interconnected communication units, canceling the command to decrease the bandwidth of interconnected communication units, canceling the command to increase the priority of interconnected communication units, canceling the command to decrease the priority of interconnected communication units, and canceling the command to establish a high-priority data flow channel.

Images