Communication method and apparatus

Abstract

A communication method applied to a bus network, the method comprising: a network management unit sending a request message to a bus device, the request message being used to request access to a first configuration space register of the bus device, the request message comprising a network address of the bus device, first indication information and information of the first configuration space register, the network address being an address allocated to the bus device by the network management unit, the first indication information being used to indicate an operation type of the first configuration space register, and the network management unit receiving a response message from the bus device in response to the request message. Access to the configuration space register of the bus device is realized through the network address of the bus device and the information of the configuration space register, thereby avoiding the problem of high latency requirement caused by the memory address access mode.

Description

Technical Field

[0001] This application relates to the field of information technology, and in particular to a communication method and apparatus. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect processors and external devices, which are called PCIe devices.

[0003] Generally, the PCIe protocol uses a 32-bit PCIe identifier (ID) to identify PCIe devices in the system. This 32-bit identifier includes: a 16-bit domain, an 8-bit bus, a 5-bit device, and a 3-bit function. The 8-bit bus ID, 5-bit device ID, and 3-bit function ID are collectively referred to as BDF (BDF stands for Bus Device Function). The Bus ID provides 256 bus numbers for each PCIe domain. Typically, a computer system supports one PCIe domain, meaning the entire computer system provides 256 bus numbers.

[0004] Specifically, there are generally two ways to access the configuration space registers of a PCIe device: memory access and input / output (I / O) access. I / O access can be simply understood as the user accessing the PCIe device's configuration space registers through input or output (IN / OUT) instructions. Specifically, the first 256 bytes of the PCIe device can be accessed through I / O ports. Memory access maps the entire PCIe device configuration space into memory. After determining the device's memory address, the PCIe device's configuration space registers can be accessed through memory read / write operations.

[0005] When accessing the configuration space registers of a bus device (e.g., a PCIe device) via memory access, the processor waits after the access instruction is issued, which imposes constraints on access latency and prevents cross-host access to configuration space registers. Therefore, improving the performance of accessing the configuration space registers of bus devices has become a pressing issue. Summary of the Invention

[0006] This application provides a communication method that aims to access the configuration space register of a bus device by using the network address of the bus device and the information of the configuration space register, thereby avoiding the problems caused by the memory address access method.

[0007] Firstly, a communication method is provided for use in a bus network. This method can be executed by a network management unit, or by a circuit or chip configured within the network management unit; this application does not limit the scope of the method.

[0008] The communication method includes: sending a request message to a bus device, the request message being used to request access to a first configuration space register of the bus device, the request message including the network address of the bus device, first indication information and information of the first configuration space register, the network address being an address assigned to the bus device by a network management unit, the first indication information being used to indicate the operation type of the first configuration space register; and receiving a response message from the bus device in response to the request message.

[0009] Based on the above technical solution, when the network management unit needs to access the configuration space register of a bus device, it can do so by including the network address of the bus device and the information of the configuration space register to be accessed in the request message. This eliminates the need for memory read / write operations. Therefore, the method of accessing the configuration space register of a bus device via a request message, provided by this technical solution, avoids the high latency requirements and inability to access across hosts associated with memory read / write methods.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the request message further includes a task identifier, and the response message includes the task identifier, which is used to determine that the response message is a message in response to the request message.

[0011] Based on the above technical solution, the request message issued by the network management unit carries a task identifier, so that when the bus device responds to the request message, the response message also carries the task identifier, indicating that the response message is a response to a certain request message, thereby enabling the network management unit to clearly know the response message corresponding to the request message based on the task identifier.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the operation type of the first configuration space register includes: a read operation or a write operation.

[0013] Based on the above technical solution, the network management unit can read or write the configuration space register of the bus device, which improves the flexibility of the solution and enriches the application scenarios of the solution.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, if the operation type of the first configuration space register is a write operation, the request message also includes the data to be written to the first configuration space register.

[0015] Based on the above technical solution, when the network management unit performs a write operation on the configuration space register of the bus device, the network management unit can carry the data to be written to the configuration space register of the bus device in the request message to realize the write operation. The write operation can be realized with a single request message, without the need to transmit the data to be written separately, thus saving signaling overhead.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the request message further includes second indication information, which is used to indicate that the data be written into at least one byte in the first configuration space register.

[0017] Based on the above technical solution, when the network management unit performs a write operation on the configuration space register of the bus device, the network management unit can notify the bus device through the second indication information that the data to be written can be written into a portion of the bytes in the configuration space register of the bus device.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the information of the first configuration space register includes at least one of the following: the type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the response message is used to indicate whether the operation on the first configuration space register was successful; or, if the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the response message further includes information indicating whether the response message is in response to a read operation or a write operation. The request message is also used to request access to a second configuration space register of the bus device, and the request message further includes third indication information and information about the second configuration space register, the third indication information indicating the type of operation on the second configuration space register.

[0021] Based on the above technical solution, the network management unit can access multiple configuration space registers of the bus device through a single message, thereby improving access efficiency.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the bus network includes a network management unit and multiple bus devices, wherein the bus device is any one of the multiple bus devices.

[0023] Secondly, a communication method is provided, applied to a bus device. This method can be executed by the bus device itself, or by circuitry configured within the bus device; this application does not limit the scope of the method.

[0024] The communication method includes: receiving a request message from a network management unit, the request message being used to request access to a first configuration space register of a bus device, the request message including a network address of the bus device, first indication information and information of the first configuration space register, the network address being an address assigned to the bus device by the network management unit, the first indication information being used to indicate the operation type of the first configuration space register; and sending a response message to the network management unit in response to the request message.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, the request message further includes a task identifier, and the response message includes the task identifier, which is used to determine that the response message is a message in response to the request message.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, the operation type of the first configuration space register includes: a read operation or a write operation.

[0027] In conjunction with the second aspect, in some implementations of the second aspect, if the operation type of the first configuration space register is a write operation, the request message also includes the data to be written to the first configuration space register.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the request message further includes second indication information, which is used to indicate that the data be written into at least one byte in the first configuration space register.

[0029] In conjunction with the second aspect, in some implementations of the second aspect, the information of the first configuration space register includes at least one of the following: the type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, the response message is used to indicate whether the operation on the first configuration space register was successful; or, if the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

[0031] In conjunction with the second aspect, in some implementations of the second aspect, the response message also includes information indicating that the response message is in response to a read operation or a write operation.

[0032] In conjunction with the second aspect, in some implementations of the second aspect, the request message is further used to request access to the second configuration space register of the bus device, and the request message also includes third indication information and information of the second configuration space register, the third indication information being used to indicate the operation type of the second configuration space register.

[0033] In conjunction with the second aspect, in some implementations of the second aspect, the bus network includes the network management unit and a plurality of bus devices, wherein the bus device is any one of the plurality of bus devices.

[0034] The technical effects of the methods shown in the second aspect and its possible designs above can be referred to the technical effects in the first aspect and its possible designs.

[0035] Thirdly, a communication device is provided, comprising: a storage module for storing a program; and a processing module for executing the program stored in the storage module, wherein when the program stored in the storage module is executed, the processing module executes the methods provided in the above aspects.

[0036] Fourthly, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing the methods provided in the above aspects.

[0037] Fifthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the methods provided in the above aspects.

[0038] In a sixth aspect, a chip is provided, the chip including a processing module and a communication interface, the processing module reading instructions stored in a memory through the communication interface for executing the methods provided in the above aspects.

[0039] Optionally, as one implementation, the chip may further include a storage module storing instructions, and the processing module is used to execute the instructions stored in the storage module. When the instructions are executed, the processing module is used to perform the methods provided in the above aspects.

[0040] In a seventh aspect, a chip is provided, the chip including a network management unit for performing the method provided in the first aspect and a bus device for performing the method provided in the second aspect.

[0041] Eighthly, a computer system is provided, the computer system including the chip shown in the seventh aspect.

[0042] Ninthly, a terminal device is provided, which includes the chip shown in the seventh aspect. For example, the terminal device includes, but is not limited to, mobile phones, vehicles, and other terminals.

[0043] In a tenth aspect, a system for accessing a configuration space is provided, the system comprising a network management unit for performing the method provided in the first aspect and a bus device for performing the method provided in the second aspect. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of a computer system provided in an embodiment of this application.

[0045] Figure 2 This is a schematic diagram of a data center provided in an embodiment of this application.

[0046] Figure 3 This is a schematic diagram of a general bus protocol message format provided in an embodiment of this application.

[0047] Figure 4 This is a schematic diagram of the structure of a host provided in an embodiment of this application.

[0048] Figure 5 This is a schematic diagram of bus number allocation in a PCIe system.

[0049] Figure 6 This is a schematic diagram of the device configuration space register provided in an embodiment of this application.

[0050] Figure 7 (a) is a schematic diagram of the device configuration space register address provided in the embodiment of this application.

[0051] Figure 7 (b) is a schematic diagram of the bus network provided in the embodiments of this application.

[0052] Figure 8 This is a schematic flowchart of a communication method provided in this application.

[0053] Figure 9 This is a schematic diagram of a transaction layer message provided in this application.

[0054] Figure 10 This is a schematic diagram of a message header for a transaction layer message provided in this application.

[0055] Figure 11 This is a schematic diagram of the payload portion of a request message provided in this application.

[0056] Figure 12This is a schematic diagram of the payload portion of a response message provided in this application.

[0057] Figure 13 A schematic diagram of the structure of a communication device 1300 provided in an embodiment of this application is shown.

[0058] Figure 14 A schematic diagram of the structure of a chip system 1400 provided in an embodiment of this application is shown.

[0059] Figure 15 A conceptual partial view of a computer program product provided in an embodiment of this application is shown schematically. Detailed Implementation

[0060] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0061] This application relates to the configuration space of a processor in a computer system accessing an external device. The computer system can be a server or a terminal. Terminals include, but are not limited to, user systems such as desktop computers, laptops, and smartphones. For ease of understanding, the structure of a computer system is described below.

[0062] See Figure 1 The schematic diagram of the computer system shown includes a processor 101, an input / output device (I / O device) 102, memory 103, cache 104, a memory management unit (MMU) 105, an input / output memory management unit (IOMMU) 106, external storage 107, and a bus 108.

[0063] Processor 101 includes at least one core. This core is also called a computing engine. Each core can execute tasks independently. When processor 101 includes multiple cores, tasks from applications can be divided, allowing applications to fully utilize multiple cores and execute more tasks within a given time. In this embodiment, processor 101 can be a main processor, such as a Central Processing Unit (CPU).

[0064] Input / output device 102 refers to a hardware device capable of inputting and / or outputting data. Input / output device 102 can be divided into input devices and output devices. Input devices may include devices such as a mouse, keyboard, joystick, stylus, and microphone, while output devices may include devices such as a monitor and speakers.

[0065] Memory 103, also known as internal memory or main memory, is used to temporarily store the data processed by the processor 101. Furthermore, memory 103 is also used to temporarily store data exchanged with secondary memory 107. Memory 103 can typically be implemented using storage media such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0066] Cache 104 (in this embodiment, it refers to the processor cache, such as the CPU cache) is a component used to reduce the average time required for the processor 101 to access memory 103. See also Figure 1 In the pyramid-shaped memory architecture, cache 104 is located in the second layer from the top, second only to the registers of processor 101. Figure 1 (Not shown in the image), above memory 103 (memory 103 is located in the third layer from top to bottom). Typically, the capacity of cache 104 is much smaller than that of memory 103, but its access speed can approach the frequency of processor 101.

[0067] The memory management unit 105 is a type of computer hardware used to process data access requests. Specifically, the memory management unit 105 maps virtual addresses (VAs) in data access requests. Specifically, the memory management unit 105 can intercept data access requests issued by the processor 101's core and map (or translate) the virtual addresses in the data access requests into physical addresses (PAs), so that memory 103 can be accessed based on those physical addresses.

[0068] The input / output memory management unit 106 is essentially a memory management unit. Similar to the memory management unit 105, which maps the virtual address visible to the processor 101 to the physical address, the input / output memory management unit 106 is used to map the virtual address (also called the device address or I / O address) visible to the input / output device 102 to the physical address.

[0069] Secondary storage 107, also known as external memory or secondary storage, is typically used for persistent data storage. For example, secondary storage 107 can persistently store computational data from processor 101. Even in the event of a power failure, data already written to secondary storage 107 can still be preserved, preventing data loss. In specific implementations, secondary storage 107 includes at least one non-volatile memory 1071. When secondary storage includes multiple non-volatile memories, these memories can be of the same type or different types. For example, in... Figure 1In the example, external storage 107 may include two types of non-volatile memory, such as storage class memory (SCM) and solid state drive (SSD).

[0070] Bus 108 is used to connect the various functional components of a computer system. Bus 108 is the common communication trunk for transmitting information between the various functional components of the computer system. Bus 108 can be a transmission line bundle formed by wires. Depending on the objects being connected, bus 108 can also be divided into internal bus and external bus.

[0071] The internal bus uses an internal bus protocol to transmit information. The internal bus protocol includes a bus protocol for accessing the computer system's memory space. The external bus uses an external bus protocol to transmit information. The external bus protocol includes a bus protocol for accessing the computer system's external storage space. Here, memory space refers to the address space of main memory, and external storage space refers to the address space of secondary storage.

[0072] In some embodiments, the internal bus protocol includes, but is not limited to, the Peripheral Component Interconnect (PCI) bus, the PCI Express (PCIe) protocol, the Intel™ Quick Path Interconnect (QPI) protocol, and the Universal Bus protocol. The external bus protocol includes, but is not limited to, the Small Computer System Interface (SCSI) protocol or the Serial Attached SCSI (SAS) protocol.

[0073] It should be noted that, Figure 1 The computer system shown is illustrated using external memory 107 as a remote external memory. Figure 1 As shown, external storage 107 includes a network interface card (NIC) 1072. This NIC 1072 can be, for example, a smart NIC (network interface card) (i.e., a network adapter card). External storage 107 accesses the network through this NIC 1072, and then connects to other components of the computer system 101 via the network. The network can be a wired communication network, such as a fiber optic communication network, or a wireless communication network, such as a wireless local area network (WLAN) or a fifth-generation (5G) mobile communication network.

[0074] In some possible implementations, the computer system's external storage 107 can also be local external storage, and other components of the computer system, such as the processor 101, can be connected to the aforementioned local external storage via bus 108. In other possible implementations, the computer system can include both remote external storage and local external storage. Furthermore, the embodiments of this application can be applied to centralized storage or distributed storage scenarios, and this embodiment does not limit them.

[0075] For example, the method of accessing the configuration space register of a bus device provided in this application embodiment can also be applied to Figure 2 The server cluster shown represents cross-network communication, such as... Figure 2 The data center shown. Among them, Figure 2 The internal structure of the switch or server shown above is as described. Figure 1 As shown in the image.

[0076] Furthermore, the internal bus protocols supported by the computer systems involved in this application include general-purpose bus protocols, enabling the establishment of transport layer connections between computer systems. These general-purpose bus protocols can also be referred to as Lingqu bus protocols or unified bus protocols; they are a type of bus protocol standard, and this application does not limit the name of this general-purpose bus protocol.

[0077] The Universal Bus Protocol breaks down existing protocol barriers and eliminates unnecessary intermediate conversion overhead, thereby achieving extremely low latency. The Universal Bus Protocol defines independent transaction and transport layers. There are connections between transport layers, but no connections between transaction layers. All transactions within a host are carried on a single transport layer. The Universal Bus Protocol includes a transport layer and a transaction layer. The transport layer is responsible for retransmitting lost packets and ensuring reliable transmission, while the transaction layer handles its respective transactions. The transport layer receives packets from the network, removes the transport layer header, and forwards them to the transaction layer.

[0078] The general bus protocol message format is as follows: Figure 3 As shown in Table 1 below, the specific field definitions in the general bus protocol message format are as follows:

[0079] Table 1

[0080]

[0081] Figure 4 This is a schematic diagram of the structure of a host provided in an embodiment of this application. The host (e.g.) Figure 4 The host A shown can be applied to Figure 2 In the application scenarios of cross-network communication shown, such as... Figure 4 As shown, host A includes a network management unit, double data rate (DDR) memory, and bus devices (such as...). Figure 4The diagram shows devices 1 (Dev1) and 2. After the system powers on, the network management unit can scan and discover Dev1 and Dev2, and assign network address 1 and network address 2 to them. The specific method by which the network management unit assigns network addresses to Dev1 and Dev2 is not limited in this application; the network management unit can scan the device ports of the entire network, such as through a hop-by-hop mechanism or by managing the network.

[0082] Specifically, Figure 4 The network management unit shown includes a core and a controller. The controller has a device bus entry engine. During system design, an address space is reserved for this entry engine (e.g., the address space required for information such as doorbell, send queue entry (SQE), receive queue entry (SQE), and complete queue entry (CQE).

[0083] The above text combines Figures 1 to 4 This paper briefly introduces the application scenarios and the internal logic units of the host involved. In order to facilitate understanding of the embodiments of this application, some basic concepts involved in this application are briefly explained.

[0084] 1. PCIe bus:

[0085] The PCIe bus, as the I / O bus of the processor system, functions similarly to the Peripheral Component Interconnect (PCI) bus, primarily for connecting external devices within the processor system. The PCIe bus uses an end-to-end connection method, with one device connected to each end of a PCIe link; these two devices act as the data sender and receiver for each other.

[0086] A typical PCIe system includes a root complex (RC), a PCIe switch, and PCIe bus devices. The RC can reside on the processor and occupies one bus number. The PCIe switch contains upstream and downstream ports. The upstream port connects to the RC's root port (RP) or the downstream port of other PCIe switches. The RC's root port, the upstream port of the PCIe switch, and the downstream port can also be referred to as bridge devices, which are used to connect other bridge devices or bus devices.

[0087] It should be noted that a PCIe switch can be a standalone physical device, such as a physical switch or switching chip; or it can be a hardware functional module implemented in a chip, such as a hardware functional module integrated into a processor chip, which implements the function of a PCIe switch.

[0088] like Figure 5 The diagram illustrates bus number allocation in a PCIe system. The Central Processing Unit (CPU) has multiple root ports (RPs). The diagram uses two RPs as an example; these RPs can reside on one or more RCs (not shown). For instance, RP0 can be connected to a bus device or a bridge device (not shown), and RP1 is connected to the upstream port (UP) of a PCIe switch. The PCIe switch includes m+1 downstream ports (DPs), labeled DP_0, DP_1, ..., DP_m. Each downstream port is connected to a bus device. Figure 1The bus devices shown are labeled EP_0, EP_1, ..., EP_m. For example, the root port RP1, connected to the upstream port UP, occupies bus X, and the link between RP1 and UP occupies bus N. In this case, the connection from the upstream port to m+1 downstream ports within the PCIe switch occupies bus N+1, and the connection between each downstream port and its corresponding bus device occupies bus N+2, bus N+3, ..., bus N+2+m, respectively. Here, X is an integer greater than or equal to 0, and N is an integer greater than X. For example, when the two RPs shown in the figure are located in different RCs, and the left RC where RP0 is located is enumerated first, the value of X depends on the number of bus numbers occupied by the PCIe structure under the left RC. For example, when the PCIe structure under the left RC occupies 5 bus numbers (i.e., buses 0-4 are occupied by the left RC and the PCIe structure under it), the value of X is 5, and the value of N is 6. When the two RPs shown in the figure are located in the same RC and this RC is the RC that the processor enumerates first, the value of X is 0. If the PCIe structure under the left RC occupies 5 bus numbers (i.e., buses 0-4 are occupied by the RC and the PCIe structure under RP0), the value of N is 5.

[0089] PCIe devices can be divided into two types: bridge devices (e.g., root port RP, upstream port, downstream port) and bus devices (Endpoint, EP). At each end of a PCI bridge, two buses are connected: the upstream bus (Primary Bus) and the downstream bus (Secondary Bus). A PCIe bridge can manage its subordinate PCIe subtree. Bridge devices have registers for Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number. The Primary Bus Number register stores the PCIe bus number upstream of the bridge device, the Secondary Bus Number register stores the PCIe bus number downstream of the bridge device, and the Subordinate Bus Number register stores the largest PCIe bus number in the downstream PCIe subtree of the bridge device. The Subordinate Bus Number is called the slave bus number.

[0090] Generally, the PCIe protocol uses a 32-bit PCIe identifier (ID) to identify PCIe devices in a system. This 32-bit identifier includes: a 16-bit domain, an 8-bit bus, a 5-bit device, and a 3-bit function. The 8-bit bus ID, 5-bit device ID, and 3-bit function ID are collectively referred to as BDF. The Bus ID provides 256 bus numbers for each PCIe domain. Typically, a computer system supports one PCIe domain, meaning the entire computer system provides 256 bus numbers.

[0091] Figure 5 This is merely an example of a possible bus allocation in a PCIe system to illustrate bus number allocation. It does not constitute any limitation on the scope of protection of this application.

[0092] 2. PCIe Device Enumeration: The process of scanning and discovering all devices on the PCIe bus is called PCIe device enumeration. Since the invention of the personal computer (PC) by International Business Machines (IBM) in 1981, motherboards have had expansion slots to expand computer functionality. The most common expansion slots today are PCIe slots. Inside the computer motherboard chipset, most hardware control modules are mounted as PCIe devices on one or more PCI or PCIe device trees. Firmware and the operating system discover most plug-and-play devices by enumerating the device tree.

[0093] After the computer system is reset or powered on, the software first scans the PCIe bus to enumerate all devices connected to it. Before scanning, the only device the software can detect is the Host / PCI bridge, and it also knows that the bus number under the Host / PCI bridge is 0.

[0094] Each PCIe Function's configuration space register contains a read-only register with a vendor identifier (ID). The Vendor ID is a 16-bit specific value assigned to each vendor by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). During PCIe device enumeration, the system software iterates through all possible combinations of Bus, Device, and Function, attempting to read the Vendor ID register at each Bus, Device, and Function location. Based on the results, it can determine whether the Function located at a particular Bus, Device, and Function actually exists. In short, the PCIe device enumeration process is the process by which system software accesses the PCIe device's configuration space register.

[0095] 3. Configuration Space: In the early PCI era, the system allocated 256 bytes of configuration space to each PCIe device. With the advancement of PCIe, as device performance improved, the configuration space for PCIe devices expanded to 4KB. It's important to note that PCIe supports 256 buses, 32 devices, and 8 functions. Under full load, the required configuration space is 4KB * 256 * 32 * 8 = 256MB. This 256MB of configuration space is reserved for PCIe devices and is unavailable to the system. Specifically, PCIe devices are backward compatible with PCI. The first 256 bytes of the configuration space for each PCIe device are PCI space, and the remaining (256 - 4KB) bytes are PCIe expansion space.

[0096] Each PCIe device has its own independent configuration space. This configuration space belongs to the PCIe device. The system will allocate a memory space to this device, and the CPU accesses this memory space, which means accessing the configuration space of the PCIe device.

[0097] For example, PCIe devices have default initial values ​​for their configuration space when they are shipped from the factory.

[0098] 4. I / O Access and Memory Access: In x86 systems, the address mapping for the configuration space of PCIe devices includes I / O mapping and memory mapping. The configuration space of PCIe devices can be accessed through I / O access and memory access.

[0099] Specifically, access to the configuration space of a PCIe device is inseparable from the numbering method of the PCIe device's bus, device, and function. Bits [23:16] represent the bus number, used to store the bus number, totaling 8 bits, which can store 256 bus numbers; bits [15:11] represent the device number, used to store the device number, totaling 5 bits, which can store 32 device numbers; bits [10:8] represent the function number, used to store the function number, totaling 3 bits, which can store 8 function numbers. This also explains why PCIe supports a total of 256 buses, 32 devices, and 8 functions. In addition, bit

[31] represents the enabled bit; bits [7:2] represent the register number of the configuration space; and bits [1:0] are always "00".

[0100] According to the protocol, x86 uses two I / O port registers: config_address (physical address 0CF8h) and config_data (physical address CFCh) to access the configuration space of PCIe devices. OUT and IN are port read / write operation instructions in assembly language. Ports are used by the host to exchange data with peripherals and are divided into data ports, status ports, and control ports. The PC assigns an address to each port, and all ports are arranged linearly to form an I / O address space independent of memory space, typically represented in hexadecimal. For example, the range of port addresses is 0000H-FFFFH.

[0101] For example, by filling in BDF in the CF8h port, the contents of the PCIe device's configuration space can be written to or read from the CFCh.

[0102] I / O access can be simply understood as a user accessing a segment of storage space through input or output (IN / OUT) commands. Some PCIe devices can be mapped to I / O space, which developers access through I / O ports. For example, the first 256 bytes of a PCIe device can be accessed through the CF8h / CFCh port.

[0103] It should be understood that the I / O access mechanism can only access the first 256 bytes of the function's 4K-byte configuration space.

[0104] To facilitate understanding, we will use specific examples to illustrate how to access the configuration space of a PCI device via I / O access:

[0105] Example 1:

[0106] Step 1: The bus number of the PCI device is filled into bits [23:16] of I / O address CF8h, the device number of the PCI device is filled into bits [15:11] of I / O address CF8h, the function number of the PCI device is filled into bits [10:8] of I / O address CF8h, the double-word address of the register to be accessed is filled into bits [7:2] of I / O address CF8h, and the highest bit of CF8h is the configuration bit, which is set to 1.

[0107] Step 2: For write operations, combine the device-specific information into a double word (4 bytes) and write it to the CFCh address; for read operations, combine the device-specific information into a double word and read the data back from the CFCh.

[0108] I / O access allows access to the first 255 bytes of configuration space of a PCIe device.

[0109] Memory mapping maps the entire configuration space of a PCIe device into memory. After determining the device address, the user can access the PCIe device configuration space through memory read and write operations. Memory mapping allows access to 4KB of address space, but each access operation is a single memory access operation.

[0110] Specifically, when software accesses the configuration space of a specified PCIe device, it needs to correctly calculate the specific memory address mapped to that configuration space. The address where bus No = 0, device No = 0, and func No = 0 is exactly BAR. The maximum space occupied by a single bus is calculated as follows:

[0111] SIZE PER BUS=4K*32*8=256K=1M=100000h

[0112] SIZE_PER_DEVICE=4K*8=8000h

[0113] SIZE_PER_FUNC=4K=1000h

[0114] The formula for calculating the configuration space of a PCIe device with bus number No., device number Dev No., and function number func No. is:

[0115] Memory Address=PCIe Configuration Register Base Address Register(BAR)+busNo*SIZE_PER_BUS+devNo*SIZE_PER_DEVICE+funcNo*SIZE_PER_FUNC+offset

[0116] To facilitate understanding, we will use specific examples to illustrate how to access the configuration space of a PCI device via memory access:

[0117] Example 2: Software accesses the configuration space of a PCIe device with bus No. 15h, device No. 00h, function No. 05h, and register offset of 84h.

[0118] Step 1: Calculate the memory address to be accessed using the formula for calculating the configuration space of the PCIe device mentioned above:

[0119] Memory Address=F0000000h+15h*100000h+00h*8000h+05h*1000h+84h=F1505084h

[0120] Step 2: After determining the device memory address, you can access the PCIe device configuration space through memory read and write operations.

[0121] 5. Bus Device Enumeration: The process of scanning and discovering all devices on the general-purpose bus is called the bus device enumeration process. Similar to the PCIe device enumeration process described above, the bus device enumeration process can also be understood as the process by which system software accesses the bus device configuration space registers.

[0122] 6. Bus Device Configuration Space Register: In this application, the bus device configuration space register can also be referred to as the bus device space register, or simply as the bus configuration space, bus device space, etc. It should be understood that the resources, configuration, and management of bus devices mainly include the common configuration management, resource configuration management, interconnect configuration management, internal task queue resources, memory resources, network resources, etc., of the physical devices. When device resources are pooled, each host does not need to manage the common configuration, resource configuration, and interconnect configuration of the devices; the host can simply use the internal memory, network, and other resources of the device.

[0123] For ease of understanding, combined with Figure 6 and Figure 7 (a) Briefly introduces the bus device configuration space register.

[0124] like Figure 6 As shown, the bus device configuration space register includes different types of registers, each corresponding to a different address block. Specifically, the configuration space register is divided into different address blocks (such as...). Figure 6The basic block, route block, capability block, port block, and user-defined block shown in the diagram correspond to different types of configuration space registers; or, different types of registers correspond to different address ranges.

[0125] like Figure 7 As shown in (a), the address block corresponding to a certain type of register can be divided into different segments. Different segments correspond to different address spaces. A segment includes a reserved bit and a 4Kbyte address space corresponding to the register.

[0126] In addition, the following points are provided to facilitate understanding of the embodiments of this application.

[0127] First, in this application, "at least one" refers to one or more, and "more than one" refers to two or more. Furthermore, in the embodiments of this application, "first," "second," and various numerical designations (e.g., "#1," "#2," etc.) are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The sequence numbers of the processes below do not imply an order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. It should be understood that the objects described in this way can be interchanged where appropriate to describe solutions other than those in the embodiments of this application. In addition, in the embodiments of this application, terms such as "S810" are merely identifiers for descriptive convenience and do not limit the order of execution steps.

[0128] Second, in the embodiments of this application, the words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0129] Third, the term "storage" in the embodiments of this application can refer to storage in one or more memories. These memories can be separate installations or integrated into an encoder, decoder, processor, or communication device. Alternatively, some memories can be separately installed, while others are integrated into the decoder, processor, or communication device. The type of memory can be any form of storage medium, and this application does not limit this.

[0130] Fourth, the term "comprising" (also referred to as "includes", "including", "comprises" and / or "comprising") used in the embodiments of this application, when used in this specification, specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0131] Fifth, the word "if" in the embodiments of this application can be interpreted as meaning "when" or "upon" or "in response to determination" or "in response to detection". Similarly, depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is detected" can be interpreted as meaning "when it is determined..." or "in response to determination..." or "when [the stated condition or event] is detected" or "in response to detection of [the stated condition or event]".

[0132] Sixth, the terminology used in the description of the various examples in the embodiments of this application is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and in the appended claims, the numerical forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0133] Seventh, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0134] The above text combined Figure 1 This paper briefly introduces the applicable scenarios for the communication method provided in this application, as well as the basic concepts involved. Within the basic concepts, it describes I / O access and memory access. When accessing the configuration space registers of a bus device (e.g., a PCIe device) via memory access, the processor enters a waiting state after the access instruction is issued, which imposes constraints on access latency and prevents cross-host access to configuration space registers. For example, the memory access method described above is not suitable for multi-host application scenarios because one host has one set of bus numbers, and two hosts have two sets of bus numbers. The memory access method is only suitable for configuration space register access in a single-host service scenario.

[0135] This application proposes a communication method whereby, when a network management unit needs to access the configuration space register of a bus device, the network management unit can access the bus device's configuration space register by including the bus device's network address and the information of the configuration space register to be accessed in the request message. This eliminates the need for memory read / write operations. Therefore, the method of accessing the bus device's configuration space register via a request message, as provided by this technical solution, avoids the high latency requirements and inability to access across hosts associated with memory read / write methods.

[0136] The communication method provided in this application will now be described in detail with reference to the accompanying drawings. It should be understood that the communication method provided in the embodiments of this application can be applied to computer systems, for example... Figure 2 The system shown is for cross-network access.

[0137] It should also be understood that the embodiments shown below do not particularly limit the specific structure of the execution subject of the method provided in the embodiments of this application. As long as the method provided in the embodiments of this application can be implemented by running a program that records the code of the method provided in the embodiments of this application. For example, the execution subject of the method provided in the embodiments of this application can be a device, or a functional module in the device that can call and execute a program.

[0138] Figure 8 This is a schematic flowchart of a communication method provided in this application. This communication method can be applied to, for example... Figure 7 In the bus network shown in (b), the bus network includes a network management unit and at least one bus device (such as...). Figure 7 The bus device #1, wire device #2...wire device #n shown in (b) are connected to the network management unit via a general-purpose bus. The bus network can include multiple hosts, and it can be understood as a wired bus network, distinct from a wireless network.

[0139] Specifically, the communication method includes the following steps:

[0140] S810, the network management unit sends a request message to the bus device, or in other words, the bus device receives a request message from the network management unit.

[0141] Specifically, in this embodiment, the network management unit and the bus devices are connected via a general-purpose bus. For example, in this embodiment, the general-purpose bus serves as a local bus of the bus network, connecting the bus devices (which may also be referred to as external devices, endpoint devices, etc.) within the bus network.

[0142] The request message includes the network address of the bus device, first indication information, and information from the first configuration space register.

[0143] The network address of the bus device is the address assigned to the bus device by the network management unit. Specifically, the bus network may include at least one bus device. It should be noted that in this embodiment, the network management unit can discover the bus devices in the bus network and assign network addresses to them before accessing the configuration space registers of the bus devices.

[0144] For example, a bus network includes a network management unit and bus devices #1, #2, and #3. The network management unit can assign network address #1 to bus device #1, network address #2 to bus device #2, and network address #3 to bus device #3. When the network management unit needs to access bus device #1, it sends a request message #1 to bus device #1, carrying network address #1 in the request message. Similarly, when the network management unit needs to access bus device #2, it sends a request message #2 to bus device #2, carrying network address #2 in the request message. When the network management unit needs to access bus device #3, it sends a request message #3 to bus device #3, carrying network address #3 in the request message.

[0145] The first indication information is used to indicate the type of operation on the first configuration space register. For example, when the network management unit performs a read operation on the first configuration space register of the bus device through a request message, the first indication information is used to indicate a read; when the network management unit performs a write operation on the first configuration space register of the bus device through a request message, the first indication information is used to indicate a write, wherein the write operation includes, but is not limited to, adding or modifying.

[0146] For example, when the first indication information indicates that the operation type for the first configuration space register is a write operation, the request message may also include the data to be written to the first configuration space register.

[0147] For example, if the network management unit requests to write data #1 into the first configuration space register of the bus device via a request message, then the request message carries the data #1.

[0148] For example, when the first indication information indicates that the operation type of the first configuration space register is a write operation, the request message may also include a second indication information, which is used to indicate that data is written to at least one byte in the first configuration space register.

[0149] For example, the size of the first configuration space register is 4 bytes. The network management unit can request to write data #1 into two bytes of the first configuration space register of the bus device through a request message. The request message carries data #1 and second indication information, which indicates that data #1 can be written into any two bytes of the first configuration space register.

[0150] The information in the first configuration space register is used to indicate the first configuration space register and is related to the first configuration space register.

[0151] For example, the information in the first configuration space register includes at least one of the following:

[0152] The type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

[0153] The type information of the first configuration space register is used to identify the type of the first configuration space register of the bus device to be accessed, as described above. Figure 6 As shown, the configuration space registers locally configured by the bus device in this application may include different types, and different types of configuration space registers correspond to different types of address blocks. Therefore, by carrying the type information of the configuration space register in the request message, the address corresponding to the configuration space register to be accessed can be accurately indicated. For example, if the type information of the first configuration space register indicates that the type of the first configuration space register of the bus device to be accessed is a basic register, then the address block accessed by the access message is... Figure 6 The basic block shown corresponds to segment 0.

[0154] Additionally, the address of the first configuration space register is used to indicate the address of the first configuration space register of the bus device to be accessed. It should be understood that a configuration space register may contain multiple address segments, as described above. Figure 7 As shown in (a), the address block corresponding to a certain configuration space register includes multiple segments, and the addresses of different segments are different. The address information of the first configuration space register can be used to indicate in detail the address of the first configuration space register of the accessed bus device.

[0155] It should be understood that this embodiment does not limit the specific form of the information in the first configuration space register, and all information that can be used to indicate the first configuration space register is within the protection scope of this application.

[0156] Furthermore, the request message also includes a task identifier (ID), which is used to identify the request message. Different request messages can carry different task identifiers. For example, the task identifier carried in request message #1 can be identifier #1; the task identifier carried in request message #2 can be identifier #2. The task identifier can also be a tag.

[0157] For example, in this embodiment, the network management unit can access multiple configuration space registers of the bus device via request messages to improve access efficiency. For ease of description, the following explanation uses an example where the request message is also used to request access to a second configuration space register of the bus device.

[0158] Specifically, when the request message is also used to request access to the second configuration space register of the bus device, the request message also includes third indication information and information about the second configuration space register, wherein the third indication information is used to indicate the type of operation on the second configuration space register.

[0159] The third indication information is used to indicate the type of operation on the second configuration space register. For example, when the network management unit performs a read operation on the second configuration space register of the bus device through a request message, the third indication information is used to indicate a read; when the network management unit performs a write operation on the second configuration space register of the bus device through a request message, the third indication information is used to indicate a write.

[0160] For example, when the third indication information indicates that the operation type for the second configuration space register is a write operation, the request message may also include the data to be written to the second configuration space register.

[0161] For example, if the network management unit requests to write data #2 into the second configuration space register of the bus device via a request message, then the request message carries the data #2.

[0162] For example, when the third indication information indicates that the operation type of the second configuration space register is a write operation, the request message may also include a fourth indication information, which is used to indicate that data is written to at least one byte in the second configuration space register.

[0163] For example, the size of the second configuration space register is 4 bytes. The network management unit can request to write data #2 into two bytes of the second configuration space register of the bus device through a request message. The request message carries data #2 and fourth indication information, which indicates that data #2 should be written into any two bytes of the second configuration space register.

[0164] Optionally, when the network management unit performs the same operation on different configuration space registers in the bus device through a request message, the first indication information and the third indication information mentioned above can be the same information, and the second indication information and the fourth indication information can also be the same information.

[0165] For example, the information in the second configuration space register includes at least one of the following:

[0166] The second configuration space register includes its type, index, or address. A description of the second configuration space register can be found above regarding the first configuration space register; it will not be repeated here.

[0167] Optionally, when the network management unit requests access to multiple configuration space registers of the bus device through a request message, the information carried in the request message for accessing the multiple configuration space registers constitutes multiple access requests. For example, when the request message requests access to the first configuration space register and the second configuration space register, the information carried in the request message that supports access to the first configuration space register (such as the first indication information, the information of the first configuration space register and the second indication information mentioned above) is called access request #1, and the information carried in the request message that supports access to the first configuration space register (such as the third indication information, the information of the second configuration space register and the fourth indication information mentioned above) is called access request #2.

[0168] It should be understood that the network management unit's request to access the first and second configuration space registers of the bus device via a request message is merely an example illustrating that the network management unit can access multiple configuration space registers with a single request message, and does not constitute any limitation on the scope of protection of this application. In this embodiment, the network management unit can request to access other configuration space registers of the bus device via a request message. For example, the request message may also include an access request #3 that supports access to the third configuration space register, which will not be elaborated here.

[0169] For example, in this embodiment, the network management unit includes a processing core and a controller. The network management unit sending a request message to the bus device includes the controller in the network management unit sending a request message to the bus device. It should be noted that the operations performed by the network management unit in this embodiment can be implemented by system software; therefore, the operations performed by the processing core and controller described below can also be implemented by system software.

[0170] In this embodiment, before the controller sends an access request message to the bus device, the internal message transmission of the network management unit includes the following steps:

[0171] Step 1: The processing core sends the descriptor of the request message to the DDR.

[0172] Specifically, the processing core uses the configuration space register information of the bus device to be accessed as the descriptor of the request message, and the descriptor of the request message is carried by the Send Queue Entry (SQE) in DDR.

[0173] Step 2: The processing core sends instruction message #1 to the controller. Instruction message #1 is used to notify the controller that there is a task to be executed. Specifically, instruction message #1 is used to instruct the controller to retrieve the descriptor of the request message from the DDR.

[0174] For example, there is an entry engine in the controller. When the system is designed, a section of address space is reserved for this entry engine (e.g., the address space required to obtain information such as doorbell, SQE, receive queue entry (SQE), and complete queue entry (CQE). The processing core sends the doorbell to notify the entry engine in the controller that there is a task to be executed.

[0175] Step 3: The controller retrieves the descriptor of the request message from the DDR.

[0176] Specifically, the entry engine in the controller retrieves the descriptor of the request message from the DDR. For example, the entry engine in the controller reads the SQE in the DDR and retrieves the descriptor of the request message from the SQE.

[0177] Step 4: The controller generates a request message.

[0178] In this embodiment, after the entry engine in the controller obtains the descriptor of the request message, it encapsulates the descriptor of the request message into a request message on the device bus. The description of the request message can be found in the description of the request message in step S810 above, and will not be repeated here.

[0179] In this embodiment, the processing core can continuously issue multiple descriptor tasks, and the controller can also have multiple hardware and software interface queues. Both the controller and the bus device support sending and receiving multiple request messages to improve performance.

[0180] Furthermore, in this embodiment, after receiving the aforementioned access request message, the bus device parses and executes the corresponding operation request, and returns an access response message. Figure 8 The method shown also includes:

[0181] S820: The bus device sends a response message to the network management unit, or in other words, the network management unit receives a response message from the bus device.

[0182] Specifically, the response message carries a task identifier. The bus device carries a task identifier in the response message so that the network management unit can determine whether the response message is in response to a specific request message based on the task identifier carried in the response message.

[0183] For example, the task identifier carried in request message #1 sent by the network management unit to bus device #1 is identifier #1; the task identifier carried in request message #2 sent by the network management unit to bus device #2 is identifier #2. After receiving request message #1, bus device #1 can send a response message #1 in response to request message #1 to the network management unit. This response message #1 carries identifier #1, which is used to indicate that the response message #1 is a message in response to request message #1.

[0184] Similarly, after receiving request message #2, bus device #2 can send a response message #2 to the network management unit in response to request message #2. This response message #2 carries an identifier #2, which indicates that the response message #2 is a response to request message #2. Therefore, the network management unit can determine that response message #1 is a response to request message #1 based on the identifier #1 carried in response message #1, and determine that response message #2 is a response to request message #2 based on the identifier #2 carried in response message #2.

[0185] As one possible implementation, the response message is used to indicate whether the operation on the configuration space register was successful.

[0186] For example, if a request message requests a write operation to the first configuration space register, and the bus device successfully writes the data #1 to be written to the first configuration space register carried in the request message to the first configuration space register, then a response message is used to indicate that the write operation to the first configuration space register was successful.

[0187] For example, a request message requests a write operation to the first configuration space register and the second configuration space register. If the bus device successfully writes the data #1 to be written to the first configuration space register carried in the request message to the first configuration space register, and successfully writes the data #2 to be written to the second configuration space register carried in the request message to the second configuration space register, then a response message is used to indicate that the write operation to the first configuration space register and the second configuration space register was successful.

[0188] For example, a request message requests a write operation to the first configuration space register and the second configuration space register. If the bus device successfully writes the data #1 to be written to the first configuration space register carried in the request message to the first configuration space register, and fails to write the data #2 to be written to the second configuration space register carried in the request message to the second configuration space register, then a response message is used to indicate that the write operation to the first configuration space register was successful and the write operation to the second configuration space register failed (e.g., the response message includes two response fields, indicating whether the operations to the two configuration space registers were successful).

[0189] It should be understood that the above are merely examples illustrating how response messages indicate whether an operation on a configuration space register was successful, and do not constitute any limitation on the scope of protection of this application. Response messages can also indicate whether an operation on different configuration space registers was successful in other ways, which will not be illustrated here.

[0190] As another possible implementation, if the operation type of the configuration space register is a read operation, the response message includes the information read from the configuration space register.

[0191] For example, if a request message requests a read operation on the first configuration space register, the response message will include the information read from the first configuration space register.

[0192] For example, if a request message requests a read operation on the first configuration space register and the second configuration space register, the response message will include the information read from the first configuration space register and the second configuration space register.

[0193] Optionally, the response message may also include information indicating whether the response message is in response to a read operation or a write operation.

[0194] Optionally, when a bus device responds to a network management unit by accessing multiple configuration space registers of the bus device via a response message, and the response message contains multiple access responses, such as a request message requesting access to a first configuration space register and a second configuration space register, when the response message responds to the request message, the response in the response message for accessing the first configuration space register is called access response #1, and the response in the response message for accessing the second configuration space register is called access response #2.

[0195] Furthermore, this embodiment does not limit the specific operations performed by the network management unit after receiving the response message. For example, after receiving the response message, the network management unit can write the information carried in the response message to the RQE, which is carried in the CQE. The controller reports an interrupt to the processing core, indicating that there is an RQE to be processed. Then, the processing core reads the CQE, processes the RQE, and determines the descriptor execution status by matching the task identifier.

[0196] Figure 8 In the communication method shown, when the network management unit needs to access the configuration space register of the bus device, it can do so by including the network address of the bus device and the information of the configuration space register to be accessed in the request message. This eliminates the need for memory read / write operations. Therefore, the method of accessing the configuration space register of the bus device via a request message, as provided by this technical solution, avoids the high latency requirements and inability to access across hosts associated with memory read / write methods.

[0197] For example, when accessing the configuration space register of a bus device via a request message, the network management unit issues an access message rather than a memory access instruction, resulting in relatively low latency requirements. Furthermore, when accessing the configuration space register of a bus device via a request message, since routing to the bus device is done via its network address rather than its memory address, it is not limited by memory address allocation within a single host. Therefore, accessing the configuration space register of a bus device via a request message can be done across hosts.

[0198] For example, accessing the configuration space registers of a bus device via its network address, compared to the memory access methods described in the basic concepts section, eliminates the need for hardware logic to decode the memory address into the bus number, device number, and function number, thus reducing hardware resource consumption. Furthermore, memory access is a synchronous access; the CPU waits for the access to complete before issuing it, therefore the response time must be short, typically within 1µs. Figure 8 The message access shown is an asynchronous access, meaning the CPU does not need to wait, has low latency requirements, and supports latency of a few microseconds to tens of microseconds. This also allows... Figure 8 The message shown is more applicable to large-scale networking.

[0199] It should be noted that the request and response messages mentioned above are transaction layer messages. The format of transaction layer messages can be found in the current protocol specifications (e.g., as shown in Table 1 above), and will not be repeated here. This embodiment mainly involves the design of the message header and payload of transaction layer messages.

[0200] The following is combined with Figures 9 to 12 This document details the design of the Header and Payload parts of the transaction layer message in this embodiment.

[0201] Transaction layer messages are divided into two parts: a header and a payload. The header is a fixed 4-byte size, and the payload is N*4 bytes, where N is a positive integer. For example... Figure 9 As shown, transaction layer messages are divided into two parts: Header and Payload.

[0202] For example, when the transaction layer message is the aforementioned request message, the message header indicates that the transaction layer message is a message accessing the configuration space register through the message code and sub-message code. The sub-message code is optional; that is, the transaction layer message header may not include the sub-message code.

[0203] The task identifier is used to match request messages with response messages.

[0204] The message payload length in the header of a transaction layer message specifies the length of the message payload.

[0205] like Figure 10 As shown, the header of a transaction layer message includes the fields Message Code, Sub-Message Code, TaskID, and Message Payload length.

[0206] As one possible implementation, the transaction layer message is the request message described above. The payload of the request message can contain multiple access requests, each accessing a different configuration space register of the bus device. Optionally, each of the multiple access requests in the request message can occupy a fixed size of 4 bytes.

[0207] In this implementation, each access request structure is as follows: Figure 11 As shown, the access request includes Opcode, ByteEnable, Block type, Function Entity Index, Request Address, and Write Data fields. The function of each field is as follows:

[0208] Opcode: Describes the read / write type of the request; for example, it indicates a read or write operation, which can be understood as the first or third indication information mentioned above.

[0209] It should be noted that if multiple access requests in a request message request the same read / write type, the read / write type can be indicated by the Sub-Message Code in the message header mentioned above; that is, the Opcode in the access request is optional. For example, if the request message includes a single access request for reading, the read / write type can be indicated by the Sub-Message Code as a read operation; or, for example, if the request message includes multiple access requests, all of which request reading, the read / write type can be indicated by the Sub-Message Code as a read operation.

[0210] Byte Enable: Describes which bytes the request accesses; for example, it indicates access to two bytes in the first configuration space register, which can be understood as the second or fourth instruction information mentioned above.

[0211] Block type, Function Entity Index, and Request Address: These describe the device configuration space registers; they can be understood as information from either the first or second configuration space register mentioned above.

[0212] Write Data: Describes the data to be written. If the request message requests that data #1 be written to the first configuration space register, the access request for the first configuration space register includes data #1.

[0213] As another possible implementation, the transaction layer message is the response message described above. The payload of the response message can contain multiple access responses, each responding to one of the multiple access requests in the request message. Optionally, each of the multiple access responses in the response message can occupy a fixed size of 4 bytes.

[0214] In this implementation, each access response structure is as follows: Figure 12 As shown, the access response includes Opcode, Status, and Read Data fields, and the function of each field is as follows:

[0215] Opcode: Describes the read / write type of the request corresponding to the response; for example, if access request #1 in the request message is a read operation request, then access response #1 in the response message is a read operation response.

[0216] Status: Describes the execution status of the request corresponding to this response; for example, it indicates whether the operation was successful.

[0217] Read Data: Describes the read data requested in this response message. If access request #1 in the request message is a read operation request, then access response #1 in the response message carries the read data.

[0218] In this embodiment, the access request message and the access response message correspond one-to-one.

[0219] It should be understood that, in the embodiments of this application Figure 8 The specific examples shown are merely to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. It should also be understood that the sequence numbers of the above processes do not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0220] It should also be understood that, in the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0221] The foregoing mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0222] The following, combined with Figures 13 to 15 This application provides a detailed description of the communication device provided in its embodiments. It should be understood that the descriptions of the device embodiments correspond to the descriptions of the method embodiments; therefore, any content not described in detail can be found in the above method embodiments. For brevity, some content is omitted.

[0223] This application embodiment can divide the transmitting or receiving device into functional modules according to the above method examples. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The following description uses the division of functional modules according to each function as an example.

[0224] Figure 13 A schematic diagram of the structure of a communication device 1300 provided in an embodiment of this application is shown.

[0225] In one example, the communication device 1300 can be the network management unit described above, and the communication device 1300 can be used to execute the communication method described above, for example, to execute... Figure 8 The method shown. The communication device 1300 may include a transceiver unit 1310 and a processing unit 1320.

[0226] Transceiver unit 1310 is configured to send a request message to a bus device, the request message being used to request access to a first configuration space register of the bus device. The request message includes the network address of the bus device, first indication information, and information about the first configuration space register. The network address is an address assigned to the bus device by a network management unit, and the first indication information indicates the type of operation on the first configuration space register. Transceiver unit 1310 is also configured to receive a response message from the bus device in response to the request message.

[0227] As an example, combined Figure 8 The transceiver unit 1310 can be used to execute S810 and S820.

[0228] In another example, the communication device 1300 can be the bus device described above, and the communication device 1300 can be used to execute the communication method described above, for example, to execute... Figure 8 The method shown.

[0229] Transceiver unit 1310 is configured to receive a request message from network management unit. The request message requests access to a first configuration space register of a bus device. The request message includes the network address of the bus device, first indication information, and information about the first configuration space register. The network address is an address assigned to the bus device by network management unit, and the first indication information indicates the type of operation on the first configuration space register. Transceiver unit 1310 is also configured to send a response message to network management unit in response to the request message.

[0230] As an example, combined Figure 8 The transceiver unit 1310 can be used to execute S810 and S820.

[0231] This application also provides a chip system 1400, such as... Figure 14 As shown, the chip system 1400 includes at least one processor and at least one interface circuit. As an example, when the chip system 1400 includes one processor and one interface circuit, the processor can be... Figure 14 The processor 1410 shown in the solid box (or the processor 1410 shown in the dashed box) can be an interface circuit. Figure 14 The interface circuit 1420 is shown in the solid box (or the interface circuit 1420 is shown in the dashed box).

[0232] When the chip system 1400 includes two processors and two interface circuits, then the two processors include Figure 14 The processor 1410 shown in the solid box and the processor 1410 shown in the dashed box, these two interface circuits include Figure 14 Interface circuit 1420 is shown in both solid and dashed boxes. This is not a limitation. Processor 1410 and interface circuit 1420 can be interconnected via lines. For example, interface circuit 1420 can be used to receive signals (e.g., instructions stored in memory). As another example, interface circuit 1420 can be used to send signals to other devices (e.g., processor 1410).

[0233] For example, interface circuit 1420 can read instructions stored in memory and send those instructions to processor 1410. When the instructions are executed by processor 1410, they can cause a communication device or a device accessing memory to perform the steps in the above embodiments. Of course, the chip system 1400 may also include other discrete devices, and this application embodiment does not specifically limit this.

[0234] Another embodiment of this application provides a computer-readable storage medium storing instructions that, when executed on a communication device, cause the communication device to perform the various steps of the method flow shown in the above-described method embodiments. In some embodiments, the disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0235] Figure 15 A conceptual partial view of a computer program product provided in an embodiment of this application is shown schematically. The computer program product includes a computer program for executing computer processes on a computing device.

[0236] In one embodiment, a computer program product is provided using a signal bearer medium 1000. This signal bearer medium 1500 may include one or more program instructions that, when executed by one or more processors, can provide the above-mentioned... Figure 8 The described function or part of the function. Therefore, for example, refer to... Figure 8 One or more features can be provided by one or more instructions associated with the signal carrying medium 1500. Furthermore, Figure 15 The program instructions in the document also describe example instructions.

[0237] In some examples, the signal carrying medium 1500 may include a computer-readable medium 1501, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video disc (DVD), a digital magnetic tape, a memory, a read-only memory (ROM), or a random access memory (RAM), etc.

[0238] In some implementations, the signal carrying medium 1500 may include a computer recordable medium 1502, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, and so on.

[0239] In some implementations, the signal-bearing medium 1500 may include a communication medium 1503, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). The signal-bearing medium 1500 may be transmitted by a wireless communication medium 1503 (e.g., a wireless communication medium conforming to the IEEE 1502.11 standard or other transmission protocols). One or more program instructions may be, for example, computer-executable instructions or logical implementation instructions.

[0240] In some examples, such as targeting Figure 8 The communication device shown can be configured to provide various operations, functions, or actions in response to one or more program instructions in a computer-readable medium 1501, a computer-recordable medium 1502, and / or a communication medium 1503.

[0241] It should be understood that the arrangements described herein are for illustrative purposes only. Therefore, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements may be omitted depending on the desired outcome. Furthermore, many of the described elements are functional entities that can be implemented as discrete or distributed components, or in any suitable combination and location with other components.

[0242] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, it can be implemented, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When executed on a computer and when the computer execution instructions are executed, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0243] Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access, or it can include one or more data storage devices such as servers or data centers that can be integrated with media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0244] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A communication method, characterized in that, Applied to a bus network, the bus network including a network management unit and bus devices, the method includes: The network management unit discovers the bus device and dynamically assigns a network address to the bus device; The network management unit sends a request message to the bus device. The request message is used to request access to the first configuration space register of the bus device. The request message includes the network address of the bus device and information about the first configuration space register. The network address is an address assigned to the bus device by the network management unit. The network management unit and the bus device belong to different hosts. The network management unit receives a response message from the bus device, wherein the request message and the response message are messages belonging to the transaction layer.

2. The method according to claim 1, characterized in that, The request message also includes a task identifier, and the response message includes the task identifier. The task identifier is used to determine that the response message is a message in response to the request message.

3. The method according to claim 1 or 2, characterized in that, The request message also includes first indication information, which indicates the operation type of the first configuration space register, including a read operation or a write operation.

4. The method according to claim 3, characterized in that, If the operation type of the first configuration space register is a write operation, the request message also includes the data to be written to the first configuration space register.

5. The method according to claim 4, characterized in that, The request message also includes a second indication, which indicates that the data be written into at least one byte of the first configuration space register.

6. The method according to claim 1 or 2, characterized in that, The information in the first configuration space register includes at least one of the following: The type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

7. The method according to claim 1 or 2, characterized in that, The response message indicates whether the operation on the first configuration space register was successful; or... If the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

8. The method according to claim 1 or 2, characterized in that, The response message also includes information indicating whether the response message is in response to a read operation or a write operation.

9. The method according to claim 1 or 2, characterized in that, The request message is also used to request access to the second configuration space register of the bus device. The request message also includes third indication information and information about the second configuration space register. The third indication information is used to indicate the operation type of the second configuration space register.

10. The method according to claim 1 or 2, characterized in that, The bus network includes multiple bus devices, and each bus device is any one of the multiple bus devices.

11. A communication method, characterized in that, Applied to a bus network, the bus network including a network management unit and bus devices, the method includes: The bus device receives a request message from the network management unit. The request message is used to request access to the first configuration space register of the bus device. The request message includes the network address of the bus device and information of the first configuration space register. The network address is an address dynamically allocated to the bus device by the network management unit. The bus device and the network management unit belong to different hosts. The bus device sends a response message to the network management unit, and the request message and the response message are messages belonging to the transaction layer.

12. The method according to claim 11, characterized in that, The request message also includes a task identifier, and the response message includes the task identifier. The task identifier is used to determine that the response message is a message in response to the request message.

13. The method according to claim 11 or 12, characterized in that, The request message further includes first indication information, which indicates the operation type of the first configuration space register, wherein the operation type of the first configuration space register includes: a read operation or a write operation.

14. The method according to claim 13, characterized in that, If the operation type of the first configuration space register is a write operation, the request message also includes the data to be written to the first configuration space register.

15. The method according to claim 14, characterized in that, The request message also includes a second indication, which indicates that the data be written into at least one byte of the first configuration space register.

16. The method according to claim 11 or 12, characterized in that, The information in the first configuration space register includes at least one of the following: The type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

17. The method according to claim 11 or 12, characterized in that, The response message indicates whether the operation on the first configuration space register was successful; or... If the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

18. The method according to claim 11 or 12, characterized in that, The response message also includes information indicating whether the response message is in response to a read operation or a write operation.

19. The method according to claim 11 or 12, characterized in that, The request message is also used to request access to the second configuration space register of the bus device. The request message also includes third indication information and information about the second configuration space register. The third indication information is used to indicate the operation type of the second configuration space register.

20. The method according to claim 11 or 12, characterized in that, The bus network includes multiple bus devices, and each bus device is any one of the multiple bus devices.

21. A communication method, characterized in that, Applied to a bus network, the bus network including a network management unit and bus devices, the method includes: The network management unit discovers the bus device and dynamically assigns a network address to the bus device; The network management unit sends a request message to the bus device. The request message is used to request access to the first configuration space register of the bus device. The request message includes the network address of the bus device and the information of the first configuration space register. The network address is the address assigned to the bus device by the network management unit. The network management unit and the bus device belong to different hosts. The bus device sends a response message to the network management unit, and the request message and the response message are messages belonging to the transaction layer.

22. A communication system, characterized in that, Includes network management unit and bus devices, The network management unit is used to discover the bus device and dynamically allocate network addresses to the bus device; The network management unit is configured to send a request message to the bus device. The request message is used to request access to the first configuration space register of the bus device. The request message includes the network address of the bus device and information of the first configuration space register. The network address is an address assigned to the bus device by the network management unit. The network management unit and the bus device belong to different hosts. The bus device is used to send response messages to the network management unit, wherein the request message and the response message are messages belonging to the transaction layer.

23. A communication device, characterized in that, include: A processor is configured to read instructions stored in a memory, and when the processor executes the instructions, cause the communication device to implement the method of any one of claims 1 to 10; or cause the communication device to implement the method of any one of claims 11 to 20.

24. A chip, characterized in that, include: At least one processing core is configured to perform the method as described in any one of claims 1 to 10; Alternatively, it can be used to perform the method as described in any one of claims 11 to 20.

25. A computer system, characterized in that, include: The chip as described in claim 24.

26. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, executes the method of any one of claims 1 to 10; or, when run on a computer, executes the method of any one of claims 11 to 20.

27. A computer-readable storage medium, characterized in that, The method includes a computer program that, when run on a computer system, causes a processing module in the computer system to perform the method as described in any one of claims 1 to 10; or, when run on a computer system, causes a processing module in the computer system to perform the method as described in any one of claims 11 to 20.

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