Large-scale operation acceleration system and method based on FPGA cluster
By employing a hybrid approach of network interconnection and bidirectional linear interconnection architecture in FPGA clusters, the bottleneck problem of data transmission between computing cores is solved, achieving efficient data sharing and improved computing performance.
Patent Information
- Application Number
- CN202510856614.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-10-28
AI Technical Summary
Existing computing clusters suffer from bandwidth bottlenecks in data transmission between computing cores when performing sparse matrix operations, leading to decreased computing performance, especially with significant resource waste when transmitting intermediate result data.
The FPGA cluster architecture adopts a hybrid of network interconnect architecture and bidirectional linear interconnect architecture. The computing cores are connected through the bidirectional linear interconnect architecture to parallelize data transmission tasks and use high-speed data interfaces for data transmission, thereby reducing the centralization of data transmission.
It enables efficient data sharing between computing cores, maximizes the use of bandwidth resources, reduces data transmission latency, and improves computing performance.
Smart Images
Figure CN120849335A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of large-scale computing hardware acceleration technology, and relates to a sparse matrix operation acceleration system and method based on FPGA cluster. Background Technology
[0002] Large-scale computations, such as sparse matrix operations, have wide applications in many scientific problems, including cardiac modeling and simulation, aerodynamic simulation, and fluid dynamics simulation. In the computational processes of these scientific problems, the most commonly used and complex sparse matrix operation is Sparse Matrix Vector Multiplication (SPMV), mathematically expressed as: A × b = x, where given a sparse matrix A and a vector b, find the vector x. Furthermore, in solving these scientific problems, the size of matrix A often reaches 10^6. 5 The computational speed of such large-scale operations is on the order of magnitude and above, and building computing clusters to accelerate such large-scale operations has always been a preferred method for researchers.
[0003] When performing large-scale operations such as sparse matrix-vector multiplication using computing clusters, data transfer between computing cores is a key factor limiting cluster performance. This data transfer can be broadly categorized into two types: ① Initialization data from the host computer to the memory of each computing core, which is transmitted infrequently and has low bandwidth requirements. This type of data has a fixed and dense transmission path. ② Intermediate result data, which is transmitted frequently and has high bandwidth requirements between computing cores. The transmission path for this type of data is often sparse within a single computation; therefore, building a fully connected network would result in a significant waste of bandwidth resources.
[0004] Currently, the network interconnection architecture commonly used in large-scale cluster computing suffers from significant bandwidth bottlenecks. For initial data with low bandwidth requirements, a network interconnection architecture based on 10 Gigabit Ethernet can meet the needs of most computations. However, when transmitting data between computing cores, each core must establish a data channel with all other cores, thus placing high demands on the bandwidth of the data center's switching nodes. As the number of nodes increases, computing cores in this design will have to reduce their processing speed to decrease data bandwidth requirements. This will weaken the original computing performance of the cores, increasing the overall solution time. Summary of the Invention
[0005] The purpose of this invention is to provide an FPGA cluster architecture that combines a network interconnect architecture and a bidirectional linear interconnect architecture to address the high bandwidth requirements for data transmission during large-scale operations such as solving large sparse matrices, and to propose a method for parallel data transmission tasks based on this architecture.
[0006] The technical solution adopted in this invention is as follows:
[0007] The large-scale computing acceleration system based on FPGA clusters adopts a hybrid FPGA cluster architecture combining network interconnect architecture and bidirectional linear interconnect architecture, including:
[0008] Multiple computing cores, each consisting of one or more FPGAs;
[0009] The host computer is connected to the computing core via a switch;
[0010] The computing core and the switch perform the sending of initialization data and the uploading of result data during large-scale computation.
[0011] The multiple computing cores adopt a bidirectional linear interconnect architecture, with all computing cores linearly connected. Adjacent computing cores are connected through a high-speed transmission interface for transmitting intermediate results during the solution process.
[0012] In the above technical solution, when each computing core contains multiple FPGAs, they have different task divisions. Specifically, the FPGA containing the system-on-a-chip is used to complete the interaction with the switch and the reconstruction of the FPGA, while the FPGA without the system-on-a-chip is used to complete the data calculation. Different FPGAs within the same computing core are connected using a high-speed transmission interface.
[0013] Furthermore, the aforementioned bidirectional linear interconnect architecture specifically refers to:
[0014] There are N computing cores in total. The FPGAs used to perform data calculations in all computing cores are numbered sequentially from front to back as FPGAs numbered 1 to N.
[0015] Each FPGA has two data transmission directions: from computing core 1 to computing core N (forward data transmission) and from computing core N to computing core 1 (reverse data transmission). The data in the two directions are independent of each other. That is, when the data on computing core 2 is transmitted on the forward data link, it will not return to computing core 1.
[0016] Each FPGA independently selects a master-slave mode for each transmission direction: Master or Slave. The data forwarding mechanism differs between the different modes.
[0017] In Master mode, while listening to and receiving data from the previous computing core, the computing core places its own data to be shared on the corresponding data link and propagates it backward.
[0018] In Slave mode, the computing core directly forwards the data received from the previous computing core to the data link.
[0019] Furthermore, when forwarding in Slave mode, the FPGA directly connects the high-speed data lines to the physical ports, thereby ensuring low latency in overall data transmission.
[0020] Furthermore, all data is transmitted in the form of data packets, and the information carried in the packet header includes: packet header identification code, data type, data source, and data length.
[0021] A method for accelerating large-scale computing based on FPGA clusters, implemented using any of the systems described above, includes the following:
[0022] The computation process is divided according to the computing power and number of FPGA computing cores used in the system and the scale of the problem to be computed;
[0023] For operations on large-scale sparse matrices, suppose there are N computational cores in the system. That is, the matrix is divided into N regions by rows according to N equal parts to obtain the initial data, and the data transmission task of all computational cores is obtained according to the data distribution in the sparse matrix.
[0024] Following the principle of high-order priority, data transmission tasks are merged and parallelized to obtain a data task table. Tasks that conform to the linear transmission rules are merged, and conflict-free tasks are parallelized. The computational core at the beginning of the linear transmission link is the highest bit. Tasks on the same linear transmission line are merged. For conflict-free tasks, two tasks will not use the same segment of the linear transmission line when they are executed.
[0025] Complete data preprocessing and obtain a master table of data transmission tasks;
[0026] Taking a sparse matrix as an example, suppose there are N computing cores in the system. That is, the matrix is divided into N regions by rows according to N equal parts to obtain the initial data, and the data transmission task of all computing cores is obtained according to the data distribution in the sparse matrix.
[0027] Data transfer tasks can be merged. For example, if the data of compute core 1 needs to be shared with both compute core 2 and compute core 3, then these two tasks can be merged into: compute core 1 sends data to compute core 2 and compute core 3 through a forward linear architecture.
[0028] When this task is executed, computing core 1 is the Master, computing core 2 is the Slave, and computing core 3 can be set as either Master or Slave according to its own data transfer task.
[0029] During task merging, in the forward transmission architecture, the task with computing core 1 has the highest priority, while in the reverse transmission architecture, the task with computing core N has the highest priority.
[0030] The shared data tasks are designed for conflict-free parallelization. When two tasks do not occupy the same part of the linear transmission architecture, they are parallelized. For example, if two tasks transfer data from core 1 to cores 2 and 3, and from core 4 to cores 5 and 6 respectively, these two tasks can be executed concurrently. During task parallelization, in the forward transmission architecture, the task on core 1 has the highest priority, and in the reverse transmission architecture, the task on core N has the highest priority. A master table of data transmission tasks is generated.
[0031] Furthermore, the method includes: the host computer sending initialization data and a data transmission task table to each computing core via a switch;
[0032] Each computing core performs computations in parallel after receiving initialization data, generating intermediate data to be shared. All computing cores share the intermediate data generated by each core and the intermediate data received, based on a bidirectional linear interconnect architecture and a data transmission task table. Intermediate data sharing among all computing cores is achieved through bidirectional transmission.
[0033] After the result data reaches the convergence condition, the computing core initiates the transmission of the result data to the host computer.
[0034] Beneficial effects
[0035] The method provided in this invention implements an FPGA cluster architecture for accelerating large-scale computations such as large sparse matrix operations. By using a proposed bidirectional linear interconnect architecture and data transmission task allocation method, data decentralization is achieved, enabling data sharing among all computing cores in a short time solely through high-speed data interfaces between FPGAs. In a computing cluster consisting of N computing core nodes, where each computing core has a computing bandwidth of B Gbps, this invention reduces the maximum bandwidth requirement from the original N*B Gbps to B Gbps. This effectively solves the problem of insufficient bandwidth, ensuring that data transmission is no longer a bottleneck limiting the computing power of FPGAs. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the FPGA cluster architecture in one embodiment of the present invention;
[0037] Figure 2 This describes the data distribution after sparse matrix partitioning and the data transmission task in this invention.
[0038] Figure 3 This invention describes the process of merging and parallelizing data transmission tasks.
[0039] Figure 4 This is a simplified hardware diagram of a single computing core board in one embodiment of the present invention;
[0040] Figure 5 This is a diagram illustrating the form of a data packet in one embodiment of the present invention;
[0041] Figure 6 This is a diagram illustrating the state changes of the computational kernel in one embodiment of the present invention. Detailed Implementation
[0042] The present invention will be further described below with reference to the embodiments, which include, but are not limited to, the following embodiments.
[0043] This invention provides a large-scale computing acceleration system and method based on FPGA clusters. The system uses multiple FPGA chips as computing cores, and its flexibility meets the data transmission path design requirements of this invention. The main FPGA resources used in this invention include: a high-speed transmission interface (Gigabit Transceiver, GT), a system-on-a-chip (SoC), various computing resources (such as lookup tables, triggers, on-chip DSPs, etc.), and memory resources (such as BRAM, URAM, etc.).
[0044] When using a high-speed data interface for data transmission between computing cores, this invention employs a basic serial-to-parallel conversion protocol to minimize transmission latency.
[0045] This invention uses a high-speed network protocol for the transmission of initialization data, and the host computer and FPGA are connected through a switch.
[0046] The communication architecture of the FPGA cluster in this invention is as follows: Figure 1 As shown in the diagram, each FPGA represents a computing core. The high-bandwidth data channel between each computing core is used to transmit intermediate results during the sparse matrix solution process, while the low-bandwidth data channel between the computing core and the switch is used to send initialization data and upload result data.
[0047] In this invention, a single computing core can be composed of one or more FPGAs, with different task divisions among the FPGAs. For example, FPGAs with on-chip systems (such as Xilinx's ZYNQ series chips) can be used to interact with the host computer and for FPGA reconfiguration, while FPGAs without on-chip systems are used to perform data calculations. FPGAs in the same computing core are connected using a high-speed data interface.
[0048] In this invention, all data is transmitted in the form of packets, and the packet header carries information such as packet header identification code, data type, data source, and data length.
[0049] In this invention, a bidirectional linear interconnect architecture is adopted between computing cores. The processing flow when performing large-scale sparse matrix operations using N computing cores is as follows:
[0050] 1. Divide the sparse matrix into N regions by row to obtain initial data and establish all data transmission tasks based on the data distribution.
[0051] 2. Data transmission tasks are merged and parallelized according to the high-order priority principle to obtain a transmission task table. Tasks conforming to the linear transmission rules can be merged, and conflict-free tasks can be parallelized. High-order priority: The computational core at the beginning of the linear transmission link is the highest-order bit. Linear transmission rules: Tasks on the same linear transmission line can be merged. Conflict-free tasks: Two tasks will not use the same segment of the linear transmission line during execution.
[0052] 3. The host computer sends initialization data and data transmission table to each computing core.
[0053] 4. The calculation core calculates the intermediate data to be shared and executes the transmission task according to the transmission task table.
[0054] 5. After the transmission is complete, the computing core continues to perform parallel computing.
[0055] 6. When the calculation kernel obtains the data to be shared again, repeat the above steps.
[0056] 7. Once the kernel obtains the solution to the sparse matrix or the calculation termination condition is met, the data is returned to the host computer, and the calculation is complete.
[0057] Figure 2 , 3 This example, using 8 computational cores, illustrates the process of matrix partitioning into the generation of the overall task table. Figure 2 The gray area represents a finite number of regions, while the others represent infinitely many. This bidirectional linear interconnect structure reduces the bandwidth pressure on data transmission between computing cores, achieves decentralized data transmission, and effectively solves the bandwidth problem in network interconnect architecture.
[0058] A computing cluster consisting of 8 computing cores is used to complete the task. Figure 2 Taking matrix operations as an example, each computing core has two FPGA chips: one is responsible for interacting with the host computer and reconstructing the FPGA (called F0), and the other is responsible for performing data operations (called F1). Figure 4 A simplified hardware diagram of a single computing core board.
[0059] The data packet format is as follows Figure 5As shown, the Packet Header is used to detect the packet header position, the Data Source is used to indicate the data source (host computer, calculation core numbered 1-20), the Data Info is used to identify the data type (initialization data, intermediate result data generated during the calculation process), the Data Length indicates the amount of data in the packet, and the Reserved bit.
[0060] The complete steps for an FPGA computing cluster to perform a sparse matrix solution are as follows:
[0061] 1. After power-on, FPGA0 completes the reconstruction of the FPGA chip and waits for the host computer to send initialization data.
[0062] 2. The host computer first sends the initialization data for computing core 4, which is then forwarded to F1 via F0. Then, the data is sent sequentially for cores 5, 3, 6... 1, 8.
[0063] 3. Each computing core performs calculations in parallel after receiving the initialization data until the data to be shared is generated.
[0064] 4. After all computing cores generate shared data, on the forward data link, core 1 switches its transmission mode to Master, core 2 becomes Master, core 3 becomes Slave, and so on; on the reverse data link, core 8 switches its mode to Master, core 6 becomes Slave, and so on.
[0065] 5. After completing its receiving task as a Slave on the forward data link, computing core #3 actively switches to Master mode to begin the next round of transmission and continues execution according to the data transmission task table. The status of the computing core during each transmission stage is as follows: Figure 6 As shown.
[0066] 6. Each computing core must add its own header to the front of the data packet when transmitting data as the Master.
[0067] 7. After bidirectional transmission, each computing core has the shared data it needs. The subsequent computing process is the same.
[0068] 8. After the result data meets the convergence condition of matrix solution, the computing core initiates the transmission of the result data to the host computer.
[0069] In this example, data transmission between FPGAs uses the high-speed GTH interface. The data exchange channel between computing cores consists of 16 pairs of high-speed interfaces. Assuming a data transmission line rate of 20.625 Gb / s, the maximum processing bandwidth of a single computing core is 41.25 GB / s.
[0070] The embodiments described above are merely some preferred embodiments of the present invention, and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.
Claims
1. A large-scale computing acceleration system based on FPGA clusters, characterized in that, An FPGA cluster architecture employing a hybrid of network interconnect architecture and bidirectional linear interconnect architecture includes: Multiple computing cores, each consisting of one or more FPGAs; The host computer is connected to the computing core via a switch; The initialization data is sent down and the result data is uploaded during the large-scale computation between the computing core and the switch; The multiple computing cores adopt a bidirectional linear interconnect architecture, with all computing cores linearly connected. Adjacent computing cores are connected through a high-speed transmission interface for transmitting intermediate results during the computation process.
2. The large-scale computing acceleration system based on FPGA cluster according to claim 1, characterized in that, When each computing core contains multiple FPGAs, they have different task assignments. FPGAs with on-chip systems are used to complete the interaction with the switch and FPGA reconfiguration, while FPGAs without on-chip systems are used to complete data calculations. Different FPGAs within the same computing core are connected using a high-speed transmission interface.
3. The large-scale computing acceleration system based on FPGA cluster according to claim 1, characterized in that, The aforementioned bidirectional linear interconnect architecture is specifically as follows: There are N computing cores in total. The FPGAs used to perform data calculations in all computing cores are numbered sequentially from front to back as FPGAs numbered 1 to N. Each FPGA has two data transmission directions: forward data transmission from computing core 1 to computing core N, and reverse data transmission from computing core N to computing core 1. The data transmission in these two directions is independent. Each FPGA independently selects a master / slave mode for each transmission direction: Master or Slave. The data forwarding mechanism differs between the different modes. In Master mode, while listening to and receiving data from the previous computing core, the computing core places its own data to be shared on the corresponding data link and propagates it backward. In Slave mode, the computing core directly forwards the data received from the previous computing core to the data link; When forwarding in Slave mode, the FPGA directly interconnects high-speed data lines on the physical ports, thereby ensuring low latency in overall data transmission.
4. The large-scale computing acceleration system based on FPGA cluster according to claim 1, characterized in that, All data is transmitted in the form of data packets, and the information carried in the packet header includes: packet header identification code, data type, data source, and data length.
5. A large-scale computing method based on FPGA clusters, characterized in that, Based on the system implementation as described in any one of claims 1-4, the method includes: Data transmission task allocation method: The computational tasks are divided according to the computing power and number of FPGA computing cores used in the system and the scale of the problems that need to be computed. For operations on large-scale sparse matrices, suppose there are N computational cores in the system. That is, the matrix is divided into N regions by rows according to N equal parts to obtain the initial data, and the data transmission task of all computational cores is obtained according to the data distribution in the sparse matrix. Following the principle of high-order priority, data transmission tasks are merged and parallelized to obtain a data task table. Tasks that conform to the linear transmission rules are merged, and conflict-free tasks are parallelized. The computational core at the beginning of the linear transmission link is the highest bit. Tasks on the same linear transmission line are merged. For conflict-free tasks, two tasks will not use the same segment of the linear transmission line when they are executed. Complete data preprocessing and obtain a summary table of data transmission tasks.
6. The large-scale computing method based on FPGA cluster as described in claim 5, characterized in that the method include: The host computer sends initialization data and data transmission task table to each computing core via a switch; Each computing core performs calculations in parallel after receiving the initialization data, generating intermediate data to be shared; All computing cores share the intermediate data to be shared and the intermediate data received by each computing core in sequence based on a bidirectional linear interconnect architecture and a data transmission task table; the sharing of intermediate data among all computing cores is achieved through bidirectional transmission. After the result data reaches the convergence condition, the computing core initiates the transmission of the result data to the host computer.