Mask transmission method and device, electronic equipment, storage medium and program product

Abstract

The present disclosure relates to the field of image rendering, and provides a mask transmission method and device, electronic equipment, storage medium and program product. The method is applied to a rendering pipeline of a graphics processor, and includes: performing rasterization processing on M primitives to determine M first masks, performing depth testing and / or stencil testing on the M first masks to determine M second masks; performing hidden surface removal testing on the M second masks to determine a third mask according to the M first masks; splitting the third mask to obtain M fourth masks, and the first mask and the fourth mask corresponding to the same primitive are the same; and inputting the M fourth masks into a pixel shader. The method not only ensures that the pixel shader can correctly receive the rasterized mask, but also avoids the defect that the depth / stencil testing and the hidden surface removal testing cannot be opened before the mask enters the pixel shader in one-way rendering pipeline, so that the graphics processor has lower design complexity and higher performance.

Description

Technical Field

[0001] This disclosure relates to the field of image rendering, and more particularly to a mask transmission method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] In the graphics processing unit (GPU) rendering pipeline, primitives undergo vertex processing, clipping, viewport transformation, and other operations before entering the rasterization stage. Rasterization calculates the positions of the pixels (or sampling points) covered by the primitives and then outputs a mask indicating the pixel (or sampling point) information covered by the primitives, along with the starting coordinates of the pixels, to the pixel shader.

[0003] In some applications, to improve image rendering quality, the rasterized mask undergoes a depth / stencil test and a hidden surface removal (HSR) test. Enabling the depth / stencil test and the hidden surface removal test may alter the rasterized mask and output a new mask. Only then does the mask output by the hidden surface removal test enter the pixel shader.

[0004] With operating system upgrades, Application Programming Interfaces (APIs) emerged that supported pixel shaders in processing data using rasterized masks. Since enabling depth / stencil testing and hidden face removal testing could alter the rasterized mask, adapting to the functionality of this API required two rendering pipelines to separately transmit the rasterized mask and the mask after hidden face removal testing. This significantly increased the design complexity of the graphics processor.

[0005] Existing technologies propose disabling depth / stencil testing and hidden face removal testing before the mask enters the pixel shader, enabling the rasterized mask to be transmitted to the pixel shader in a single rendering pipeline. This reduces the design complexity of the graphics processor (GPU), at the cost of reduced GPU performance. Therefore, ensuring the correct transmission of the rasterized mask to the pixel shader while maintaining low design complexity and high performance for the GPU has become a pressing technical problem. Summary of the Invention

[0006] In view of this, this disclosure proposes a mask transmission method, apparatus, electronic device, storage medium, and program product. The mask transmission method according to the embodiments of this disclosure improves the hidden face removal test mechanism, which not only ensures that the pixel shader can correctly receive the rasterized mask, but also avoids the defect that the depth / stencil test and hidden face removal test cannot be opened before the mask enters the pixel shader in one rendering pipeline, so that the graphics processor has lower design complexity and higher performance.

[0007] According to one aspect of this disclosure, a mask transmission method is provided, the method being applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the method comprising: performing rasterization on M primitives respectively to determine M first masks corresponding to the M primitives, where M is an integer greater than 1; performing depth testing and / or stencil testing on the M first masks respectively to determine M second masks corresponding to the M primitives respectively; performing hidden face removal testing on the M first masks based on the M second masks to determine a third mask corresponding to all M primitives; splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively, wherein the first and fourth masks corresponding to the same primitive are identical; and inputting the M fourth masks into the pixel shader in response to a first instruction.

[0008] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Each first mask comprises N masks corresponding to the N pixels, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels, each mask comprising K bits; the third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels, each mask comprising K bits.

[0009] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The step of performing a hidden surface removal test on the M first masks based on the M second masks to determine the third mask corresponding to all M primitives includes: processing the M first masks to obtain M fifth masks based on the M second masks, each fifth mask comprising N sets of masks corresponding to the N pixels, each set comprising K masks, and each mask comprising K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0010] In one possible implementation, the step of processing the M first masks according to the M second masks to obtain the M fifth masks includes: when the t-th bit of the j-th mask of the i-th second mask is equal to a first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the t-th bit of the j-th mask of the i-th second mask is equal to a second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0011] In one possible implementation, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: according to the stacking order of the M primitives, using the fifth mask corresponding to the later-stacked primitive to cover the fifth mask corresponding to the earlier-stacked primitive, thereby obtaining the third mask.

[0012] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: when the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the K second-value masks are used as the j-th mask of the i-th fourth mask.

[0013] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: the t-th mask corresponding to the j-th set of masks in the third mask for the i-th primitive. When the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, 0 < t ≤ K and are integers; when the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0014] In one possible implementation, the method further includes: performing a hidden face removal test on the M second masks to determine a sixth mask that corresponds to all M primitives; splitting the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and inputting the M eighth masks into the pixel shader in response to a second instruction.

[0015] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0016] In one possible implementation, the rendering pipeline corresponds to a cache used when performing hidden surface removal tests on the M first masks. The third mask includes N sets of masks corresponding to N pixels, each set of masks includes K masks, and each mask includes K bits, where N and K are integers greater than 1. The cache includes N storage locations, where the j-th storage location stores the j-th set of masks of the third mask, where 0 < j ≤ N and is an integer.

[0017] According to another aspect of this disclosure, a mask transmission apparatus is provided, the apparatus being applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the apparatus comprising: a rasterization module, configured to rasterize M primitives respectively, determining M first masks corresponding to the M primitives respectively, where M is an integer greater than 1; a first testing module, configured to perform depth testing and / or stencil testing on the M first masks respectively, determining M second masks corresponding to the M primitives respectively; a second testing module, configured to perform hidden face removal testing on the M first masks based on the M second masks, determining third masks corresponding to all M primitives; splitting the third masks to obtain M fourth masks corresponding to the M primitives respectively; and inputting the M fourth masks into the pixel shader in response to a first instruction.

[0018] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Each first mask comprises N masks corresponding to the N pixels, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels, each mask comprising K bits; the third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels, each mask comprising K bits.

[0019] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The step of performing a hidden surface removal test on the M first masks based on the M second masks to determine the third mask corresponding to all M primitives includes: processing the M first masks to obtain M fifth masks based on the M second masks, each fifth mask comprising N sets of masks corresponding to the N pixels, each set comprising K masks, and each mask comprising K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0020] In one possible implementation, the step of processing the M first masks according to the M second masks to obtain the M fifth masks includes: when the t-th bit of the j-th mask of the i-th second mask is equal to a first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the t-th bit of the j-th mask of the i-th second mask is equal to a second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0021] In one possible implementation, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: according to the stacking order of the M primitives, using the fifth mask corresponding to the later-stacked primitive to cover the fifth mask corresponding to the earlier-stacked primitive, thereby obtaining the third mask.

[0022] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: when the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the K second-value masks are used as the j-th mask of the i-th fourth mask.

[0023] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: the t-th mask corresponding to the j-th set of masks in the third mask for the i-th primitive. When the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, 0 < t ≤ K and are integers; when the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0024] In one possible implementation, the second test module is further configured to: perform a hidden face removal test on the M second masks to determine a sixth mask that corresponds to all M primitives; split the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and input the M eighth masks into the pixel shader in response to a second instruction.

[0025] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0026] In one possible implementation, the rendering pipeline corresponds to a cache, which is used during hidden face removal tests on the M first masks.

[0027] The third mask includes N sets of masks corresponding to N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1.

[0028] The cache includes N storage locations, where the j-th storage location stores the j-th group of the third mask, 0 < j ≤ N and is an integer.

[0029] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing instructions stored in the memory.

[0030] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0031] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0032] According to the mask transmission method of this disclosure, by performing rasterization processing on M primitives respectively, M first masks corresponding to the M primitives are determined, where M is an integer greater than 1, thus completing the rasterization of the primitives and obtaining the rasterized first masks; by performing depth testing and / or stencil testing on the M first masks respectively, M second masks corresponding to the M primitives can be determined, enabling the graphics processor to implement depth testing and / or stencil testing functions; based on the M second masks, hidden face removal testing is performed on the M first masks to determine the third masks corresponding to all M primitives; by splitting the third masks, M fourth masks corresponding to the M primitives can be obtained, enabling the graphics processor to implement hidden face removal testing functions; the first and fourth masks corresponding to the same primitive are the same, and in response to a first instruction, the M fourth masks are input into the pixel shader, ensuring that the pixel shader can correctly receive the rasterized masks. The mask transmission method of this disclosure is executed by a single rendering pipeline. It eliminates the need to disable early depth / stencil testing, reducing the amount of data entering the pixel shader and lowering the data processing pressure on the graphics processor. It also eliminates the need to enable late depth / stencil testing, reducing the rendering cycle time. Furthermore, it eliminates the need to disable hidden face removal testing, improving graphics processor performance. In summary, the mask transmission method of this disclosure improves the hidden face removal testing mechanism, ensuring that the pixel shader can correctly receive the rasterized mask while avoiding the drawback of depth / stencil testing and hidden face removal testing not being enabled before the mask enters the pixel shader in a single rendering pipeline. This results in a graphics processor with lower design complexity and higher performance.

[0033] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0034] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0035] Figure 1 An example of a rasterized mask is shown.

[0036] Figure 2 This shows another example of a mask after rasterization.

[0037] Figure 3 An example of a mask after an early depth / template test is shown.

[0038] Figure 4 This shows an example of a mask after a hidden face removal test.

[0039] Figure 5aThis illustrates an exemplary application scenario of the mask transmission method according to embodiments of the present disclosure.

[0040] Figure 5b This illustrates an exemplary application scenario of the mask transmission method according to embodiments of the present disclosure.

[0041] Figure 6 A schematic diagram illustrating the flow of a mask transmission method according to an embodiment of the present disclosure is shown.

[0042] Figure 7 Examples are shown of the mask determined in each step of the mask transmission method according to embodiments of the present disclosure, and the indicated sampling point coverage.

[0043] Figure 8 A schematic diagram of a cache according to an embodiment of the present disclosure is shown.

[0044] Figure 9 A schematic diagram of a seventh mask according to an embodiment of the present disclosure is shown.

[0045] Figure 10 A schematic diagram illustrating an exemplary flow of a mask transmission method according to an embodiment of the present disclosure is shown.

[0046] Figure 11 A schematic diagram showing the structure of a mask transmission apparatus according to an embodiment of the present disclosure is provided.

[0047] Figure 12 A block diagram of an apparatus 1900 according to an embodiment of the present disclosure is shown. Detailed Implementation

[0048] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0049] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0050] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0051] The principles of mask generation and transmission are explained below.

[0052] In the Graphics Processing Unit (GPU) rendering pipeline, after primitives undergo vertex processing, clipping, and viewport transformation, they enter the rasterization stage. Rasterization calculates the positions of the pixels (or sampling points) covered by the primitives, and then outputs a mask indicating the pixel (or sampling point) information covered by the primitives, along with the starting coordinates of the pixels, to the pixel shader for shading. The mask indicates the coverage of pixels (or sampling points) by the primitives.

[0053] Figure 1 An example of a rasterized mask is shown.

[0054] like Figure 1 As shown, the pixel block consists of four pixels, P3-P0. Assuming that each pixel corresponds to a sampling point during rasterization and is located at the center of the pixel, the triangular primitive covers the sampling points of pixels P2-P0 but not the sampling point of pixel P3. Each sampling point corresponds to a one-bit binary mask. The mask for a covered sampling point can be 1, and the mask for an uncovered sampling point can be 0. Therefore, the mask for this pixel block can be 0111 (in the order of pixels P3-P0).

[0055] The mask output from the rasterization stage can be called the raster mask. Since the starting coordinates of the pixels are known, combining the mask and the starting coordinates makes it easy to calculate whether each pixel is covered. Of course, in a graphics processor, a pixel block may contain more than four pixels; it could be a 32x32 or 8x8 pixel block. For these pixel blocks containing a large number of pixels, it is more convenient to pass information about whether a pixel (or sampling point) has a value in the rendering pipeline using a mask and starting coordinates.

[0056] If multisample antialiasing (MSAA) is used during rasterization, more sampling points will be rasterized for a single pixel, and the number of mask bits will also increase. Figure 2 Another example of a rasterized mask is shown. For ease of understanding, the following description uses 4 sample points per pixel (i.e., MSAA 4x) as an example. It should be understood that this disclosure is not limited to this, and for example, it also applies to cases with 2 to 16 sample points per pixel (e.g., MSAA 2x, MSAA 8x, MSAA 16x).

[0057] like Figure 2As shown, the pixel block includes 4 pixels P3-P0, each pixel includes 4 sampling points, and the pixel block includes a total of 16 sampling points. One sampling point corresponds to one bit of binary mask, so each pixel has a 4-bit mask, and the pixel block mask has 16 bits. The sampling points of pixel P3 are not covered, so the mask for pixel P3 is 0000. The sampling points of pixel P2 are all covered, so the mask for pixel P2 is 1111. The first and third sampling points of pixel P1 (in bottom-up order, which will be the same throughout) are not covered, while the second and fourth sampling points are covered, so the mask for pixel P1 is 0101. The sampling points of pixel P0 are all covered, so the mask for pixel P0 is 1111. Therefore, the mask for the pixel block is 00001111 01011111 (in the order of pixels P3-P0).

[0058] In some applications, to improve image rendering quality, the rasterized mask undergoes a depth / stencil test. This test determines whether the coverage of pixels (or sampling points) by the primitives determined by rasterization is valid; some previously valid coverage may be deemed invalid. The mask output from the depth / stencil test indicates the sampling point information covered by the primitives after the test. Only then does the mask output from the depth / stencil test enter the pixel shader. This depth / stencil test, performed before the mask enters the pixel shader, is also called an early depth / stencil test. Figure 3 An example of a mask after an early depth / template test is shown.

[0059] like Figure 3 As shown, the original mask of the rasterized pixel block is 0000 1111 0101 1111. A depth / stencil test might determine that the primitive does not cover the 4th sampling point of pixel P0 and the 1st and 3rd sampling points of pixel P2. Based on this determination, the mask output is 0000 0101 0101 1110. This mask output by the depth / stencil test can be called the active mask. If all 4 bits of the mask corresponding to a pixel are 0, the pixel shader does not need to determine the color of that pixel when it is covered by the triangular primitive. Therefore, depth / stencil testing can significantly reduce the data processing cost of the pixel shader.

[0060] For rendering pipelines employing a tile-based deferred rendering (TBDR) architecture, the mask after the depth / stencil test must also undergo a hidden surface removal (HSR) test. This test determines whether the primitive's coverage of pixels (or sample points) determined after the depth / stencil test is valid. Some coverages that were originally valid may be deemed invalid because they are covered by pixels or sample points of other primitives. The mask output by the hidden surface removal test indicates the sample point information covered by the primitive after the hidden surface removal test. Only then does the mask output by the hidden surface removal test enter the pixel shader.

[0061] Figure 4 This shows an example of a mask after a hidden face removal test. For clarity, in... Figure 4 Only one pixel is shown.

[0062] like Figure 4 As shown, assume there are 4 sampling points during pixel rasterization. The mask after rasterization of primitive A can be 1111, and the mask output from the depth / stencil test can be 1110. In this case, primitive A covers the 1st to 3rd sampling points (in bottom-to-top order). The mask after rasterization of primitive B can be 1101, and the mask output from the depth / stencil test can also be 1101. In this case, primitive B covers the 1st, 2nd, and 4th sampling points (in bottom-to-top order). Assuming primitive B covers primitive A, the 1st, 2nd, and 4th sampling points of the pixel (in bottom-to-top order) will display the color of primitive B, and the 3rd sampling point will display the color of primitive A. Whether the 1st, 2nd, and 4th bits of the mask corresponding to primitive A input to the pixel shader have values ​​does not affect the shading. To save shading costs, the 1st, 2nd, and 4th bits of the mask can be set to 0, that is, the mask output from the hidden face removal test of primitive A is 0010. Primitive B is not covered by other primitives, so the mask of primitive B output by the hidden face removal test is still 1101. In this case, the mask of primitive A input to the pixel shader and the mask of primitive A after rasterization differ.

[0063] With operating system upgrades, Application Programming Interfaces (APIs) emerged, such as DirectX 11, that supported pixel shaders in processing data using rasterized masks. This API allowed the use of rasterized masks as input attributes for data calculations or centroid interpolation. Because enabling depth / stencil testing and hidden face removal testing could alter the rasterized mask, two rendering pipelines were needed to handle the rasterized mask and the mask after hidden face removal testing, respectively. Limited by mask buffer size, this significantly increased the design complexity of the graphics processor.

[0064] Existing technical solutions employ a simplified approach: the mask is still transmitted through a single rendering pipeline from the rasterization stage to the pixel shader. If it is known in advance that the pixel shader uses the rasterized mask, early depth / stencil tests are directly disabled, along with hidden face removal tests, to ensure that the mask obtained by the pixel shader is consistent with the rasterized mask. Depth / stencil tests are then initiated after the pixel processor has completed shading; this type of depth / stencil test, performed after the mask enters the pixel shader, is also known as a late depth / stencil test.

[0065] While this existing technical solution achieves the transmission of the rasterized mask to the pixel shader through a single rendering pipeline, reducing the design complexity of the graphics processor, it comes at the cost of reduced graphics processor performance. The inventors discovered that this performance reduction manifests itself in the following ways:

[0066] 1. Forcibly disabling early depth / stencil testing may cause a surge in the number of pixels entering the pixel shader. For example, in scenes involving overdraw, other pixels will be drawn again at the location of an existing pixel. Originally, early depth / stencil testing could remove most of the pixels in advance, but now the masks of these pixels have to enter the pixel shader, increasing the data processing pressure on the graphics processor.

[0067] 2. Forcibly enabling late-stage depth / template testing will extend the entire rendering cycle accordingly.

[0068] 3. Hidden face removal test is a key technology for improving performance based on tile-based deferred rendering architecture. Forcibly disabling this function will undoubtedly lead to a further decrease in graphics processor performance.

[0069] Therefore, how to ensure that the rasterized mask is correctly transmitted to the pixel shader while the graphics processor has low design complexity and high performance has become an urgent technical problem to be solved.

[0070] In view of this, this disclosure proposes a mask transmission method, apparatus, electronic device, storage medium, and program product. The mask transmission method according to the embodiments of this disclosure improves the hidden face removal test mechanism, which not only ensures that the pixel shader can correctly receive the rasterized mask, but also avoids the defect that the depth / stencil test and hidden face removal test cannot be opened before the mask enters the pixel shader in one rendering pipeline, so that the graphics processor has lower design complexity and higher performance.

[0071] Figure 5a and Figure 5b This illustrates an exemplary application scenario of the mask transmission method according to embodiments of the present disclosure.

[0072] exist Figure 5a and Figure 5b In the illustrated application scenario, the graphics processor includes a rendering pipeline that supports tile-based deferred rendering and can be used to render an image comprising N pixels (N is an integer greater than 1). This rendering pipeline may include a rasterization module (for rasterization processing), a first testing module (for depth / stencil testing), a second testing module (for hidden face removal testing), and pixel shaders. The first testing module may perform only depth testing, only stencil testing, or both depth and stencil testing; this disclosure does not impose any limitations on this aspect.

[0073] exist Figure 5a In the application scenario shown, in the rendering pipeline, multiple primitives are input into the rasterization module after vertex processing, clipping, and viewport transformation. After rasterization, one mask (i.e., the first mask mentioned below) is output to the first test module. After the first test module completes the depth / stencil test, two masks (i.e., the first mask and the second mask mentioned below) are output to the second test module. After the second test module completes the hidden face removal test (and splitting), one mask (i.e., the fourth mask mentioned below) can be output to the pixel shader. This mask and the rasterized mask (i.e., the first mask mentioned below) can be the same.

[0074] exist Figure 5bIn the application scenario shown, in the rendering pipeline, multiple primitives are input into the rasterization module after vertex processing, clipping, and viewport transformation. After rasterization, one mask (the first mask mentioned below) is output to the first test module. After the first test module completes the depth / stencil test, two masks (the first and second masks mentioned below) are output to the second test module. After the second test module completes the hidden face removal test (and splitting), two masks can be output to the pixel shader. The first mask (the fourth mask mentioned below) and the rasterized mask (the first mask mentioned below) can be the same. The second mask (the eighth mask mentioned below) and the mask obtained after rasterization, depth / stencil testing, and hidden face removal testing according to existing technology can be the same.

[0075] Figure 5a and Figure 5b The functions of each module in the rendering pipeline shown can be found in the following description of the mask transmission method.

[0076] Figure 6 A schematic diagram illustrating the flow of a mask transmission method according to an embodiment of the present disclosure is shown.

[0077] like Figure 6 As shown, in one possible implementation, this disclosure proposes a mask transmission method applied to the rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the method comprising:

[0078] Step S61: Rasterize the M primitives respectively to determine the M first masks corresponding to the M primitives, where M is an integer greater than 1;

[0079] Step S62: Perform depth testing and / or template testing on the M first masks respectively to determine the M second masks corresponding to the M primitives;

[0080] Step S63: Based on the M second masks, perform hidden surface removal tests on the M first masks to determine the third mask that corresponds to all M primitives;

[0081] Step S64: Split the third mask to obtain M fourth masks corresponding to M primitives. The first and fourth masks corresponding to the same primitive are the same.

[0082] In step S65, in response to the first instruction, M fourth masks are input into the pixel shader.

[0083] For example, the structure of the rendering pipeline can be found in [reference needed]. Figure 5a and Figure 5b Examples.

[0084] Step S61 can be completed by the rasterization module. The M primitives (primitive 1 to primitive M) received by the rasterization module can be primitives after vertex processing, clipping, and viewport transformation. M can be an integer greater than 1. The rasterization module performs rasterization processing on the M primitives respectively, and can determine the M first masks (mask G1 to mask GM) corresponding to the M primitives. Among them, primitive 1 corresponds to mask G1, ..., primitive M corresponds to mask GM.

[0085] The rendering pipeline is used to render M primitives to generate an image containing N pixels (N is an integer greater than 1). Therefore, when performing rasterization processing on any primitive in step S61, it can determine which of the N pixels the primitive covers, and specifically which sampling points of the pixels it covers. The first mask corresponding to the primitive, determined by the rasterization process, can indicate the sampling point information covered by the primitive after rasterization. An example of the first mask can be found later. Figure 7 Related descriptions.

[0086] Rasterization can be achieved using existing technologies, and the specific implementation methods of rasterization will not be elaborated here.

[0087] The rasterization module can output M first masks (mask G1 - mask GM) and the starting address of the pixel (not shown) to the first test module. Step S62 can be completed by the first test module.

[0088] The first test module executes step S62, performing depth testing and / or template testing on the M first masks (mask G1-mask GM) respectively, which determines the M second masks (mask S1-mask SM) corresponding to the M primitives. The mask determined by depth testing and / or template testing of mask G1 can be mask S1, and the mask determined by depth testing and / or template testing of mask GM can be mask SM. Primitive 1 corresponds to mask G1, ..., primitive M corresponds to mask GM; therefore, primitive 1 corresponds to mask S1, ..., primitive M corresponds to mask SM. Examples of the second masks can be found later. Figure 7 Related descriptions.

[0089] When performing step S62 to perform depth testing and / or stencil testing on the first mask corresponding to any primitive, it may be necessary to determine whether the coverage of the primitive indicated by the first mask on each sampling point is still valid. If the rasterization process determines that the primitive covers a sampling point, and the depth testing and / or stencil testing determines that the primitive no longer covers that sampling point, then the coverage of that sampling point by the primitive indicated by the first mask may be invalid. Conversely, if the rasterization process determines that the primitive covers a sampling point, and the depth testing and / or stencil testing determines that the primitive still covers that sampling point, then the coverage of that sampling point by the primitive indicated by the first mask may be valid.

[0090] The first test module can determine the second mask corresponding to the graphic element based on the first mask corresponding to the graphic element and the effective coverage of the graphic element to each sampling point after the depth test and / or template test, so that the second mask indicates the sampling point information covered by the graphic element after the depth test and / or template test.

[0091] Deep testing and template testing can be implemented based on existing technologies, and the specific implementation methods of deep testing and template testing will not be elaborated here.

[0092] The first test module can output M first masks (mask G1 - mask GM) and M second masks (mask S1 - mask SM) to the second test module via two separate outputs. The starting address of the pixel can be output via either output. Steps S63-S65 can be completed by the second test module.

[0093] The second test module first executes step S63, which performs a hidden face removal test on the M first masks based on the M second masks, and determines a third mask D3 corresponding to all M primitives. That is, there are M first masks, M second masks, and one third mask. The implementation of the hidden face removal test in step S63 can differ from existing hidden face removal tests. For example, when performing the hidden face removal test in step S63, the pixel-level mask in each first mask can be extended to the sampling point level to obtain the corresponding fifth mask (the extension method is determined by the second mask corresponding to each first mask). Then, the fifth masks corresponding to multiple primitives are layered according to the primitive coverage order, and the final coverage result of the M fifth masks is the third mask D3. Therefore, the third mask D3 corresponds to all M primitives. At this time, the third mask D3 can indicate which sampling points each primitive serves as the top primitive, and when serving as the top primitive of a sampling point, it indicates the coverage of each sampling point in the pixel containing that sampling point. (After the fifth mask coverage ends, if the fifth mask corresponding to a certain sampling point covered by a certain primitive is still valid, that primitive is the top-level primitive of that sampling point.) Examples of extension methods and fifth and third masks can be found in [link to relevant documentation]. Figure 7 Related descriptions.

[0094] The second test module then executes step S64 to split the third mask D3. The purpose of splitting is to extract the parts of the third mask D3 that are related to each primitive, and obtain M fourth masks (mask Y1-mask YM) that are the same as the M first masks. Among them, primitive 1 corresponds to mask Y1, ..., primitive M corresponds to mask YM.

[0095] The user can instruct the pixel shader on which mask to use for data processing. For example, a first instruction can be given when the pixel shader uses a rasterized mask for data processing. The second test module then executes step S65, responding to the first instruction by inputting M fourth masks (identical to the M first masks) into the pixel shader. Simultaneously, the starting address of the pixel (not shown) can also be output to the pixel shader. When the pixel shader uses the fourth masks for data processing, the effect is the same as using the rasterized mask (first mask); that is, the pixel shader can output color data for N pixels based on masks Y1-YM and the starting address of the pixel. Subsequently, an image to be rendered to the screen can be generated based on this color data.

[0096] If it can be determined in advance that the pixel shader will use a rasterized mask for data processing, the first indication can be pre-stored in a specific location, such as memory, and after the graphics processor's rendering pipeline is started, the processor reads the first indication from memory and outputs it to the rendering pipeline. This disclosure does not limit the source of the first indication.

[0097] In this case, the graphics processor can make the input pixel shader mask consistent with the rasterized mask while using one rendering pipeline and retaining the early depth / stencil test and hidden face removal test, thus conforming to the capabilities of specific application programming interfaces such as DirectX 11.

[0098] According to the mask transmission method of this disclosure, by performing rasterization processing on M primitives respectively, M first masks corresponding to the M primitives are determined, where M is an integer greater than 1, thus completing the rasterization of the primitives and obtaining the rasterized first masks; by performing depth testing and / or stencil testing on the M first masks respectively, M second masks corresponding to the M primitives can be determined, enabling the graphics processor to implement depth testing and / or stencil testing functions; based on the M second masks, hidden face removal testing is performed on the M first masks to determine the third masks corresponding to all M primitives; by splitting the third masks, M fourth masks corresponding to the M primitives can be obtained, enabling the graphics processor to implement hidden face removal testing functions; the first and fourth masks corresponding to the same primitive are the same, and in response to a first instruction, the M fourth masks are input into the pixel shader, ensuring that the pixel shader can correctly receive the rasterized masks. The mask transmission method of this disclosure is executed by a single rendering pipeline. It eliminates the need to disable early depth / stencil testing, reducing the amount of data entering the pixel shader and lowering the data processing pressure on the graphics processor. It also eliminates the need to enable late depth / stencil testing, reducing the rendering cycle time. Furthermore, it eliminates the need to disable hidden face removal testing, improving graphics processor performance. In summary, the mask transmission method of this disclosure improves the hidden face removal testing mechanism, ensuring that the pixel shader can correctly receive the rasterized mask while avoiding the drawback of depth / stencil testing and hidden face removal testing not being enabled before the mask enters the pixel shader in a single rendering pipeline. This results in a graphics processor with lower design complexity and higher performance.

[0099] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0100] Because the rendering pipeline retains the hidden face removal test functionality, it can support tile-based deferred rendering. It is understood that the rendering pipeline can also support other rendering methods that require hidden face removal testing, as implemented in existing technologies. This disclosure does not limit the specific rendering methods supported by the rendering pipeline.

[0101] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image comprising N pixels, where each pixel comprises K sample points, and N and K are integers greater than 1.

[0102] Each first mask includes N masks corresponding to N pixels, and each mask includes K bits;

[0103] Each second mask includes N masks corresponding to N pixels, and each mask includes K bits;

[0104] The third mask includes N sets of masks corresponding to N pixels, each set of masks includes K masks, and each mask includes K bits;

[0105] Each fourth mask includes N masks corresponding to N pixels, and each mask includes K bits.

[0106] For example, the rendering pipeline can be used to render M primitives to generate an image comprising N pixels, where each pixel may include K sampling points. K can be an integer greater than 1, such as equal to 2, 4, 6, 8, 16, etc. This disclosure does not limit the specific value of K.

[0107] M primitives correspond to M first masks, therefore the first masks are primitive-level masks. Each primitive includes N pixels, so each first mask includes N masks corresponding to N pixels, and each mask in the first mask is a pixel-level mask. Each pixel includes K sampling points. During rasterization in step S61, one sampling point corresponds to one bit of binary mask; therefore, each mask in the first mask can include K bits.

[0108] M primitives correspond to M second masks, therefore the second masks are primitive-level masks. Each primitive includes N pixels, ensuring that each second mask includes N masks corresponding to N pixels, and each mask in the second mask is a pixel-level mask. Each pixel includes K sampling points. During depth testing and / or template testing in step S62, one sampling point corresponds to one bit of binary mask; therefore, each mask in the second mask can include K bits.

[0109] The third mask corresponds to all M primitives, therefore it is an image-level mask. Each primitive includes N pixels, allowing the third mask to include N sets of masks corresponding to each of the N pixels. Each pixel includes K sampling points. During the hidden surface removal test in step S63, each set of masks in the third mask can include K masks corresponding to the K sampling points. That is, each mask in each set corresponds to a sampling point, therefore each set of masks is a sampling point-level mask. Each mask in each set can include K bits.

[0110] M primitives correspond to M fourth masks, therefore the fourth mask is a primitive-level mask. Each primitive includes N pixels, so each fourth mask includes N masks corresponding to N pixels, and each mask in the fourth mask is a pixel-level mask. Each pixel includes K sampling points. During the splitting process in step S64, one sampling point corresponds to one bit of binary mask; therefore, each mask in the fourth mask can include K bits.

[0111] Figure 7Examples are shown of the mask determined in each step of the mask transmission method according to embodiments of the present disclosure, and the indicated sampling point coverage.

[0112] Assuming M=2, N=4, and K=4, the mask transmission method of this embodiment is applied to a scenario where two primitives (primitive 1 and primitive 2) are rendered. The rendered image includes four pixels, and each pixel includes four sampling points. For clarity, Figure 7 The image only shows the coverage of primitive 1 and primitive 2 for the four sampling points of the first pixel.

[0113] After the rasterization process in step S61, primitive 1 can obtain mask G1 (first mask). Mask G1 may include masks G11-G14, where mask G11 corresponds to the first pixel. See also Figure 7 The mask G11 can include 4 bits. After rasterization, primitive 1 can cover the first to fourth sampling points of the first pixel (in order from bottom to top). Therefore, the mask G11 can be 1111.

[0114] After primitive 2 is rasterized in step S61, mask G2 (first mask) can be obtained. Mask G2 may include masks G21-G24, where mask G21 corresponds to the first pixel. See also Figure 7 The mask G21 can include 4 bits. After rasterization, primitive 2 can cover the 1st, 2nd, and 4th sampling points of the 1st pixel (in order from bottom to top). Therefore, the mask G21 can be 1101.

[0115] After the depth test and / or stencil test in step S62, mask G1 (first mask) yields mask S1 (second mask). Mask S1 corresponds to primitive 1. Mask S1 may include masks S11-S14, where mask S11 corresponds to the first pixel. See also Figure 7 The mask S11 can include 4 bits. After the depth test and / or template test, the coverage of the second sampling point of the first pixel by primitive 1 becomes invalid, while the coverage of the first, third and fourth sampling points of the first pixel by primitive 1 is still valid (in the order from bottom to top). Therefore, the mask S11 can be 1011.

[0116] After the depth test and / or stencil test in step S62, mask G2 (first mask) yields mask S2 (second mask). Mask S2 corresponds to primitive 2. Mask S2 may include masks S21-S24, where mask S21 corresponds to the first pixel. See also... Figure 7 The mask S21 can include 4 bits. After the depth test and / or template test, the coverage of the first, second and fourth sampling points of the first pixel by primitive 2 is still valid (in the order from bottom to top). Therefore, the mask S21 can be 1101.

[0117] After the hidden surface removal test in step S63, masks G1 and G2 (first masks) yield mask D3 (third mask). Mask D3 corresponds to primitive 1 and primitive 2. Mask D3 may include a first group of masks D31 to a fourth group of masks D34, where the first group of masks D31 corresponds to the first pixel. See also... Figure 7 The first group of masks, D31, can include masks D311-D314, where mask D311 corresponds to the first sampling point s0 of the first pixel, mask D312 corresponds to the second sampling point s1 of the first pixel, mask D313 corresponds to the third sampling point s2 of the first pixel, and mask D314 corresponds to the fourth sampling point s3 of the first pixel. Masks D311-D314 can each contain 4 bits. Figure 7 In the example, mask D311 can be 1101, mask D312 can be 1101, mask D313 can be 1111, and mask D314 can be 1101. Mask D3 can be 11011101 1111 1101. An exemplary method for determining the values ​​of masks D311-D314 can be found in the further description of step S63 below.

[0118] After the splitting process in step S64, mask D3 (the third mask) yields mask Y1 and mask Y2 (the fourth mask). Mask Y1 corresponds to primitive 1, and mask Y2 corresponds to primitive 2. Mask Y1 may include masks Y11-Y14, where mask Y11 corresponds to the first pixel. Mask Y11 may include 4 bits... Figure 7 In the example, mask Y11 can be 1111. Mask Y2 can include masks Y21-Y24, where mask Y21 corresponds to the first pixel. Mask Y21 can include 4 bits, in Figure 7 In the example, mask Y21 can be 1101. An exemplary method for determining the values ​​of mask Y11 and mask Y21 can be found in the further description of step S63 below.

[0119] The following describes an exemplary implementation of the hidden face removal test in step S63.

[0120] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Step S63 includes:

[0121] Based on the M second masks, the M first masks are processed to obtain the M fifth masks. Each fifth mask includes N sets of masks corresponding to N pixels. Each set of masks includes K masks, and each mask includes K bits.

[0122] Perform hidden surface removal tests on M fifth masks to determine the third mask.

[0123] For example, in step S63, M first masks can be processed based on M second masks to obtain M fifth masks. Therefore, the fifth masks are primitive-level masks. When processing the M first masks to obtain the M fifth masks, the pixel-level mask in each first mask can be extended to the sampling point level, thus obtaining the fifth mask corresponding to that first mask. Each first mask includes N masks corresponding to N pixels, and each fifth mask includes N groups of masks corresponding to N pixels. That is, one mask (pixel level) in the first mask is extended into one group of masks (sampling point level) in the fifth mask. Each mask in the first mask includes K bits. The number of masks in each extended group can be equal to the number of sampling points per pixel, i.e., each group can include K masks, and each mask can include K bits.

[0124] Still with Figure 7 For example, step S63 can process mask G1 (first mask) based on mask S1 (second mask) to obtain mask G_1 (fifth mask). Mask G_1 may include the first group of masks G_11 to the fourth group of masks G_14, where the first group of masks G_11 corresponds to the first pixel. See also Figure 7 The first group of masks G_11 can include masks G_111-G_114, where mask G_111 corresponds to the first sampling point s0 of the first pixel, mask G_112 corresponds to the second sampling point s1 of the first pixel, mask G_113 corresponds to the third sampling point s2 of the first pixel, and mask G_114 corresponds to the fourth sampling point s3 of the first pixel. Masks G_111-G_114 can each contain 4 bits. Figure 7 In the example, mask G_111 can be 1111, mask G_112 can be 0000, mask G_113 can be 1111, and mask G_114 can be 1111. Mask G_11 can be 1111 00001111 1111. An exemplary method for determining the values ​​of masks G_111-G_114 can be found in the further description of step S63 below.

[0125] Step S63 can process mask G2 (first mask) based on mask S2 (second mask) to obtain mask G_2 (fifth mask). Mask G_2 may include the first group of masks G_21 to the fourth group of masks G_24, where the first group of masks G_21 corresponds to the first pixel. See also... Figure 7The first group of masks G_21 can include masks G_211-G_214, where mask G_211 corresponds to the first sampling point s0 of the first pixel, mask G_212 corresponds to the second sampling point s1 of the first pixel, mask G_213 corresponds to the third sampling point s2 of the first pixel, and mask G_214 corresponds to the fourth sampling point s3 of the first pixel. Masks G_211-G_214 can each contain 4 bits. Figure 7 In the example, mask G_211 can be 1101, mask G_212 can be 1101, mask G_213 can be 0000, and mask G_214 can be 1101. Mask G_21 can be 1101 110100001101. An exemplary method for determining the values ​​of masks G_211-G_214 can be found in the further description of step S63 below.

[0126] After expansion, the fifth mask corresponding to the M primitives is used as the object of the hidden surface removal test. The third mask is obtained by processing it according to the existing implementation method of hidden surface removal testing. The hidden surface removal test does not change the number of bits in the mask; therefore, the data structure of the fifth and third masks can be the same, both including N sets of masks, each set containing K masks, and each mask containing K bits. In this case, each mask in each set of the third mask corresponds to a sampling point; therefore, each set of masks in the third mask is also a sampling point-level mask.

[0127] For example, masks G_1 and G_2 can be used as objects for hidden face removal testing, ultimately resulting in a third mask D3. The third mask D3 can include the first set of masks D31 through the fourth set of masks D34, where the first set of masks D31 corresponds to the first pixel. See also... Figure 7 The first group of masks D31 may include masks D311-D314, where mask D311 corresponds to the first sampling point s0 of the first pixel, mask D312 corresponds to the second sampling point s1 of the first pixel, mask D313 corresponds to the third sampling point s2 of the first pixel, and mask D314 corresponds to the fourth sampling point s3 of the first pixel. Masks D311-D314 may include 4 bits. Mask D311 may be 1101, mask D312 may be 1101, mask D313 may be 1111, and mask D314 may be 1101. Mask D31 may be 1101 1101 1111 1101. An exemplary method for determining the values ​​of masks D311-D314 can be found in the further description of step S63 below.

[0128] The following is combined with Figure 7 An exemplary method is described to extend a single mask corresponding to a pixel in the first mask to a set of masks corresponding to that pixel in the fifth mask.

[0129] In one possible implementation, step S63 involves processing the M first masks based on the M second masks to obtain M fifth masks, including:

[0130] When the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of the i-th fifth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer;

[0131] When the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th fifth mask.

[0132] For example, the i-th primitive (0 < i ≤ M and is an integer) corresponds to the i-th second mask, the i-th first mask, and the i-th fifth mask. For instance, the first primitive (primitive 1) corresponds to the first second mask (S1), the first first mask (G1), and the first fifth mask (G_1). The second primitive (primitive 2) corresponds to the second second mask (S2), the second first mask (G2), and the second fifth mask (G_2).

[0133] The first value may, for example, represent a value indicating that the sampling point is covered, and in this embodiment, it may be 1. The second value may, for example, represent a value indicating that the sampling point is not covered, and in this embodiment, it may be 0. It is understood that the first value and the second value may also be set to other values, as long as the first value indicates that the sampling point is covered and the second value indicates that the sampling point is not covered, this disclosure does not impose any restrictions on this.

[0134] Figure 7The example shows the first pixel, taking j=1 as an example. When the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of the i-th fifth mask. Alternatively, when the t-th bit of the first mask (mask S11) of the first second mask (S1) is equal to the first value (1), the first mask (G11) of the first first mask (G1) is used as the t-th mask of the first group of the first fifth mask (G_1) G_11. For example, when t=1, the first bit of mask S11 is equal to the first value (1), and mask G11 (1111) is used as the first mask G_111 of the first group of the first mask G_11. Therefore, mask G_111 can be 1111. Similarly, at t=3, the third bit of mask S11 equals the first value (1), and mask G11 is used as the third mask G_113 of the first group of masks G_11. Therefore, mask G_113 can be 1111. At t=4, the fourth bit of mask S11 equals the first value (1), and mask G11 is used as the fourth mask G_114 of the first group of masks G_11. Therefore, mask G_114 can be 1111.

[0135] When the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of K second values ​​is used as the t-th mask of the j-th group of the i-th fifth mask. This can be done when the t-th bit is equal to the second value (0), using 4 (K=4) masks.

[0136] The mask of the second value (0) is used as the t-th mask of the first group mask G_11 of the first fifth mask (G_1). For example, when t=2, the second bit of the mask S11 is equal to the second value (0), and the four 0s are used as the second mask G_112 of the first group mask G_11. Therefore, the mask G_112 can be 0000.

[0137] In this case, the first group mask G_11 of the first fifth mask (G_1) can be 1111 0000 11111111.

[0138] Similarly, when the t-th bit of the first mask (mask S21) of the second second mask (S2) is equal to the first value (1), the first mask (G21) of the second first mask (G2) is used as the t-th mask of the first group mask G_21 of the second fifth mask (G_2). When the t-th bit is equal to the second value (0), the mask of the four second values ​​(0) is used as the t-th mask of the first group mask G_21 of the second fifth mask (G_2). See also Figure 7The mask G21 is 1101. The first bit of the mask S21 (1101) is 1, the second bit is 1, the third bit is 0, and the fourth bit is 1. The first group of masks G_21 includes masks G_211-mask G_214. Therefore, mask G_211 can be 1101, mask G_212 can be 1101, mask G_213 can be 0000, and mask G_214 can be 1101.

[0139] In this case, the first group mask G_21 of the second fifth mask (G_2) can be 1101 1101 00001101.

[0140] Similarly, each first mask corresponding to each primitive can be expanded into a fifth mask. The expansion method of each first mask will not be elaborated here.

[0141] In this way, the pixel-level mask can be extended to the sampling point-level mask.

[0142] The following describes an exemplary method for performing hidden surface removal tests on M fifth masks according to existing technology.

[0143] In one possible implementation, a hidden surface removal test is performed on M fifth masks to determine the third mask, including:

[0144] Based on the stacking order of the M primitives, the fifth mask corresponding to the primitives stacked later is used to cover the fifth mask corresponding to the primitives stacked earlier, thus obtaining the third mask.

[0145] For example, to determine the third mask by performing a hidden face removal test on M fifth masks, the third mask can be obtained by using the fifth mask corresponding to the later-added primitive to cover the fifth mask corresponding to the earlier-added primitive, based on the stacking order of the M primitives. When two fifth masks overlap, the two sets of masks corresponding to the same pixel overlap; when two sets of masks overlap, the masks corresponding to the same sampling point overlap. During the overlay, the later-added mask corresponding to the same sampling point covers the earlier-added mask, i.e., a copying method is used, writing the later-added mask to the corresponding storage location of the earlier-added mask. The mask presented after the overlay is the third mask. It should be noted that when masks corresponding to the same sampling point overlap, the overlay operation is only effective if at least one bit of the later-added mask is not 0, and it can completely cover the earlier-added mask. For example, if the later-added mask is 1011 and the earlier-added mask is 0111, the overlay mask will be 1011. If every bit of the mask superimposed later is 0, then the overlay operation of the mask later is invalid, and the superimposed mask still has the same effect as the mask superimposed earlier. For example, if the mask superimposed later is 0000 and the mask superimposed earlier is 0111, the mask superimposed later will be 0111.

[0146] Assume primitive 2 is a later-stacked primitive, and primitive 1 is a earlier-stacked primitive. The fifth mask (G_2) corresponding to primitive 2 can be used to cover the fifth mask (G_1) corresponding to primitive 1. Specifically, the first group of masks G_2 (G_21) covers the first group of masks G_1 (G_11) (corresponding to the first pixel). See [link to relevant documentation]. Figure 7The first mask of mask G_21 (G_211 = 1101) overwrites the first mask of mask G_11 (G_111 = 1111) to obtain mask D311 = 1101. This mask D311 serves as the first mask of the first group of masks D31 in the third mask D3 (corresponding to the first sampling point). The second mask of mask G_21 (G_212 = 1101) overwrites the second mask of mask G_11 (G_112 = 0000) to obtain mask D312 = 1101. This mask D312 serves as the second mask of the first group of masks D31 in the third mask D3 (corresponding to the second sampling point). The third mask of mask G_21 (G_213 = 0000) overwrites the third mask of mask G_11 (G_113 = 1111). Since every bit of the subsequently superimposed mask G_21 is 0, mask G_21 is invalid. The superimposed mask is still consistent with the previously superimposed mask G_11, resulting in mask D313 = 1111. This mask D313 serves as the third mask of the first group of masks D31 in the third mask D3 (corresponding to the third sampling point). The fourth mask of mask G_21 (G_214 = 1101) overwrites the fourth mask of mask G_11 (G_114 = 1111), resulting in mask D314 = 1101. This mask D314 serves as the fourth mask of the first group of masks D31 in the third mask D3 (corresponding to the fourth sampling point).

[0147] In this case, the first group of masks D31 of the third mask D3 can be 1101 1101 1111 1101.

[0148] Similarly, by overlapping the M sets of masks corresponding to the same pixel in the M fifth masks, a set of masks corresponding to that pixel in the third mask can be obtained. The N sets of masks obtained by combining these overlapping masks are the third mask. The overlapping method for every two sets of masks corresponding to other pixels will not be described in detail here.

[0149] As can be seen, the third mask includes the same mask as the first mask. In the example above, this is represented as D311 = D312 = D314 = G21, and D313 = G11. In this way, the information of the first mask can be preserved in the third mask, making it easier to obtain the fourth mask, which is the same as the first mask, by splitting the third mask later.

[0150] Those skilled in the art should understand that there can be many other ways to perform the hidden face removal test in step S63, as long as the third mask can include the information of the first mask and the third mask is a mask obtained after depth / stencil testing and hidden face removal testing. This disclosure does not limit the specific method of the hidden face removal test in step S63.

[0151] In one possible implementation, the rendering pipeline corresponds to a cache, which is used during hidden face removal tests on the M first masks.

[0152] The third mask includes N sets of masks corresponding to N pixels. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1.

[0153] The cache includes N storage locations, where the j-th storage location stores the j-th group of the third mask, and 0 < j ≤ N and is an integer.

[0154] For example, the rendering pipeline can correspond to a cache, such as one located in the second test module. The cache is used when performing hidden face removal tests on M first masks, and specifically for implementing the overlay of the fifth mask. Figure 8 A schematic diagram of a cache according to an embodiment of the present disclosure is shown.

[0155] like Figure 8 As shown, the cache can have N storage locations, each corresponding to one pixel. Each storage location can store the mask corresponding to one pixel. Each storage location can include K rows (or K columns). Figure 8 In the example, the storage location for each pixel can include four rows. Each row corresponds to one sampling point, meaning each row stores one mask from a set of masks corresponding to that sampling point. Figure 8 In the example, the first row corresponds to the first sampling point s0, the second row corresponds to the second sampling point s1, the third row corresponds to the third sampling point s2, and the fourth row corresponds to the fourth sampling point s3. Each row can store a 4-bit mask.

[0156] After the stacking order of the M primitives is determined, the N sets of masks included in the fifth mask corresponding to the first stacked primitive are sequentially written into the N storage locations of the cache. The N sets of masks included in the fifth mask corresponding to the second stacked primitive overwrite the existing masks in the N storage locations one by one. At this point, the fifth mask corresponding to the second stacked primitive is completely covered. This process continues until the fifth mask corresponding to the Mth stacked primitive is completely covered. The N sets of masks stored in the N storage locations are the third mask determined by the hidden surface removal test of the M fifth masks.

[0157] In this case, only K bits are needed to complete the hidden surface removal test in step S63 for each sampling point, and the required cache is also relatively small. The cost is still much smaller than that of two rendering pipelines, so the function of hidden surface removal test can be guaranteed to be executed normally at a small cost.

[0158] Since the mask overlay uses a copying method, the K masks stored in the storage location corresponding to a pixel may come from different primitives. Therefore, to obtain the M fourth masks corresponding to M primitives, the third mask can be split, separating the parts belonging to the same primitive.

[0159] The following describes an exemplary method for splitting the third mask in step S64.

[0160] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits.

[0161] Step S64 includes:

[0162] When the i-th primitive corresponds to the t-th mask of the j-th group of the third mask, the t-th mask of the j-th group of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer.

[0163] When the i-th primitive does not correspond to any of the masks in the j-th group of the third mask, the mask of the K second values ​​is used as the j-th mask of the i-th fourth mask.

[0164] The correspondence between the t-th mask of the j-th group of the third mask and the primitive can be determined using existing technology, and will not be elaborated here.

[0165] For example, through Figure 7 It can be seen that the effective mask corresponding to a sampling point in the fifth mask (i.e., the mask where K bits are not all zero, such as G_111) and the mask corresponding to the pixel to which the sampling point belongs in the first mask corresponding to the fifth mask (such as G11) are actually the same. The mask corresponding to the sampling point in the third mask is derived from the mask corresponding to the sampling point in the fifth mask. Therefore, if the i-th primitive corresponds to the t-th mask of the j-th group of masks in the third mask, it can be considered that the i-th primitive is the top primitive of the t-th sampling point of the j-th pixel. The corresponding mask of the t-th mask of the j-th group of masks in the fifth mask is a valid mask. Therefore, the t-th mask of the j-th group of masks in the third mask can be used as the j-th mask of the i-th fourth mask.

[0166] by Figure 7For example, the first group of masks D31 of the third mask D3 is 1101 1101 1111 1101, where the 1st, 2nd, and 4th masks (1101) correspond to the 2nd primitive (primitive 2), and the 3rd mask (1111) corresponds to the 1st primitive (primitive 1). Therefore, 1101 can be used as the first mask of the second fourth mask (corresponding to primitive 2). 1111 can be used as the first mask of the first fourth mask (corresponding to primitive 1).

[0167] If the i-th primitive does not correspond to any of the masks in the j-th group of the third mask, it can be considered that the i-th primitive is not the top primitive of the t-th sampling point of the j-th pixel. The corresponding mask of the t-th mask in the j-th group of the third mask is an invalid mask (all K bits are 0). Therefore, the mask of K second values ​​(e.g., 0000) can be used as the j-th mask of the i-th fourth mask.

[0168] In this way, a fourth mask can be obtained that is identical to the first mask. This method reduces the cost required by the graphics processor.

[0169] The following describes another exemplary method for splitting the third mask in step S64.

[0170] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits.

[0171] Step S64 includes:

[0172] When the i-th primitive corresponds to the t-th mask of the j-th group of the third mask, the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer.

[0173] When the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask.

[0174] The result of the OR operation of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0175] For example, another way to split the third mask is through an OR operation. Using this method, the third mask is first split to obtain M seventh masks. Each seventh mask consists of N groups of masks, each group of masks contains K masks, and each mask contains K bits. Each group of masks corresponds to one pixel, and each mask in each group corresponds to one sampling point. Figure 9 A schematic diagram of a seventh mask according to an embodiment of the present disclosure is shown.

[0176] Assuming M=2, N=4, and K=4, the mask transmission method of this embodiment is applied to a scenario where two primitives (primitive 1 and primitive 2) are rendered. The rendered image includes four pixels, and each pixel includes four sampling points. For clarity, Figure 9 The image only shows the coverage of primitive 1 and primitive 2 for the four sampling points of the first pixel.

[0177] like Figure 9 As shown, the first group of masks D31 of the third mask D3 corresponds to the first pixel, which can be 1101 110111111101, where the first, second and fourth masks (1101) correspond to the second primitive (primitive 2), and the third mask (1111) corresponds to the first primitive (primitive 1). Therefore, 1101 can be used as the first mask P211, the second mask P212, and the fourth mask P214 of the first group of masks P21 (corresponding to the first pixel) of the second seventh mask P2 (corresponding to primitive 2). The third mask P213 of the first group of masks P21 of the second seventh mask can be 0000. 1111 can be used as the third mask P113 of the first group of masks P11 (corresponding to the first pixel) of the first seventh mask P1 (corresponding to primitive 1). The first mask P111, the second mask P112, and the fourth mask P114 of the first group of masks of the first seventh mask can all be 0000.

[0178] In this case, the first group mask P11 of the first seventh mask can be 0000 0000 1111 0000, and the first group mask P21 of the second seventh mask can be 1101 1101 0000 1101.

[0179] Then, an OR operation is performed on the K masks in the j-th group of the i-th seventh mask, and the result of the OR operation is used as the j-th mask of the fourth mask corresponding to the i-th primitive. Figure 9In the example, the OR operation of the first mask P111 = 0000, the second mask P112 = 0000, the third mask P113 = 1111, and the fourth mask P114 = 0000 of the first group of the first seventh mask can result in 1111. Therefore, 1111 can be used as the first mask Y11 of the fourth mask Y1 corresponding to primitive 1 (corresponding to the first pixel). The OR operation of the first mask P211 = 1101, the second mask P212 = 1101, the third mask P213 = 0000, and the fourth mask P214 = 1101 of the first group of the second seventh mask can result in 1101. Therefore, 1101 can be used as the first mask Y21 of the fourth mask Y2 corresponding to primitive 2 (corresponding to the first pixel).

[0180] This approach increases the flexibility of how the third mask is split.

[0181] Those skilled in the art should understand that there can be many other ways to split the third mask, as long as it is possible to split the third mask into M fourth masks, and the M fourth masks are the same as the M first masks respectively. The embodiments of this disclosure do not limit the specific method of splitting the third mask.

[0182] Figure 10 A schematic diagram illustrating an exemplary flow of a mask transmission method according to an embodiment of the present disclosure is shown.

[0183] like Figure 10 As shown, in one possible implementation, the method further includes:

[0184] Step S71: Perform hidden surface removal test on the M second masks to determine the sixth mask that corresponds to all M primitives;

[0185] Step S72: Split the sixth mask to obtain M eighth masks corresponding to M primitives;

[0186] In step S73, in response to the second instruction, M eighth masks are input into the pixel shader.

[0187] For example, see Figure 5b In this application scenario, the second test module can have two branches. The first branch performs the functions described in steps S63-S65 above, outputting a fourth mask (identical to the first mask) to the pixel shader. The second branch performs the functions described in steps S71-S73, outputting the mask (i.e., the eighth mask) after rasterization, depth stencil testing, and hidden face removal testing of the primitives using existing methods to the pixel shader. The workflow of the first branch can be found in [link to documentation]. Figure 6 The relevant descriptions will not be repeated here. The workflow of the second branch will be introduced below.

[0188] For example, in step S71, the second branch of the second test module can perform hidden surface removal testing on the M second masks (masks S1-SM) in the manner of existing technology to determine the sixth mask D6 corresponding to all M primitives. When performing the hidden surface removal test in step S71, the second masks corresponding to multiple primitives can be directly covered layer by layer according to the coverage order of the primitives. The final coverage result of the M second masks is the sixth mask D6, so the sixth mask D6 corresponds to all M primitives. The sixth mask includes N masks corresponding to N pixels respectively, and each mask includes K bits. At this time, the sixth mask D6 can indicate which sampling points each primitive is the top primitive of (after the inter-primary coverage is completed, if the second mask corresponding to a sampling point covered by a primitive is still valid, the primitive is the top primitive of that sampling point).

[0189] For example, after the hidden surface removal test in step 71, masks S1 and S2 (the second mask) yield mask D6 (the sixth mask). Mask D6 corresponds to primitive 1 and primitive 2. Mask D6 may include masks D61-D64, where mask D61 corresponds to the first pixel. Figure 7 In the example, the mask D61 can be 1111, where the 1st, 2nd, and 4th bits come from the mask S2 and therefore correspond to element 2, and the 3rd bit comes from the mask S1 and therefore corresponds to element 1.

[0190] The second branch of the second test module then executes step S72 to split the sixth mask D6. The purpose of this splitting is to extract the parts of the sixth mask D6 related to each primitive. After performing depth testing and / or stencil testing, as well as hidden face removal testing, M eighth masks (mask Y_1 - mask Y_M) are obtained. Primitive 1 corresponds to mask Y_1, ..., primitive M corresponds to mask Y_M. The eighth mask can include N masks, each mask corresponding to one pixel, and each mask includes K bits. Figure 7 or Figure 9 Taking the mask D61 corresponding to the first pixel in the split mask D6 as an example, after splitting the mask D61, we can obtain the first mask Y_11 in the eighth mask Y_1 corresponding to primitive 1 and the first mask Y_21 in the eighth mask Y_2 corresponding to primitive 2. Since the first, second and fourth bits of the mask D61 correspond to primitive 2 and the third bit corresponds to primitive 1, the mask Y_11 can be 0010 and the mask Y_21 can be 1101.

[0191] The method for obtaining the masks corresponding to other pixels by splitting the sixth mask is similar to that for obtaining the mask Y_11, and will not be repeated here.

[0192] The first and eighth masks corresponding to each primitive may be the same or different. If the second and first masks corresponding to a primitive are the same, and the primitive is the top-level primitive covering all sample points after the primitive undergoes depth / template testing, then the eighth and first masks corresponding to the primitive are also the same. If the second and first masks corresponding to a primitive are different, then the eighth and first masks corresponding to the primitive are also different. If the second and first masks corresponding to a primitive are the same, but the primitive is not the top-level primitive covering all sample points after the primitive undergoes depth / template testing, then the eighth and first masks corresponding to the primitive are different.

[0193] The user can provide a second instruction when the pixel shader processes data using the mask after performing a hidden face removal test according to existing techniques. The second branch of the second test module then executes step S73, and in response to the second instruction, M eighth masks can be input into the pixel shader. Simultaneously, the starting address of the pixel can also be output to the pixel shader. The pixel shader processes the data using the eighth masks and the starting address of the pixel, outputting color data for N pixels. Based on this color data, an image to be rendered to the screen can be generated.

[0194] If it can be determined in advance that the pixel shader will use a mask after performing a hidden face removal test according to existing technology for data processing, the second instruction can also be pre-stored in a specific location, such as memory, and after the graphics processor's rendering pipeline is started, the processor reads the second instruction from memory and outputs it to the rendering pipeline. This disclosure does not limit the source of the second instruction.

[0195] In this case, the graphics processor can output both a mask consistent with the rasterized mask to the pixel shader and another mask consistent with the mask after the hidden face removal test in the prior art, while using one rendering pipeline and retaining the early depth / stencil test and hidden face removal test. This gives the pixel shader more options for the data used when performing shading.

[0196] This disclosure also provides a mask transmission device. Figure 11 A schematic diagram showing the structure of a mask transmission apparatus according to an embodiment of the present disclosure is provided.

[0197] like Figure 11 As shown, the apparatus is applied to the rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, and the apparatus includes:

[0198] The rasterization module 10 is used to perform rasterization processing on M primitives respectively, and determine the M first masks corresponding to the M primitives respectively, where M is an integer greater than 1;

[0199] The first test module 20 is used to perform depth testing and / or template testing on the M first masks respectively, and determine the M second masks corresponding to the M primitives respectively;

[0200] The second test module 30 is used to perform hidden face removal tests on the M first masks based on the M second masks, determine the third mask corresponding to all M primitives, split the third mask to obtain M fourth masks corresponding to the M primitives respectively, and input the M fourth masks into the pixel shader in response to the first instruction.

[0201] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Each first mask comprises N masks corresponding to the N pixels, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels, each mask comprising K bits; the third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels, each mask comprising K bits.

[0202] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The step of performing a hidden surface removal test on the M first masks based on the M second masks to determine the third mask corresponding to all M primitives includes: processing the M first masks to obtain M fifth masks based on the M second masks, each fifth mask comprising N sets of masks corresponding to the N pixels, each set comprising K masks, and each mask comprising K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0203] In one possible implementation, the step of processing the M first masks according to the M second masks to obtain the M fifth masks includes: when the t-th bit of the j-th mask of the i-th second mask is equal to a first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the t-th bit of the j-th mask of the i-th second mask is equal to a second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0204] In one possible implementation, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: according to the stacking order of the M primitives, using the fifth mask corresponding to the later-stacked primitive to cover the fifth mask corresponding to the earlier-stacked primitive, thereby obtaining the third mask.

[0205] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: when the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the K second-value masks are used as the j-th mask of the i-th fourth mask.

[0206] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: the t-th mask corresponding to the j-th set of masks in the third mask for the i-th primitive. When the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, 0 < t ≤ K and are integers; when the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0207] In one possible implementation, the second test module is further configured to: perform a hidden face removal test on the M second masks to determine a sixth mask that corresponds to all M primitives; split the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and input the M eighth masks into the pixel shader in response to a second instruction.

[0208] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0209] In one possible implementation, the rendering pipeline corresponds to a cache used when performing hidden surface removal tests on the M first masks. The third mask includes N sets of masks corresponding to N pixels, each set of masks includes K masks, and each mask includes K bits, where N and K are integers greater than 1. The cache includes N storage locations, where the j-th storage location stores the j-th set of masks of the third mask, where 0 < j ≤ N and is an integer.

[0210] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0211] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0212] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0213] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0214] Figure 12 A block diagram of an apparatus 1900 according to an embodiment of the present disclosure is shown. For example, apparatus 1900 may be provided as an electronic device. (Refer to...) Figure 12 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0215] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0216] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0217] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0218] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0219] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0220] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0221] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0222] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0223] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0224] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0225] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A masked transmission method, characterized in that, The method is applied to the rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, and the method includes: Rasterization is performed on each of the M primitives to determine the M first masks corresponding to each of the M primitives, where M is an integer greater than 1; Perform depth testing and / or template testing on the M first masks respectively to determine the M second masks corresponding to the M primitives; Based on the M second masks, a hidden surface removal test is performed on the M first masks to determine the third mask that corresponds to all M primitives. The third mask is split to obtain M fourth masks corresponding to the M primitives respectively. The first mask and the fourth mask corresponding to the same primitive are the same. In response to the first instruction, the M fourth masks are input into the pixel shader.

2. The method according to claim 1, characterized in that, The rendering pipeline is used to render the M primitives to generate an image comprising N pixels, where each pixel includes K sampling points, and N and K are integers greater than 1. Each first mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits; Each second mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits; The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks includes K masks, and each mask includes K bits; Each fourth mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits.

3. The method according to claim 1, characterized in that, The rendering pipeline is used to render the M primitives to generate an image comprising N pixels, where each pixel includes K sampling points, and N and K are integers greater than 1. The step of performing hidden surface removal tests on the M first masks based on the M second masks to determine the third mask corresponding to all M primitives includes: Based on the M second masks, the M first masks are processed to obtain the M fifth masks. Each fifth mask includes N sets of masks corresponding to the N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. The hidden surface removal test is performed on the M fifth masks to determine the third mask.

4. The method according to claim 3, characterized in that, The process of processing M first masks based on M second masks to obtain M fifth masks includes: When the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of the i-th fifth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer; When the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th fifth mask.

5. The method according to claim 3, characterized in that, The process of performing hidden surface removal tests on the M fifth masks to determine the third mask includes: Based on the stacking order of the M primitives, the fifth mask corresponding to the primitives stacked later is used to cover the fifth mask corresponding to the primitives stacked earlier, thus obtaining the third mask.

6. The method according to claim 1, characterized in that, The rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: When the i-th primitive corresponds to the t-th mask of the j-th group of the third mask, the t-th mask of the j-th group of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer. When the i-th primitive does not correspond to any of the masks in the j-th group of the third mask, the mask of the K second values ​​is used as the j-th mask of the i-th fourth mask.

7. The method according to claim 1, characterized in that, The rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: When the i-th primitive corresponds to the t-th mask of the j-th group of the third mask, the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer. When the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask. The result of the OR operation of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

8. The method according to claim 1, characterized in that, The method further includes: Perform a hidden surface removal test on the M second masks to determine the sixth mask that corresponds to all M primitives; The sixth mask is split to obtain M eighth masks corresponding to the M primitives respectively; In response to the second instruction, the M eighth masks are input into the pixel shader.

9. The method according to claim 1, characterized in that, The rendering pipeline supports tile-based deferred rendering.

10. The method according to claim 9, characterized in that, The rendering pipeline corresponds to a cache, which is used when performing hidden face removal tests on the M first masks. The third mask includes N sets of masks corresponding to N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1. The cache includes N storage locations, where the j-th storage location stores the j-th group of the third mask, 0 < j ≤ N and is an integer.

11. A mask transmission device, characterized in that, The apparatus is applied to the rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, and the apparatus includes: The rasterization module is used to rasterize M primitives respectively and determine the M first masks corresponding to the M primitives, where M is an integer greater than 1; The first testing module is used to perform depth testing and / or template testing on the M first masks respectively, and determine the M second masks corresponding to the M primitives respectively; The second test module is used to perform hidden face removal tests on the M first masks based on the M second masks to determine the third mask that corresponds to all M primitives; to split the third mask to obtain M fourth masks corresponding to the M primitives respectively; and to input the M fourth masks into the pixel shader in response to the first instruction.

12. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the method of any one of claims 1 to 10 when executing instructions stored in the memory.

13. A non-volatile computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 10.

14. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, characterized in that, When the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the method according to any one of claims 1 to 10.

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