Gate drive circuit, display panel and abnormality detection method

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a display panel and an anomaly detection method, the gate driving circuit comprises N cascaded driving circuit modules and a middle section control line, each driving circuit module at least comprises a driving control node, a driving output end and a stage transmission output end, the nth-stage driving circuit module further comprises a pull-up unit which is used for pulling up the potential of the driving control node of the stage to a target voltage in a normal driving stage; the middle section pull-up unit is used for pulling up the potential of the driving control node of the current stage to a target voltage under the action of a grid driving signal output by the (n-i) th stage of driving circuit module and a middle section control signal output by the middle section control line in a test stage; the output unit is used for outputting a corresponding gate driving signal and a stage transmission signal; while the omission ratio is reduced, the abnormal level position of the gate drive circuit can be quickly positioned.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit, a display panel, and an anomaly detection method. Background Technology

[0002] During the manufacturing process of display panels, the normal output of the GOA (Gate Driver on Array) circuit integrated into the panel is crucial to ensuring stable display functionality. The GOA circuit is typically composed of multiple stages. If any thin-film transistor in the GOA fails, it will not only affect the output of that stage but also cause a stage-to-stage signal interruption, leading to abnormal display of the entire panel.

[0003] Currently, in order to improve the yield of display panels, electrical testing and repair of the GOA circuit are usually performed after the array manufacturing process. The relevant testing method is as follows: test points are set in the bonding area, the in-plane circuit is charged and discharged by inputting the gate drive signal, and then the charge status of the pixels is monitored by the charge detection equipment to indirectly determine whether the GOA is working properly. However, this testing method not only has the problems of low testing efficiency and high false negative rate, but also makes it difficult to locate abnormal locations, increasing the difficulty of repair.

[0004] Therefore, how to quickly locate the abnormal level of the gate drive circuit while reducing the false negative rate is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit, a display panel, and an anomaly detection method, which solves the problems of high false negative rate and difficulty in locating the anomaly position in the gate driving circuit anomaly detection in related technologies.

[0006] In a first aspect, this application provides a gate driving circuit, which includes N cascaded driving circuit modules and a mid-stage control line. Each driving circuit module includes at least a driving control node, a driving output terminal, and a stage transmission output terminal. The nth stage driving circuit module further includes a pull-up unit connected to the driving control node of that stage. The pull-up unit is also connected to the stage transmission output terminal and / or the driving output terminal of the nith stage driving circuit module. During normal driving, under the action of the stage transmission signal and / or the gate driving signal output by the nith stage driving circuit module, the pull-up unit... The potential of the drive control node of this stage is pulled up to the target voltage; the middle section pull-up unit is connected to the drive output terminal of the ni-th stage drive circuit module, the middle section control line and the pull-up unit respectively, and is used to pull up the potential of the drive control node of this stage to the target voltage under the action of the gate drive signal output by the ni-th stage drive circuit module and the middle section control signal output by the middle section control line during the test phase; the output unit is connected to the drive control node and is used to output the corresponding gate drive signal and stage transmission signal under the action of the target voltage on the drive control node.

[0007] Optionally, the pull-up unit includes a first transistor, the control terminal of which is connected to the stage output terminal of the ni-th stage driving circuit module, the first terminal of which is connected to the drive output terminal of the ni-th stage driving circuit module, and the second terminal of which is connected to the drive control node of the same stage; the mid-section pull-up unit includes: a second transistor, the control terminal and the first terminal of which are respectively connected to the drive output terminal of the ni-th stage driving circuit module; and a third transistor, the control terminal of which is connected to the mid-section control line, the first terminal of which is connected to the second terminal of the second transistor, and the second terminal of which is connected to the drive control node.

[0008] Optionally, the pull-up unit includes a first transistor, the control terminal of the first transistor is connected to the stage output terminal of the ni-th stage driving circuit module, the first terminal of the first transistor is connected to the drive output terminal of the ni-th stage driving circuit module, and the second terminal of the first transistor is connected to the drive control node of this stage; the mid-section pull-up unit includes a second transistor, the control terminal of the second transistor is connected to the mid-section control line, the first terminal of the second transistor is connected to the first terminal of the first transistor, and the second terminal of the second transistor is connected to the control terminal of the first transistor.

[0009] Optionally, the pull-up unit includes a first transistor, the control terminal and the first terminal of the first transistor are respectively connected to the stage output terminal of the ni-th stage driving circuit module, and the second terminal of the first transistor is connected to the driving control node of this stage; the mid-section pull-up unit includes a second transistor, the control terminal of the second transistor is connected to the mid-section control line, the first terminal of the second transistor is connected to the driving output terminal of the ni-th stage driving circuit module, and the second terminal of the second transistor is connected to the first terminal of the first transistor.

[0010] Optionally, the pull-up unit includes a first transistor, the first terminal of which is connected to the drive output terminal of the ni-th stage drive circuit module, and the second terminal of which is connected to the drive control node of the same stage; the mid-section pull-up unit includes a second transistor, the control terminal of which is connected to the mid-section control line, the first terminal of which is connected to the drive output terminal of the ni-th stage drive circuit module, and the second terminal of which is connected to the control terminal of the first transistor.

[0011] Secondly, this application provides a display panel, the display panel comprising: a pixel array, the pixel array including at least N scan lines, the pixel array having a first side and a second side disposed opposite to each other; a first gate driving circuit, the first gate driving circuit being disposed on the first side of the pixel array and electrically connected to the multiple scan lines; a second gate driving circuit, the second gate driving circuit being disposed on the second side of the pixel array and electrically connected to the multiple scan lines; a first test connection terminal, the first test connection terminal being electrically connected to the output terminal of the final stage driving circuit module of the first gate driving circuit, for connecting the output terminal of the final stage driving circuit module of the first gate driving circuit to an external test device; a second test connection terminal, the second test connection terminal being electrically connected to the output terminal of the final stage driving circuit module of the second gate driving circuit, for connecting the output terminal of the final stage driving circuit module of the second gate driving circuit to an external test device; wherein the first gate driving circuit and the second gate driving circuit are the gate driving circuits described above.

[0012] Thirdly, this application provides an anomaly detection method applied to the aforementioned display panel. The anomaly detection method includes: performing a single-drive test on a first gate drive circuit and a second gate drive circuit in the display panel to obtain an abnormal gate drive circuit and a normal gate drive circuit; when performing a trigger test on the nth-level drive circuit module of the abnormal gate drive circuit, driving the normal gate drive circuit to the (n+i)th-level drive circuit module and then stopping the output, and activating the middle pull-up unit of the nth-to-n+i-th-level drive circuit modules in the abnormal gate drive circuit during the period when the normal gate drive circuit outputs the gate drive signals from the nth to the (n+i)th levels; and determining the anomaly detection result of the nth-to-Nth-level drive circuit modules of the abnormal gate drive circuit based on the output waveform of the Nth-level drive circuit module of the abnormal gate drive circuit.

[0013] Optionally, when the pull-up unit is connected to the stage transmission output terminal and the drive output terminal of the ni-th stage drive circuit module, or when the pull-up unit is connected to the stage transmission output terminal of the ni-th stage drive circuit module, the middle section pull-up unit of the ni-th to ni-th stage drive circuit modules in the abnormal gate drive circuit is activated during the period when the normal gate drive circuit outputs the ni-th to ni-th stage gate drive signals, including: during the period when the normal gate drive circuit outputs the ni-th to ni-th stage gate drive signals, controlling the middle section control line to output a high-level middle section control signal, so that the ni-th to ni-th stage gate drive signals output by the normal gate drive circuit are transmitted to the ni-th to ni-th+2i-th stage pull-up units in the abnormal gate drive circuit through the scan line respectively.

[0014] Optionally, when the pull-up unit is connected to the drive output terminal of the ni-th stage drive circuit module, the middle section pull-up unit of the n-th to n+i-th stage drive circuit module in the abnormal gate drive circuit is activated during the period when the normal gate drive circuit outputs the n-th to n+i-th stage gate drive signals. This includes: during the period when the normal gate drive circuit outputs the n-th to n+i-th stage gate drive signals, controlling the middle section control line to output a high-level middle section control signal, so that the ni-th to n+i-th stage gate drive signals output by the normal gate drive circuit are transmitted to the n-th to n+2i-th stage pull-up units in the abnormal gate drive circuit through the scan line respectively; and continuing to control the middle section control line to output a high-level middle section control signal during the period when the abnormal gate drive circuit outputs the n+i-th to N-th stage gate drive signals.

[0015] Optionally, based on the output waveform of the Nth-level drive circuit module of the abnormal gate drive circuit, the abnormal detection result of the drive circuit modules from the nth to the Nth level of the abnormal gate drive circuit is determined, including: when the output waveform of the Nth-level drive circuit module of the abnormal gate drive circuit is abnormal, it is determined that there is an abnormal level in the drive circuit modules from the nth to the Nth level of the abnormal gate drive circuit; the abnormal detection method further includes: taking any m-level of any level in the drive circuit modules from the nth to the Nth level of the abnormal gate drive circuit as a trigger test level, and stopping the output after the normal gate drive module drives to the m+i-level drive circuit module, and starting the middle pull-up unit of the drive circuit modules from the mth to the m+i-level in the abnormal gate drive circuit during the period when the normal gate drive circuit outputs the gate drive signals from the nth to the n+i-level. Based on the output waveform of the Nth-level drive circuit module of the abnormal gate drive circuit, the abnormal detection result of the drive circuit modules from the mth to the Nth level of the abnormal gate drive circuit is determined.

[0016] The technical solution provided in this application has at least the following beneficial effects: 1. In the normal driving phase, this application pulls up the voltage on the drive control node through a pull-up unit, thereby enabling the output unit to output the corresponding gate drive signal and stage transmission signal. In the testing phase, the voltage on the drive control node of any stage can be pulled up at any time through the mid-stage pull-up unit, so that the output unit of any stage can output the corresponding gate drive signal and stage transmission signal, which is used to realize the abnormal detection of the gate drive circuit. Therefore, this application can improve the efficiency and flexibility of abnormal detection of the gate drive circuit by starting the stage transmission from any stage.

[0017] 2. This application transmits the gate drive signal output by the normal gate drive circuit to the abnormal gate drive circuit through a scan line, and uses it as the stage transmission signal of the abnormal gate drive circuit. Under the action of the mid-stage control signal output on the mid-stage control line, it drives the normal output and stage transmission of any stage drive circuit module of the abnormal gate drive circuit. Finally, the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit determines whether there is an abnormality in any stage to the Nth stage drive circuit module. By repeating this process, the abnormal position of the abnormal gate drive circuit can be quickly detected, while reducing the missed detection rate and the difficulty of repair. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 The diagram shown is a structural schematic of a display panel in related technologies.

[0020] Figure 2 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0021] Figure 3 The diagram shown is a circuit diagram of the first type of driving circuit module provided in an embodiment of this application.

[0022] Figure 4 The diagram shown is a circuit diagram of the second type of driving circuit module provided in an embodiment of this application.

[0023] Figure 5 The diagram shown is a circuit diagram of the third type of driving circuit module provided in the embodiment of this application.

[0024] Figure 6 The diagram shown is a circuit diagram of the fourth type of driving circuit module provided in the embodiment of this application.

[0025] Figure 7 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0026] Figure 8 The diagram shown is a flowchart of an anomaly detection method provided in an embodiment of this application.

[0027] Figure 9 The diagram shown is a schematic diagram of a driving waveform provided in an embodiment of this application.

[0028] Figure 10 The diagram shown is another driving waveform provided in an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures: 10. Display panel; 100. Drive circuit module; 110. Pull-up unit; 120. Mid-section pull-up unit; 130. Output unit; 140. Reset unit; 150. Pull-down unit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; C, storage capacitor; GOA1, First gate drive circuit; GOA2, Second gate drive circuit; 200, Scan line; 300, First test connection terminal; 400, Second test connection terminal; 500, First test pad group; 600, Second test pad group; STV-mid, Middle section control line; Qn, Drive control node; Gn, Drive output terminal; Fn, Stage transmission output terminal; CK, Clock signal line; Reset, Reset signal line. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0031] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0032] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0033] The working principle of liquid crystal in TFT-LCD is as follows: When an external voltage is applied to a single pixel in the display area, the liquid crystal molecules within the pixel rotate, causing a change in light transmittance and thus color transmission. All pixels in the display area array switch frame by frame, achieving dynamic display. A single frame is displayed line by line; completing the display of all lines completes one frame. The process of progressive display is generally implemented by a gate driving circuit. Each driving circuit module outputs a waveform for each corresponding line in each frame, with a one-hour time difference between the waveforms output by adjacent driving circuit modules, thus completing the progressive display process.

[0034] Optionally, the basic structure of each driving circuit module typically includes pull-up units, pull-down units, output units, reset units, noise reduction units, etc. Pull-up units and pull-down units produce Q-point voltages. Pull-up units and pull-down units need to request stage transmission signals from adjacent stage driving circuit modules. The Q-point provides the turn-on condition for the output unit and provides the turn-on voltage for the display area. The reset unit avoids the influence between frames, and the noise reduction unit reduces noise for each important signal. The normal output of the gate driving circuit is a necessary condition to ensure normal display. Its abnormality will directly lead to display abnormality. The failure of a single driving circuit module not only affects the display output of the current stage, but also affects the stage transmission output, causing the output of other driving circuit modules to be abnormal, and thus the entire screen is abnormal.

[0035] Because a single drive circuit module contains numerous components, a malfunction in any transistor at any stage can lead to failure, causing the panel to malfunction and display incorrectly. Currently, to improve panel yield, an internal inspection is typically performed after each layer of glass is manufactured, and targeted repairs are made to improve the panel manufacturer's efficiency. For example... Figure 1 As shown, related technologies involve setting up test pads in the bonding area of ​​the panel. After the gate drive circuit is fabricated, in-plane testing is performed. The general approach is to input a GOA drive signal into the test pad, initiating in-plane charging and discharging. Then, charge monitoring is used to confirm the in-plane charging and discharging status, thereby inferring whether the GOA is normal or not. However, this method relies on the charge status of the pixels in the plane to infer whether the GOA is abnormal. Therefore, it is limited by the accuracy of the charge detection equipment and has a certain number of missed detections. Multiple pulses and weak outputs of the GOA cannot be monitored, which also leads to missed detections. During the charge monitoring process, the equipment needs to scan the plane, resulting in low efficiency per chip. Furthermore, in the case of a full-plane charging and discharging abnormality, it is impossible to locate the abnormality level, which also poses a challenge to repair.

[0036] To address the aforementioned problems, this application provides a gate driving circuit, specifically including the following embodiments: Figure 2 The diagram shown is a schematic representation of a gate driving circuit according to an embodiment of this application; as follows: Figure 2 As shown, the gate drive circuit includes multiple clock signal lines CK, N cascaded drive circuit modules 100, and a mid-section control line STV-mid. The mid-section control line STV-mid outputs a mid-section control signal. Each drive circuit module 100 includes at least a drive control node Qn, a drive output terminal Gn, and a stage transmission output terminal Fn. In this embodiment, the drive control node Qn is commonly referred to as the Q-point. The voltage on the drive control node Qn is the turn-on voltage of the output unit 130 in the drive circuit module 100. The drive output terminal Gn is used to output the gate drive signal, and the stage transmission output terminal Fn is used to output the stage transmission signal. The gate drive signal provides the turn-on voltage for the scan lines 200 in the display area.

[0037] The nth stage driving circuit module 100 in this embodiment further includes a pull-up unit 110, a mid-stage pull-up unit 120, and an output unit 130. Specifically, the pull-up unit 110 is connected to the driving control node Qn of this stage, and the pull-up unit 110 is also connected to the stage transmission output terminal Fn of the nith stage driving circuit module 100 and / or the driving output terminal Gn of the nith stage driving circuit module 100. It is used to pull up the potential of the driving control node Qn of this stage to the target voltage under the action of the stage transmission signal and / or the gate driving signal output by the nith stage driving circuit module 100 during the normal driving phase. The mid-section pull-up unit 120 is connected to the drive output terminal Gn of the ni-th stage drive circuit module 100, the mid-section control line STV-mid, and the pull-up unit 110, respectively. During the testing phase, it is used to pull up the potential of the drive control node Qn of this stage to the target voltage under the action of the gate drive signal output by the ni-th stage drive circuit module 100 and the mid-section control signal output by the mid-section control line STV-mid. The output unit 130 is connected to the drive control node Qn and is used to output the corresponding gate drive signal and stage transmission signal under the action of the target voltage on the drive control node Qn.

[0038] It should be noted that the normal driving phase in this embodiment refers to the phase in which the gate driving circuit drives the pixel array to display normally, while the testing phase refers to the phase in which anomalies are detected in the gate driving circuit. The specific working principle of the gate driving circuit in this embodiment is as follows: (1) During the normal driving phase, the pull-up unit 110 of the current driving circuit module 100, under the combined action of the stage transmission signal and the gate driving signal output by the previous i-th stage driving circuit module 100, or under the action of either the stage transmission signal or the gate driving signal, pulls the voltage of the driving control node Qn of the current stage to the target voltage (e.g., 30V), turns on the output unit 130, and makes the output unit 130 output the gate driving signal and the stage transmission signal corresponding to the current driving circuit module 100, thereby realizing the function of opening the pixel row in the panel and transmitting to the next stage.

[0039] (2) During the testing phase, the middle pull-up unit 120 of the current stage drive circuit module 100, under the combined action of the gate drive signal and the middle control signal output by the upper i-stage drive circuit module 100, pulls up the voltage of the drive control node Qn of the current stage to the target voltage (such as 30V), turns on the output unit 130, and makes the output unit 130 output the gate drive signal and stage transmission signal corresponding to the current stage drive circuit module 100, thereby realizing the function of transmitting to the lower stage.

[0040] Therefore, it can be seen that during the normal driving phase, the voltage on the driving control node Qn is pulled up by the pull-up unit 110, so that the output unit 130 outputs the corresponding gate driving signal and stage transmission signal. During the testing phase, the voltage on the driving control node Qn of any stage can be pulled up at any time by the mid-stage pull-up unit 120, so that the output unit 130 of any stage outputs the corresponding gate driving signal and stage transmission signal, which is used to realize the abnormal detection of the gate driving circuit. Therefore, by starting the stage transmission from any stage, this application can improve the efficiency and flexibility of the abnormal detection of the gate driving circuit.

[0041] like Figure 2 As shown, the nth-stage drive circuit module 100 in this embodiment also includes a reset unit 140. The input terminal of the reset unit 140 is electrically connected to the reset signal line Reset, and the output terminal of the reset unit 140 is connected to the drive control node Qn, which is used to reset the voltage on the drive control node Qn.

[0042] like Figure 2 As shown, the nth-stage driving circuit module 100 in this embodiment further includes a pull-down unit 150. The input terminal of the pull-down unit 150 is connected to the stage transmission output terminal Fn of the (n+j)th-stage driving circuit module 100, and the output terminal of the pull-down unit 150 is connected to the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn of the current stage, respectively. The pull-down unit 150 is used to pull down the voltage on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn of the current stage under the action of the stage transmission signal output by the (n+j)th-stage driving circuit module 100, so as to avoid signal crosstalk.

[0043] Figure 3 The diagram shown is a circuit diagram of the first type of driving circuit module provided in an embodiment of this application; as shown Figure 3 As shown, the pull-up unit 110 in this embodiment includes a first transistor T1. The control terminal of the first transistor T1 is connected to the stage transmission output terminal Fn of the ni-th stage drive circuit module 100. The first terminal of the first transistor T1 is connected to the drive output terminal Gn of the ni-th stage drive circuit module 100. The second terminal of the first transistor T1 is connected to the drive control node Qn of this stage.

[0044] The output unit 130 in this embodiment includes a fourth transistor T4, a fifth transistor T5, and a storage capacitor C. The control terminals of the fourth transistor T4 and the fifth transistor T5 are respectively connected to the drive control node Qn. The first terminals of the fourth transistor T4 and the fifth transistor T5 are both connected to the clock signal line CK. The second terminal of the fourth transistor T4 serves as the stage transmission output terminal Fn, and the second terminal of the fifth transistor T5 serves as the drive output terminal Gn. In addition, the control terminal of the fifth transistor T5 is also connected to the second terminal of the fifth transistor T5 through the storage capacitor C.

[0045] It should be noted that all transistors involved in this application can be either N-type MOSFETs or P-type MOSFETs; this explanation will use an example where all transistors are N-type MOSFETs. In this embodiment, i and j can take any values ​​such as 1, 2, 3, or 4 depending on the actual situation. This embodiment uses i=3 and j=4 as an example for illustration. The high-level stage transmission signal output by the (n-3)th stage drive circuit module 100 turns on the first transistor T1, causing the high-level gate drive signal output by the (n-3)th stage drive circuit module 100 to pull the voltage on the drive control node Qn up to the target voltage, thereby turning on the fourth transistor T4 and the fifth transistor T5. When the clock signal corresponding to this stage drive circuit module 100 arrives, the corresponding stage transmission signal and gate drive signal are output through the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5.

[0046] In this embodiment, the mid-section pull-up unit 120 includes a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 and the first terminal of the second transistor T2 are respectively connected to the drive output terminal Gn of the ni-th stage drive circuit module 100; the control terminal of the third transistor T3 is connected to the mid-section control line STV-mid, the first terminal of the third transistor T3 is connected to the second terminal of the second transistor T2, and the second terminal of the third transistor T3 is connected to the drive control node Qn.

[0047] It should be noted that in this embodiment, the mid-stage control line STV-mid continuously outputs a low level during the normal driving phase, turning off the third transistor T3, so that the mid-stage pull-up unit 120 is not activated during the normal driving phase. During the testing phase, when it is necessary to activate the cascade function of the nth stage driving circuit module 100, the mid-stage control line STV-mid outputs a high-level mid-stage control signal to turn on the third transistor T3. When the gate drive signal output by the nith stage driving circuit module 100 turns on the second transistor T2, it pulls the voltage on the drive control node Qn up to the target voltage, thereby turning on the fourth transistor T4 and the fifth transistor T5. When the clock signal corresponding to the current stage driving circuit module 100 arrives, the corresponding cascade signal and gate drive signal are output through the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5.

[0048] It is worth noting that during the testing phase, for the pull-up unit 110 of the nth-stage drive circuit module 100, there is no stage transmission signal output by the nth-stage drive circuit module 100, so the first transistor T1 is in the off state and the pull-up unit 110 is not started; therefore, during the testing phase, only the middle pull-up unit 120 can pull up the voltage of the drive control node Qn. The specific reasons for the absence of a stage transmission signal during the testing phase will be explained in subsequent embodiments.

[0049] In this embodiment, the reset unit 140 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is connected to the reset signal line Reset, the first terminal of the sixth transistor T6 is connected to the drive control node Qn, and the second terminal of the sixth transistor T6 is connected to the low-level terminal.

[0050] In this embodiment, the pull-down unit 150 includes a seventh transistor T7 and an eighth transistor T8. The control terminals of the seventh transistor T7 and the eighth transistor T8 are respectively connected to the stage transmission output terminal Fn of the (n+j)th stage drive circuit module 100. The first terminal of the seventh transistor T7 is connected to the drive control node Qn of this stage, and the first terminal of the eighth transistor T8 is connected to the drive output terminal Gn of this stage. The second terminals of the seventh transistor T7 and the eighth transistor T8 are respectively connected to the low-level terminal.

[0051] Figure 4 The diagram shown is a circuit diagram of the second type of driving circuit module provided in an embodiment of this application. Figure 4 The drive circuit module 100 shown is Figure 3 The only difference lies in the circuit structure of the middle pull-up unit 120; such as Figure 4 As shown, the mid-section pull-up unit 120 includes a second transistor T2. The control terminal of the second transistor T2 is connected to the mid-section control line STV-mid. The first terminal of the second transistor T2 is connected to the first terminal of the first transistor T1. The second terminal of the second transistor T2 is connected to the control terminal of the first transistor T1.

[0052] It should be noted that since the ni-th stage drive circuit module 100 does not output a stage transmission signal during the testing phase, this embodiment turns on the second transistor T2 through the intermediate control signal, introduces the gate drive signal output by the ni-th stage drive circuit module 100 to the control terminal of the first transistor T1, and turns on the first transistor T1, thereby pulling the voltage of the drive control node Qn up to the target voltage.

[0053] Figure 5 The diagram shown is a circuit diagram of the third type of driving circuit module provided in an embodiment of this application. Figure 5 The drive circuit module 100 shown is Figure 3 The only difference lies in the circuit structure of pull-up unit 110 and mid-section pull-up unit 120; specifically as follows: Figure 5 As shown: The pull-up unit 110 includes a first transistor T1. The control terminal and the first terminal of the first transistor T1 are respectively connected to the stage transmission output terminal Fn of the ni-th stage drive circuit module 100. The second terminal of the first transistor T1 is connected to the drive control node Qn of this stage.

[0054] The mid-section pull-up unit 120 in this embodiment includes: a second transistor T2, the control terminal of the second transistor T2 is connected to the mid-section control line STV-mid, the first terminal of the second transistor T2 is connected to the drive output terminal Gn of the ni-th stage drive circuit module 100, and the second terminal of the second transistor T2 is connected to the first terminal of the first transistor T1.

[0055] It should be noted that, Figure 3 and Figure 4 The pull-up unit 110 shown, during the normal driving phase, pulls the voltage of the driving control node Qn of this stage to the target voltage through the combined action of the stage transmission signal and the gate driving signal output by the ni-th stage driving circuit module 100; however, Figure 5 The pull-up unit 110 shown pulls the voltage of the drive control node Qn of this stage to the target voltage only through the stage transmission signal output by the ni-th stage drive circuit module 100 during the normal drive phase.

[0056] However, during the testing phase, the ni-th stage drive circuit module 100 does not output a stage transmission signal. Therefore, in this embodiment, the second transistor T2 is turned on by the intermediate control signal, and the gate drive signal output by the ni-th stage drive circuit module 100 is introduced into the control terminal of the first transistor T1 and the first terminal of the first transistor T1. After turning on the first transistor T1, the voltage of the drive control node Qn is pulled up to the target voltage.

[0057] Figure 6 The diagram shown is a circuit diagram of the fourth type of driving circuit module provided in an embodiment of this application. Figure 6 The drive circuit module 100 shown is Figure 3 , Figure 4 and Figure 5 The difference is: (1) Figure 6 The driving circuit module 100 shown only has a driving output terminal Gn and no stage transmission output terminal Fn; while the driving circuit modules 100 in other embodiments all have a driving output terminal Gn and a stage transmission output terminal Fn; (2) Figure 6 In the first embodiment, the mid-range control line STV-mid maintains a high-level mid-range control signal output during the normal driving phase, while in other embodiments, the mid-range control line STV-mid maintains a low-level mid-range control signal output during the normal driving phase.

[0058] Specifically, such as Figure 6As shown: Pull-up unit 110 includes a first transistor T1, the first terminal of which is connected to the drive output terminal Gn of the ni-th stage drive circuit module 100, and the second terminal of which is connected to the drive control node Qn of this stage; the middle pull-up unit 120 includes a second transistor T2, the control terminal of which is connected to the middle control line STV-mid, the first terminal of which is connected to the drive output terminal Gn of the ni-th stage drive circuit module 100, and the second terminal of which is connected to the control terminal of the first transistor T1.

[0059] It should be noted that the specific working principle of the drive circuit module 100 in this embodiment is as follows: (1) During the normal driving phase, the middle control line STV-mid continuously outputs a high-level middle control signal, and the second transistor T2 is always in the open state. Under the action of the gate drive signal output by the ni-stage drive circuit module 100, the first transistor T1 is turned on, and the voltage on the drive control node Qn of this stage is pulled up to the target voltage, so that when the clock signal corresponding to the drive circuit module 100 of this stage arrives, the gate drive signal corresponding to this stage is output through the fifth transistor T5.

[0060] (2) During the testing phase, when the nth stage drive circuit module 100 needs to output a gate drive signal, the control line STV-mid outputs a high-level control signal, thereby turning on the second transistor T2. Under the action of the gate drive signal output by the nith stage drive circuit module 100, the first transistor T1 is turned on, and the voltage on the drive control node Qn of this stage is pulled up to the target voltage, so that when the clock signal corresponding to this stage drive circuit module 100 arrives, the gate drive signal corresponding to this stage is output through the fifth transistor T5. Before the nth stage drive circuit module 100 outputs the gate drive signal, the control line STV-mid outputs a low-level control signal, and the second transistor T2 is turned off to avoid signal crosstalk.

[0061] Figure 7 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application; as follows: Figure 7 As shown, the display panel 10 includes a pixel array, which includes at least N scan lines 200. The pixel array has a first side and a second side that are arranged opposite to each other. The pixel array also includes multiple data lines and pixel circuits arranged in an array.

[0062] The display panel 10 in this embodiment further includes a first gate driving circuit GOA1 and a second gate driving circuit GOA2. The first gate driving circuit GOA1 is disposed on the first side of the pixel array and electrically connected to multiple scan lines 200. The second gate driving circuit GOA2 is disposed on the second side of the pixel array and electrically connected to multiple scan lines 200. In other words, the display panel 10 in this embodiment is a dual-drive panel. By simultaneously driving the same scan line 200 through two gate driving circuits disposed on both sides of the pixel array, the display effect of the panel can be improved.

[0063] In this embodiment, the display panel 10 further includes a first test connection terminal 300 and a second test connection terminal 400; the first test connection terminal 300 is electrically connected to the output terminal of the final stage drive circuit module 100 of the first gate drive circuit GOA1, so that the output terminal of the final stage drive circuit module 100 of the first gate drive circuit GOA1 is connected to an external test device; the second test connection terminal 400 is electrically connected to the output terminal of the final stage drive circuit module 100 of the second gate drive circuit GOA2, so that the output terminal of the final stage drive circuit module 100 of the second gate drive circuit GOA2 is connected to an external test device. In other words, the gate drive signal waveform output by the last stage drive circuit module 100 in the first gate drive circuit GOA1 can be exported to an external test device for display through the first test connection terminal 300; similarly, the gate drive signal waveform output by the last stage drive circuit module 100 in the second gate drive circuit GOA2 can be exported to an external test device for display through the second test connection terminal 400. The purpose of this configuration is that this application can determine whether there is an abnormality in the drive circuit module 100 between the nth and Nth stages by observing the output waveform of the last stage gate drive signal, without needing to determine whether there is an abnormality by observing the pixel display in the pixel array. This not only improves the detection efficiency but also the detection accuracy.

[0064] In this embodiment, the display panel 10 further includes a first test pad group 500 and a second test pad group 600; wherein, the first test pad group 500 is used to output a corresponding test signal to the first gate drive circuit GOA1 through an external test device, and the second test pad group 600 is used to output a corresponding test signal to the second gate drive circuit GOA2 through an external test device; the test signal includes, but is not limited to, clock signal, frame start signal, reset signal, etc.; that is, for the first gate drive circuit GOA1 and the second gate drive circuit GOA2, the first test pad group 500 and the second test pad group 600 are equivalent to signal input connection terminals, and the first test connection terminal 300 and the second test connection terminal 400 are equivalent to signal output connection terminals.

[0065] The first gate driving circuit GOA1 and the second gate driving circuit GOA2 in this embodiment are as described above. Figures 3-6 The specific circuit structure shown in the embodiment.

[0066] Figure 8 The diagram shown is a flowchart illustrating an anomaly detection method provided in an embodiment of this application; this anomaly detection method is applied to... Figure 7 The display panel 10 shown performs anomaly detection on the first gate drive circuit GOA1 and the second gate drive circuit GOA2 in the display panel 10; such as Figure 8 As shown, the anomaly detection method in this embodiment specifically includes the following steps: Step S100: Perform a single-drive test on the first gate drive circuit and the second gate drive circuit in the display panel to obtain the abnormal gate drive circuit and the normal gate drive circuit.

[0067] Specifically, in this embodiment, clock signals, frame start signals, etc., are input to the first gate drive circuit GOA1 through the first test pad group 500, thereby driving the first-level drive circuit module 100 to the Nth-level drive circuit module 100 in the first gate drive circuit GOA1 to work. The gate drive signal waveform output by the Nth-level drive circuit module 100 is obtained through the first test connection terminal 300. If the waveform is detected to be normal, it indicates that the first gate drive circuit GOA1 is a normal gate drive circuit; if the waveform is detected to be abnormal, it indicates that the first gate drive circuit GOA1 is an abnormal gate drive circuit.

[0068] Similarly, the second gate drive circuit GOA2 is tested using the above method to determine whether the second gate drive circuit GOA2 is a normal gate drive circuit. This embodiment uses the example of the first gate drive circuit GOA1 being an abnormal gate drive circuit and the second gate drive circuit GOA2 being a normal gate drive circuit for explanation.

[0069] Step S200: When triggering the nth stage drive circuit module of the abnormal gate drive circuit, drive the normal gate drive circuit to the (n+i)th stage drive circuit module and then stop outputting. During the period when the normal gate drive circuit outputs the nth stage gate drive signal and the (n+i)th stage gate drive signal, start the middle pull-up unit of the nth stage drive circuit module in the abnormal gate drive circuit.

[0070] In one embodiment, when the pull-up unit 110 is connected to the stage transmission output terminal Fn and the drive output terminal Gn of the ni-th stage drive circuit module 100, or when the pull-up unit 110 is connected to the stage transmission output terminal Fn of the ni-th stage drive circuit module 100, the middle section pull-up unit 120 of the ni-th to ni-th stage drive circuit module 100 in the abnormal gate drive circuit is activated during the period when the normal gate drive circuit outputs the ni-th to ni-th stage gate drive signals. This includes: during the period when the normal gate drive circuit outputs the ni-th to ni-th stage gate drive signals, controlling the middle section control line STV-mid to output a high-level middle section control signal, so that the ni-th to ni-th stage gate drive signals output by the normal gate drive circuit are transmitted to the ni-th to ni-th+2i stage pull-up units 110 in the abnormal gate drive circuit through the scan line 200, respectively.

[0071] It should be noted that, Figure 3 , Figure 4 and Figure 5 The pull-up unit 110 shown is based on Figure 9 The middle section control signal shown is used for driving.

[0072] In one embodiment, when the pull-up unit 110 is connected to the drive output terminal Gn of the ni-th stage drive circuit module 100, the middle section pull-up unit 120 of the ni-th to ni-th stage drive circuit module 100 in the abnormal gate drive circuit is activated during the period when the normal gate drive circuit outputs the gate drive signals of the n-th to n+i-th stages, including: During the period when the normal gate drive circuit outputs gate drive signals from level n to level n+i, the control line STV-mid outputs a high-level middle-level control signal, so that the gate drive signals from level ni to level n+i output by the normal gate drive circuit are transmitted through the scan line 200 to the pull-up units 110 of level n to level n+2i in the abnormal gate drive circuit respectively; when the abnormal gate drive circuit outputs gate drive signals from level n+i to level N, the control line STV-mid continues to output a high-level middle-level control signal.

[0073] It should be noted that, Figure 6 The pull-up unit 110 shown is based on Figure 10 The middle section control signal shown is used for driving.

[0074] Step S300: Based on the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit, determine the abnormal detection results of the nth to Nth stage drive circuit modules of the abnormal gate drive circuit.

[0075] Specifically, based on the output waveform of the Nth stage drive circuit module 100 of the abnormal gate drive circuit, the abnormal detection results of the nth to Nth stage drive circuit modules 100 of the abnormal gate drive circuit are determined, including: when the output waveform of the Nth stage drive circuit module 100 of the abnormal gate drive circuit is abnormal, it is determined that there is an abnormal stage in the nth to Nth stage drive circuit modules 100 of the abnormal gate drive circuit.

[0076] After determining that an abnormal level exists in the nth to Nth level drive circuit modules 100 of the abnormal gate drive circuit, the abnormal detection method further includes: taking any mth level of any level in the nth to Nth level drive circuit modules 100 of the abnormal gate drive circuit as a trigger test level, and stopping the output after the normal gate drive module drives to the m+ith level drive circuit module 100, and starting the middle pull-up unit 120 of the mth to m+ith level drive circuit modules 100 in the abnormal gate drive circuit during the period when the normal gate drive circuit outputs the gate drive signals of the nth to n+ith levels; determining the abnormal detection result of the mth to Nth level drive circuit modules 100 of the abnormal gate drive circuit based on the output waveform of the Nth level drive circuit module 100 of the abnormal gate drive circuit; repeating this process until an abnormal level is found.

[0077] It should be noted that in this embodiment, the gate drive signal of the normal gate drive circuit is used as the stage transmission signal of the abnormal gate drive circuit. Only an additional pull-up control line needs to be added to connect to each stage drive circuit module, thereby enabling stage transmission from any stage in the abnormal gate drive circuit and reducing additional control signals.

[0078] The newly added test connection in this embodiment does not only detect the last stage, but may detect multiple stages. When the stage transmission numbers (i & j) are both even, the GOA units of the odd and even stages do not affect each other. In order to fully verify whether the single-sided GOA is abnormal, the tail stage test connection (i.e., the first test connection or the second test connection) should be set to output the last two stages.

[0079] like Figure 9 The source-finding drive waveform is shown; taking stage transmission number i=2 as an example, the anomaly detection steps are as follows: (1) Perform a single-drive test on the first gate drive circuit and the second gate drive circuit. Drive the left or right gate drive circuit independently and detect whether the tail stage output is abnormal. If both the left and right outputs are normal, there is no abnormality. If only one side is abnormal, proceed to the next step.

[0080] (2) Taking the abnormal output of the left single drive as an example, perform an arbitrary bit trigger test on the left gate drive circuit. Taking the nth trigger as an example, the right normal gate drive circuit drives the circuit to the n+2th level. After the n+2nd level, cancel the CK output and enable the reset signal to prevent the right side from outputting. Then, the Gout of the 1st to n+2nd levels is driven by the right side. The left drive waveform is as follows: Figure 9 As shown, the STV_mid signal is pulled high at the rising edge of the nth level Gout and pulled low at the falling edge of the (n+2)th level signal. Figure 3 When the third transistor in the circuit is turned on, Qn+3, Qn+4, and Qn+5, which are pulled up by stages n, n+1, and n+2, can all be pulled high normally. The left gate drive circuit then starts normal stage transmission. Then, the output pad of the tail stage is used to test whether the tail stage output is normal in order to confirm whether the abnormal position is after stage n or before stage n.

[0081] (3) Change the trigger location and test repeatedly to gradually locate the abnormal location.

[0082] It should be noted that in the above source tracing process, the normal side (right side) needs to be passed up to the n+2 level. Therefore, the right side is normally driven before the n+2 level, so the STV, CK and other drive signals on the right side are normally given. STV_mid is low level throughout. After the n+2 level, CK is no longer output, and the right side no longer drives Gout after the n+2 level. The waveform diagram is omitted here.

[0083] Optionally, when the abnormal side (left side) is driven, STV is pulled low throughout, and the left GOA is not triggered. STV_mid is pulled high at the rising edge of Gout at level n and pulled low at the falling edge of the signal at level n+2, so that Qn+3, Qn+4, and Qn+5 pulled up at levels n, n+1, and n+2 can all be pulled high normally, and the cascading can start from here. Therefore, the CK signal needs to be output from level n+3 onwards.

[0084] The above determines the location of the STV_mid signal as follows: Figure 9 As shown, this also covers Gn-2 and Gn-1. Since STV_mid is a global control signal, Qn+1 and Qn+2 will also be precharged (although their left shoulder is slightly shorter). Qn+1 and Qn+2 are pulled up, and Gn+1 and Gn+2 are still output from the right side. Therefore, their Q points also bootstrap due to capacitor C. The fifth transistor responsible for the output of Qn+1 and Qn+2 is turned on. Therefore, the corresponding CKn+1 and CKn+2 on the left side need to be output normally. Otherwise, the output of n+1 and n+2 stages will be pulled low, affecting the normal side (right side) output. Therefore, the CK signal on the left side needs to start outputting with n+1 stage.

[0085] In this embodiment, the pause position on the normal side and the width of STV_mid on the abnormal side are both affected by the number of levels. For example, when i=4, the normal side should scan to level n+3 and then stop; the width of STV_mid on the abnormal side needs to be increased by 1h, that is, pulled down at the falling edge of level n+3; and the number of levels given in advance for the abnormal side CK needs to be adjusted according to which levels STV_mid specifically covers in advance.

[0086] When the GOA anomaly is a shot at the drain and gate of the output unit, Gout is multipulse, which will affect the normal display. However, since the Fn output is normal, the above method will miss this type of problem. Therefore, a special detection step needs to be set up for this type of problem. When the abnormal point is confirmed on the single drive, the drive-side STV_mid is kept on so that the abnormal signal is transmitted downwards, ensuring that this type of anomaly can be detected. After the abnormal side is determined, when the level of the abnormal point is determined, the STV_mid is not pulled down after it is turned on, which also ensures that the abnormal signal is transmitted downwards, ensuring that this type of anomaly can be detected.

[0087] When anomalies in GOA occur in unnecessary units, or are minor short or interrupted, GOA may still propagate normally to the next level. In this case, to ensure the detection rate, VGH can be reduced and the system can be re-detected to improve the detection rate.

[0088] During the above-mentioned anomaly location process, due to the existence of cascading relationships and interconnected signals, it is not possible to strictly locate the anomaly at a certain level of GOA. However, after multiple location searches, it can be located at least within level 7 of GOA, which greatly reduces the difficulty of finding the source of GOA anomalies.

[0089] Although the above driving process requires multiple position triggering drives, multiple voltage drives, and multiple timing drives, and requires a large number of tests, the testing process is rapid. At least 60 (60Hz) output tests can be performed within 1 second, so single-chip testing can be completed in a few seconds, which is highly efficient.

[0090] All the driving processes and logic involved in the appeal can be completed by the controller, which will monitor and output the results, generate test reports, and guide the repair process.

[0091] During non-detection periods, the normal driving process requires STV_mid to be pulled low.

[0092] Therefore, this application transmits the gate drive signal output by the normal gate drive circuit to the abnormal gate drive circuit through the scan line, and uses it as the stage transmission signal of the abnormal gate drive circuit. Under the action of the middle control signal output on the middle control line, the normal output and stage transmission of any stage drive circuit module of the abnormal gate drive circuit are driven. Finally, the detection result of whether there is an abnormality in any stage to the Nth stage drive circuit module is determined by the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit. By repeating this process, the abnormal position of the abnormal gate drive circuit can be quickly detected, while reducing the missed detection rate and the difficulty of repair.

[0093] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0094] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0095] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate drive circuit includes N cascaded drive circuit modules and intermediate control lines. Each drive circuit module includes at least a drive control node, a drive output terminal, and a stage output terminal. The nth stage drive circuit module further includes: A pull-up unit is connected to the drive control node of this stage. The pull-up unit is also connected to the stage transmission output terminal and / or the drive output terminal of the ni-th stage drive circuit module. It is used to pull up the potential of the drive control node of this stage to the target voltage under the action of the stage transmission signal and / or the gate drive signal output by the ni-th stage drive circuit module during the normal drive phase. The middle section pull-up unit is connected to the drive output terminal of the ni-th stage drive circuit module, the middle section control line and the pull-up unit respectively. It is used to pull up the potential of the drive control node of this stage to the target voltage under the action of the gate drive signal output by the ni-th stage drive circuit module and the middle section control signal output by the middle section control line during the test phase. An output unit, connected to the drive control node, is used to output corresponding gate drive signals and stage transmission signals under the action of the target voltage on the drive control node.

2. The gate driving circuit according to claim 1, characterized in that, The pull-up unit includes a first transistor, the control terminal of the first transistor is connected to the stage output terminal of the ni-th stage drive circuit module, the first terminal of the first transistor is connected to the drive output terminal of the ni-th stage drive circuit module, and the second terminal of the first transistor is connected to the drive control node of this stage. The mid-section pull-up unit includes: The second transistor, the control terminal of the second transistor and the first terminal of the second transistor are respectively connected to the drive output terminal of the ni-th stage drive circuit module; The third transistor has its control terminal connected to the middle control line, its first terminal connected to the second terminal of the second transistor, and its second terminal connected to the drive control node.

3. The gate driving circuit according to claim 1, characterized in that, The pull-up unit includes a first transistor, the control terminal of the first transistor is connected to the stage output terminal of the ni-th stage drive circuit module, the first terminal of the first transistor is connected to the drive output terminal of the ni-th stage drive circuit module, and the second terminal of the first transistor is connected to the drive control node of this stage. The mid-section pull-up unit includes: The second transistor has its control terminal connected to the middle control line, its first terminal connected to the first terminal of the first transistor, and its second terminal connected to the control terminal of the first transistor.

4. The gate driving circuit according to claim 1, characterized in that, The pull-up unit includes a first transistor, the control terminal and the first terminal of the first transistor are respectively connected to the stage output terminal of the ni-th stage drive circuit module, and the second terminal of the first transistor is connected to the drive control node of this stage. The mid-section pull-up unit includes: The second transistor has its control terminal connected to the middle control line, its first terminal connected to the drive output terminal of the ni-th stage drive circuit module, and its second terminal connected to the first terminal of the first transistor.

5. The gate driving circuit according to claim 1, characterized in that, The pull-up unit includes a first transistor, the first terminal of which is connected to the drive output terminal of the ni-th stage drive circuit module, and the second terminal of which is connected to the drive control node of this stage. The mid-section pull-up unit includes: The second transistor has its control terminal connected to the middle control line, its first terminal connected to the drive output terminal of the ni-th stage drive circuit module, and its second terminal connected to the control terminal of the first transistor.

6. A display panel, characterized in that, The display panel includes: A pixel array, the pixel array comprising at least N scan lines, the pixel array having a first side and a second side disposed opposite to each other; A first gate driving circuit is disposed on a first side of the pixel array and electrically connected to multiple scan lines. A second gate driving circuit is disposed on the second side of the pixel array and electrically connected to the plurality of scan lines. The first test connection terminal is electrically connected to the output terminal of the final stage drive circuit module of the first gate drive circuit, so as to connect the output terminal of the final stage drive circuit module of the first gate drive circuit to an external test device. The second test connection terminal is electrically connected to the output terminal of the final stage drive circuit module of the second gate drive circuit, so as to connect the output terminal of the final stage drive circuit module of the second gate drive circuit to an external test device. Wherein, the first gate driving circuit and the second gate driving circuit are the gate driving circuits according to any one of claims 1-5.

7. An anomaly detection method, characterized in that, The anomaly detection method, applied to the display panel of claim 6, comprises: A single-drive test was performed on the first gate drive circuit and the second gate drive circuit in the display panel to obtain the abnormal gate drive circuit and the normal gate drive circuit. When triggering the nth stage drive circuit module of the abnormal gate drive circuit, the normal gate drive circuit is driven to the (n+i)th stage drive circuit module and then stops outputting. During the period when the normal gate drive circuit outputs the gate drive signals from the nth stage to the (n+i)th stage, the middle pull-up unit of the nth stage to the (n+i)th stage drive circuit module in the abnormal gate drive circuit is started. Based on the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit, determine the abnormal detection results of the drive circuit modules from the nth stage to the Nth stage of the abnormal gate drive circuit.

8. The anomaly detection method according to claim 7, characterized in that, When the pull-up unit is connected to the stage transmission output terminal and the drive output terminal of the ni-th stage drive circuit module, or when the pull-up unit is connected to the stage transmission output terminal of the ni-th stage drive circuit module, the middle section pull-up unit of the ni-th to ni-th stage drive circuit modules in the abnormal gate drive circuit is activated during the period when the normal gate drive circuit outputs the gate drive signals of the n-th to n+i-th stages, including: During the period when the normal gate drive circuit outputs the gate drive signals from level n to level n+i, the control line outputs a high-level control signal, so that the gate drive signals from level ni to level n+i output by the normal gate drive circuit are transmitted to the pull-up units from level n to level n+2i in the abnormal gate drive circuit through the scan line.

9. The anomaly detection method according to claim 7, characterized in that, When the pull-up unit is connected to the drive output terminal of the ni-th stage drive circuit module, during the period when the normal gate drive circuit outputs the gate drive signals of the nth to n+i stages, the middle section pull-up unit of the nth to n+i stage drive circuit modules in the abnormal gate drive circuit is activated, including: During the period when the normal gate drive circuit outputs the gate drive signals from level n to level n+i, the control middle section control line outputs a high-level middle section control signal, so that the gate drive signals from level ni to level n+i output by the normal gate drive circuit are transmitted to the pull-up units from level n to level n+2i in the abnormal gate drive circuit through the scan line respectively. The abnormal gate drive circuit outputs gate drive signals from level n+i to level N, and continues to control the middle section control line to output a high-level middle section control signal.

10. The anomaly detection method according to any one of claims 7-9, characterized in that, Based on the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit, determine the abnormal detection results of the drive circuit modules from the nth stage to the Nth stage, including: When the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit is abnormal, it is determined that there is an abnormal stage in the drive circuit modules from the nth stage to the Nth stage of the abnormal gate drive circuit. The anomaly detection method further includes: The m-th stage of any stage in the drive circuit module from the nth to the Nth stage of the abnormal gate drive circuit is used as the trigger test stage. The output stops after the normal gate drive module drives to the m+i-th stage drive circuit module. The middle pull-up unit of the m-th to m+i-th stage drive circuit module in the abnormal gate drive circuit is started during the period when the normal gate drive circuit outputs the gate drive signal from the nth to the n+i-th stage. Based on the output waveform of the Nth stage drive circuit module of the abnormal gate drive circuit, determine the abnormal detection results of the drive circuit modules from the mth stage to the Nth stage of the abnormal gate drive circuit.

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