Charge circulation type SRAM (Static Random Access Memory) low-power-consumption mode switching circuit and control method thereof
By using a charge-cycled SRAM low-power mode switching circuit and employing partitioned enable and charge reuse module design, the static leakage current and mode switching power consumption of SRAM are reduced, thereby improving the battery life of IoT devices.
Patent Information
- Application Number
- CN202410505068.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-10-28
AI Technical Summary
Existing SRAM has high static leakage power consumption and high dynamic power consumption during mode switching, which limits the battery life of IoT devices.
A low-power mode switching circuit using charge-cycled SRAM is adopted. Static leakage current is reduced by partitioning the enable storage block, and energy is collected by the charge collection module. During mode switching, the power network is charged in advance by the charge multiplexing module using the storage capacitor, thereby reducing dynamic power consumption.
It significantly reduces static leakage current of SRAM and dynamic power consumption during mode switching, thereby improving the battery life of IoT devices.
Smart Images
Figure CN120853644A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SRAM technology, and in particular to a charge-cycled SRAM low-power mode switching circuit and its control method. Background Technology
[0002] In recent years, the widespread use of IoT mobile devices has posed a severe challenge to their battery life, leading to a growing demand for ultra-low-power small platforms. Microcontroller units (MCUs), with their advantages of low power consumption and high performance, are typically used as the core chip in IoT devices requiring long battery life. As process nodes advance, the leakage power consumption of MCUs has gradually increased as a proportion of total power consumption, becoming a significant source of power consumption. Static leakage current in SRAM is a major component of this, therefore, reducing the static power consumption of SRAM is crucial for improving the battery life of IoT devices.
[0003] In existing technologies, reducing the system operating voltage can effectively reduce SRAM power consumption, but it significantly reduces SRAM read / write stability and drastically degrades performance. Designing multiple power management modes for SRAM allows for mode control at the system level. SRAM that is not frequently accessed can be put into a low-power mode, significantly reducing leakage current. However, this approach suffers from high dynamic energy consumption during mode switching, resulting in limited overall power savings. Therefore, designing a dedicated SRAM dynamic mode switching circuit to reduce energy consumption during mode switching is crucial for reducing the overall power consumption of SRAM. Summary of the Invention
[0004] Purpose of the invention: The purpose of this invention is to provide a charge-cycled SRAM low-power mode switching circuit and its control method. By partitioning the enabled memory blocks, the static leakage current is reduced, and energy is collected through a charge collection module during read and write operations. Secondly, during mode switching, the power network is pre-charged using a storage capacitor by a charge multiplexing module. The dynamic power consumption of SRAM when switching from low-power mode to working mode is effectively reduced by the charge cycling method.
[0005] Technical solution: A low-power mode switching circuit for charge-cycle SRAM, characterized in that it includes a 2-to-4 decoder, a zeroth memory block, a first memory block, a second memory block, and a third memory block; the 2-to-4 decoder is used to control the partition enabling of the zeroth memory block, the first memory block, the second memory block, and the third memory block; the zeroth selection block signal, the first selection block signal, the second selection block signal, and the third selection block signal of the 2-to-4 decoder are respectively connected to the zeroth memory block, the first memory block, the second memory block, and the third memory block; the zeroth memory block, the first memory block, the second memory block, and the third memory block have the same components and circuit structure;
[0006] Furthermore, the zeroth memory block includes a word line driving module, a charge collection module, a memory array module, a charge multiplexing timing control module, a charge multiplexing module, a read / write driving and timing module, and a capacitor. The word line driving module is used to generate word lines, the charge collection module controls the collection of energy during the word line signal flipping process, the memory array module is used to store data, the charge multiplexing timing control module is used to generate charge multiplexing module control signals, the charge multiplexing module is used to implement charge multiplexing during SRAM mode switching, the read / write driving and timing module is used to generate SRAM read / write control signals and timing signals, and the capacitor is used to store charge.
[0007] Specifically, the zero word line signal of the word line driver module is connected to the zero word line terminal of the charge collection module and the zero word line output signal of the storage array module. The first node signal and the second node signal of the word line driver module are connected to the first node terminal and the second node terminal of the charge collection module, respectively. The output signal of the charge collection module is connected to the output terminal of the charge multiplexing module. The P-transistor control signal, N-transistor control signal, and charge multiplexing control signal of the charge multiplexing timing control module are connected to the P-transistor control terminal, N-transistor control terminal, and charge multiplexing control terminal of the charge multiplexing module, respectively. The input power supply terminal of the charge multiplexing module is connected to the first power supply terminal, and the input ground terminal is connected to the first ground terminal. The second power supply terminal and the second ground terminal are connected to the third power supply terminal and the third ground terminal of the read / write drive and timing module, respectively. In addition, one end of the capacitor is connected to the output terminal of the charge multiplexing module, and the other end is connected to the first ground terminal.
[0008] Furthermore, the word line driving module includes N word line driving units, and the N word line driving units operate on the same principle. Each word line driving unit includes a clock signal, an enable input signal, a first-level NAND gate, a first-level delay chain, a second-level NAND gate, a first-level inverter, a first MOSFET, a second MOSFET, a zeroth word line signal, a first node signal, a second node signal, a fourth power supply terminal, and a fourth ground terminal.
[0009] In this configuration, one input of the first-level NAND gate is connected to the clock signal, and the other input is connected to the enable input signal. The output of the first-level NAND gate is connected to the input of the first-level delay chain. One input of the second-level NAND gate is connected to the output of the first-level delay chain, and the other input is connected to the input of the first-level delay chain. The output of the second-level NAND gate is connected to the input of the first-level inverter, which is connected to the second node signal. The gate of the second MOSFET is connected to the output of the first-level inverter, and its drain is connected to the drain of the first MOSFET, which is connected to the zero word line signal. Its source is connected to the fourth ground terminal. The gate of the first MOSFET is connected to the output of the first-level NAND gate, which is connected to the first node signal, and its source is connected to the fourth power supply terminal.
[0010] Furthermore, the storage array module includes N storage cells, each of which can be connected to the word line driving module and the charge collection module via a corresponding word line (such as the zeroth word line output signal).
[0011] Furthermore, the charge collection module includes N charge collection units, all of which operate on the same principle. Each charge collection unit includes an AND gate, a third MOS transistor, a charge collection control signal, a zero word line terminal, a first node terminal, a second node terminal, and an output signal.
[0012] In this system, one input of the first-level AND gate is connected to the first node, and the other input is connected to the second node. The gate of the third MOS transistor is connected to the output of the first-level AND gate, which is connected to the charge collection control signal. The source is connected to the zero word line, and the drain is connected to the output signal.
[0013] Furthermore, the charge multiplexing timing control module includes a first-stage OR gate, a second-stage inverter, a second-stage NOR gate, a third-stage inverter, a second-stage delay chain, a third-stage NOR gate, a first-stage XOR gate, a zero-selection block signal, a P-transistor control signal, an N-transistor control signal, a charge multiplexing control signal, a delay chain input signal, a delay chain output signal, a first hold mode enable signal, and a second hold mode enable signal;
[0014] In this circuit, one input of the first-stage OR gate is connected to the zero-selection block signal, and the other input is connected to the second hold mode enable signal. The input of the second-stage inverter is connected to the first hold mode enable signal. One input of the second-stage NOR gate is connected to the output of the first-stage OR gate, and the other input is connected to the output of the second-stage inverter. The output is connected to the input of the third-stage inverter. The input of the second-stage delay chain is connected to the output of the second-stage NOR gate and connected to the delay chain input signal. One input of the first-stage XOR gate is connected to the output of the second-stage delay chain and connected to the delay chain output signal. The other input is connected to the input of the second-stage delay chain. One input of the third-stage NOR gate is connected to the output of the first-stage XOR gate and connected to the charge multiplexing control signal. The other input is connected to the output of the third-stage inverter and connected to the P-channel control signal. The output is connected to the N-channel control signal.
[0015] Furthermore, the charge multiplexing module includes an input power supply terminal, an input ground terminal, a second power supply terminal, a second ground terminal, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a P-channel control terminal, an N-channel control terminal, a charge multiplexing control terminal, and an output terminal;
[0016] In this configuration, the gate of the fourth MOSFET is connected to the control terminal of the P-transistor, the source is connected to the input power supply terminal, and the drain is connected to the second power supply terminal. The gate of the fifth MOSFET is connected to the control terminal of the N-transistor, the source is connected to the input ground terminal, and the drain is connected to the second ground terminal. The gate of the sixth MOSFET is connected to the charge multiplexing control terminal, the source is connected to the second ground terminal, and the drain is connected to the output terminal.
[0017] The charge cycling SRAM low-power mode switching circuit and its control method firstly enable the SRAM to select the storage block containing the selected row by generating a selection block signal through a 2-4 decoder in the working mode, while the other three storage blocks are still in low-power mode, thereby reducing leakage current.
[0018] Furthermore, assuming the zeroth memory block is selected, in the working mode, the first hold mode enable signal and the second hold mode enable signal are active high, the zeroth select block signal is active high, the P-channel control signal is low, the fourth MOSFET is turned on, the N-channel control signal is high, the fifth MOSFET is turned on, the charge multiplexing control signal is low, and the sixth MOSFET is off. The third power supply terminal and the third ground terminal of the read / write drive and timing module are both active, and the read / write drive and timing module can work normally. At the same time, the enable input signal is always active high, and the rising edge of the clock signal controls the rising edge of the zeroth word line signal. After the read / write is completed, the delay circuit in the word line drive module pulls the zeroth word line signal to low level in stages, which can collect a portion of the high-energy charge in the parasitic capacitance of the zeroth word line signal without affecting the read / write power consumption, and charge the capacitor.
[0019] When the zeroth memory block switches to low-power mode, in the initial stage, the first and second hold mode enable signals are active low, the zeroth select block signal is active high, the P-channel control signal is high, the fourth MOSFET is off, the N-channel control signal is low, and the fifth MOSFET is off. Due to the presence of a two-stage delay chain in the control circuit of the charge multiplexing timing control module, the charge multiplexing control signal is initially high, and the sixth MOSFET is briefly on. At this time, the second ground terminal is charged by the storage capacitor. After a period of time, when the low-power mode reaches a stable stage, the charge multiplexing control signal jumps to low, and the sixth MOSFET is off.
[0020] When the zeroth memory block is woken up, the first hold mode enable signal is active high, the second hold mode enable signal is active low, the zeroth select block signal is active high, the P-channel control signal is low, the fourth MOSFET is turned on, the N-channel control signal is high, and the fifth MOSFET is turned on. Due to the presence of a two-stage delay chain in the control circuit of the charge reuse timing control module, the charge reuse control signal is initially high, and the sixth MOSFET is also briefly turned on. At this time, the second ground terminal charges the capacitor once during the discharge process. After a period of time, it enters the stable phase of the wake-up mode, the charge reuse control signal jumps to low, and the sixth MOSFET is turned off. By using the delay circuit of the charge reuse timing control module to control the charge reuse module, the charge released to the second ground terminal is recovered by the storage capacitor in advance, realizing charge cycling and reducing mode switching power consumption. Compared with the prior art, the significant effects of this invention are as follows:
[0021] 1. This invention uses partitioned enabled storage blocks, enabling only the storage block with read / write requirements where the selected row of SRAM is located, while the other three storage blocks remain in low-power mode, greatly reducing static leakage current.
[0022] 2. This invention utilizes a charge collection module in working mode to pull down the word line signal step by step, collecting a portion of the high-energy charge in the parasitic capacitance of the word line signal without affecting the power consumption of reading and writing, and charging the storage capacitor, thus proposing a new approach to charge cycling.
[0023] 3. This invention designs a novel mode switching control method based on charge cycling power gating. It utilizes a charge reuse module to precharge the power network with a storage capacitor, and effectively reduces the dynamic power consumption of SRAM when switching from low-power mode to working mode through charge cycling. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the charge-cycled SRAM low-power mode switching circuit of the present invention;
[0025] Figure 2 This is a waveform diagram illustrating the working principle of the charge collection module under the operating mode of the present invention.
[0026] Figure 3 The waveform diagram is for timing control and mode switching based on the charge reuse module of the present invention. Detailed Implementation
[0027] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, a charge-cycle SRAM low-power mode switching circuit of the present invention includes a 2-4 decoder, a zeroth memory block BANK0, a first memory block BANK1, a second memory block BANK2, and a third memory block BANK3; the 2-4 decoder is used to control partition enable of the zeroth memory block BANK0, the first memory block BANK1, the second memory block BANK2, and the third memory block BANK3; the zeroth selection block signal BANKSEL0, the first selection block signal BANKSEL1, the second selection block signal BANKSEL2, and the third selection block signal BANKSEL3 of the 2-4 decoder are respectively connected to the zeroth memory block BANK0, the first memory block BANK1, the second memory block BANK2, and the third memory block BANK3; the components and circuit structure of the zeroth memory block BANK0, the first memory block BANK1, the second memory block BANK2, and the third memory block BANK3 are the same;
[0028] The zeroth memory block BANK0 includes a word line driver module, a charge collection module, a memory array module, a charge multiplexing timing control module, a charge multiplexing module, a read / write driver and timing module, and a capacitor C. store The word line driver module generates word lines, the charge collection module controls the collection of energy during the word line signal switching process, the storage array module stores data, the charge multiplexing timing control module generates the charge multiplexing module control signal TG, the charge multiplexing module implements charge multiplexing during SRAM mode switching, the read / write driver and timing module generates SRAM read / write control signals and timing signals, and capacitor C... store Used to store electrical charge;
[0029] Specifically, the zero word line signal WL0 of the word line driver module is connected to the zero word line terminal wl0 of the charge collection module and the zero word line output signal wlout0 of the storage array module. The first node signal NET1 and the second node signal NET2 of the word line driver module are connected to the first node terminal net1 and the second node terminal net2 of the charge collection module, respectively. The output signal OUT of the charge collection module is connected to the output terminal out of the charge multiplexing module. The P-transistor control signal PG_P, the N-transistor control signal PG_N, and the charge multiplexing control signal TG of the charge multiplexing timing control module are connected to the P-transistor control terminal pg_p, the N-transistor control terminal pg_n, and the charge multiplexing control terminal tg of the charge multiplexing module, respectively. The input power supply terminal VDDIN of the charge multiplexing module is connected to the first power supply terminal VDD1, and the input ground terminal VSSIN is connected to the first ground terminal VSS1. The second power supply terminal VDD2 and the second ground terminal VSS2 are connected to the third power supply terminal VDD3 and the third ground terminal VSS3 of the read / write driver and timing module, respectively. In addition, capacitor C... store One end is connected to the output terminal out of the charge multiplexing module, and the other end is connected to the first ground terminal VSS1.
[0030] Firstly, in the working mode, only the 2-4 decoder generates the selection block signal to enable the SRAM to select the memory block where the row is located, while the other three memory blocks are still in low-power mode, in order to reduce leakage current;
[0031] Furthermore, assuming the zeroth storage block BANK0 is selected, such as Figure 2As shown, during one cycle of read or write operation in working mode, the enable input signal SEL remains high. The rising edge of the clock signal CLK controls the rising edge of the zero word line signal WL0, turning on the first MOSFET M1 and turning off the second MOSFET M2. The zero word line signal WL0 is gradually charged to a high level, and the SRAM begins read or write operation. After the read or write operation is completed, the falling edge of the clock signal CLK turns off the first MOSFET M1, and the first signal node NET1 becomes high. Due to the existence of the first-level delay chain buffer1, the second signal node NET2 remains high, turning off the second MOSFET M2. The charge collection control signal tg_wl becomes high, and the third MOSFET M3 turns on. The charge in the parasitic capacitance of the zero word line signal WL0 is first transferred to the storage capacitor C through the third MOSFET M3. store During charging, the zero-word line signal WL0 initially drops slightly. After a brief delay, it waits for the second signal node NET2 to go low, the charge collection control signal tg_wl goes low, the third MOSFET M3 turns off, and the second MOSFET M2 turns on. The remaining charge in the zero-word line signal WL0 continues to be released to ground through the second MOSFET M2, and the zero-word line signal WL0 is pulled low again. Therefore, the delay circuit in the word line driver module pulls the zero-word line signal WL0 low in stages, collecting a portion of the high-energy charge in the zero-word line signal WL0 without affecting read / write power consumption, which is then used for the storage capacitor C. store The design of the charge collection circuit for charging and operating modes offers a new approach to charge cycling.
[0032] Furthermore, a novel mode-switching control method based on charge cycling power supply gating was designed for the zeroth storage block BANK0. Specifically, in the charge multiplexing timing control module and the charge multiplexing module, such as... Figure 3 As shown, in the working mode, the first hold mode enable signal RET1N and the second hold mode enable signal RET2N are active high, the zero selection block signal BANKSEL0 is active high, the P-channel control signal PG_P is low, the fourth MOSFET M4 is turned on, the N-channel control signal PG_N is high, the fifth MOSFET M5 is turned on, the charge multiplexing control signal TG is low, the sixth MOSFET M6 is turned off, and the third power supply terminal VDD3 and the third ground terminal VSS3 of the read / write drive and timing module are both active, allowing the read / write drive and timing module to work normally.
[0033] When the zeroth memory block BANK0 switches to low-power mode, in the initial stage, the first hold mode enable signal RET1N and the second hold mode enable signal RET2N are active low, the zeroth select block signal BANKSEL0 is active high, the P-channel control signal PG_P is high, the fourth MOSFET M4 is off, the N-channel control signal PG_N is low, and the fifth MOSFET M5 is off. Due to the presence of a two-stage delay chain buffer2 in the control circuit of the charge multiplexing timing control module, the charge multiplexing control signal TG is initially high, and the sixth MOSFET M6 is briefly turned on. At this time, the second ground terminal VSS2 is blocked by capacitor C. store Charging; after a period of time, when the low-power mode is in a stable phase, the charge reuse control signal TG jumps to a low level, and the sixth MOSFET M6 is turned off.
[0034] When the zeroth memory block BANK0 is woken up, the first hold mode enable signal RET1N is active high, the second hold mode enable signal RET2N is active low, the zeroth select block signal BANKSEL0 is active high, the P-channel control signal PG_P is low, the fourth MOSFET M4 is turned on, the N-channel control signal PG_N is high, and the fifth MOSFET M5 is turned on. Due to the presence of a two-stage delay chain buffer2 in the control circuit of the charge multiplexing timing control module, the charge multiplexing control signal TG is initially high, and the sixth MOSFET M6 is also briefly turned on. At this time, the second ground terminal VSS2 first supplies power to capacitor C during the discharge process of the falling phase. store After a single charge, the system enters a stable wake-up mode phase after a period of time. The charge reuse control signal TG jumps to a low level, turning off the sixth MOSFET M6. The delay circuit of the charge reuse timing control module controls the charge reuse module to ensure that the charge released from the second ground terminal VSS2 is pre-recovered by the storage capacitor, achieving charge cycling and reducing mode switching power consumption. As described above, this invention designs a charge-cycling SRAM low-power mode switching circuit and its control method. First, by partitioning the enabled memory blocks, only the memory blocks that need to be read and written are enabled, reducing static leakage current. Second, during mode switching, the charge reuse module pre-charges the power network using the storage capacitor. Through charge cycling, the dynamic power consumption of the SRAM when switching from low-power mode to operating mode is effectively reduced.
[0035] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A charge-cycle SRAM low-power mode switching circuit, characterized in that, It includes a 2-to-4 decoder, a zeroth memory block (BANK0), a first memory block (BANK1), a second memory block (BANK2), and a third memory block (BANK3). The 2-to-4 decoder is used to control the partition enabling of the zeroth memory block (BANK0), the first memory block (BANK1), the second memory block (BANK2), and the third memory block (BANK3). The zeroth selection block signal (BANKSEL0), the first selection block signal (BANKSEL1), the second selection block signal (BANKSEL2), and the third selection block signal (BANKSEL3) of the 2-to-4 decoder are respectively connected to the zeroth memory block (BANK0), the first memory block (BANK1), the second memory block (BANK2), and the third memory block (BANK3). The zeroth memory block (BANK0), the first memory block (BANK1), the second memory block (BANK2), and the third memory block (BANK3) have the same components and circuit structure. The zeroth memory block (BANK0) includes a word line driver module, a charge collection module, a memory array module, a charge multiplexing timing control module, a charge multiplexing module, a read / write driver and timing module, and a capacitor (C). store The module includes a first power supply terminal (VDD1) and a first ground terminal (VSS1). A word line driver module generates word lines. A charge collection module controls the collection of energy during word line signal switching. A storage array module stores data. A charge multiplexing timing control module generates charge multiplexing module control signals (TG). The charge multiplexing module implements charge multiplexing during SRAM mode switching. A read / write driver and timing module generates SRAM read / write control signals and timing signals. A capacitor (C...) store Used to store electric charge; Specifically, the zero word line signal (WL0) of the word line driver module is connected to the zero word line terminal (wl0) of the charge collection module and the zero word line output signal (wlout0) of the memory array module. The first node signal (NET1) and the second node signal (NET2) of the word line driver module are connected to the first node terminal (net1) and the second node terminal (net2) of the charge collection module, respectively. The output signal (OUT) of the charge collection module is connected to the output terminal (out) of the charge multiplexing module. The P-transistor control signals (PG_P) and N-transistor control signals (N) of the charge multiplexing timing control module are connected to the charge multiplexing timing control module. The transistor control signal (PG_N) and charge multiplexing control signal (TG) are connected to the P-transistor control terminal (pg_p), N-transistor control terminal (pg_n), and charge multiplexing control terminal (tg) of the charge multiplexing module, respectively. The input power supply terminal (VDDIN) of the charge multiplexing module is connected to the first power supply terminal (VDD1), and the input ground terminal (VSSIN) is connected to the first ground terminal (VSS1). The second power supply terminal (VDD2) and the second ground terminal (VSS2) are connected to the third power supply terminal (VDD3) and the third ground terminal (VSS3) of the read / write drive and timing module, respectively. Additionally, a capacitor (C...) store One end is connected to the output terminal (out) of the charge multiplexing module, and the other end is connected to the first ground terminal (VSS1).
2. The word line driving module according to claim 1, characterized in that, The word line driving module includes N word line driving units, and the N word line driving units operate on the same principle. Each word line driving unit includes a clock signal (CLK), an enable input signal (SEL), a first-level NAND gate (NAND1), a first-level delay chain (buffer1), a second-level NAND gate (NAND2), a first-level inverter (INV1), a first MOSFET (M1), a second MOSFET (M2), a zero-word line signal (WL0), a first node signal (NET1), a second node signal (NET2), a fourth power supply terminal (VDDC), and a fourth ground terminal (VSSC). In this configuration, one input of the first-level NAND gate (NAND1) is connected to the clock signal (CLK), and the other input is connected to the enable input signal (SEL). The output of the first-level NAND gate (NAND1) is connected to the input of the first-level delay chain (buffer1). One input of the second-level NAND gate (NAND2) is connected to the output of the first-level delay chain (buffer1), and the other input is connected to the input of the first-level delay chain (buffer1). The output of the second-level NAND gate (NAND2) is connected to the input of the first-level inverter (INV1) and then to the second node signal (NET2). The gate of the second MOSFET (M2) is connected to the output of the first-level inverter (INV1), and its drain is connected to the drain of the first MOSFET (M1) and then to the zero word line signal (WL0). Its source is connected to the fourth ground terminal (VSSC). The gate of the first MOSFET (M1) is connected to the output of the first-level NAND gate (NAND1) and then to the first node signal (NET1). Its source is connected to the fourth power supply terminal (VDDC). According to claim 1, the storage array module is characterized in that the storage array module includes N storage cells, and each storage cell can be connected to the word line driving module and the charge collection module through a corresponding word line (such as the zeroth word line output signal (wlout0)).
3. The charge collection module according to claim 1, characterized in that, The charge collection module includes N charge collection units, and the N charge collection units work on the same principle. Each charge collection unit includes an AND gate (AND1), a third MOS transistor (M3), a charge collection control signal (tg_wl), a zero word line terminal (wl0), a first node terminal (net1), a second node terminal (net2), and an output signal (OUT). In this circuit, one input of the first-level AND gate (AND1) is connected to the first node (net1), and the other input is connected to the second node (net2). The gate of the third MOSFET (M3) is connected to the output of the first-level AND gate (AND1) and connected to the charge collection control signal (tg_wl). The source is connected to the zero word line (wl0), and the drain is connected to the output signal (OUT).
4. The charge multiplexing timing control module according to claim 1, characterized in that, The charge multiplexing timing control module includes a first-stage OR gate (NOR1), a second-stage inverter (INV2), a second-stage NOR gate (NOR2), a third-stage inverter (INV3), a second-stage delay chain (buffer2), a third-stage NOR gate (NOR3), a first-stage XOR gate (XOR1), a zero-selection block signal (BANKSEL0), a P-transistor control signal (PG_P), an N-transistor control signal (PG_N), a charge multiplexing control signal (TG), a delay chain input signal (PG), a delay chain output signal (PG_bf), a first hold mode enable signal (RET1N), and a second hold mode enable signal (RET2N). In this circuit, one input of the first-stage NOR gate (NOR1) is connected to the zero-order selection block signal (BANKSEL0), and the other input is connected to the second hold mode enable signal (RET2N). The input of the second-stage inverter (INV2) is connected to the first hold mode enable signal (RET1N). One input of the second-stage NOR gate (NOR2) is connected to the output of the first-stage NOR gate (NOR1), and the other input is connected to the output of the second-stage inverter (INV2). The output of this second-stage inverter is connected to the input of the third-stage inverter (INV3). The input of the second-stage delay chain (buffer2) is connected to the second-stage NOR gate (NOR1). The output of NOR2 is connected to the input signal (PG) of the delay chain. One input of the first-stage XOR gate (XOR1) is connected to the output signal (PG_bf) of the second-stage delay chain (buffer2), and the other input is connected to the input of the second-stage delay chain (buffer2). One input of the third-stage NOR gate (NOR3) is connected to the output signal (TG) of the first-stage XOR gate (XOR1), and the other input is connected to the output signal (PG_P) of the third-stage inverter (INV3), and the output is connected to the control signal (PG_N) of the P-transistor.
5. The charge multiplexing module according to claim 1, characterized in that, The charge multiplexing module includes an input power terminal (VDDIN), an input ground terminal (VSSIN), a second power terminal (VDD2), a second ground terminal (VSS2), a fourth MOSFET (M4), a fifth MOSFET (M5), a sixth MOSFET (M6), a P-channel control terminal (pg_p), an N-channel control terminal (pg_n), a charge multiplexing control terminal (tg), and an output terminal (out). Among them, the gate of the fourth MOSFET (M4) is connected to the P-channel control terminal (pg_p), the source is connected to the input power supply terminal (VDDIN), and the drain is connected to the second power supply terminal (VDD2). The gate of the fifth MOSFET (M5) is connected to the N-channel control terminal (pg_n), the source is connected to the input ground terminal (VSSIN), and the drain is connected to the second ground terminal (VSS2). The gate of the sixth MOSFET (M6) is connected to the charge multiplexing control terminal (tg), the source is connected to the second ground terminal (VSS2), and the drain is connected to the output terminal (out).
6. The charge-cycle SRAM low-power mode switching circuit and its control method as described in any one of claims 1-5, characterized in that, Firstly, in the working mode, only the 2-4 decoder generates the selection block signal to enable the SRAM to select the memory block where the row is located, while the other three memory blocks are still in low-power mode, in order to reduce leakage current; Furthermore, assuming the zeroth memory block (BANK0) is selected, in the operating mode, the first hold mode enable signal (RET1N) and the second hold mode enable signal (RET2N) are active high, the zeroth select block signal (BANKSEL0) is active high, the P-channel control signal (PG_P) is low, the fourth MOSFET (M4) is turned on, the N-channel control signal (PG_N) is high, the fifth MOSFET (M5) is turned on, the charge multiplexing control signal (TG) is low, and the sixth MOSFET (M6) is turned off. Both the third power supply terminal (VDD3) and the third ground terminal (VSS3) of the read / write driver and timing module are valid, and the read / write driver and timing module can work normally. Simultaneously, the enable input signal (SEL) remains high, and the rising edge of the clock signal (CLK) controls the rising edge of the zeroth word line signal (WL0). After read / write operations are completed, the delay circuit in the word line driver module pulls the zeroth word line signal (WL0) low in stages. This allows for the collection of a portion of the high-energy charge from the parasitic capacitance of the zeroth word line signal (WL0) without affecting read / write power consumption, thus providing energy for the capacitor (C). store )Charge; When the zeroth memory block (BANK0) switches to low-power mode, in the initial stage, the first hold mode enable signal (RET1N) and the second hold mode enable signal (RET2N) are active low, the zeroth select block signal (BANKSEL0) is active high, the P-channel control signal (PG_P) is high, the fourth MOSFET (M4) is off, the N-channel control signal (PG_N) is low, and the fifth MOSFET (M5) is off. Due to the presence of a two-stage delay chain (buffer2) in the control circuit of the charge multiplexing timing control module, the charge multiplexing control signal (TG) is initially high, and the sixth MOSFET (M6) is briefly turned on. At this time, the second ground terminal (VSS2) is connected to the storage capacitor (C). store Charging; after a period of time, when the low-power mode is in a stable phase, the charge reuse control signal (TG) jumps to a low level, and the sixth MOSFET (M6) is turned off. When the zeroth memory block (BANK0) is woken up, the first hold mode enable signal (RET1N) is active high, the second hold mode enable signal (RET2N) is active low, the zeroth select block signal (BANKSEL0) is active high, the P-channel control signal (PG_P) is low, the fourth MOSFET (M4) is turned on, the N-channel control signal (PG_N) is high, and the fifth MOSFET (M5) is turned on. Due to the presence of a two-stage delay chain (buffer2) in the control circuit of the charge multiplexing timing control module, the charge multiplexing control signal (TG) is initially high, and the sixth MOSFET (M6) is also briefly turned on. At this time, the second ground terminal (VSS2) first supplies power to the capacitor (C) during the falling discharge process. store After being charged once, the device enters a stable phase of wake-up mode after a period of time. The charge reuse control signal (TG) jumps to a low level, and the sixth MOSFET (M6) is turned off. By using the delay circuit of the charge reuse timing control module, the charge reuse module is controlled to realize the early recovery of the charge released to the second ground terminal (VSS2) by the storage capacitor, thereby achieving charge cycling and reducing power consumption during mode switching.