Storage system, method of operating a storage system, controller, and storage medium

Abstract

The application provides a storage system, an operation method of the storage system, a controller and a storage medium, and relates to the technical field of storage. The storage system comprises a memory and a controller. The controller is configured to send a read command to the memory. The memory is configured to read data stored in a first storage unit in the memory according to the read command. The first storage unit and a second storage unit are located in the same storage string, and word lines coupled by the first storage unit and the second storage unit are adjacent. The second storage unit is a storage unit that has not yet written data. The controller is further configured to send a write command to the memory. The memory is further configured to write the data read from the first storage unit into the second storage unit according to the write command. The above scheme can improve the data retention performance of the edge word line.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage system, a method for operating the storage system, a controller, and a storage medium. Background Technology

[0002] In memory products such as NAND, data retention performance is an important indicator for measuring the performance of storage products.

[0003] In related technologies, when the programming states of two adjacent memory cells in the same memory string differ significantly, there will be a relatively obvious phenomenon of lateral electron migration. Therefore, for data blocks in memory that are not fully written, the data retention performance of their edge word lines is poor. Summary of the Invention

[0004] This application provides a storage system, a method for operating the storage system, a controller, and a storage medium, which can improve the data retention performance of edge word lines in data blocks that are not fully written. The technical solution is as follows:

[0005] On one hand, a storage system is provided, characterized in that the storage system includes: a memory and a controller; the controller is configured to send a read command to the memory; the memory is configured to read data stored in a first storage cell in the memory according to the read command; the first storage cell and a second storage cell are located in the same memory string, and the word lines coupled to the first storage cell and the second storage cell are adjacent; the second storage cell is a storage cell that has not yet been written with data; the controller is further configured to send a write command to the memory; the memory is further configured to write data read from the first storage cell to the second storage cell according to the write command.

[0006] In an optional embodiment, the controller is further configured to obtain the physical address of the first storage unit and the physical address of the second storage unit; the controller is configured to send the read command to the memory based on the physical address of the first storage unit, and to send the write command to the memory based on the physical address of the second storage unit.

[0007] In an optional embodiment, the controller is further configured to: before sending the read command to the memory, if the memory block is not full and the data in the third memory cell of the memory block is valid data, determine the first memory cell in the memory block and the second memory cell corresponding to the first memory cell based on the position of the third memory cell in the memory block; wherein the third memory cell is the last memory cell among the memory cells in the memory block that have been written with data.

[0008] In an optional embodiment, the controller is configured to: when the third storage unit is the last storage unit in the nth word line of the storage block, determine the storage units in the nth word line as the first storage unit; and determine the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0009] In an optional embodiment, the controller is configured to: if the third storage unit is not the last storage unit in the nth word line of the storage block, determine the non-empty storage unit in the nth word line as the first storage unit, and determine the storage unit in the (n+1)th word line of the storage block that is located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; and determine the storage unit in the nth word line that has not yet been written with data as the second storage unit, and determine the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit as the first storage unit corresponding to the second storage unit; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0010] In an optional embodiment, the controller is further configured to: before determining the first storage unit and the second storage unit in the storage block based on the location of the third storage unit in the storage block, query whether the third storage unit in the storage block has a fill mark; the fill mark is used to indicate that the data in the corresponding storage unit is invalid fill data; if the third storage unit does not have a fill mark, determine that the data in the third storage unit is valid data.

[0011] In an optional embodiment, the controller is further configured to set the fill mark on the second storage cell after the memory has successfully written the data read from the first storage cell into the second storage cell.

[0012] In an optional embodiment, the controller is configured to: set the padding flag in the logical address to physical address mapping table corresponding to the physical address of the second storage unit; or, set the padding flag outside the logical address to physical address mapping table corresponding to the identification information of the second storage unit.

[0013] In an optional embodiment, the controller is further configured to: cancel the fill mark corresponding to the storage cell in the storage block when the storage block is erased.

[0014] In an optional embodiment, the controller is configured to send the read command to the memory when the duration for which data has been written to the first storage unit reaches a duration threshold.

[0015] On the other hand, a method for operating a storage system is provided, comprising: a controller sending a read command to a memory; the memory reading data stored in a first storage cell according to the read command; the first storage cell and a second storage cell being located in the same storage string, and the word lines coupled to the first storage cell and the second storage cell being adjacent; the second storage cell being a storage cell for which no data has yet been written; the controller sending a write command to the memory; and the memory writing data read from the first storage cell to the second storage cell according to the write command.

[0016] In an optional embodiment, before the controller sends a read command to the memory, the method further includes: the controller obtaining the physical address of the first memory cell and the physical address of the second memory cell; the controller sending a write command to the memory includes: the controller sending the read command to the memory based on the physical address of the first memory cell; the controller sending a write command to the memory includes: the controller sending the write command to the memory based on the physical address of the second memory cell.

[0017] In an optional embodiment, before the controller sends the read command to the memory, the method further includes: if the storage block is not full and the data in the third storage unit of the storage block is valid data, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit based on the position of the third storage unit in the storage block; wherein the third storage unit is the storage unit of the storage block containing written data, the last storage unit.

[0018] In an optional embodiment, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit based on the position of the third storage unit in the storage block, including: when the third storage unit is the last storage unit in the nth word line of the storage block, the controller determines the storage units in the nth word line as the first storage unit; and determines the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0019] In an optional embodiment, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit based on the position of the third storage unit in the storage block, including: if the third storage unit is not the last storage unit in the nth word line of the storage block, the controller determines the non-empty storage unit in the nth word line as the first storage unit, and determines the storage unit in the (n+1)th word line of the storage block that is located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; and the controller determines the storage unit in the nth word line that has not yet been written with data as the second storage unit, and determines the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit as the first storage unit corresponding to the second storage unit; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0020] In an optional embodiment, the method further includes: before determining the first storage unit and the second storage unit in the storage block based on the position of the third storage unit in the storage block, the controller queries whether the third storage unit in the storage block has a fill mark; the fill mark is used to indicate that the data in the corresponding storage unit is invalid fill data; if the third storage unit does not have a fill mark, the data in the third storage unit is determined to be valid data.

[0021] In an optional embodiment, the method further includes: after the memory successfully writes data read from the first storage unit into the second storage unit, the controller sets the fill mark on the second storage unit.

[0022] In an optional embodiment, the controller sets the padding mark for the second storage unit by: the controller setting the padding mark in the logical address to physical address mapping table corresponding to the physical address of the second storage unit; or, the controller setting the padding mark outside the logical address to physical address mapping table corresponding to the identification information of the second storage unit.

[0023] In an optional embodiment, the method further includes: when the storage block is erased, the controller cancels the fill mark corresponding to the storage cell in the storage block.

[0024] In an optional embodiment, the controller sends a read command to the memory, including: the controller sending the read command to the memory when the duration for which data has been written to the first storage unit reaches a duration threshold.

[0025] On the other hand, a controller is provided, the controller including memory and control circuitry, the control circuitry being configured to: send a read command to the memory; the read command instructing the memory to read data stored in a first storage cell in the memory; the first storage cell and a second storage cell are located in the same memory string, and the word lines coupled to the first storage cell and the second storage cell are adjacent; the second storage cell is a storage cell that has not yet been written with data; and send a write command to the memory; the write command instructing the memory to write data read from the first storage cell to the second storage cell.

[0026] In an optional embodiment, the control circuit is further configured to acquire the physical address of the first storage unit and the physical address of the second storage unit; the control circuit is configured to send the read command to the memory based on the physical address of the first storage unit, and to send the write command to the memory based on the physical address of the second storage unit.

[0027] In an optional embodiment, the control circuit is further configured to: before sending the read command to the memory, if the memory block is not full and the data in the third memory cell of the memory block is valid data, determine the first memory cell in the memory block and the second memory cell corresponding to the first memory cell based on the position of the third memory cell in the memory block; wherein the third memory cell is the last memory cell among the memory cells in the memory block that have been written with data.

[0028] In an optional embodiment, the control circuit is configured to: when the third storage unit is the last storage unit in the nth word line of the storage block, determine the storage units in the nth word line as the first storage unit; and determine the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0029] In an optional embodiment, the control circuit is configured to: if the third storage cell is not the last storage cell in the nth word line of the storage block, determine the non-empty storage cell in the nth word line as the first storage cell, and determine the storage cell in the (n+1)th word line of the storage block that is located in the same storage string as the first storage cell as the second storage cell corresponding to the first storage cell; and determine the storage cell in the nth word line that has not yet been written with data as the second storage cell, and determine the storage cell in the (n-1)th word line of the storage block that is located in the same storage string as the second storage cell as the first storage cell corresponding to the second storage cell; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0030] In an optional embodiment, the controller is further configured to: before determining the first storage unit and the second storage unit in the storage block based on the location of the third storage unit in the storage block, query whether the third storage unit in the storage block has a fill mark; the fill mark is used to indicate that the data in the corresponding storage unit is invalid fill data; if the third storage unit does not have a fill mark, determine that the data in the third storage unit is valid data.

[0031] In an optional embodiment, the control circuit is further configured to set the fill mark on the second storage cell after the memory has successfully written the data read from the first storage cell into the second storage cell.

[0032] In an optional embodiment, the control circuit is configured to: set the padding flag in the logical address to physical address mapping table corresponding to the physical address of the second memory cell; or, set the padding flag outside the logical address to physical address mapping table corresponding to the identification information of the second memory cell.

[0033] In an optional embodiment, the control circuit is further configured to: cancel the fill mark corresponding to the storage cell in the storage block when the storage block is erased.

[0034] In an optional embodiment, the control circuit is configured to send the read command to the memory when the duration for which data has been written to the first storage unit reaches a duration threshold.

[0035] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a controller in a storage system, implement the operation method of the storage system as described in any of the above embodiments.

[0036] The technical solution provided in this application may include the following beneficial effects:

[0037] For a memory string that is not fully written, if the first memory cell in the memory string has been written with data and the second memory cell adjacent to the first memory cell in the memory string has not been written with data, then the word line where the first memory cell is located is the edge word line. In this embodiment, the data in the first memory cell can be read out and then written to the second memory cell by reading first and then writing. This allows the first memory cell and the second memory cell to store the same data, that is, to put the first memory cell and the second memory cell in the same programming state. This can suppress the phenomenon of lateral electron migration between the first memory cell and the memory cell, thereby improving the data retention performance of the first memory cell, that is, improving the data retention performance of the edge word line. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the structure of a memory card involved in this application;

[0041] Figure 3 This is a schematic diagram of the structure of a solid-state driver involved in this application;

[0042] Figure 4 This is a block diagram of a memory illustrated in an exemplary embodiment of this application;

[0043] Figure 5 This is a schematic circuit diagram of a memory shown in an exemplary embodiment of this application;

[0044] Figure 6 This is a cross-sectional side view of a storage string shown in an exemplary embodiment of this application;

[0045] Figure 7 This is a schematic diagram of lateral electron migration between storage cells;

[0046] Figure 8 This is a schematic diagram of another type of lateral electron migration between storage cells;

[0047] Figure 9 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application;

[0048] Figure 10 This is a schematic diagram of the structure of the storage system involved in the embodiments of this application;

[0049] Figure 11 This is a schematic diagram of the programming state of a storage unit according to an embodiment of this application;

[0050] Figure 12 This is a flowchart illustrating a read / write operation according to an embodiment of this application;

[0051] Figure 13 This is a diagram illustrating the effect of a read / write operation according to an embodiment of this application.

[0052] Figure 14 This is a flowchart illustrating another read / write operation according to an embodiment of this application;

[0053] Figure 15 This is a diagram illustrating the effect of another read / write operation involved in an embodiment of this application.

[0054] Figure 16 This is a system framework diagram related to an embodiment of this application;

[0055] Figure 17 This is another system framework diagram involving embodiments of this application;

[0056] Figure 18 This is a flowchart of an operation method of a storage system provided in an exemplary embodiment of this application;

[0057] Figure 19 This is a schematic diagram of the controller provided in an exemplary embodiment of this application. Detailed Implementation

[0058] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0059] The computer system provided in this application embodiment may include a host and a storage system. The storage system may include 3D memory, such as 3D NAND flash memory.

[0060] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application. Figure 1 As shown, the computer system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100. The controller 200 may also be referred to as a memory controller.

[0061] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0062] The controller 200 can also communicate with external devices according to specific communication protocols. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. Interface protocols may include Universal Serial Bus (USB) protocol, Multi-Media Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Development Environment (IDE) protocol, FireWire protocol, etc.

[0063] In an optional embodiment, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices can be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In this scenario, such as... Figure 1 As shown, the computer system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0064] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0065] As an example, Figure 2 This is a schematic diagram of the structure of a memory card involved in this application. Figure 2 As shown, the controller 200 and a single memory 100 can be integrated into the memory card 40. The memory card 40 may include PCMCIA (PC) cards, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 40 may also include a connector 410 for coupling the memory card 40 to the host.

[0066] As another example Figure 3 This is a schematic diagram of the structure of a solid-state drive involved in this application. Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 50. The solid-state drive 50 may also include a connector 510 for coupling the solid-state drive 50 to the host. The storage capacity and / or operating speed of the solid-state drive 50 is greater than that of the memory card 40.

[0067] also, Figures 1 to 3The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0068] Figure 4 This is a block diagram illustrating a memory according to an exemplary embodiment of this application. (Reference) Figure 4 The memory 400 may include a memory cell array 401, a page buffer 404, a column decoder 406, a row decoder 408, a voltage generator 410, a control logic unit 412, a register 414, and data input / output circuitry 416. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0069] Page buffer 404 can be configured to read data from memory cell array 401 and program (write) data to memory cell array 401 according to control signals from control logic unit 412. In one example, page buffer 404 can store data to be programmed into selected pages of memory cell array 401 (write data). In another example, page buffer 404 can output read data during a programming verification operation to ensure that data has been correctly programmed into the corresponding memory cell coupled to the selected word line of memory cell array 401. Column decoder 406 can operate in response to control signals provided by control logic unit to select one or more NAND memory strings in memory cell array 401. Row decoder can operate in response to control signals provided by control logic unit and select / deselect selected rows of memory cell array 401. Row decoder can also be configured to supply voltage generated from voltage generator 410 to selected and unselected word lines of memory cell array 401. As described in detail below, row decoder / word line driver 408 is configured to perform erase operations on memory cells coupled to one or more selected word lines of memory cell array 401. Voltage generator 410 can use external or internal power supply voltages to generate various voltages required by the memory, such as programming voltage, read voltage, pass voltage, verification voltage, bit line voltage, and combinations thereof.

[0070] Control logic unit 412 can be coupled to voltage generator 410, page buffer 404, column decoder 406, row decoder 408, and data input / output circuit 416, etc., and is configured to control the operation of each peripheral circuit. Control logic unit can generate operation signals in response to commands or control signals from the memory controller. Register 414 can be coupled to control logic unit 412 and includes a status register, command register, and address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit. Data input / output circuit 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 412, and to buffer status information received from control logic unit 412 and relay it to the host. Data input / output circuit 416 can also be coupled to column decoder and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 401.

[0071] Figure 5 This is a schematic circuit diagram of a memory shown in an exemplary embodiment of this application. Figure 5 As shown, memory 500 may include a memory cell array device 501 and peripheral circuitry 502 coupled to the memory cell array device 501. The memory cell array device 501 may be a NAND flash memory cell array, wherein memory cells 506 are provided in the form of an array of NAND memory strings 508, each NAND memory string 508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. In some embodiments, each memory cell 506 is a single-level cell (SLC) having two possible memory states and capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 506 is a multilevel cell capable of storing more than a single bit of data in more than two memory states. For example, each cell can store two bits (i.e., Multi-Level Cell (MLC)), three bits (i.e., Triple-Level Cell (TLC)), or four bits (i.e., Quad-Level Cell (QLC)).

[0072] like Figure 5 As shown, each NAND memory string 508 may include at least one source select transistor 510 at its source end and at least one drain select transistor 512 at its drain end. The source select transistor 510 and drain select transistor 512 may be configured to activate a selected NAND memory string 508 during read and program operations. In some embodiments, the sources of NAND memory strings 508 in the same block 504 are coupled via the same source line (SL). According to some embodiments, the drain select transistor 512 of each NAND memory string 508 is coupled to a corresponding bit line 516. In some embodiments, each NAND memory string 508 is configured to be selected or deselected by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding drain select transistor 512 via one or more drain select lines 513 and / or by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding source select transistor 510 via one or more source select lines 515.

[0073] like Figure 5 As shown, the memory cell array may include multiple blocks. In some embodiments, each block 504 is a basic data unit for erase operations, that is, all memory cells 506 on the same block 504 are erased simultaneously.

[0074] Figure 6 This is a cross-sectional side view of a storage string illustrated in an exemplary embodiment of this application. See also: Figure 6 The memory string 508 can extend vertically through the memory cell stack layer 620 above the doped semiconductor layer 610. The doped semiconductor layer 610 is coupled to the source line. In some embodiments, the doped semiconductor layer 610 is an N-type doped semiconductor layer, in which case the doped semiconductor layer 610 can serve as a substrate, i.e., an N-type substrate. In other embodiments, the doped semiconductor layer 610 is a P-type doped semiconductor layer, in which case the doped semiconductor layer 610 is a P-well in the substrate, i.e., a P-type substrate.

[0075] The memory cell stack 620 includes alternating gate conductive layers 630 and gate-to-gate dielectric layers 640. The logarithm of the gate conductive layers 630 and gate-to-gate dielectric layers 640 in the memory cell stack 620 determines the number of memory cells in the memory array. The gate conductive layers 630 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In one possible implementation, each gate conductive layer 630 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 630 includes a doped polysilicon layer. Each gate conductive layer 630 may include a gate surrounding a memory cell and may extend laterally at the top of the memory cell stack 620 as a drain select line (DSL) 513, at the bottom of the memory cell stack 620 as a source select line (SSL) 515, or between the DSL and SSL as a word line (WL) 670.

[0076] like Figure 6 As shown, the memory string 508 also includes a channel structure 650 extending vertically through the memory cell stack layer 620. The channel structure 650 includes channel vias filled with at least one semiconductor material (such as a semiconductor channel) and at least one dielectric material (such as a memory film). In some embodiments, the semiconductor channel includes silicon (such as a memory film). In some embodiments, the memory film is a composite dielectric layer including a tunnel layer, a trap layer, and a barrier layer. The channel structure 650 may have a cylindrical shape (such as a pillar shape). According to some embodiments, the semiconductor channel, the trap layer (also referred to as the memory layer), and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The trap layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide.

[0077] like Figure 6 As shown, a doped semiconductor layer 660 is stacked on top of the memory cell stacking layer 620 in the memory string 508. The doped semiconductor layer 660 is also called the bit line contact. The doped semiconductor layer 660 is coupled to the bit line and is an N-type doped semiconductor layer.

[0078] When the doped semiconductor layer 660 is an N-type doped semiconductor layer, the memory string 508 can be erased using a gate-induced drain leakage (GIDL) erasure method via the bit lines coupled to the doped semiconductor layer 660 and the DSL coupled to the TSG in the memory string 508. For example, an erase voltage is applied to the bit lines coupled to the doped semiconductor layer 660, so that the erase voltage acts on the doped semiconductor layer 660. A voltage smaller than the erase voltage is applied to the DSL coupled to the TSG in the memory string 508, creating a voltage difference between the gate of the TSG and the doped semiconductor layer 660. This voltage difference causes band-to-band tunneling at the location between the gate of the TSG and the doped semiconductor layer 660, generating GIDL. Holes in the GIDL move from this location into the channel of the memory string 508, thereby injecting holes into the channel of the memory string 508 from this location, increasing the channel potential. A voltage less than the erase voltage (referred to as a low voltage, such as 0V) is applied to the word line coupled to each memory cell in the memory string 508 to apply the low voltage to the gate of the memory cell. As the channel potential of the memory cell increases, the voltage difference between the gate and the channel of the memory cell increases. When the voltage difference is greater than the tunneling voltage of the memory cell, the voltage difference causes a tunneling effect between the channel and the gate of the memory cell. As a result, the holes in the channel of the memory cell tunnel to the memory layer of the memory cell to eliminate the electrons in the memory layer, thereby erasing the memory cell.

[0079] In some embodiments, when the doped semiconductor layer 610 is an N-type doped semiconductor layer, the sub-string block can be erased using a GIDL erasure method via the source line coupled to the doped semiconductor layer 610 and the SSL coupled to the BSG in the memory string 508. For example, an erase voltage is applied to the source line, and a voltage lower than the erase voltage (referred to as a low voltage) is applied to the SSL coupled to the BSG, causing a GIDL to be generated at the position between the gate of the BSG and the doped semiconductor layer 610. Holes in the GIDL move towards the channel, thereby injecting holes into the channel of the memory string 508 from this position, increasing the potential of the channel. A low voltage is applied to the word line coupled to each memory cell in the memory string 508. As the channel potential of the memory cell increases, when the voltage difference between the gate of the memory cell and the channel of the memory cell is greater than the tunneling voltage of the memory cell, the holes in the channel tunnel to the memory layer of the memory cell to eliminate electrons in the memory layer, thereby erasing the memory cell.

[0080] Based on this, when both the doped semiconductor layer 610 and the doped semiconductor layer 610 are N-type doped semiconductor layers, the peripheral circuit can perform the GIDL erasure operation on the storage string 508 at either end (i.e., single-ended GIDL erasure), or it can perform the GIDL erasure operation on both ends of the storage string 508 (i.e., double-ended GIDL erasure).

[0081] In other embodiments, when the doped semiconductor layer 610 is a P-type doped semiconductor layer, the memory string 508 is erased based on the erasure method of the P-type doped semiconductor layer. For example, an erase voltage is applied to the source line to apply the erase voltage to the P-type doped semiconductor layer, causing holes to be generated in the P-type doped semiconductor layer. A low voltage is applied to the BSG of the memory string 508 and the word lines coupled to each memory cell, so that the low voltage applies to the gate of the BSG and the gate of each memory cell. Since the low voltage is less than the erase voltage, holes move from the P-type doped semiconductor layer to the channel of the memory string 508 to inject holes from the P-type doped semiconductor layer into the channel, causing the channel potential to rise. As the channel potential of the memory cell increases, when the voltage difference between the gate of the memory cell and the channel of the memory cell is greater than the tunneling voltage of the memory cell, the holes in the channel tunnel to the memory layer of the memory cell to eliminate electrons in the memory layer, thereby erasing the memory cell.

[0082] Therefore, when the doped semiconductor layer 660 is an N-type doped semiconductor layer and the doped semiconductor layer 610 is a P-type doped semiconductor layer, double-ended erasure can be performed on the memory string 508. For example, a single-ended GIDL erasure can be performed at the end of the memory string 508 closest to the N-type doped semiconductor layer, and an erasure based on the P-type doped semiconductor layer can be performed at the other end of the memory string 508. Alternatively, single-ended erasure can be performed on the memory string 508. For example, a single-ended GIDL erasure can be performed at the end of the memory string 508 closest to the P-type doped semiconductor layer, without performing an erasure based on the P-type doped semiconductor layer at the other end of the memory string 508; or, a single-ended GIDL erasure can be performed at the end of the memory string 508 closest to the P-type doped semiconductor layer, and an erasure based on the P-type doped semiconductor layer can be performed at the other end of the memory string 508.

[0083] For any technical details not disclosed in the above memory-related hardware embodiments, please refer to the descriptions of the computer system embodiments and method embodiments of this application for understanding.

[0084] Please refer to Figure 7 This illustrates a schematic diagram of lateral electron migration between memory cells. (For example...) Figure 7As shown, the same storage string contains at least three storage units: the storage unit corresponding to word line n-1 (WL n-1), the storage unit corresponding to word line n (WL n), and the storage unit corresponding to word line n+1 (WL n+1). It is assumed that the storage units corresponding to WL n-1 and WL n are storage units where data has been written (in which case WL n is an edge word line), and the storage unit corresponding to WL n+1 is a storage unit where no data has been written. Figure 7 As shown in part (a), when the programming state of the memory cell corresponding to WL n is high and no data is written to the memory cell corresponding to WL n+1, electrons in the memory cell corresponding to WL n will migrate laterally to the memory cell corresponding to WL n+1; as Figure 7 As shown in part (b), when the programming state of the memory cell corresponding to WL n is in a low state and no data is written to the memory cell corresponding to WL n+1, the electrons in the memory cell corresponding to WL n+1 will migrate laterally to the memory cell corresponding to WL n.

[0085] In one possible implementation, random data can be written into the memory cell where no data has been written to suppress the difference in programming state between the memory cell corresponding to word line n (WL n) and the memory cell corresponding to word line n+1 (WL n+1). However, since the programming state of the memory cell where random data is written is unpredictable, it may not be possible to guarantee that there is a small difference in programming state between the memory cell corresponding to word line n (WL n) and the memory cell corresponding to word line n+1 (WL n+1), and it may even have the opposite effect.

[0086] For example, in the case of writing random data to a storage unit that has not yet been written to, please refer to... Figure 8 This illustrates another type of lateral electron migration between memory cells. (Example) Figure 8 As shown in part (a), when the programming state of the memory cell corresponding to WL n is high and the memory cell corresponding to WL n+1 is low after writing random data, the memory cell corresponding to WL n+1 will have strong coupling with the adjacent memory cell corresponding to WL n. That is, compared to Figure 7 In the case shown in part (a), electrons in the memory cell corresponding to WL n will undergo a more significant lateral migration to the memory cell corresponding to WL n+1; as Figure 8 As shown in part (b), when the programming state of the memory cell corresponding to WL n is low, and the memory cell corresponding to WL n+1 is high after writing random data, compared to Figure 8In the case shown in part (b), the electrons in the memory cell corresponding to WL n+1 will undergo a more significant lateral migration to the memory cell corresponding to WL n.

[0087] To address the aforementioned issues, the solutions presented in subsequent embodiments of this application provide a novel method for operating a storage system that enables storage cells in an edge word line to have the same programming state as storage cells in the next word line, thereby suppressing lateral migration of electrons between storage cells in the edge word line and the same storage cells, and improving the data retention performance of the edge word line.

[0088] Figure 9 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 9 As shown, the storage system 900 includes: one or more memories 910, and,

[0089] A controller 920 is coupled to the memory 910 and configured to control the memory 910.

[0090] The storage system 900 may be all or part of a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0091] Optionally, the storage system 900 may include a host and a storage subsystem, the storage subsystem having one or more memories 910 and a controller 920. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 910. Alternatively, the host may be configured to receive data from the memory 910.

[0092] According to some implementations, the controller 920 is also coupled to a host. The controller 920 can manage data stored in the memory 910 and communicate with the host.

[0093] In some implementations, the controller 920 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0094] In some implementations, the controller 920 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0095] The controller 920 can be configured to control operations of the memory 910, such as read, erase, and program operations. The controller 920 can also be configured to manage various functions relating to data stored or to be stored in the memory 910, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 920 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 910.

[0096] The controller 920 can also perform any other suitable functions, such as formatting the memory 910. The controller 920 can communicate with external devices according to a specific communication protocol.

[0097] The controller 920 and one or more memories 910 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 900 can be implemented and packaged into different types of end electronic products.

[0098] Schematic illustration: The controller 920 and a single memory 910 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0099] Schematic, the controller 920 and multiple memories 910 can be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0100] The aforementioned memory 910 can be implemented as Figures 1 to 3 The memory 100 in any of the illustrated embodiments; the controller 920 described above can be implemented as Figures 1 to 3 Controller 200 in any of the illustrated embodiments.

[0101] In this embodiment, the controller 920 is configured to send a read command to the memory 910.

[0102] For example, the microcontroller unit in the aforementioned controller 920 can generate a read command and send the read command to the memory 910 through the memory interface in the controller 920. The aforementioned memory interface can be the interface between the controller 920 and the memory 910.

[0103] The memory 910 is configured to read data stored in a first memory cell according to a read command; the first memory cell and the second memory cell are located in the same memory string, and the word lines coupled to the first memory cell and the second memory cell are adjacent; the second memory cell is a memory cell that has not yet been written with data.

[0104] For example, the peripheral circuit in the memory 910 can read the data of the first memory cell in the memory cell array of the memory 910 according to the read command, and return the read data to the controller 920.

[0105] The controller 920 is also configured to send write commands to the memory 910.

[0106] For example, after receiving data returned by the memory 910, the microcontroller unit in the controller 920 can generate a write command, which can be a command to write the aforementioned data to the second memory unit. Then, the microcontroller unit sends the write command to the memory 910 through the memory interface in the controller 920.

[0107] The memory 910 is also configured to write data read from the first memory cell to the second memory cell according to a write command.

[0108] For example, the peripheral circuit in the memory 910 can write data into the second memory cell in the memory cell array of the memory 910 according to the write command, and return a write completion response to the controller 920.

[0109] Please refer to Figure 10 This illustrates a schematic diagram of the storage system involved in an embodiment of this application. For example... Figure 10 As shown, in the memory cell array of memory 910, the same memory string contains multiple memory cells. Among them, memory cell 1010 corresponding to WL n has been written with data (DATA2), while memory cell 1020 corresponding to WL n+1 has not yet been written with data. At this time, WL n can be regarded as an edge word line. In order to improve the data retention capability of memory cell 1010 in WL n, controller 920 can perform data filling processing on memory cell 1020 in WL n+1 by reading first and then writing.

[0110] like Figure 10 As shown, during the reading phase, the controller 920 generates a read command and sends it to the memory 910. The peripheral circuits in the memory 910 read the data (DATA2) in the storage unit 1010 according to the read command, and then return the read data to the controller 920 for caching.

[0111] During the writing phase, the controller 920 generates a write command to write the cached data (DATA2) to the storage cell 1020 in WL n+1, and sends the write command to the memory 910. The peripheral circuits in the memory 910 write the data (DATA2) to the storage cell 1020 according to the write command, and return a write completion response to the controller 920 after the write is completed.

[0112] The storage system described in the above embodiments of this application uses a read-then-write method to copy data from storage cell 1010 in the edge word line to adjacent storage cell 1020 in the same storage string that has not yet been written to, so that storage cell 1010 and storage cell 1020 have the same programming state, thereby suppressing the phenomenon of lateral electron migration between storage cell 1010 and storage cell 1020 and improving the data retention performance of storage cell 1010.

[0113] Please refer to the details. Figure 11 This diagram illustrates the programming state of a memory cell according to an embodiment of this application. Word line n (WL n) corresponds to memory cell 1010, and word line n+1 (WL n+1) corresponds to memory cell 1020; after... Figure 10 After the read-then-write operation shown, the same data was written into the corresponding memory cells WLn-1 and WLn; as shown Figure 11 As shown in part (a), assuming the programming state of the memory cell corresponding to WL n is low, after performing the above read-then-write operation, the programming state of the memory cell corresponding to WL n+1 is also low, compared to... Figure 7 Part (a) and Figure 8 In the case of part (a), the lateral migration of electrons between the two memory cells is suppressed to the greatest extent; as... Figure 11 As shown in part (b), assuming the programming state of the memory cell corresponding to WL n is in a high state, after performing the above read-then-write operation, the programming state of the memory cell corresponding to WL n+1 is also in a high state, compared to... Figure 7 Part (b) and Figure 8 In the case of part (b), the lateral migration of electrons between the two storage cells is suppressed to the greatest extent.

[0114] In summary, through the solutions shown in the above embodiments of this application, for a memory string that is not fully written, if the first memory cell in the memory string has been written with data, and the second memory cell adjacent to the first memory cell in the memory string has not been written with data, then the word line where the first memory cell is located is the edge word line. In the embodiments of this application, the data in the first memory cell can be read out and then written to the second memory cell by reading first and then writing. This allows the first memory cell and the second memory cell to store the same data, that is, to make the first memory cell and the second memory cell be in the same programming state. This can suppress the phenomenon of lateral electron migration between the first memory cell and the memory cell, thereby improving the data retention performance of the first memory cell, that is, improving the data retention performance of the edge word line.

[0115] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is configured to send a read command to the memory 910 when the duration of data written in the first storage unit reaches a duration threshold.

[0116] After data is written to the first storage cell in a storage block, the adjacent second storage cell may also be written to within a short period of time. In this case, the first storage cell does not need to enhance its data retention performance. If, after data is written to the first storage cell, the data in the first storage cell is immediately read and written to the second storage cell, and then new data is written to the data block within a short period of time, this will result in unnecessary occupation of the second storage cell, leading to a decrease in the utilization rate of storage resources. In addition, the phenomenon of electronic lateral migration between storage cells does not affect the accuracy of the data in the storage cells at the edge word line in a short period of time, but only after a period of time will it have a significant impact on the accuracy of the data.

[0117] In this embodiment, when the controller 920 determines that the first storage unit is a storage unit in the edge word line and no data has been written to the second storage unit, it can first determine whether the writing duration of the data in the first storage unit has reached a duration threshold, that is, whether the data in the first storage unit has been stored in the first storage unit for a long enough time. The controller 920 can store the time information (such as the writing timestamp) of the data in each storage unit being written to the memory 910. The controller 920 can query the time information of the data in the first storage unit being written to the memory 910 and determine the duration between the time indicated by the time information and the current time as the writing duration of the data in the first storage unit.

[0118] If the write duration of data in the first storage cell reaches the duration threshold, it indicates that the storage block has not been written with new data for a relatively long time, meaning that the storage block is currently in a state of no data writing, and the storage cells at the edge word lines of the storage block need to enhance data retention performance. In this case, the controller 920 can send a read command to the memory 910. Conversely, if the write duration of data in the first storage cell does not reach the duration threshold, it indicates that data has been written to the storage block in a short period of time, and new data may continue to be written in the short period of time. Furthermore, the lateral migration of electrons between storage cells has not yet affected the data in the first storage cell. In this case, the controller 920 may not send a read command to the memory 910. The above scheme can ensure the utilization rate of storage resources while guaranteeing the data retention performance of the first storage cell.

[0119] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is further configured to obtain the physical address of the first storage unit and the physical address of the second storage unit; the controller 920 is configured to send a read command to the memory 910 according to the physical address of the first storage unit, and send a write command to the memory 910 according to the physical address of the second storage unit.

[0120] In this embodiment of the application, the controller 920 can generate the above-mentioned read command and write command according to the physical addresses of the first storage unit and the second storage unit. For example, the controller 920 can generate a read command containing the physical address of the first storage unit and a write command containing the physical address of the second storage unit.

[0121] For example, the controller 920 may store the physical addresses of each memory cell in the memory. The controller 920 can obtain the physical addresses of the first memory cell and the second memory cell by querying the stored physical addresses of each memory cell.

[0122] For example, the controller 920 can obtain the physical address of the first storage unit that has been written with data by querying the Logical to Physical (L2P) table, and then determine the physical address of the second storage unit that is adjacent to the first storage unit in the same memory string and has not yet been written with data by using the physical address of the first storage unit.

[0123] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is further configured to: before sending a read command to the memory 910, if the memory block is not full and the data in the third memory cell of the memory block is valid data, determine the first memory cell in the memory block and the second memory cell corresponding to the first memory cell according to the position of the third memory cell in the memory block; wherein, the third memory cell is the last memory cell among the memory cells in the memory block that have been written with data.

[0124] In the above embodiments of this application, the aforementioned valid data refers to the data written by the controller 920 to each storage unit of the memory according to the host's write request. Correspondingly, according to the above embodiments of this application, data written to an empty storage unit by reading first and then writing can be called invalid padding data. That is to say, the aforementioned valid data is data that the host actively requests the controller to write to the memory, and the host may subsequently request the controller to read the valid data from the memory. Conversely, the aforementioned padding data is not data that the host requests to write, but data that the controller automatically fills in an empty storage unit. Under normal circumstances, the host will not subsequently request the controller to read the padding data from the memory.

[0125] Since the filling data is not the data needed by the host and will not affect the business in the host, the storage unit for writing filling data has low performance requirements for data retention. If the storage unit for writing filling data is used as the first storage unit, it will bring unnecessary filling operations, which will affect the power consumption of the memory on the one hand, and occupy too much storage resources on the other hand.

[0126] Furthermore, the storage cells in a storage block are typically written with data sequentially in an adjacent order. For example, in the memory 910 described above, the storage cells in each storage block are written with data sequentially in ascending order of string number and word line number. When writing data to the storage block, the controller 920 writes data sequentially to each storage cell of WL0 of the storage block in ascending order of the storage string number. After all the storage cells in WL0 have been written with data, the controller 920 then writes data sequentially to each storage cell of WL1 of the storage block in ascending order of the storage string number, and so on.

[0127] In response to this, in the solution described in the above embodiments of this application, for an open block that is not fully written, if the data in the last storage cell arranged in the writing order among the storage cells that have been written to in the block is fill data, it means that the edge word line storing valid data in this storage cell has already performed the above-mentioned read-then-write operation, and no further read-then-write processing is needed; conversely, if the data in the last storage cell arranged in the writing order among the storage cells that have been written to in the block is valid data, it means that the edge word line storing valid data in this storage cell has not undergone the above-mentioned read-then-write operation, and the storage cells in this edge word line require higher data retention performance. In this case, the last storage cell among the storage cells that have been written to in the block can be identified as the third storage cell. Based on the position of the third storage cell in the block, it is possible to determine which storage cells in the block are the first storage cells that need enhanced data retention performance and which storage cells are the second storage cells that need to be filled with fill data. The above scheme avoids unnecessary read-before-write operations on storage units in data blocks, and reduces memory power consumption and storage resource usage while ensuring data retention performance in storage units at the edge word line.

[0128] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is configured to: when the third storage unit is the last storage unit in the nth word line of the storage block, determine the storage units in the nth word line as the first storage unit; determine the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; where 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0129] For example, in the memory 910 described above, the sequence numbers of each memory string in the memory block are sequentially increased from 0, and the sequence numbers of each word line in the memory block are also sequentially increased from 0. When data is written sequentially to the memory cells in the memory block according to the word line sequence number from smallest to largest, if the sequence number of the memory string corresponding to the third memory cell is the maximum value of the string sequence number, it can be determined that the third memory cell is the last memory cell in the nth word line. This indicates that the edge word line in the memory block is the nth word line, and all memory cells in the nth word line need to enhance data retention performance. At this time, the controller 920 can determine all memory cells in the nth word line as the first memory cell. For each first memory cell, the controller 920 determines the memory cell in the memory string where the first memory cell is located, corresponding to the (n+1)th word line, as the second memory cell corresponding to the first memory cell.

[0130] For example, please refer to Figure 12 and Figure 13 ,in, Figure 12 A flowchart illustrating a read / write operation according to an embodiment of this application is shown. Figure 13 The diagram illustrates the effect of a read / write operation according to an embodiment of this application.

[0131] like Figure 12 and Figure 13 As shown, the above read / write operation includes the following steps:

[0132] S1201, Edge word line WL n was detected in an unprogrammed memory block.

[0133] like Figure 13 As shown, the storage unit corresponding to all storage strings (string 0 to string 3) in WL n is the first storage unit.

[0134] S1202, It was detected that the duration of data written to WL n has exceeded the duration threshold t. WAIT In other words, the total writing time of data D5 to D8 mentioned above is greater than the duration threshold.

[0135] S1203, read data from WL n, for example, read... Figure 13 Data D5 to D8.

[0136] S1204, write the data in WL n to WL n+1, that is, in Figure 13 In WL n+1, data D5 to D8 are written sequentially according to the sequence number of the storage string from 0 to 3.

[0137] like Figure 13 As shown, after executing steps S1201 to S1204 above, the data in the two storage units belonging to the same storage string in WL n and WL n+1 are the same, that is, the programming state is the same.

[0138] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is configured to: when the third storage unit is not the last storage unit in the nth word line of the storage block, determine the non-empty storage unit in the nth word line as the first storage unit, and determine the storage unit in the (n+1)th word line of the storage block that is located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; and determine the storage unit in the nth word line that has not yet been written with data as the second storage unit, and determine the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit as the first storage unit corresponding to the second storage unit; wherein, 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0139] For example, in the aforementioned memory 910, the sequence numbers of each memory string in the memory block increase sequentially from 0, and the sequence numbers of each word line in the memory block also increase sequentially from 0. When data is written sequentially to the memory cells in the memory block according to the word line sequence number from smallest to largest, if the sequence number of the memory string corresponding to the third memory cell is not the maximum value of the string sequence number, it can be determined that the third memory cell is not the last memory cell in the nth word line. This indicates that the edge word lines in the memory block are the nth word line and the (n-1)th word line, and that some memory cells in the nth and (n-1)th word lines require enhanced data retention performance. Specifically, in the nth and (n-1)th word lines... In the word line, for a storage cell A, if storage cell A belongs to the same storage string and its adjacent storage cell B has not been written to, then storage cell A needs to enhance its data retention performance. In this case, for any storage cell in the nth word line that has been written to, the controller 920 can identify it as a first storage cell and identify the adjacent storage cell of the first storage cell in the (n+1)th word line as a corresponding second storage cell. Furthermore, for any storage cell in the nth word line that has not been written to, the controller 920 can identify it as a second storage cell and identify the adjacent storage cell of the second storage cell in the (n-1)th word line as a corresponding first storage cell.

[0140] For example, please refer to Figure 14 and Figure 15 ,in, Figure 14 A flowchart illustrating another read / write operation according to an embodiment of this application is shown. Figure 15 The diagram illustrates the effect of another read / write operation involved in an embodiment of this application.

[0141] like Figure 14 and Figure 15 As shown, the above read / write operation includes the following steps:

[0142] S1401, edge word line WL n in the unprogrammed storage block is detected, and the last storage cell with written data corresponds to storage string X.

[0143] like Figure 14 As shown, the storage unit corresponding to string 1 in WL n is the last storage unit in the data block that has been written with data.

[0144] S1402, It was detected that the duration of data written to WL n has exceeded the duration threshold t. WAIT In other words, the duration for which data D6 has been written exceeds the duration threshold.

[0145] S1403, read the data from storage units corresponding to storage strings X+1 to the last storage string in WL n-1; specifically, for example, read... Figure 15 Data D3 and D4 in WL n-1.

[0146] S1404, write the data from storage string X+1 to the last storage string in WLn into the storage units corresponding to storage strings X+1 to the last storage string in WLn; specifically, for example, in Figure 15 In the process, D3 is written into the storage unit corresponding to WL n and storage string 2, and D3 is written into the storage unit corresponding to WL n and storage string 3.

[0147] S1405, read the data from the storage units corresponding to storage strings 0 to X in WL n. Specifically, for example, read... Figure 15 Data D5 and D6 of WL n.

[0148] S1406, write the data in the storage units corresponding to storage strings 0 to X in WL n to the storage units corresponding to storage strings 0 to X in WL n+1; specifically, for example, in Figure 15 In the process, write D5 in the storage unit corresponding to WL n+1 and storage string 0, and write D6 in the storage unit corresponding to WL n+1 and storage string 1.

[0149] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is further configured to: before determining the first storage unit and the second storage unit in the storage block according to the position of the third storage unit in the storage block, query whether the third storage unit in the storage block has a padding mark; the padding mark is used to indicate that the data in the corresponding storage unit is invalid padding data; if the third storage unit does not have a padding mark, determine that the data in the third storage unit is valid data.

[0150] In this embodiment of the application, for data (i.e., padding data) written to the storage unit in the above-described read-then-write manner, the controller 920 may store a padding mark corresponding to the storage unit. For example, it may store the correspondence between the physical address of the storage unit and the padding mark, indicating that the data in the storage unit is padding data.

[0151] Accordingly, during the above-mentioned read-then-write operation, after the controller 920 determines the third storage unit, it can first query whether the third storage unit corresponds to the above-mentioned padding mark. For example, the controller 920 can query locally whether there is a corresponding padding mark through the physical address of the third storage unit. If no padding mark is found for the third storage unit, it means that the data in the third storage unit is valid data and not padding data. Conversely, if a padding mark is found for the third storage unit, it means that the data in the third storage unit is padding data.

[0152] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is further configured to set a fill mark on the second storage cell after the memory 910 successfully writes the data read from the first storage cell into the second storage cell.

[0153] In this embodiment, if the controller 920 does not find the padding flag corresponding to the third storage unit, and determines the first storage unit and the second storage unit based on the third storage unit, and writes the data in the first storage unit to the second storage unit by reading first and then writing, it will also set a padding flag for the second storage unit to avoid performing unnecessary data retention performance enhancement processing on the second storage unit in the future, thereby improving the utilization rate of the storage resources of the memory.

[0154] For example, the controller 920 can create and save a local mapping between the physical address of the second storage unit and the aforementioned padding marker.

[0155] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller 920 is configured to: set a padding flag in the logical address to physical address mapping table corresponding to the physical address of the second storage unit; or, set a padding flag outside the logical address to physical address mapping table corresponding to the identification information of the second storage unit.

[0156] In this embodiment, the controller 920 can use the existing local L2P mapping table to store the correspondence between the second storage unit and the padding mark, without needing to set up an additional mapping table between the physical address of the storage unit and the padding mark, thereby improving the utilization rate of cache resources in the controller 920.

[0157] For example, please refer to Figure 16 This illustrates a system framework diagram related to an embodiment of this application. For example... Figure 16 As shown, the controller 920 is equipped with an L2P mapping table 1601. When fill data is written into a storage unit using the read-before-write method described in this embodiment, the controller 920 sets a fill flag 1602 in the L2P mapping table 1601 corresponding to the physical address of the storage unit. When the controller 920 needs to perform a read-before-write operation on the first storage unit, it can query the physical address corresponding to the first storage unit from the L2P mapping table to determine whether the physical address corresponding to the first storage unit has a fill flag 1602 in the L2P mapping table. If so, the data in the first storage unit will not be read; otherwise, the data in the first storage unit will be read and written to the second storage unit.

[0158] In this embodiment, the controller 920 can also set up an independent mapping table in addition to the existing local mapping table to store the correspondence between the second storage unit and the filling mark. This solution does not require modification of the existing mapping table and can improve compatibility.

[0159] For example, please refer to Figure 17 This illustrates another system framework diagram related to an embodiment of this application. For example... Figure 17 As shown, the controller 920 is provided with an L2P mapping table 1701. In addition to the L2P mapping table 1701, a fill mark mapping table 1702 is also provided. When fill data is written into a storage unit using the read-before-write method described in this embodiment, the controller 920 sets a fill mark 1703 in the fill mark mapping table 1702 corresponding to the identification information (such as physical address, number, etc.) of the storage unit. When the controller 920 needs to perform a read-before-write operation on the first storage unit, it can query the physical address corresponding to the first storage unit from the fill mark mapping table 1702 to determine whether the physical address corresponding to the first storage unit has a fill mark 1703 in the fill mark mapping table 1702. If so, the data in the first storage unit will not be read; otherwise, the data in the first storage unit will be read and written to the second storage unit.

[0160] Based on the solution shown in the above embodiments, in an optional embodiment, the controller 920 is further configured to: cancel the fill mark corresponding to the storage cell in the storage block when the storage block is erased.

[0161] In this embodiment of the application, when a storage block is erased, the controller 920 can [perform the above-mentioned...]. Figure 16 In the L2P mapping table 1601 shown, the correspondence between the physical address of the memory cell within the corresponding memory block and the padding marker 1602 is deleted; or, when a memory block is erased, the controller 920 can delete the above-mentioned correspondence. Figure 17 In the filling mark mapping table 1702 shown, the correspondence between the identification information of the storage cell in the corresponding storage block and the filling mark 1703 is deleted.

[0162] Through the above processing, on the one hand, the invalid padding markers can be prevented from interfering with the subsequent read-then-write operation process; on the other hand, the cache resources in the controller 920 can be prevented from being occupied by invalid padding markers in a timely manner, thereby improving the utilization rate of the cache resources in the controller 920.

[0163] Please refer to Figure 18This is a flowchart illustrating an operational method of a storage system provided in an exemplary embodiment of this application. The storage system may include a controller and a memory, and the operational method of the storage system can be executed by the controller within the storage system. Figure 18 As shown, the method may include the following steps.

[0164] Step 1810: The controller sends a read command to the memory.

[0165] Step 1820: The memory reads the data stored in the first storage cell according to the read command; the first storage cell and the second storage cell are located in the same storage string, and the word lines coupled to the first storage cell and the second storage cell are adjacent; the second storage cell is a storage cell that has not yet been written with data.

[0166] Step 1830: The controller sends a write command to the memory.

[0167] Step 1840: The memory writes the data read from the first storage cell to the second storage cell according to the write command.

[0168] Based on the scheme shown in the above embodiments, in an optional embodiment, before the controller sends a read command to the memory, it further includes: the controller obtaining the physical address of the first memory unit and the physical address of the second memory unit.

[0169] The controller sends write commands to the memory, including sending read commands to the memory based on the physical address of the first memory cell.

[0170] The controller sends a write command to the memory, including sending the write command to the memory based on the physical address of the second memory cell.

[0171] Based on the scheme shown in the above embodiments, in an optional embodiment, before the controller sends a read command to the memory, the method further includes: when the storage block is not full and the data in the third storage unit of the storage block is valid data, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit according to the position of the third storage unit in the storage block; wherein, the third storage unit is the storage unit of the storage block with written data, the last storage unit.

[0172] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit according to the position of the third storage unit in the storage block, including: when the third storage unit is the last storage unit in the nth word line of the storage block, the controller determines the storage units in the nth word line as the first storage unit; and determines the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; wherein, 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0173] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit according to the position of the third storage unit in the storage block, including: when the third storage unit is not the last storage unit in the nth word line of the storage block, the controller determines the non-empty storage unit in the nth word line as the first storage unit, and determines the storage unit in the (n+1)th word line of the storage block that is located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; and the controller determines the storage unit in the nth word line that has not yet been written with data as the second storage unit, and determines the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit as the first storage unit corresponding to the second storage unit; wherein, 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0174] Based on the solution shown in the above embodiments, in an optional embodiment, the method further includes: before the controller determines the first storage unit and the second storage unit in the storage block according to the position of the third storage unit in the storage block, it queries whether the third storage unit in the storage block is set with a padding mark; the padding mark is used to indicate that the data in the corresponding storage unit is invalid padding data; if the third storage unit is not set with a padding mark, it determines that the data in the third storage unit is valid data.

[0175] Based on the solution shown in the above embodiments, in an optional embodiment, the method further includes: after the memory successfully writes the data read from the first storage unit into the second storage unit, the controller sets a fill mark for the second storage unit.

[0176] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller sets a filling mark for the second storage unit, including: the controller sets a filling mark in the logical address to physical address mapping table corresponding to the physical address of the second storage unit; or, the controller sets a filling mark outside the logical address to physical address mapping table corresponding to the identification information of the second storage unit.

[0177] Based on the solution shown in the above embodiments, in an optional embodiment, the above method further includes: when the storage block is erased, the controller cancels the filling mark corresponding to the storage cell in the storage block.

[0178] Based on the scheme shown in the above embodiments, in an optional embodiment, the controller sends a read command to the memory, including: when the time elapsed since the data in the first storage unit has been written reaches a time elapsed threshold, the controller sends a read command to the memory.

[0179] Figure 19 This is a schematic diagram of the controller structure provided in an exemplary embodiment of this application. Figure 19 As shown, the controller 1900 includes a front-end interface 1910, a memory interface 1920, a microcontroller 1930, a bus 1940, and a flash memory control unit 1950.

[0180] The front-end interface 1910, also known as the Host I / F, is connected to the host and used for communication with the host.

[0181] The memory interface 1920 is connected to the memory (which may be non-volatile memory) and is used to convert data exchange on the bus into data exchange that conforms to the storage timing of the storage medium.

[0182] The microcontroller unit 1930 and the flash memory control unit 1950 are used to control the functions of the entire controller, ensuring that the memory interface 1920 correctly completes data exchange between the memory and the bus, and managing interrupt signals, etc. Specifically, the microcontroller unit 1930 and the flash memory control unit 1950 can be used to control functions such as data writing, data reading, garbage collection, wear leveling, and error correction.

[0183] Optionally, the controller 1900 may also include a storage unit 1960. Optionally, the storage unit 1960 may include read-only memory (ROM) and random access memory (RAM).

[0184] The read-only memory can be connected to the microcontroller unit 1930 and the flash memory control unit 1950, and can be used to store the firmware program of the controller 1900, fixed configuration information, non-fixed setting data, etc.

[0185] The random access memory can be connected to the front-end interface 1910, memory interface 1920, microcontroller 1930 and flash memory control unit 1950 via bus 1940. It can be used for data exchanged between the cache controller 1900 and the host or memory, as well as some configuration information of the cache controller 1900.

[0186] The controller 1900 described above can perform the following actions: Figure 18 In the method shown, all or part of the steps are performed by the controller.

[0187] The controller 1900 may include memory (such as the storage unit 1960) and control circuitry (such as one or more of the front-end interface 1910, memory interface 1920, microcontroller 1930, bus 1940, and flash memory control unit 1950). The control circuitry is configured to: send a read command to the memory; the read command instructs the memory to read data stored in a first storage unit in the memory; the first storage unit and the second storage unit are located in the same memory string, and the word lines coupled to the first storage unit and the second storage unit are adjacent; the second storage unit is a storage unit that has not yet been written with data; and send a write command to the memory; the write command instructs the memory to write data read from the first storage unit to the second storage unit.

[0188] In an optional embodiment, the control circuit is further configured to acquire the physical address of the first memory cell and the physical address of the second memory cell; the control circuit is configured to send a read command to the memory based on the physical address of the first memory cell and a write command to the memory based on the physical address of the second memory cell.

[0189] In an optional embodiment, the control circuit is further configured to: before sending a read command to the memory, if the memory block is not full and the data in the third memory cell of the memory block is valid data, determine the first memory cell in the memory block and the second memory cell corresponding to the first memory cell based on the position of the third memory cell in the memory block; wherein the third memory cell is the last memory cell among the memory cells in the memory block that have been written with data.

[0190] In an optional embodiment, the control circuit is configured to: when the third storage unit is the last storage unit in the nth word line of the storage block, determine the storage units in the nth word line as first storage units; and determine the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit; where 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0191] In an optional embodiment, the control circuit is configured to: if the third storage cell is not the last storage cell in the nth word line of the storage block, determine the non-empty storage cell in the nth word line as the first storage cell, and determine the storage cell in the (n+1)th word line of the storage block that is located in the same storage string as the first storage cell as the second storage cell; and determine the storage cell in the nth word line that has not yet been written with data as the second storage cell, and determine the storage cell in the (n-1)th word line of the storage block that is located in the same storage string as the second storage cell as the first storage cell; wherein 1≤n<N, n is an integer, and M is the number of word lines in the storage block.

[0192] In an optional embodiment, the controller is further configured to: query whether the third storage cell in the storage block has a padding marker set before determining the first storage cell and the second storage cell in the storage block based on the location of the third storage cell in the storage block; the padding marker is used to indicate that the data in the corresponding storage cell is invalid padding data; if the third storage cell does not have a padding marker set, determine that the data in the third storage cell is valid data.

[0193] In an optional embodiment, the control circuit is further configured to set a fill mark on the second storage cell after the memory has successfully written data read from the first storage cell into the second storage cell.

[0194] In an optional embodiment, the control circuit is configured to: set a padding flag in the logical address to physical address mapping table corresponding to the physical address of the second memory cell; or, set a padding flag outside the logical address to physical address mapping table corresponding to the identification information of the second memory cell.

[0195] In an optional embodiment, the control circuit is further configured to: cancel the padding markers corresponding to the memory cells in the memory block when the memory block is erased.

[0196] In an optional embodiment, the control circuit is configured to send a read command to the memory when the duration for which data has been written to the first storage unit reaches a duration threshold.

[0197] This application provides a computer-readable storage medium storing instructions that, when executed on the control logic circuit of a controller (such as the aforementioned microcontroller and flash memory control unit), implement the following: Figure 18 The illustrated embodiment provides an operation method for the storage system. Optionally, the controller may be as follows: Figure 19 The controller shown, the storage system can be as follows: Figure 9 The storage system shown.

[0198] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0199] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0200] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage system, characterized in that, The storage system includes: a memory and a controller; The controller is configured to send a read command to the memory; The memory is configured to read data stored in a first storage cell according to the read command; the first storage cell and the second storage cell are located in the same memory string, and the word lines coupled to the first storage cell and the second storage cell are adjacent; the second storage cell is a storage cell that has not yet been written with data. The controller is also configured to send write commands to the memory; The memory is also configured to write data read from the first storage unit to the second storage unit according to the write command.

2. The storage system according to claim 1, characterized in that, The controller is also configured to obtain the physical address of the first storage unit and the physical address of the second storage unit; The controller is configured to send the read command to the memory based on the physical address of the first storage unit, and to send the write command to the memory based on the physical address of the second storage unit.

3. The storage system according to claim 1 or 2, characterized in that, The controller is also configured to: Before sending the read command to the memory, if the memory block is not full and the data in the third memory cell of the memory block is valid data, the first memory cell in the memory block and the second memory cell corresponding to the first memory cell are determined according to the position of the third memory cell in the memory block. The third storage unit is the last storage unit among the storage units containing the data already written to the storage block.

4. The storage system according to claim 3, characterized in that, The controller is configured to: When the third storage unit is the last storage unit in the nth word line of the storage block, the storage units in the nth word line are respectively determined as the first storage unit; the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit are determined as the second storage unit corresponding to the first storage unit. Where 1 ≤ n < N, n is an integer, and M is the number of word lines in the storage block.

5. The storage system according to claim 3, characterized in that, The controller is configured to: If the third storage unit is not the last storage unit in the nth word line of the storage block, then the non-empty storage unit in the nth word line is determined as the first storage unit, and the storage unit in the (n+1)th word line of the storage block that is located in the same storage string as the first storage unit is determined as the second storage unit corresponding to the first storage unit; and the storage unit in the nth word line that has not yet been written with data is determined as the second storage unit, and the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit is determined as the first storage unit corresponding to the second storage unit; Where 1 ≤ n < N, n is an integer, and M is the number of word lines in the storage block.

6. The storage system according to claim 3, characterized in that, The controller is also configured to: Before determining the first storage unit and the second storage unit in the storage block based on the position of the third storage unit in the storage block, it is queried whether the third storage unit in the storage block is set with a fill mark; the fill mark is used to indicate that the data in the corresponding storage unit is invalid fill data; If no fill mark is set in the third storage unit, the data in the third storage unit is determined to be valid data.

7. The storage system according to claim 6, characterized in that, The controller is also configured to: After the memory successfully writes the data read from the first storage cell into the second storage cell, the fill mark is set for the second storage cell.

8. The storage system according to claim 7, characterized in that, The controller is configured to: In the logical address to physical address mapping table, the padding flag is set corresponding to the physical address of the second storage unit; or, outside the logical address to physical address mapping table, the padding flag is set corresponding to the identification information of the second storage unit.

9. The storage system according to claim 7, characterized in that, The controller is also configured to: When the storage block is erased, the fill mark corresponding to the storage cell in the storage block is canceled.

10. The storage system according to claim 1 or 2, characterized in that, The controller is configured to: When the duration of data written to the first storage unit reaches a duration threshold, the read command is sent to the storage unit.

11. A method for operating a storage system, characterized in that, include: The controller sends a read command to the memory; The memory reads the data stored in the first storage unit in the memory according to the read command; The first storage cell and the second storage cell are located in the same storage string, and the word lines coupled to the first storage cell and the second storage cell are adjacent. The second storage unit is a storage unit that has not yet been written with data; The controller sends a write command to the memory; The memory writes the data read from the first storage unit to the second storage unit according to the write command.

12. The method according to claim 11, characterized in that, Before the controller sends a read command to the memory, it also includes: The controller obtains the physical address of the first storage unit and the physical address of the second storage unit; The controller sends a write command to the memory, including: The controller sends the read command to the memory based on the physical address of the first storage unit; The controller sends a write command to the memory, including: The controller sends the write command to the memory based on the physical address of the second storage unit.

13. The method according to claim 11 or 12, characterized in that, Before the controller sends the read command to the memory, the method further includes: If the storage block is not full and the data in the third storage unit of the storage block is valid data, the controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit based on the position of the third storage unit in the storage block. The third storage unit is the storage unit for the data already written to the storage block, and is the last storage unit.

14. The method according to claim 13, characterized in that, The controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit based on the location of the third storage unit in the storage block, including: When the third storage unit is the last storage unit in the nth word line of the storage block, the controller determines the storage units in the nth word line as the first storage unit; and determines the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit as the second storage unit corresponding to the first storage unit. Where 1 ≤ n < N, n is an integer, and M is the number of word lines in the storage block.

15. The method according to claim 13, characterized in that, The controller determines the first storage unit in the storage block and the second storage unit corresponding to the first storage unit based on the location of the third storage unit in the storage block, including: If the third storage cell is not the last storage cell in the nth word line of the storage block. The controller identifies the non-empty storage cell in the nth word line as the first storage cell, and identifies the storage cell in the (n+1)th word line of the storage block that is located in the same storage string as the first storage cell as the second storage cell corresponding to the first storage cell; and... The controller determines the storage unit in the nth word line that has not yet been written with data as the second storage unit, and determines the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit as the first storage unit corresponding to the second storage unit. Where 1 ≤ n < N, n is an integer, and M is the number of word lines in the storage block.

16. The method according to claim 13, characterized in that, The method further includes: Before determining the first and second storage units in the storage block based on the location of the third storage unit in the storage block, the controller queries whether the third storage unit in the storage block has a fill mark set; the fill mark is used to indicate that the data in the corresponding storage unit is invalid fill data; if the third storage unit does not have a fill mark set, the data in the third storage unit is determined to be valid data.

17. The method according to claim 16, characterized in that, The method further includes: After the memory successfully writes the data read from the first storage unit into the second storage unit, the controller sets the fill mark for the second storage unit.

18. The method according to claim 17, characterized in that, The controller sets the fill mark for the second storage unit, including: The controller sets the filling flag in the logical address to physical address mapping table corresponding to the physical address of the second storage unit; or, The controller sets the filling flag corresponding to the identification information of the second storage unit, outside of the logical address to physical address mapping table.

19. The method according to claim 17, characterized in that, The method further includes: When the storage block is erased, the controller cancels the fill mark corresponding to the storage cell in the storage block.

20. The method according to claim 11 or 12, characterized in that, The controller sends a read command to the memory, including: When the time elapsed since the data in the first storage unit has been written reaches a time threshold, the controller sends the read command to the storage unit.

21. A controller, characterized in that, The controller includes memory and control circuitry, the control circuitry being configured to: Send a read command to the memory; the read command instructs the memory to read the data stored in the first memory cell. The first storage cell and the second storage cell are located in the same storage string, and the word lines coupled to the first storage cell and the second storage cell are adjacent. The second storage unit is a storage unit that has not yet been written with data; Send a write command to the memory; The write command is used to instruct the memory to write the data read from the first storage unit to the second storage unit.

22. The controller according to claim 21, characterized in that, The control circuit is further configured to acquire the physical address of the first storage unit and the physical address of the second storage unit; The control circuit is configured to send the read command to the memory based on the physical address of the first memory cell, and to send the write command to the memory based on the physical address of the second memory cell.

23. The controller according to claim 21 or 22, characterized in that, The control circuit is further configured to: Before sending the read command to the memory, if the memory block is not full and the data in the third memory cell of the memory block is valid data, the first memory cell in the memory block and the second memory cell corresponding to the first memory cell are determined according to the position of the third memory cell in the memory block. The third storage unit is the last storage unit among the storage units containing the data already written to the storage block.

24. The controller according to claim 23, characterized in that, The control circuit is configured as follows: When the third storage unit is the last storage unit in the nth word line of the storage block, the storage units in the nth word line are respectively determined as the first storage unit; the storage units in the (n+1)th word line of the storage block that are located in the same storage string as the first storage unit are determined as the second storage unit corresponding to the first storage unit. Where 1 ≤ n < N, n is an integer, and M is the number of word lines in the storage block.

25. The controller according to claim 23, characterized in that, The control circuit is configured as follows: If the third storage unit is not the last storage unit in the nth word line of the storage block, then the non-empty storage unit in the nth word line is determined as the first storage unit, and the storage unit in the (n+1)th word line of the storage block that is located in the same storage string as the first storage unit is determined as the second storage unit corresponding to the first storage unit; and the storage unit in the nth word line that has not yet been written with data is determined as the second storage unit, and the storage unit in the (n-1)th word line of the storage block that is located in the same storage string as the second storage unit is determined as the first storage unit corresponding to the second storage unit; Where 1 ≤ n < N, n is an integer, and M is the number of word lines in the storage block.

26. The controller according to claim 23, characterized in that, The controller is also configured to: Before determining the first storage unit and the second storage unit in the storage block based on the position of the third storage unit in the storage block, it is queried whether the third storage unit in the storage block is set with a fill mark; the fill mark is used to indicate that the data in the corresponding storage unit is invalid fill data; If no fill mark is set in the third storage unit, the data in the third storage unit is determined to be valid data.

27. The controller according to claim 26, characterized in that, The control circuit is further configured to: After the memory successfully writes the data read from the first storage cell into the second storage cell, the fill mark is set for the second storage cell.

28. The controller according to claim 27, characterized in that, The control circuit is configured as follows: In the logical address to physical address mapping table, the padding flag is set corresponding to the physical address of the second storage unit; or, outside the logical address to physical address mapping table, the padding flag is set corresponding to the identification information of the second storage unit.

29. The controller according to claim 27, characterized in that, The control circuit is further configured to: When the storage block is erased, the fill mark corresponding to the storage cell in the storage block is canceled.

30. The controller according to claim 21 or 22, characterized in that, The control circuit is configured as follows: When the duration of data written to the first storage unit reaches a duration threshold, the read command is sent to the storage unit.

31. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a controller in the storage system, implement the operation method of the storage system as described in any one of claims 11 to 20.

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