Semiconductor packaging structure and manufacturing method thereof

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The method comprises the following steps: providing a first rewiring layer; one side of the first rewiring layer is connected with at least one bridging chip; providing a target chip packaging structure; electrically connecting the end surface of one side, far away from the second rewiring layer, of the conductive column with the first rewiring layer, so as to enable the target chip packaging structure to be electrically connected with the first rewiring layer; and forming a second packaging layer. A target chip packaging structure with a copper column, a second rewiring layer and a target chip is preset; then, the target chips are electrically connected with the bridge chip, so that the target chips are electrically connected with one another; and finally, the semiconductor packaging structure is integrally packaged, so that the alignment error generated between the bridging chip and the second rewiring layer due to the fact that the bridging chip is packaged firstly and then integrally packaged is avoided, the reliability of electric connection among a plurality of target chips is improved, and the product yield of the semiconductor packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a semiconductor packaging structure and its fabrication method. Background Art

[0002] In related technologies, when forming a fan-out package structure, a step-by-step molding method is usually adopted: first, bridging chips are placed on the surface of the first wiring layer and a copper pillar structure is formed, followed by the first overall molding package; then, a second wiring layer is made on the packaged surface, and multiple target chips are connected through this wiring layer, and finally, a second overall package is implemented.

[0003] During the initial packaging process, the epoxy molding compound undergoes thermal shrinkage during curing, causing the bridging chip to shift position. Since the pattern of the second wiring layer is fabricated based on the initial design's photomask, this thermal displacement can cause misalignment between the contact pads of the bridging chip and the corresponding connection points of the second wiring layer. This ultimately leads to interconnect failure, resulting in the loss of electrical pathways between multiple target chips that require interconnection via the bridging chip, impacting the signal transmission function and overall reliability of the package structure. Summary of the Invention

[0004] To overcome the aforementioned shortcomings in the prior art, this application provides a semiconductor packaging structure and a method for fabricating the same, the method comprising: Provide the first wiring layer; At least one bridging chip is connected to one side of the first rewiring layer; A target chip packaging structure is provided; wherein the target chip packaging structure includes a second wiring layer; at least two target chips and a first packaging layer are spaced apart on one side of the second wiring layer, the first packaging layer being located on the side of the second wiring layer closer to the target chips and in the gap between the spaced-apart target chips; at least two conductive pillars are spaced apart on the side of the second wiring layer away from the target chips; wherein the conductive pillars are electrically connected to the target chips via the second wiring layer; The end face of the conductive post away from the second wiring layer is electrically connected to the first wiring layer, so that the target chip package structure is electrically connected to the first wiring layer; wherein, the conductive post and the bridging chip are arranged alternately, and the bridging chip connects at least two target chips that are spaced apart through the second wiring layer; A second encapsulation layer is formed; wherein the second encapsulation layer is located on the side of the first redistribution layer near the target chip encapsulation structure and in the gap between at least two of the conductive pillars and at least one of the bridging chips.

[0005] In one possible implementation, before performing the step of providing the target chip package structure, the method further includes: Provide the first carrier board; At least two of the target chips are placed at intervals on one side of the first carrier board; An integrally formed first encapsulation layer is formed on the side of the first carrier board near the target chip and in the gap between at least two target chips spaced apart; Flip the first encapsulation layer and the target chip so that the side of the target chip away from the first carrier is exposed to the first encapsulation layer; A second wiring layer is formed on the side of the first encapsulation layer away from the first carrier board; wherein the second wiring layer is electrically connected to the target chip; At least two conductive pillars are formed at intervals on the side of the second redistribution layer away from the target chip; wherein the conductive pillars are electrically connected to the target chip through the second redistribution layer; Remove the first carrier board to form the target chip package structure.

[0006] In one possible implementation, before performing the step of providing the first redistribution layer, the method further includes: Provide a second carrier board; A first redistribution layer is formed on the second carrier board; After performing the step of forming the second encapsulation layer, the method further includes: Remove the second carrier board.

[0007] In one possible implementation, after performing the step of removing the second carrier plate, the method further includes: Multiple solder balls are formed at intervals on the side of the first redistribution layer away from the bridging chip.

[0008] In one possible implementation, the step of forming the second encapsulation layer includes: A first sub-encapsulation layer is formed in the gap between at least two of the conductive pillars and at least one of the bridging chips; A second sub-package layer is formed on the side of the first redistribution layer that is close to the target chip package structure.

[0009] This application also provides a semiconductor packaging structure, manufactured using the semiconductor packaging structure fabrication method described in any one of the foregoing claims, comprising: The first wiring layer includes a first surface and a second surface opposite to each other, and the first wiring layer also includes a plurality of first metal traces extending from the first surface to the second surface; A plurality of conductive pillars and at least one bridging chip are spaced apart on one side of the first redistribution layer; wherein the plurality of conductive pillars and at least one bridging chip are arranged alternately. A second redistribution layer is located on the side of the plurality of conductive pillars and at least one of the bridging chips away from the first redistribution layer. The second redistribution layer includes opposing third and fourth surfaces. The second redistribution layer also includes a plurality of second metal traces extending from the third surface to the fourth surface. The second metal traces are electrically connected to the first metal traces via the conductive pillars. Multiple target chips located on one side of the second redistribution layer; wherein at least two of the target chips are electrically connected to the same bridging chip via a second metal trace; The second packaging layer includes a first sub-packaging layer and a second sub-packaging layer. The first sub-packaging layer is located on the side of the first redistribution layer close to the target chip, and the second sub-packaging layer is located in the gap between the plurality of conductive pillars, at least one of the bridging chips and the plurality of target chips.

[0010] In one possible implementation, the semiconductor package structure further includes solder balls located on the side of the first redistribution layer away from the target chip; The solder balls are electrically connected to the target chip via the first metal trace, the conductive pillar, and the second metal trace.

[0011] In one possible implementation, the first sub-encapsulation layer and the second sub-encapsulation layer are integrally formed.

[0012] In one possible implementation, the material of the first sub-encapsulation layer includes epoxy resin; the material of the second sub-encapsulation layer includes epoxy encapsulant.

[0013] This application also provides an electronic device, which includes the semiconductor packaging structure described in any of the preceding claims.

[0014] Compared with the prior art, this application has the following beneficial effects: This application provides a semiconductor packaging structure and its manufacturing method. By pre-setting a target chip packaging structure with copper pillars, a second wiring layer and target chips, the structure is then electrically connected to a bridging chip, thereby forming an electrical connection between multiple target chips. Finally, the entire structure is packaged, avoiding the alignment error between the bridging chip and the second wiring layer caused by packaging the bridging chip first and then packaging the entire structure. This improves the reliability of the electrical connection between multiple target chips and increases the product yield of the semiconductor packaging structure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is one of the flowcharts illustrating the method for fabricating the semiconductor packaging structure provided in this embodiment; Figure 2 This is one of the schematic diagrams illustrating the fabrication process of the semiconductor packaging structure provided in this embodiment. Figure 3 This is a second schematic flowchart illustrating the method for fabricating the semiconductor packaging structure provided in this embodiment; Figure 4 This is the second schematic diagram of the fabrication process of the semiconductor packaging structure provided in this embodiment. Figure 5 This is one of the schematic diagrams of the semiconductor packaging structure provided in this embodiment; Figure 6 This is the second schematic diagram of the semiconductor packaging structure provided in this embodiment.

[0017] Icons: Semiconductor package structure - 10; First redistribution layer - 100; Bridge chip - 200; Second package layer - 300; First carrier board - 900; Target chip - 410; First package layer - 420; Second redistribution layer - 430; Conductive pillar - 440; Target chip package structure - 400; Solder ball - 500; First sub-package layer - 310; Second sub-package layer - 320; First metal trace - 101; Second metal trace - 431. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0024] In related technologies, the formation of fan-out package structures typically employs a step-by-step molding process: first, bridging chips are placed on the surface of the first wiring layer to form copper pillar structures, followed by a first overall molding package; then, a second wiring layer is fabricated on the packaged surface, connecting multiple target chips through this layer, and finally, a second overall package is performed. During the first packaging process, the epoxy molding compound undergoes thermal shrinkage during curing, causing the bridging chips to shift. Since the pattern of the second wiring layer is based on the initially designed photomask, this thermal displacement can cause misalignment between the contact pads of the bridging chips and the corresponding connection points of the second wiring layer, ultimately leading to interconnect failure. This results in the loss of electrical pathways between the multiple target chips that require interconnection via the bridging chips, affecting the signal transmission function and overall reliability of the package structure.

[0025] In view of this, this application provides a method for manufacturing a semiconductor package structure 10.

[0026] Optionally, the semiconductor package structure 10 in this embodiment uses a fan-out embedded bridge (FOEB) method, that is, a small bridge chip 200 is embedded in the fan-out package structure to achieve ultra-high bandwidth interconnection between multiple target chips 410.

[0027] Please see Figure 1 and Figure 2 The method includes the following steps.

[0028] Step S11: Provide the first rewiring layer 100.

[0029] Specifically, the first redistribution layer 100 includes a first surface and a second surface facing each other, and also includes multiple first metal traces 101 extending from the first surface to the second surface. The material of the first metal traces 101 includes a conductive material, which enables electrical connection between the structures on both sides of the first redistribution layer 100. In addition, the first redistribution layer 100 can achieve high-density interconnection in a limited space, simplifying the packaging structure; at the same time, the application of the redistribution layer enables the semiconductor packaging structure 10 in this embodiment to improve the integrity of signal transmission and reduce the overall power consumption of the electronic device when applied in an electronic device.

[0030] In step S12, at least one bridging chip 200 is connected to one side of the first rewiring layer 100. The bridging chip 200 can interconnect multiple functional chips within a limited package structure, reducing the substrate wiring requirements of the semiconductor package structure 10.

[0031] Step S13, providing a target chip 410 packaging structure; wherein the target chip 410 packaging structure includes a second redistribution layer 430; at least two target chips 410 and a first packaging layer 420 are spaced apart on one side of the second redistribution layer 430, the first packaging layer 420 is located between the side of the second redistribution layer 430 near the target chips 410 and the gap between the spaced-apart target chips 410; at least two conductive pillars 440 are spaced apart on the side of the second redistribution layer 430 away from the target chips 410; wherein the conductive pillars 440 are electrically connected to the target chips 410 via the second redistribution layer 430.

[0032] It should be noted that, in this embodiment, multiple target chip 410 package structures can be provided. Correspondingly, each target chip 410 package structure needs to be interconnected with its internal target chips 410 through a bridge chip 200.

[0033] Specifically, in one possible implementation, please refer to Figure 3 and Figure 4 Before performing step S13, it is also necessary to form the target chip 410 package structure. The method also includes the following steps.

[0034] Step S21, provide the first carrier board 900.

[0035] In this embodiment, the first carrier 900 serves as a temporary support substrate for subsequent processes, ensuring stability during the formation of the target chip 410 package structure. The material of the first carrier 900 includes materials with good thermal stability, high surface flatness, and easy removal; for example, glass, silicon wafers, or metal plates with temporary bonding adhesive coated on their surfaces can be selected.

[0036] In step S22, at least two target chips 410 are placed at intervals on one side of the first carrier board 900. The at least two target chips 410 are used to achieve electrical connection through the bridging chip 200.

[0037] Step S23: An integrally formed first encapsulation layer 420 is formed on the side of the first carrier board 900 near the target chip 410 and in the gap between at least two target chips 410 spaced apart.

[0038] In this embodiment, the first packaging layer 420 is used to provide mechanical protection and environmental isolation for the target chip 410.

[0039] Specifically, the first encapsulation layer 420 can be formed using an epoxy molding compound through a molding process.

[0040] Step S24: Flip the first encapsulation layer 420 and the target chip 410 so that the side of the target chip 410 away from the first carrier board 900 is exposed to the first encapsulation layer 420.

[0041] In this embodiment, since step S23 forms a first encapsulation layer 420 on the side of the first carrier 900 near the target chip 410, the first encapsulation layer 420 has a flat surface on the contact surface between the first carrier 900 and the first encapsulation layer 420. At the same time, since at least two target chips 410 are placed on the first carrier 900, after flipping, the side of the target chip 410 away from the first carrier 900 is exposed to the first encapsulation layer 420, laying the foundation for subsequently constructing other flat interconnect structures on the surface of the first encapsulation layer 420 and the target chip 410.

[0042] Step S25: A second redistribution layer 430 is formed on the side of the first encapsulation layer 420 away from the first carrier board 900; wherein the second redistribution layer 430 is electrically connected to the target chip 410.

[0043] Specifically, the second redistribution layer 430 includes opposing third and fourth surfaces, and also includes multiple second metal traces 431 extending from the third surface to the fourth surface. The second metal traces 431 are made of conductive materials, enabling electrical connections between the structures on both sides of the second redistribution layer 430. The second redistribution layer 430 can be formed by depositing a dielectric layer and a metal layer on the surface of the first package layer 420, and then using photolithography to form fine lines. In this way, electrical signals from the target chip 410 can be redistributed to the desired locations.

[0044] Step S26: At least two conductive pillars 440 are formed at intervals on the side of the second redistribution layer 430 away from the target chip 410; wherein the conductive pillars 440 are electrically connected to the target chip 410 through the second redistribution layer 430.

[0045] In this embodiment, the conductive post 440 can be used to achieve electrical connection with other structures. For example, the conductive post 440 can be electrically connected to the first redistribution layer 100, thereby enabling signal transmission between the target chip 410 and other structures.

[0046] Specifically, the conductive pillar 440 can be formed by electroplating, and the conductive pillar 440 includes a copper pillar.

[0047] Step S27: Remove the first carrier board 900 to form the target chip 410 package structure.

[0048] Specifically, if the target chip 410 package structure is bonded to the glass first substrate 900 by photosensitive bonding adhesive, then when the first substrate 900 is removed in step S27, the photosensitive bonding adhesive can be reduced or lose its adhesiveness by laser irradiation of a specific wavelength.

[0049] Thus, the required target chip 410 package structure is formed. In this embodiment, forming the target chip 410 package structure first and then electrically connecting it to the bridge chip 200 can improve the reliability of the alignment between the target chip 410 and the bridge chip 200.

[0050] Step S14: Connect the end face of the conductive post 440 away from the second redistribution layer 430 to the first redistribution layer 100, so that the target chip 410 package structure is electrically connected to the first redistribution layer 100; wherein, the conductive post 440 and the bridging chip 200 are arranged alternately, and the bridging chip 200 connects at least two target chips 410 that are spaced apart through the second redistribution layer 430.

[0051] In this way, an electrical connection is achieved between the bridging chip 200, the target chip 410, the first wiring layer 100, and the second wiring layer 430.

[0052] Step S15: A second encapsulation layer 300 is formed; wherein the second encapsulation layer 300 is located on the side of the first redistribution layer 100 near the target chip 410 encapsulation structure and in the gap between at least two conductive pillars 440 and at least one bridging chip 200. The first encapsulation layer 420 is used to provide mechanical protection and environmental isolation for the target chip 410, bridging chip 200, and conductive pillars 440.

[0053] In this embodiment, a target chip 410 package structure with conductive pillars 440, a second wiring layer 430, and a target chip 410 is pre-set; then it is electrically connected to the bridge chip 200, thereby forming an electrical connection between multiple target chips 410; finally, it is packaged as a whole, avoiding the alignment error between the bridge chip 200 and the second wiring layer 430 caused by packaging the bridge chip 200 first and then packaging the whole, improving the reliability of the electrical connection between multiple target chips 410, and improving the product yield of the semiconductor package structure 10.

[0054] In one possible implementation, the method further includes the following steps before performing step S11.

[0055] Step S16: Provide a second carrier board.

[0056] In this embodiment, the second carrier plate serves as a temporary support substrate for the fabrication process of the semiconductor package structure 10, ensuring stability during the formation of the semiconductor package structure 10. The material of the second carrier plate includes materials with good thermal stability, high surface flatness, and easy removal; for example, glass, silicon wafers, or metal plates with a temporary bonding adhesive coating can be selected. Correspondingly, the bonding adhesive can be selected based on the properties of the substrate and the removal method. For example, for a second carrier plate made of glass, the bonding adhesive can be a photosensitive material.

[0057] Step S17: A first redistribution layer 100 is formed on the second carrier board.

[0058] Specifically, a second redistribution layer 430 can be formed by depositing a dielectric layer and a metal layer on the surface of the second substrate and using photolithography to form fine lines.

[0059] After performing step S15, the method further includes the following steps.

[0060] Step S18: Remove the second carrier board.

[0061] Specifically, if the semiconductor packaging structure 10 is bonded to the second glass substrate by a photosensitive bonding adhesive, then when the first substrate 900 is removed in step S17, the photosensitive bonding adhesive can be reduced or lose its adhesiveness by laser irradiation of a specific wavelength.

[0062] In one possible implementation, after performing step S18, the method further includes the following steps.

[0063] Step S19: A plurality of solder balls 500 are formed at intervals on the side of the first redistribution layer 100 away from the bridging chip 200.

[0064] In this embodiment, the solder balls 500 can serve as a conductive path between the semiconductor package structure 10 and external circuitry, such as a printed circuit board, substrate, or other package structure. The solder balls 500 form low-resistance electrical contacts through a reflow soldering process, enabling signal transmission and power supply. Furthermore, the solder balls 500 can control the gap between the semiconductor package structure 10 and other structures, preventing short circuits.

[0065] In one possible implementation, step S15 includes the following sub-steps.

[0066] Step S151: A first sub-encapsulation layer 310 is formed in the gap between at least two of the conductive pillars 440 and at least one of the bridging chips 200.

[0067] Optionally, a first sub-encapsulation layer 310 can be formed by forming filler adhesive in the gap between at least two of the conductive pillars 440 and at least one of the bridging chips 200 through an underfill process.

[0068] In this embodiment, the first sub-encapsulation layer 310 is used to form a dense stress buffer layer to alleviate mechanical stress caused by the mismatch of the thermal expansion coefficients of the materials inside the semiconductor packaging structure 10, thereby preventing cracks or delamination failures between the conductive pillar 440 and the bridging chip 200; at the same time, it can also isolate external moisture and contaminants from intrusion, improving the long-term reliability of the semiconductor packaging structure 10.

[0069] Step S152: A second sub-package layer 320 is formed on the side of the first redistribution layer 100 near the package structure of the target chip 410.

[0070] Alternatively, a second sub-package layer 320 can be formed by using a molding process on the side of the first overlay layer 100 close to the package structure of the target chip 410 using molding material.

[0071] In this embodiment, the second sub-package layer 320 can completely cover the exposed areas of the conductive pillar 440 bridging the chip 200 and the first redistribution layer 100 and the second redistribution layer 430. This improves the bending and impact resistance of the semiconductor package structure 10; further blocks external moisture and contamination, improving service life and reliability; and also suppresses the risk of interface delamination.

[0072] In one possible implementation, a monolithically formed second encapsulation layer 300 is formed in step S15.

[0073] Optionally, a second encapsulation layer 300 can be formed by a molding process.

[0074] In this embodiment, the integral molding of the second encapsulation layer 300 can effectively disperse and release the stress generated during the encapsulation process, thereby reducing the risk of the semiconductor package structure 10 cracking due to stress concentration. Furthermore, the integral molding process can reduce the number of fabrication steps for the semiconductor package structure 10, improving production efficiency.

[0075] Based on the same inventive concept, this application also provides a semiconductor packaging structure 10, please refer to... Figure 5 The semiconductor package structure 10 is fabricated using the method described in any one of the preceding claims, comprising: a first redistribution layer 100, the first redistribution layer 100 including opposing first and second surfaces, the first redistribution layer 100 further including a plurality of first metal traces 101 extending from the first surface to the second surface; a plurality of conductive pillars 440 and at least one bridging chip 200 spaced apart on one side of the first redistribution layer 100; wherein the plurality of conductive pillars 440 and at least one bridging chip 200 are alternately arranged; a second redistribution layer 430 located on the side of the plurality of conductive pillars 440 and at least one bridging chip 200 away from the first redistribution layer 100, the second redistribution layer 430 including opposing third and fourth surfaces, the second redistribution layer 430... It also includes multiple second metal traces 431 extending from the third surface to the fourth surface; wherein the second metal traces 431 are electrically connected to the first metal trace 101 via the conductive post 440; multiple target chips 410 located on one side of the second redistribution layer 430; wherein at least two of the target chips 410 are electrically connected to the same bridging chip 200 via the second metal traces 431; a second packaging layer 300, the second packaging layer 300 including a first sub-packaging layer 310 and a second sub-packaging layer 320, the first sub-packaging layer 310 being located on the side of the first redistribution layer 100 near the target chip 410, and the second sub-packaging layer 320 being located in the gap between the multiple conductive posts 440, at least one bridging chip 200 and the multiple target chips 410.

[0076] In this embodiment, the semiconductor package structure 10 achieves high-density interconnection of multiple target chips 410 in a limited package structure by bridging the chip 200, the first rewiring layer 100, and the first metal trace 101 and the second metal trace 431 in the second rewiring layer 430, thereby reducing signal delay and power consumption; the conductive pillar 440 also provides a low-impedance vertical interconnect channel.

[0077] Since the semiconductor package structure 10 in this embodiment is manufactured using the aforementioned semiconductor package structure 10 manufacturing method, the semiconductor package structure 10 in this embodiment has good reliability.

[0078] In one possible implementation, please refer to Figure 6 The semiconductor package structure 10 further includes solder balls 500 located on the side of the first redistribution layer 100 away from the target chip 410; wherein, a plurality of solder balls 500 are electrically connected to the target chip 410 through the first metal trace 101, the conductive pillar 440 and the second metal trace 431.

[0079] In this embodiment, the solder balls 500 can serve as a conductive path between the semiconductor package structure 10 and external circuitry, such as a printed circuit board, substrate, or other package structure. The solder balls 500 form low-resistance electrical contacts through a reflow soldering process, enabling signal transmission and power supply. Furthermore, the solder balls 500 can control the gap between the semiconductor package structure 10 and other structures in this embodiment, preventing short circuits.

[0080] Optionally, the solder ball 500 may be made of a tin-based alloy.

[0081] In one possible implementation, the first sub-encapsulation layer 310 and the second sub-encapsulation layer 320 are integrally formed. This effectively disperses and releases the stress generated during the packaging process of the semiconductor package structure 10 in this embodiment, thereby reducing the risk of the semiconductor package structure 10 cracking due to stress concentration.

[0082] In one possible implementation, the first sub-encapsulation layer 310 is made of epoxy resin; the second sub-encapsulation layer 320 is made of epoxy encapsulant. Thus, different materials can be used for two encapsulations at different locations to improve the stability of the semiconductor package structure 10 in this embodiment.

[0083] It should be noted that, in addition to epoxy resin or epoxy encapsulant, other materials may be used as the materials for the first sub-encapsulation layer 310 and the second sub-encapsulation layer 320.

[0084] Based on the same inventive concept, this application also provides an electronic device, which includes the semiconductor packaging structure 10 described in any of the preceding claims. Since the aforementioned semiconductor packaging structure 10 avoids the alignment error between the bridge chip 200 and the second wiring layer 430 caused by first packaging the bridge chip 200 and then packaging the entire device, the reliability of the semiconductor packaging structure 10 is improved, thus increasing the product yield of the electronic device using the aforementioned semiconductor packaging structure 10.

[0085] In summary, this application provides a semiconductor package structure 10 and a method for manufacturing the same. The method includes: providing a first redistribution layer 100; connecting at least one bridging chip 200 to one side of the first redistribution layer 100; providing a target chip 410 package structure; electrically connecting the end face of the conductive post 440 away from the second redistribution layer 430 to the first redistribution layer 100, so that the target chip 410 package structure is electrically connected to the first redistribution layer 100; and forming a second package layer 300. By pre-setting a target chip 410 package structure having conductive posts 440, a second redistribution layer 430, and a target chip 410; then electrically connecting it to the bridging chip 200, thereby forming an electrical connection between multiple target chips 410; and finally encapsulating it as a whole, the alignment error between the bridging chip 200 and the second redistribution layer 430 caused by first encapsulating the bridging chip 200 and then encapsulating the whole is avoided, thus improving the reliability of the electrical connection between multiple target chips 410 and increasing the product yield of the semiconductor package structure 10.

[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor package structure, characterized in that, The method includes: Provide the first wiring layer; At least one bridging chip is connected to one side of the first rewiring layer; A target chip packaging structure is provided; wherein the target chip packaging structure includes a second wiring layer; at least two target chips and a first packaging layer are spaced apart on one side of the second wiring layer, the first packaging layer being located on the side of the second wiring layer closer to the target chips and in the gap between the spaced-apart target chips; at least two conductive pillars are spaced apart on the side of the second wiring layer away from the target chips; wherein the conductive pillars are electrically connected to the target chips via the second wiring layer; The end face of the conductive post away from the second wiring layer is electrically connected to the first wiring layer, so that the target chip package structure is electrically connected to the first wiring layer; wherein, the conductive post and the bridging chip are arranged alternately, and the bridging chip connects at least two target chips that are spaced apart through the second wiring layer; A second encapsulation layer is formed; wherein the second encapsulation layer is located on the side of the first redistribution layer near the target chip encapsulation structure and in the gap between at least two of the conductive pillars and at least one of the bridging chips.

2. The method according to claim 1, characterized in that, Before performing the step of providing the target chip package structure, the method further includes: Provide the first carrier board; At least two of the target chips are placed at intervals on one side of the first carrier board; An integrally formed first encapsulation layer is formed on the side of the first carrier board near the target chip and in the gap between at least two target chips spaced apart; Flip the first encapsulation layer and the target chip so that the side of the target chip away from the first carrier is exposed to the first encapsulation layer; A second wiring layer is formed on the side of the first encapsulation layer away from the first carrier board; wherein the second wiring layer is electrically connected to the target chip; At least two conductive pillars are formed at intervals on the side of the second redistribution layer away from the target chip; wherein the conductive pillars are electrically connected to the target chip through the second redistribution layer; Remove the first carrier board to form the target chip package structure.

3. The method according to claim 1, characterized in that, Before performing the step of providing the first redistribution layer, the method further includes: Provide a second carrier board; A first redistribution layer is formed on the second carrier board; After performing the step of forming the second encapsulation layer, the method further includes: Remove the second carrier board.

4. The method according to claim 3, characterized in that, After performing the step of removing the second carrier plate, the method further includes: Multiple solder balls are formed at intervals on the side of the first redistribution layer away from the bridging chip.

5. The method according to claim 1, characterized in that, The step of forming the second encapsulation layer includes: A first sub-encapsulation layer is formed in the gap between at least two of the conductive pillars and at least one of the bridging chips; A second sub-package layer is formed on the side of the first redistribution layer that is close to the target chip package structure.

6. A semiconductor packaging structure, characterized in that, The semiconductor package structure is manufactured using the method described in any one of claims 1-5, comprising: The first wiring layer includes a first surface and a second surface opposite to each other, and the first wiring layer also includes a plurality of first metal traces extending from the first surface to the second surface; A plurality of conductive pillars and at least one bridging chip are spaced apart on one side of the first redistribution layer; wherein the plurality of conductive pillars and at least one bridging chip are arranged alternately. A second redistribution layer is located on the side of the plurality of conductive pillars and at least one of the bridging chips away from the first redistribution layer. The second redistribution layer includes opposing third and fourth surfaces. The second redistribution layer also includes a plurality of second metal traces extending from the third surface to the fourth surface. The second metal traces are electrically connected to the first metal traces via the conductive pillars. Multiple target chips located on one side of the second redistribution layer; wherein at least two of the target chips are electrically connected to the same bridging chip via a second metal trace; The second packaging layer includes a first sub-packaging layer and a second sub-packaging layer. The first sub-packaging layer is located on the side of the first redistribution layer close to the target chip, and the second sub-packaging layer is located in the gap between the plurality of conductive pillars, at least one of the bridging chips and the plurality of target chips.

7. The semiconductor packaging structure according to claim 6, characterized in that, The semiconductor packaging structure also includes solder balls located on the side of the first redistribution layer away from the target chip; The solder balls are electrically connected to the target chip via the first metal trace, the conductive pillar, and the second metal trace.

8. The semiconductor packaging structure according to claim 6, characterized in that, The first sub-encapsulation layer and the second sub-encapsulation layer are integrally formed.

9. The semiconductor packaging structure according to claim 8, characterized in that, The material of the first sub-encapsulation layer includes epoxy resin; the material of the second sub-encapsulation layer includes epoxy encapsulant.

10. An electronic device, characterized in that, The electronic device includes the semiconductor packaging structure according to any one of claims 6-9.

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