A chip, a method for improving transient response performance of the chip, and an electronic device

Abstract

Embodiments of the present application provide a chip, a method for improving transient response performance of the chip, and an electronic device, which can solve the technical problem of poor transient response performance caused by load or power mutation in the related art. The error comparator of the chip feeds back a feedback voltage and a reference voltage in real time, and triggers an on-period instruction in the case that the feedback voltage is less than the reference voltage. The on-time generator generates an on-time pulse in response to the on-period instruction. The control module receives a feedback signal output by the error comparator and an on-time pulse generated by the on-time generator, and generates a driving timing. The gate driver switches the device according to the driving timing. The feedback module proportionally reduces an output voltage to the feedback voltage. The on-time generator adjusts the charging current of the control capacitor according to the current output voltage to adjust the current on-time in the case that the load changes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chip, a method for improving transient response performance of the chip, and an electronic device. BACKGROUND

[0002] Constant ON-time (COT) is an architecture in which the on time is constant and the off time can vary in a switching power supply chip. Compared with traditional constant frequency (Constant Frequency) architectures, such as a peak current mode (Peak Current Mode, PCM) architecture, a traditional voltage mode architecture (Traditional Voltage Mode), and the like, the Constant ON-time (COT) architecture can obtain a faster inductor current (Inductor Current) change speed, that is, a better transient response performance (Transient Response Performance), because the off time can change when a transient change occurs (that is, there is no need to run at a constant frequency). Therefore, in the current situation in which the power supply demand of digital chips such as a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), a field-programmable gate array (Field-Programmable Gate Array, FPGA), and an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC) is increasingly high, the Constant ON-time (COT) technology has been increasingly widely applied.

[0003] At present, the implementation manner of the Constant ON-time (COT) can be adaptive Constant ON-time (Adaptive Constant ON-time, ACOT). In addition to the advantage of fast loop response of the traditional Constant ON-time (COT), the adaptive Constant ON-time (Adaptive Constant ON-time, ACOT) can also make the switching frequency (Switching Frequency) relatively constant, which is convenient for inductor (Inductor) selection and reduction of system electromagnetic interference (Electromagnetic Interference, EMI).

[0004] However, although the ACOT can obtain a faster inductance current change speed by changing the off time (TOFF) only when the load or power supply transient changes, the load or power supply transient response performance is still limited. SUMMARY

[0005] Embodiments of the present application provide a chip, a method for improving chip transient response performance, and an electronic device, which can solve the technical problem of poor transient response performance caused by load or power supply mutation in related technologies.

[0006] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide a chip, which comprises: an error comparator, a conduction time generator, a control module, a gate driver, and a feedback module; the error comparator is configured to feed back a feedback voltage and a reference voltage in real time, and trigger a conduction period instruction in the case that the feedback voltage is less than the reference voltage; the conduction time generator is configured to generate a conduction time pulse in response to the conduction period instruction; the control module is configured to receive a feedback signal output by the error comparator and a conduction time pulse generated by the conduction time generator, and generate a driving timing; the gate driver is configured to realize device switching according to the driving timing; and the feedback module is configured to reduce an output voltage to the feedback voltage in proportion; and the conduction time generator is further configured to adjust a charging current of a conduction time control capacitor according to a current output voltage to adjust a current conduction time in the case that the load changes.

[0008] Based on the above description of the chip provided by embodiments of the present application, it can be known that the chip comprises an innovative adaptive loop adjustment mechanism, which significantly improves the dynamic response performance of a switching power supply (such as a Buck converter) in load transient, while maintaining system stability and adjustment accuracy. The charging current of the conduction time control capacitor in the feedback module is adjusted according to the current output voltage, that is, the lower the output voltage, the smaller the charging current, and the longer the conduction time; the higher the output voltage, the greater the charging current, and the shorter the conduction time. Through the innovative adaptive loop adjustment mechanism (adjusting the conduction time control capacitor charging current according to the output voltage), the dynamic response performance of the system in load transient is greatly optimized, while maintaining high stability and accurate voltage regulation, and fast and smooth voltage recovery is realized.

[0009] In an implementation of the first aspect, the on-time generator comprises a transconductance amplifier, a first filter circuit; the transconductance amplifier comprises a first positive electrode, a first negative electrode and a first output pin; the first output pin is connected with the on-time control capacitor; the first negative electrode inputs a current reference voltage; the first filter circuit comprises a filter capacitor and a first resistor; one end of the filter capacitor and one end of the first resistor are connected with the first positive electrode; the other end of the filter capacitor is grounded; the other end of the first resistor inputs a current feedback voltage; wherein, in the case that the current feedback voltage is less than the current reference voltage, the charging current of the on-time control capacitor decreases; in the case that the current feedback voltage is greater than the current reference voltage, the charging current of the on-time control capacitor increases.

[0010] In an implementation of the first aspect, the tail current of the transconductance amplifier is less than a normal charging current value; the normal charging current value is the charging current value of the on-time generator to the on-time control capacitor when the load is unchanged.

[0011] In an implementation of the first aspect, the on-time generator comprises a first hysteresis comparator, a second hysteresis comparator, a second filter circuit, a high-level switch and a low-level switch; the hysteresis negative electrode of the first hysteresis comparator and the hysteresis negative electrode of the second hysteresis comparator are connected; the first hysteresis positive electrode of the first hysteresis comparator inputs a first reference voltage, and the second hysteresis positive electrode of the first hysteresis comparator inputs a second reference voltage; the first reference voltage is greater than the second reference voltage, and the second reference voltage is greater than a normal reference voltage; the first hysteresis positive electrode of the second hysteresis comparator inputs a third reference voltage, and the second hysteresis positive electrode of the second hysteresis comparator inputs a fourth reference voltage; the third reference voltage is greater than the fourth reference voltage, and the fourth reference voltage is greater than the normal reference voltage; the output electrode of the first hysteresis comparator is connected with the low-level switch; the output electrode of the second hysteresis comparator is connected with the high-level switch; the second filter circuit comprises a filter capacitor and a first resistor; one end of the filter capacitor and one end of the first resistor are connected with the hysteresis negative electrode of the first hysteresis comparator; the other end of the filter capacitor is grounded; the other end of the first resistor inputs a current feedback voltage; the current output electrode of the low-level switch, the current input electrode of the high-level switch and the on-time control capacitor are connected; wherein, in the case that the current output voltage and the current reference voltage are less than the third reference voltage, the low-level switch is in an open state to make the charging current of the on-time control capacitor decrease and the current on-time increase; in the case that the current reference voltage is equal to the fourth reference voltage, the low-level switch is in a closed state; in the case that the current output voltage and the current reference voltage are greater than the first reference voltage, the high-level switch is in an open state to make the charging current of the on-time control capacitor increase and the current on-time decrease; in the case that the current reference voltage is equal to the second reference voltage, the high-level switch is in a closed state.

[0012] In a possible implementation of the first aspect, the combined current of the high-level switch and the low-level switch is less than a conventional charging current value, and a ratio of the combined current to the conventional charging current value is fixed; the conventional charging current value is a charging current value of the on-time generator to the on-time control capacitor when the load is unchanged.

[0013] In a possible implementation of the first aspect, the high-level switch is a P-channel metal-oxide-semiconductor field-effect transistor switch, and the low-level switch is an N-channel metal-oxide-semiconductor field-effect transistor switch.

[0014] In a possible implementation of the first aspect, the chip is applied to a buck converter, a boost converter, or a buck-boost converter.

[0015] In a possible implementation of the first aspect, the chip further includes a reference voltage source and a protection function module; the reference voltage source provides a stable voltage target for the error comparator; and the protection function module is configured to monitor the output voltage and forcibly turn off the power switch tube when the output voltage exceeds a safety threshold.

[0016] In a second aspect, an embodiment of the present application provides a method for improving transient response by changing TON, the method including: feeding back a feedback voltage and a reference voltage in real time; triggering an on-period instruction in a case where the feedback voltage is less than the reference voltage; generating an on-time pulse in response to the on-period instruction; receiving the feedback voltage and the on-time pulse, and generating a driving timing; switching a device according to the driving timing; proportionally reducing an output voltage to the feedback voltage; and adjusting a charging current of an on-time control capacitor according to a current output voltage to adjust a current on-time in a case where a load mutates.

[0017] In a third aspect, an embodiment of the present application provides an electronic device, including a circuit board and a chip as in the first aspect, the chip being arranged on the circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 shows a structural schematic diagram of an electronic device according to an embodiment of the present application;

[0019] Figure 2 FIG. 2 shows a structural schematic diagram of a chip according to an embodiment of the present application;

[0020] Figure 3a FIG. 3 shows a structural schematic diagram of a chip according to an embodiment of the present application;

[0021] Figure 3b FIG. 4 shows a structural schematic diagram of a chip according to an embodiment of the present application; Figure 3a FIG. 5 shows a structural schematic diagram of an OTA in a chip shown in FIG. 4 according to an embodiment of the present application;

[0022] Figure 4 FIG. 6 shows a structural schematic diagram of a chip according to an embodiment of the present application;

[0023] Figure 5 A chip structure schematic diagram provided for an embodiment of the present application;

[0024] Figure 6 A key node waveform comparison schematic diagram in a method of improving transient response of a COT architecture when a load mutates, provided for related technologies and an embodiment of the present application;

[0025] Figure 7 A key node waveform comparison schematic diagram in a method of improving transient response of a COT architecture when a load mutates, provided for related technologies and an embodiment of the present application;

[0026] Figure 8 A flowchart of a method of improving chip transient response provided for an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, “multiple” refers to two or more than two, unless otherwise specified. “At least one of the following” or similar expressions refers to any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0028] In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same function and role are distinguished by using “first”, “second” and the like. Those skilled in the art can understand that “first”, “second” and the like do not limit the quantity and execution order, and “first”, “second” and the like do not necessarily mean different. At the same time, in the embodiments of the present application, “exemplary” or “for example” is used to represent as an example, illustration or description. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, “exemplary” or “for example” is used to present the relevant concept in a specific manner, and to facilitate understanding.

[0029] The principles and features of the present application will be described below, and the examples are only used to explain the present application, and not to limit the scope of the present application.

[0030] This application provides an electronic device including a switching power supply chip. This electronic device can be a portable terminal device, such as a smartphone, tablet, smartwatch, wireless headset, e-reader, portable game console, digital camera, or drone; it can also be a fixed computing device, such as a personal computer (PC), laptop, workstation, server, or network storage device; it can also be a smart home device, such as a smart TV, router, set-top box, smart speaker, home game console, or smart appliance controller; it also includes industrial equipment, such as industrial control computers, PLC controllers, industrial sensors, and medical electronic instruments (e.g., electrocardiogram monitors, portable ultrasound devices); furthermore, it includes new energy equipment, such as photovoltaic inverters, on-board chargers (OBCs) for electric vehicles, and in-vehicle infotainment systems; and communication infrastructure equipment, such as 5G base stations, fiber optic switches, and data center servers. This application does not impose any special limitations on the specific form of the above-mentioned electronic device.

[0031] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 1 As shown, the electronic device 1 includes a switching power supply chip 10 and a circuit board 20. The switching power supply chip 10 is disposed on the circuit board 20 and is connected to the circuit board 20.

[0032] Figure 2 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 2 As shown, in some embodiments, the COT architecture chip for improving transient response includes: an error comparator 110, an on-time generator 120, a control module 130, a gate driver 140, and a feedback module 150.

[0033] Error comparator 110 is configured to provide real-time feedback of the feedback voltage and reference voltage, and to trigger a conduction cycle command when the feedback voltage is less than the reference voltage.

[0034] The on-time generator 120 is configured to generate an on-time pulse in response to a conduction cycle command. The on-time generator 120 is the core module. For example, the on-time generator 120 precisely generates a fixed-width on-time pulse based on the input voltage, the output voltage (or both), and an internally set constant. This pulse width determines the on-time of each power switch. The implementation can be analog (e.g., based on RC charging / discharging) or digital (lookup table or calculation unit).

[0035] The control module 130 is configured to receive the feedback signal output by the error comparator 110 and the conduction time pulse generated by the conduction time generator 120, and generate the drive timing sequence.

[0036] The gate driver 140 is configured to implement device switching according to a driving timing.

[0037] The feedback module 150 is configured to proportionally reduce the output voltage to a feedback voltage.

[0038] The on-time control capacitor 151 (which can be denoted as Con). The on-time generator 120 is further configured to adjust the charging current of the on-time control capacitor 151 according to the current output voltage (VOUT) to adjust the current on-time in the case of load change.

[0039] The following describes several possible implementations of the on-time generator in detail in combination with the accompanying drawings.

[0040] For example,

[0041] As shown in Figure 3a In one implementation, the on-time generator 120 includes an operational transconductance amplifier (OTA) 1211, a first filter circuit 1212.

[0042] The operational transconductance amplifier (OTA) 1211 includes a first positive electrode 1211a, a first negative electrode 1211b, and a first output pin 1211c. The first output pin 1211c is connected to the on-time control capacitor 151. The first negative electrode 1211b inputs the current reference voltage (VREF). The operational transconductance amplifier is a voltage input, current output amplifier, whose core characteristic is to describe the gain with the transconductance parameter gm (the ratio of the output current to the input voltage). The tail current size of the operational transconductance amplifier is B (where B < A, A is the charging current value of the conventional TON generator to Con).

[0043] In some embodiments, the operational transconductance amplifier is as shown in Figure 3bThe differential input stage is composed of NMOS MN1 and MN2: MN1 gate is connected to reference voltage VREF, MN2 gate is connected to feedback voltage FBN, and the sources of the two are connected to the drain of tail current source MN3 (MN3 source is connected to ground, and the gate needs to be biased); the current mirror load is composed of PMOS MP1 and MP2: the sources of the two are connected to power supply VDD, the gates are interconnected, the drain of MP1 is connected to the drain of MN1 (forming node A), and the drain of MP2 is connected to the drain of MN2 (forming node B). The output stage adopts a push-pull structure: node A drives the gate of PMOS MP3 (MP3 source is connected to VDD, and the drain outputs OUT), and node B drives the gate of NMOS MN4 (MN4 source is connected to ground, and the drain is connected to the drain of MP4 to form the OUT node). The compensation and feedback network includes a turn-on time control capacitor and a feedback resistor Rf: the turn-on time control capacitor is connected across the output node OUT and the high-gain node A. One end of the feedback resistor Rf is connected to the main output OUT, and the other end is fed back to the FBN input to form a closed-loop regulation (a voltage dividing resistor needs to be externally connected to ground). The signal flow is as follows: the difference between VREF and FBN is converted into a current difference by a differential pair → the current difference is mirrored to nodes A / B by the current mirror of MP1 / MP2 → the push-pull output stage synthesizes an amplified signal to OUT → the feedback loop is closed through Rf. This structure realizes the function of a high-gain, strong-drive-capability error amplifier, which is suitable for fast voltage regulation of power management chips.

[0044] The first filter circuit 1212 includes a filter capacitor Cf and a first resistor Rf. One end of the filter capacitor Cf and one end of the first resistor Rf are connected to the first positive electrode 1211a. The other end of the filter capacitor Cf is connected to ground. The other end of the first resistor Rf inputs the current feedback voltage.

[0045] It can be understood that the feedback voltage FB of the output voltage VOUT is compared with the chip reference voltage VREF after passing through the filter circuit. When the load or the power supply is constant, FB is locked to VREF by the loop, i.e., FB=VREF; according to the characteristics of the OTA, Ichg=Idisg at this time, and no additional current charges or discharges Con.

[0046] In the case that the current feedback voltage is less than the current reference voltage (VREF), the charging current of the turn-on time control capacitor 151 is reduced. When the load suddenly becomes heavy, the FB voltage is less than VREF, and the OTA output current is in the direction of Idisg (Idisg>Ichg) at this time; the Idisg current is opposite to the original charging current Iton of the TON generator, and the current for charging Con is reduced, so that TON is increased, and the drop of VOUT is reduced.

[0047] When the current feedback voltage is greater than the current reference voltage (VREF), the charging current of the on-time control capacitor 151 increases. When the load suddenly becomes lighter, VOUT surges, and the FB voltage is greater than VREF. At this time, the OTA output current is in the direction of Ichg (Ichg>Idisg). The Ichg current is in the same direction as the original charging current Iton of the TON generator, which increases the final charging current to Con, that is, TON becomes smaller, reducing the surge of VOUT.

[0048] In some embodiments, the tail current of the transconductance amplifier 1211 is less than the conventional charging current value. The conventional charging current value is the charging current value of the on-time generator 120 to the on-time control capacitor 151 when the load remains constant.

[0049] For example,

[0050] like Figure 4 As shown, in another implementation, the on-time generator 120 includes a first hysteresis comparator 1221, a second hysteresis comparator 1222, a second filter circuit 1223, a high-level switch 1224, and a low-level switch 1225.

[0051] In some embodiments, the high-level switch 1224 is a P-channel metal-oxide-semiconductor field-effect transistor (PMOS) switch, and the low-level switch 1225 is an N-channel metal-oxide-semiconductor field-effect transistor (NMOS) switch.

[0052] The negative hysteresis electrode of the first hysteresis comparator 1221 and the negative hysteresis electrode of the second hysteresis comparator 1222 are connected. The first positive hysteresis electrode of the first hysteresis comparator 1221 receives a first reference voltage (VREF2), and the second positive hysteresis electrode receives a second reference voltage (VREF3). The first reference voltage (VREF2) is greater than the second reference voltage (VREF3), and the second reference voltage (VREF3) is greater than the normal reference voltage. The first positive hysteresis electrode of the second hysteresis comparator 1222 receives a third reference voltage (VREF4), and the second positive hysteresis electrode receives a fourth reference voltage (VREF5). The third reference voltage (VREF4) is greater than the fourth reference voltage (VREF5), and the third reference voltage (VREF4) is less than the normal reference voltage. The output electrode of the first hysteresis comparator 1221 is connected to a low-level switch 1225. The output electrode of the second hysteresis comparator 1222 is electrically connected to a high-level switch 1224.

[0053] The second filter circuit 1223 includes a filter capacitor Cf and a first resistor Rf. One end of the filter capacitor Cf and one end of the first resistor Rf are connected to the hysteresis negative electrode of the first hysteresis comparator 1221. The other end of the filter capacitor Cf is grounded. The other end of the first resistor Rf inputs the current feedback voltage.

[0054] The current output end of the low-level switch 1225, the current input end of the high-level switch 1224, and the on-time control capacitor 151 are connected.

[0055] In the case where the current output voltage (VOUT) and the current feedback voltage (FB) are less than the fourth reference voltage (VREF5), the low-level switch 1225 is in an open state, so that the charging current of the on-time control capacitor 151 is reduced, and the current on-time is increased. In the case where the current feedback voltage (FB) is greater than or equal to the third reference voltage (VREF4), the low-level switch 1225 is in a closed state. For example, when the load suddenly becomes heavy, VOUT and FB are reduced to be less than VREF5, the NMOS switch is opened, the charging current of Con is reduced to (A-B), that is, the on-time TON is lengthened, and the inductor current rising speed is accelerated. Due to the characteristics of the hysteresis comparator, the NMOS switch needs to wait until FB rises to VREF4 before being closed.

[0056] In the case where the current output voltage (VOUT) and the current feedback voltage (FB) are greater than the first reference voltage (VREF2), the high-level switch 1224 is in an open state, so that the charging current of the on-time control capacitor 151 is increased, and the current on-time is reduced. In the case where the current feedback voltage (FB) is less than or equal to the second reference voltage (VREF3), the high-level switch 1224 is in a closed state. When the load becomes light, VOUT and FB rise to be greater than VREF2, the PMOS switch is opened, the charging current of Con is increased to (A+B), that is, the on-time TON is shortened, the inductor current rising speed and the overshoot of VOUT at this time are reduced, and the PMOS switch needs to wait until FB falls to VREF3 before being closed.

[0057] In some embodiments, the combined current of the high-level switch 1224 and the low-level switch 1225 is less than the conventional charging current value, and the ratio of the combined current to the conventional charging current value is fixed. The conventional charging current value is the charging current value of the on-time generator 120 to the on-time control capacitor 151 when the load is unchanged.

[0058] In some embodiments, the chip is applied to a buck converter, a boost converter, or a buck-boost converter. It can be understood that the above only exemplarily gives several feasible application scenarios, and does not constitute a limitation on the application scenarios of the chip provided by the present application.

[0059] As Figure 5 shown, an exemplary on-time generator 120 for a buck converter (BUCK COT) can be any of the on-time generators shown in Figure 3a or Figure 4 The on-time TON is a fixed on-time generated by the on-time generator in the dashed box. The off-time TOFF is determined by the comparator CMP comparing the feedback voltage FB and the reference voltage VREF. When the feedback voltage FB of the output voltage VOUT plus the inductor current ripple component voltage FBR (i.e., FBR = FB + Ripple) is less than the reference voltage VREF, the TOFF ends and a new TON period starts.

[0060] In some embodiments, the chip further comprises a reference voltage source and a protection function module. The reference voltage source provides a stable target for the error comparator 110. The protection function module is configured to monitor the output voltage and force the power switch to turn off when the output voltage exceeds a safety threshold. Exemplary protection function modules include over-voltage protection, over-temperature protection, under-voltage lockout, soft-start, short-circuit protection, and / or bias and auxiliary functions.

[0061] Over-voltage protection monitors the output voltage and forces the power switch to turn off when it exceeds a safety threshold. Over-current protection / limiting: monitors the inductor current or the current of the high-side / low-side MOSFET (by detecting the resistance or Rds(on) of the MOSFET) and terminates the current on-time or turns off the output when the current exceeds a set threshold. Common types include peak current limit, valley current limit, hiccup mode, etc.

[0062] Over-temperature protection monitors the die temperature of the chip and turns off the output when it exceeds a safety threshold and automatically recovers when the temperature decreases.

[0063] Under-voltage lockout keeps the chip off when the input voltage is too low (not enough to ensure normal operation of the chip and the driver) to prevent abnormal operation.

[0064] Soft-start gradually increases the output voltage or limits the start-up current during the start-up phase to prevent input voltage droop and output overshoot.

[0065] Short-circuit protection detects whether the output is shorted to ground and takes appropriate protective measures (such as hiccup mode).

[0066] Bias and auxiliary functions: internal bias power supply provides stable low-voltage power supply for all internal modules of the chip (comparators, logic, drivers, etc.), usually generated by the input voltage through a linear regulator.

[0067] In some embodiments, the chip further includes a minimum turn-off time control module, which forces a minimum turn-off time (e.g., 100ns~500ns) to be inserted between two turn-on pulses to prevent the switching frequency from increasing indefinitely (especially under light load) and to avoid loss and noise problems.

[0068] In some embodiments, the chip further includes: a slope compensation module, and a drive and power stage interface (control logic: receives the output signals of the error comparator and the on-time generator, and integrates constraints such as the minimum off-time to generate the final gate drive logic signal. Gate driver: amplifies the low-power logic signal generated by the control logic to a sufficiently high current and voltage to quickly and reliably drive the gate of the external power MOSFET, reducing switching losses. It typically includes a bootstrap circuit (for high-side drive) or a level shifting circuit.)

[0069] The following detailed description, in conjunction with the accompanying drawings, explains the relevant technologies and the response changes of this application under varying loads.

[0070] like Figure 6 As shown in (a) in the figure, this is a schematic diagram of the waveform of a sudden increase in load current in the relevant technology (i.e., conventional COT). Figure 7 As shown in (a) of the diagram, this is a schematic diagram of the waveform when the load current suddenly decreases in a related technology (i.e., a conventional COT). If the load suddenly becomes heavier, VOUT and FBR decrease rapidly, meaning the off-time TOFF shortens. Since TON remains constant, the increase in inductor current IL is greater than the decrease, meaning the inductor current eventually rises to the load current, and the system achieves balance. If the load suddenly becomes lighter, VOUT and FBR increase rapidly, meaning the off-time TOFF increases. Since TON remains constant, the decrease in IL is greater than the increase, meaning the inductor current eventually decreases to the load current, and the system achieves balance. Theoretically, the TOFF of a COT architecture can increase or decrease infinitely with the rate of load change, while TON remains constant, meaning the frequency can vary infinitely. Therefore, compared to traditional constant-frequency architectures (such as peak current mode architectures, traditional voltage mode architectures, etc.), COT can achieve a faster inductor current change rate, i.e., better transient response performance. Taking the most commonly used Adaptive Constant On-Time (ACOT) buck converter, also known as a step-down chip, as an example, its on-time (TON) is determined by charging capacitor Con with a current I proportional to the input voltage (VIN). The capacitor voltage is then compared with the output voltage (VO). When the voltage of Con reaches VO, the high-side switch on-time (TON) ends. The on-time (TON) is calculated as follows:

[0071] ;

[0072] In combination with the formula of the buck duty cycle (Duty Cycle, D) D=Vo / Vin, it can be concluded that:

[0073] ;

[0074] The expression of the switching frequency (Switching Frequency, fs) of the final adaptive constant on-time (Adaptive Constant ON-time, ACOT) architecture is:

[0075] .

[0076] In this way, the switching frequency (Switching Frequency, fs) of the adaptive constant on-time (Adaptive Constant ON-time, ACOT) is irrelevant to variables such as Vin and Vo, and is only related to the fixed parameters Con, Ron and the proportional coefficient A in chip design.

[0077] Therefore, this architecture can better stabilize the switching frequency (Switching Frequency, fs) of the buck, and solve the problem of the frequency of the traditional constant on-time (Constant ON-time, COT) being unstable.

[0078] Although ACOT can obtain a faster inductor current change speed by changing the off time TOFF when the load or power supply transient changes, the on time TON cannot be changed, which still limits the load or power supply transient response performance to a certain extent.

[0079] After adopting the TON generation circuit of Figure 3a or Figure 4 , the waveforms of the key nodes when the load suddenly increases and the comparison analysis with their conventional COT are shown in (b) of Figure 6 , and the waveforms of the key nodes when the load suddenly decreases and the comparison analysis with their conventional COT are shown in (b) of Figure 7 . It can be seen from Figure 6 and Figure 7 that the chip provided in the application has a faster transient response speed, that is, the overshoot or undershoot of VOUT when the load suddenly changes is smaller.

[0080] Figure 8 A flowchart of a method for improving transient response by changing TON provided in an embodiment of the application. As shown in Figure 8As shown, in some embodiments, the method of improving transient response by changing TON includes the following steps:

[0081] S1, feeding back the feedback voltage and the reference voltage in real time;

[0082] S2, triggering the on-period instruction in the case that the feedback voltage is less than the reference voltage;

[0083] S3, generating the on-time pulse in response to the on-period instruction;

[0084] S4, receiving the feedback voltage and the on-time pulse, and generating the driving timing;

[0085] S5, implementing the device switching according to the driving timing;

[0086] S6, proportionally reducing the output voltage to the feedback voltage;

[0087] S7, in the case that the load changes, adjusting the charging current of the on-time control capacitor according to the current output voltage to adjust the current on-time.

[0088] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0089] In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. The plurality of units or devices stated in the device claim can also be implemented by one unit or device through software or hardware. The words first, second, etc. are used to indicate names, and not to indicate any specific order.

Claims

1. A chip, characterized in that, include: Error comparator, on-time generator, control module, gate driver, and feedback module; The error comparator is configured to provide real-time feedback of the feedback voltage and the reference voltage, and to trigger a conduction cycle command when the feedback voltage is less than the reference voltage. The conduction time generator is configured to generate a conduction time pulse in response to the conduction cycle command; The control module is configured to receive the feedback signal output by the error comparator and the conduction time pulse generated by the conduction time generator, and generate a drive timing sequence. The gate driver is configured to switch devices according to the driving timing. The feedback module is configured to proportionally reduce the output voltage to the feedback voltage; The on-time generator is also configured to adjust the charging current of the on-time control capacitor according to the current output voltage in the event of load changes, so as to adjust the current on-time. The on-time generator includes a first hysteresis comparator, a second hysteresis comparator, a second filter circuit, a high-level switch, and a low-level switch; The negative hysteresis electrode of the first hysteresis comparator and the negative hysteresis electrode of the second hysteresis comparator are connected; the first hysteresis positive electrode of the first hysteresis comparator is input with a first reference voltage, and the second hysteresis positive electrode of the first hysteresis comparator is input with a second reference voltage; the first reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the normal reference voltage. The first hysteresis positive electrode of the second hysteresis comparator is input to a third reference voltage, and the second hysteresis positive electrode of the second hysteresis comparator is input to a fourth reference voltage; the third reference voltage is greater than the fourth reference voltage, and the fourth reference voltage is greater than the normal reference voltage; the output electrode of the first hysteresis comparator is connected to the low-level switch; the output electrode of the second hysteresis comparator is connected to the high-level switch. The second filter circuit includes a filter capacitor and a first resistor; one end of the filter capacitor and one end of the first resistor are both connected to the negative hysteresis electrode of the first hysteresis comparator; the other end of the filter capacitor is grounded; the other end of the first resistor is input with the current feedback voltage. The current output terminal of the low-level switch, the current input terminal of the high-level switch, and the on-time control capacitor are connected. Specifically, when the current output voltage and the current reference voltage are less than the third reference voltage, the low-level switch is in the open state to reduce the charging current of the conduction time control capacitor and increase the current conduction time; when the current reference voltage is equal to the fourth reference voltage, the low-level switch is in the closed state. When the current output voltage and the current reference voltage are both greater than the first reference voltage, the high-level switch is in the open state, thereby increasing the charging current of the conduction time control capacitor and decreasing the current conduction time; when the current reference voltage is equal to the second reference voltage, the high-level switch is in the closed state.

2. The chip according to claim 1, characterized in that, The combined current of the high-level switch and the low-level switch is less than the normal charging current value, and the ratio of the combined current to the normal charging current value is fixed; the normal charging current value is the charging current value of the on-time control capacitor by the on-time generator when the load remains unchanged.

3. The chip according to claim 2, characterized in that, The high-level switch is a P-channel metal-oxide-semiconductor field-effect transistor switch, and the low-level switch is an N-channel metal-oxide-semiconductor field-effect transistor switch.

4. The chip according to claim 1 or 2, characterized in that, The chip also includes: a reference voltage source and a protection function module; The reference voltage source provides a voltage regulation target for the error comparator; The protection module is configured to monitor the output voltage and forcibly shut down the power switch when the output voltage exceeds a safety threshold.

5. A method for improving the transient response performance of a chip, characterized in that, Applied to the chip according to any one of claims 1-4, the method comprises: Real-time feedback of feedback voltage and reference voltage; If the feedback voltage is less than the reference voltage, a conduction cycle command is triggered; In response to the conduction cycle command, a conduction time pulse is generated; Receive the feedback voltage and the conduction time pulse, and generate a drive timing sequence; Device switching is achieved according to the driving timing; The output voltage is proportionally reduced to the feedback voltage; When the load changes, the charging current of the control capacitor is adjusted according to the current output voltage to regulate the current conduction time.

6. An electronic device, characterized in that, include: circuit board The chip as described in any one of claims 1-4, wherein the chip is disposed on the circuit board.

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