Gilbert mixer

Abstract

A Gilbert mixer for a radar transceiver comprises: first and second multi-interdigital field effect transistor (FET) devices, each FET device comprising a plurality of gate interdigitals arranged between alternating source and drain terminals along a longitudinal axis, the plurality of gate interdigitals of each FET device extending transverse to the longitudinal axis of the FET device; first and second pairs of voltage rails are arranged parallel to the longitudinal axis across the first and second FET devices, respectively, each of the first and second pairs of voltage rails comprising an upper rail and a lower rail; a first gate interconnect connects an upper rail of the first pair of voltage rails and a lower rail of the second pair of voltage rails to a first input; a second gate interconnect connects the lower rail of the first pair of voltage rails and the upper rail of the second pair of voltage rails to a second input. Alternating adjacent pairs of gate fingers of the first FET device are connected to respective upper and lower rails of the first pair of voltage rails, and alternating adjacent pairs of gate fingers of the second FET device are connected to respective upper and lower rails of the second pair of voltage rails.

Description

Technical Field

[0001] This disclosure relates to a Gilbert mixer for radar transceivers. Background Technology

[0002] Gilbert mixers are commonly used in automotive radar and communication transceivers to perform up-conversion and down-conversion functions. Typically, Gilbert mixers suffer from frequency-dependent local oscillator (LO) leakage. This leakage is primarily caused by asymmetry in the circuit layout of the Gilbert mixer. In radar systems utilizing Doppler frequency division multiplexing (DDM) coding, this LO leakage leads to the repetition of the same phase error. This can cause spurious frequencies in the Doppler spectrum to exceed the noise floor, thus reducing radar sensitivity. In communication systems, LO leakage also limits the error vector magnitude (EVM) and the resulting channel processing capacity.

[0003] When considering millimeter-wave radar systems, the circuit layout of the Gilbert mixer is crucial. Micrometer-scale unequal trace lengths can introduce significant phase errors, thereby introducing LO leakage that degrades Gilbert mixer performance. Therefore, a key issue is how to reduce LO leakage in Gilbert mixers. Summary of the Invention

[0004] According to a first aspect, a Gilbert mixer is provided, the Gilbert mixer comprising:

[0005] A first multi-finger field-effect transistor (FET) device and a second multi-finger field-effect transistor (FET) device, each FET device including a plurality of gate interdigitates arranged along a longitudinal axis between alternating source and drain terminals, wherein the plurality of gate interdigitates of each FET device extend transversely to the longitudinal axis of the FET device;

[0006] A first pair of voltage rails and a second pair of voltage rails are arranged parallel to the longitudinal axis, spanning the first FET device and the second FET device respectively. Each pair of voltage rails includes an upper rail and a lower rail.

[0007] A first gate interconnect, wherein the first gate interconnect connects the upper rail of the first pair of voltage rails and the lower rail of the second pair of voltage rails to a first input terminal; and

[0008] A second gate interconnect connects the lower rail of the first pair of voltage rails and the upper rail of the second pair of voltage rails to a second input terminal.

[0009] The alternating adjacent pairs of the gate interdigitates of the first FET device are connected to the corresponding upper and lower rails of the first pair of voltage rails, and the alternating adjacent pairs of the gate interdigitates of the second FET device are connected to the corresponding upper and lower rails of the second pair of voltage rails.

[0010] The plurality of gate interdigitates of each FET device can be aligned orthogonally to the longitudinal axis.

[0011] The second FET device may be offset relative to the first FET device in a direction orthogonal to the longitudinal axis.

[0012] The Gilbert mixer may additionally include:

[0013] A first drain interconnect, wherein the first drain interconnect connects a plurality of drains of the first FET device to a first output terminal; and

[0014] The second drain interconnect connects multiple drains of the second FET device to the second output.

[0015] Each of the plurality of source terminals of the first FET device may be connected to a corresponding source terminal of the plurality of source terminals of the second FET device.

[0016] The Gilbert mixer may further include a first current rail and a second current rail, wherein alternating adjacent source terminals of the first FET device are connected to the respective first current rail and the second current rail.

[0017] Each of the first gate interconnect and the second gate interconnect may include:

[0018] Upper and lower arms, the upper and lower arms being connected to the respective upper and lower voltage rails of the pairs of voltage rails; and

[0019] A bonding component that connects the upper arm to the lower arm and connects the gate interconnect of the first gate interconnect and the second gate interconnect to the corresponding input of the first input and the second input.

[0020] The first gate interconnect may be arranged to at least partially cover the top of the second gate interconnect.

[0021] The first gate interconnect and the second gate interconnect may be symmetrical about an axis orthogonal to the longitudinal axis.

[0022] The upper arm and the lower arm of the first gate interconnect may be arranged to at least partially cover the bonding portion of the second gate interconnect, wherein the bonding portion of the first gate interconnect is arranged to at least partially cover the upper arm and the lower arm of the second gate interconnect.

[0023] Each of the first and second gate interconnects further includes a via, wherein the via connects the engagement portion of the first and second gate interconnects to a corresponding input terminal of the first and second input terminals.

[0024] The Gilbert mixer may additionally include:

[0025] A third FET device is aligned along the longitudinal axis of the first FET device;

[0026] A fourth FET device, the fourth FET device being aligned along the longitudinal axis of the second FET device; and

[0027] A third pair of voltage rails and a fourth pair of voltage rails are arranged parallel to the longitudinal axis, spanning the third FET device and the fourth FET device respectively. Each pair of voltage rails includes an upper rail and a lower rail.

[0028] The first gate interconnect connects the lower rail of the third pair of voltage rails and the upper rail of the fourth pair of voltage rails to the second input terminal, and the second gate interconnect connects the upper rail of the third pair of voltage rails and the lower rail of the fourth pair of voltage rails to the first input terminal.

[0029] The Gilbert mixer may further include a local oscillator generator configured to provide a non-inverting input signal to the first input and an inverting input signal to the second input.

[0030] The Gilbert mixer may additionally include a first current source and a second current source connected to the respective first and second current rails.

[0031] According to a second aspect, a radar transmitter is provided, the radar transmitter including a Gilbert mixer according to a first aspect. The radar transmitter may be part of a radar transceiver.

[0032] These and other aspects of the invention will be apparent from the embodiments described below and will be illustrated with reference to the embodiments described below. Attached Figure Description

[0033] The embodiments are described using the reference drawings as examples only, wherein:

[0034] Figure 1 A schematic diagram of an example transmission line used in a Doppler frequency division multiplexing (DDM) radar system;

[0035] Figure 2 for Figure 1 Example Doppler spectrum of the transmission line;

[0036] Figure 3a and 3b A schematic circuit diagram of a transistor-level implementation of a non-inverting / quadrature-inverting (I / Q) modulator incorporating a mixer based on a dual-balanced Gilbert unit;

[0037] Figure 4 for Figure 3a and 3b Example curves of the LO phase error of a Gilbert mixer as the desired phase varies;

[0038] Figure 5 for Figure 3a and 3b Example graph of LO leakage of a Gilbert mixer as a function of input signal frequency;

[0039] Figure 6 In response to Figure 1 A schematic graph of the instantaneous frequency versus time for a given transmitter of the transmission line;

[0040] Figure 7 for Figure 1 Another example of a transmission line is the Doppler spectrum;

[0041] Figure 8 for Figure 1 Another example of a transmission line is the Doppler spectrum;

[0042] Figure 9 A schematic diagram of an example transmitter used in a quadrature amplitude modulation (QAM) communication system;

[0043] Figure 10 For use Figure 9 A schematic constellation diagram of a communication system;

[0044] Figure 11a A schematic diagram of a multi-finger MOSFET device in the first manufacturing stage;

[0045] Figure 11b for Figure 11a A schematic circuit diagram of the device;

[0046] Figure 12aFor the second manufacturing stage Figure 11a A schematic diagram of a MOSFET device;

[0047] Figure 12b for Figure 12a A schematic circuit diagram of the device;

[0048] Figure 13a For the third manufacturing stage Figure 12a A schematic diagram of a MOSFET device;

[0049] Figure 13b For corresponding Figure 13a A schematic circuit diagram of a MOSFET device;

[0050] Figure 14a A schematic diagram of a pair of MOSFET devices with a shared source connection;

[0051] Figure 14b For corresponding Figure 14a A schematic circuit diagram of the pair of devices;

[0052] Figures 15a-15c and Figures 16a-16c A schematic diagram of the first gate interconnect and the second gate interconnect used in a Gilbert mixer;

[0053] Figure 17 A schematic diagram of an example arrangement of the combined first gate interconnect and second gate interconnect;

[0054] Figure 18 A schematic diagram of an example double-balanced Gilbert mixer with interconnects;

[0055] Figure 19 A schematic diagram of an example dual-balanced Gilbert mixer with four symmetrically arranged multi-finger MOSFET devices;

[0056] Figure 20 For corresponding Figure 19 A schematic circuit diagram of a section of a Gilbert mixer; and

[0057] Figure 21 and Figure 22 Example graph showing the LO phase error of a Gilbert mixer as the desired phase varies.

[0058] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience in the figures, the relative dimensions and scales of the parts have been shown as enlarged or reduced in size. The same reference numerals are generally used to indicate corresponding or similar features in modified and different embodiments. Detailed Implementation

[0059] Figure 1 An example transmitter line 100 for a Doppler frequency division multiplexing (DDM) radar system is shown. Transmitter line 100 includes multiple transmitter outputs TX1-TX4 corresponding to multiple phase rotators 150a-d. Each phase rotator 150a-d is configured to receive an input signal from a common input 151 via frequency multipliers 153a-d and is connected to a common digital controller 152. Each phase rotator 150a-d is configured to provide a phase-rotated output signal to a corresponding amplifier 154a-d, which provides the transmitter outputs TX1-TX4. The digital controller 152 is configured to provide control signals to each phase rotator 150a-d to control the relative phase shift between the multiple phase-rotated output signals. Each transmitter output TX1-TX4 is phase-rotated and frequency-shifted relative to the input signal 151.

[0060] The signal received by the radar system's receiver is the sum of the transmitted signals TX1-TX4 after reflection from one or more objects. The phase difference and frequency offset of the transmitted signals allow the radar system to recover the plurality of transmitted signals.

[0061] The input signal at input terminal 151 can be a sequence of frequency-modulated continuous wave (FMCW) signals. The radar system can perform 2DFFT operation to estimate the distance to the object and the object's relative radial velocity (estimated based on the measured Doppler frequency). This is achieved through... Figure 2 The Doppler spectrum is shown in the image. The Doppler spectrum is used for... Figure 1 A single reflector and a transmitting line 100. Frequency peaks 201a-d each correspond to Doppler frequency measurements generated by the respective transmitted signals TX1-TX4. In the example of the Doppler spectrum, the frequency offsets between the transmitted signals TX1-TX4 are equal.

[0062] The maximum measurable Doppler frequency is inversely proportional to the duration of a single FMCW frequency ramp (including settling time and flight time). To satisfy the sampling theorem, the frequency offset between the transmitted signals TX1-TX4 must be less than the maximum Doppler frequency. This means that phase rotation between multiple transmitted signals TX1-TX4 from multiple transmitters is crucial for allowing the recovery of these multiple transmitted signals from the sum of the received signals received by the radar system.

[0063] Potential circuit-level implementations of the phase rotator 150a-d of the emitter line 100 are shown in Figure 3a and Figure 3b middle. Figure 3a and Figure 3bIt is based on dual-balanced Gilbert unit mixers 301 and 303, and implements a weighted summation of orthogonal RF signals. The input signals vg0I, vg180I and vg0Q, vg180Q are the in-phase and quadrature phase input frequency ramps of the RF signals, while the output signals vd0 and vd180 are phase-rotated output signals. The weighting function can be obtained by simply using... Figure 3a Implemented by the baseband circuit system 302, or through Figure 3b The implementation is achieved through contributions from both the baseband circuit system 304 and the Gilbert mixer 303. In the latter, the Gilbert mixer 303 is segmented in binary or thermocouple code (or a combination of both), where the source nodes are not shorted together, unlike... Figure 3a The Gilbert mixer 301 shown is illustrated.

[0064] Asymmetries or defects in the physical layout of a Gilbert mixer can lead to local oscillator (LO) leakage and subsequent phase errors in the phase-rotated output signals vd0 and vd180. LO leakage can be caused in particular by: i) asymmetries in coupling from the input to the output (e.g., vg to vd); ii) baseband current offset; and iii) unequal MMW (vg and vd) trace lengths of transistors M1, M3 and M2, M4.

[0065] Figure 4 An example graph showing the phase error of a phase rotator experiencing LO leakage is presented. This type of phase error is frequency-dependent, therefore its effect is... Figure 5 The frequency chirp duration is further illustrated in the diagram. To mitigate frequency-dependent LO feedthrough, dynamic compensation will be required, which introduces dynamic effects that will impair chirp linearity.

[0066] Figure 4 The phase error generated by LO leakage, as shown, produces a deterministic pattern associated with the desired phase. Therefore, the repeated use of the same phase leads to the recurrence of the same phase error. This results in spurious frequencies in the Doppler spectrum. Spurious frequencies in the Doppler spectrum may exceed the thermal noise floor and reduce radar sensitivity near strong reflectors.

[0067] Figure 6 The transmission phases of a 4-transmitter DDM system are shown, where the repetitive nature of different phases is indicated by the repetition of phase angles over time. This implies that transmitting the same phase error in a repetitive manner results in clutter in the Doppler dimension.

[0068] Figure 7An example Doppler spectrum of a transmission line 100 is shown with the first transmitted signal TX1 active and the other transmitted signals TX2-TX4 inactive. The first peak 701 corresponds to a Doppler frequency measurement of the transmitted signal TX1 from the transmitter, while the second peak 702 is clutter originating from LO leakage.

[0069] Figure 8 An alternative example Doppler spectrum is shown where the transmitters are irregularly distributed across the Doppler spectrum. In this case, spurious frequency 802 is visible even when all four transmitters are decoded and in operation, resulting in four peaks 801a-d. The spurious frequency is the result of the superposition of LO leakage from all transmitters. This spurious frequency is undesirable because it can be mistaken for a genuine reflection, leading to the detection of ghosted targets. Increasing the detection threshold is not a practical solution because the dynamic range is compromised. In a practical automotive radar example, this could, for example, result in the failure to detect small targets (e.g., children) next to large targets (e.g., trucks) due to the increased threshold.

[0070] Figure 9 An example conventional direct conversion transmitter 900 for use in a quadrature amplitude modulation (QAM) communication system is shown. Figure 10 The corresponding 16QAM constellation diagram is shown. The cross 1001 on constellation diagram 1000 indicates the ideal positions of the in-phase and quadrature components of the output signal. The circle 1002 on the constellation diagram indicates the actual positions of the in-phase and quadrature components of the output signal due to LO leakage.

[0071] The positional difference between cross 1001 and circle 1002 illustrates that LO leakage introduces a compound offset on the constellation diagram. This degrades the error vector magnitude (EVM) of the transmit system 900. EVM is a measure of the distance between the ideal position 1001 (cross) and the actual position 1002 (circle). Assuming that EVM is caused solely by LO leakage and that the constellation diagram is normalized to unit average power, then EVM is given by the following equation:

[0072]

[0073] Where I DC +jQ DC This is the composite offset between positions 1001 and 1002 on the constellation diagram. The EVM directly affects the data processing capacity of the communication system. For example, to transmit a 256QAM signal with a sufficiently low bit error rate, an EVM of at least -29 dB is required.

[0074] This paper presents a solution that reduces ghosting targets in FMCW automotive radar systems and improves EVM and processing power in communication systems by minimizing LO leakage. This is achieved using a symmetrical Gilbert mixer layout, as described in more detail below.

[0075] Typically, devices M1-M4 in the type of Gilbert mixer shown in Figure 3 are each multi-interdigitated FET devices, usually consisting of hundreds of interdigits depending on the LO frequency. The large number of interdigits introduces considerable physical distance between the devices, resulting in unequal propagation lengths. This can lead to LO leakage. As described herein, the proposed solution to this problem involves merging devices M1 with M3 and M2 with M4. This is achieved by providing multiple parallel double-balanced Gilbert mixers with two interdigits and the same propagation length, thereby minimizing LO leakage.

[0076] Figure 11a The diagram shows a MOSFET device 1101 having open gates G1-G12, drains D1-D7, and sources S1-S6 in a first manufacturing stage before the formation of connections to voltage rails and interconnects. Figure 11b This is a schematic circuit diagram corresponding to MOSFET device 1101. Multiple gate interdigitators G1-G12 are arranged between alternating source terminals S1-S6 and drain terminals D1-D7, thereby forming a... Figure 11b The diagram shows a series combination of transistors with adjacent common source and adjacent common drain. The width W and length L of the unit device are... Figure 11a The instructions are in accordance with the central government.

[0077] Figure 12a The MOSFET device 1101 is shown at a second manufacturing stage where voltage rails 103a, 103b are connected to the gate group of the device 1101. Figure 12b This is a schematic circuit diagram of the corresponding device 1101. Voltage rails 103a-b are arranged in parallel across the first device 1101. Alternating adjacent pairs of gate interdigitates G1 and G2, G5 and G6, G9 and G10 are connected to the upper voltage rail 103a, while other alternating pairs of gate interdigitates G3 and G4, G7 and G8, G11 and G12 are connected to the lower voltage rail 103b. The upper voltage rail 103a is connected to the first input vg0. The lower voltage rail 103b is connected to the second input vg180. This connects the first gate G1 and the second gate G2 to the first input vg0, and the third gate G3 and the fourth gate G4 to the second input vg180. Similarly, gates G5, G6 and G9, G10 are connected to the first voltage rail 103a, while gates G7, G8 and G11, G12 are connected to the second voltage rail 103b. At this stage, vias are added to the source S1-S6 and drain D1-D7 for further interconnection.

[0078] Figure 13a The MOSFET device 1101 is shown in the third manufacturing stage. Figure 13b This is a schematic circuit diagram of device 1101 corresponding to this stage. All drains D1-D7 are shorted to drain interconnect 130, which extends along the longitudinal axis L of device 1101 and connects to the output terminal vd0. Source terminals S1-S6 extend outside the device edge for further interconnection. In this example, alternating source terminals are connected to corresponding alternating inputs bpp, bbn. In alternative examples, such as... Figure 3b In this configuration, the source terminals S1-S6 can each be connected to different inputs.

[0079] Figure 14a A Gilbert mixer 1400 is shown, the Gilbert mixer 1400 having Figure 13a A pair of devices 1101, 1101' arranged in parallel of the type shown, wherein each of the sources S1-S6, S1'-S6' is connected together. Figure 14b The schematic circuit diagram corresponds to this arrangement. The drain interconnect 130 of the first device 1101 is connected to the first output vd0, and the drain interconnect 130' of the second device 1101' is connected to the second output vd180.

[0080] The gate interdigitates G1-G12, source terminals S1-S6, and drain terminals D1-D7 of the first device 1101 are laterally aligned with the first longitudinal axis L, orthogonally aligned with the first longitudinal axis L. The corresponding gate interdigitates G1'-G12', source terminals S1'-S6', and drain terminals D1'-D7' of the second device 1101 are laterally aligned with the second longitudinal axis L', orthogonally aligned with the second longitudinal axis L'. The second device 1101' is offset relative to the first device 1101 in a direction orthogonal to the first longitudinal axis L. This alignment of the first and second devices maintains the symmetry of the physical layout of the Gilbert mixer, thereby reducing LO leakage that can be caused by unequal trace lengths between components.

[0081] The plurality of source terminals S1-S6 of the first device 1101 and the plurality of source terminals S1'-S6' of the second device 1101' extend laterally to the longitudinal axes L, L', to connect each source terminal S1-S6 of the first device 1101 to the corresponding source terminal S1'-S6' of the second device 1101'. This in Figure 14bThe circuit diagram shows that sources S1 and S1' are connected at node bpp, and sources S2 and S2' are connected together at node bbn. Connections between each of the plurality of source ends S1-S6 of the first device 1101 and the plurality of source ends S1'-S6' of the second device 1101 can be made via traces extending from vias located on source ends S1-S6 of the first device 1101 to vias located on corresponding source ends S1'-S6' of the second FET device 1101.

[0082] Figures 15a-15c and Figures 16a-16c A first example gate interconnect 111 and a second example gate interconnect 112 for a Gilbert mixer are shown. Figure 15a and Figure 16a In the first gate interconnect 111 and the second gate interconnect 112, each gate interconnect includes an upper arm 114a-b and a lower arm 115a-b. The upper arms 114a-b and the lower arms 115a-b are connectable to the corresponding upper and lower voltage rails of a pair of voltage rails 103a-b and 104a-b, as shown below. Figure 18 As shown in the Gilbert mixer. Figure 15b and 16b The diagram shows engagement components 116 and 117 that connect the upper arms 114a and 115a to the lower arms 114b and 115b and connect the gate interconnects in the first gate interconnect 111 and the second gate interconnect 112 to the corresponding inputs in the first input terminal vg0 and the second input terminal vg180.

[0083] Figure 17 A first gate interconnect 111 and a second gate interconnect 112 are shown, wherein the first gate interconnect 111 is arranged to at least partially cover the top of the second gate interconnect 112. The first gate interconnect 111 and the second gate interconnect 112 are symmetrical about an axis O orthogonal to the longitudinal axes L and L' of the first FET device 1101 and the second FET device 1101'. The upper arm 114a and the lower arm 114b of the first gate interconnect 111 are arranged to at least partially cover the bonding member 117 of the second gate interconnect 112. The bonding member 116 of the first gate interconnect 111 is arranged to at least partially cover the upper arm 115a and the lower arm 115b of the second gate interconnect 112. Other arrangements of the first gate interconnect 111 and the second gate interconnect 112 are also possible. By partially overlapping the first gate interconnect 111 with the second gate interconnect 112 and introducing symmetry between the first gate interconnect 111 and the second gate interconnect 112 (as shown by assembly 113), LO leakage caused by unequal trace lengths between the components of the Gilbert mixer is reduced.

[0084] Each of the first gate interconnect 111 and the second gate interconnect 112 includes vias 118 and 119. The vias 118 and 119 connect the mating portions 116 and 117 of the first gate interconnect 111 and the second gate interconnect 112 to corresponding input terminals in the first input terminal vg0 and the second input terminal vg180. The first input terminal vg0 and the second input terminal vg180 can be connected to the corresponding vias 118 and 119 via a first input rail 121 and a second input rail 122. Alternatively, the first input terminal vg0 and the second input terminal vg180 can be connected to the corresponding vias 118 and 119 via PCB traces extending from each of the vias 118 and 119 and the corresponding first input terminal vg0 and the second input terminal vg180.

[0085] Figure 18 A dual-balanced Gilbert mixer 1800 with the aforementioned gate interconnects is shown. A first gate interconnect 111 connects the upper rail 103a of the first pair of voltage rails 103a-b and the lower rail 103b' of the second pair of voltage rails 103a', 103b' to the first input terminal vg0. A second gate interconnect 112 connects the lower rail 103b of the first pair of voltage rails 103a-b and the upper rail 103a' of the second pair of voltage rails 103a', 103b' to the second input terminal vg180.

[0086] The Gilbert mixer 1800 further includes a first current rail 140 and a second current rail 141 arranged in parallel across a first FET device 1101. Alternating adjacent source terminals S1-S2 of the first FET device 1101 are connected to the corresponding first current rail 140 and second current rail 141. Multiple vias located on the multiple source terminals S1-S2 allow the first current rail 140 and second current rail 141 to connect to the alternating adjacent source terminals S1-S2. A first current source bpp and a second current source bbn are connected to the corresponding first current rail 140 and second current rail 141. In an alternative arrangement, the sources may be connected differently, for example, to a common rail. The first current rail 140 and second current rail 141 allow multiple source terminals S1-S2, S1'-S2' of both the first FET device 1101 and the second FET device 1101' to be connected to the current sources bpp, bbn, while minimizing the difference in PCB trace lengths. This minimization reduces LO leakage caused by the offset of the input current from the first current source bpp and the second current source bpp.

[0087] Figure 18 The cell 1801 indicated in the Gilbert mixer 1800 represents the corresponding Figure 20 The circuit diagram shows a two-digit dual-balanced Gilbert mixer, with transistors M1 and M3 in the first device 1101 and transistors M2 and M4 in the second device 1101'.

[0088] Figure 19 An alternative example, the Gilbert mixer 1900, is shown. The Gilbert mixer 1900 includes... Figure 18 The Gilbert mixer 1800 includes a first FET device 1101 and a second FET device 1101', a first pair of voltage rails 103a-b and a second pair of voltage rails 103a'-b', a first current rail 140 and a second current rail 141, a first gate interconnect 111 and a second gate interconnect 112, and a first drain interconnect 130 and a second drain interconnect 131. The Gilbert mixer 1900 includes a third FET device 1102 aligned along the longitudinal axis L of the first FET device 1101, and a fourth FET device 1102' aligned along the longitudinal axis L' of the second FET device 1101'. The third FET device 1102 is offset relative to the first FET device 1101 along the longitudinal axis L' of the first FET device 1101. The fourth FET device 1102' is offset relative to the second FET device 1101' along the longitudinal axis L' of the second FET device 1101'.

[0089] The Gilbert mixer 1900 further includes a third pair of voltage rails 105a-b and a fourth pair of voltage rails 105a'-b' arranged in parallel across the third FET device 1102 and the fourth FET device 1102', respectively. A first gate interconnect 111 connects the lower rail 105b of the third pair of voltage rails 105a-b and the upper rail 105a' of the fourth pair of voltage rails 105a'-b' to a first input terminal vg0. A second gate interconnect 112 connects the upper rail 105a of the third pair of voltage rails 105a-b and the lower rail 105b' of the fourth pair of voltage rails 105a'-b' to a second input terminal vg180.

[0090] A first drain interconnect 130 extends along the longitudinal axis L of the first device 1101 and the third device 1102 to connect a plurality of drains of the third FET device 1102 to a first output terminal vd0. A second drain interconnect 131 extends along the longitudinal axis L' of the second device 1101' and the fourth device 1102' to connect a plurality of drains of the fourth FET device 1102' to a second output terminal vd180. A first current rail 140 and a second current rail 141 extend across the third FET device 1102, wherein alternating adjacent source terminals of the third FET device 1102 are connected to corresponding first current rail 140 and second current rail 141.

[0091] The symmetry and overlap of the first gate interconnect 111 and the second gate interconnect 112 maintain equal signal routing lengths for each of the multiple voltage rail pairs 103a-b, 103a'-b', 105a-b, 105a'-b' to the corresponding inputs of the first input vg0 and the second input vg180.

[0092] Figure 20 This is a schematic circuit diagram of the Gilbert Mixer 2000. Figure 19 Section 1801 of the Gilbert mixer 1900 contains two combined Gilbert mixers, each corresponding to a Gilbert mixer circuit 2000. The first FET device 1101 contains transistors M1 and M3 of the mixer circuit 2000.

[0093] Figure 21 This is a graph showing the phase error versus desired phase for a conventional Gilbert mixer. Due to the sinusoidal shape of the curve, the phase error can be considered to be largely dominated by LO leakage. Figure 22 The corresponding plot of the phase error of the Gilbert mixer with the combined layout as described above is shown. The phase error is now lower and is not dominated by a periodic sinusoidal signal, indicating that the combined FET device has the effect of reducing LO leakage due to the improved layout symmetry.

[0094] By reading this disclosure, those skilled in the art will understand other changes and modifications. Such changes and modifications may involve equivalent and other features already known in the field of Gilbert mixers and may be used in place of or in addition to the features already described herein.

[0095] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalized form thereof explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention as claimed in any of the present claims or whether it alleviates the same technical problem as any or all of the technical problems alleviated by this invention.

[0096] Features described in the context of multiple embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, multiple features described in the context of a single embodiment may also be provided separately or in any suitable sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0097] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude a plurality, a single processor or other unit can perform the functions of several components recited in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A Gilbert mixer, characterized in that, include: A first multi-finger field-effect transistor (FET) device and a second multi-finger field-effect transistor (FET) device, each FET device including a plurality of gate interdigitates arranged along a longitudinal axis between alternating source and drain terminals, wherein the plurality of gate interdigitates of each FET device extend transversely to the longitudinal axis of the FET device; A first pair of voltage rails and a second pair of voltage rails are arranged parallel to the longitudinal axis, spanning the first FET device and the second FET device respectively. Each pair of voltage rails includes an upper rail and a lower rail. A first gate interconnect, wherein the first gate interconnect connects the upper rail of the first pair of voltage rails and the lower rail of the second pair of voltage rails to a first input terminal; and A second gate interconnect connects the lower rail of the first pair of voltage rails and the upper rail of the second pair of voltage rails to a second input terminal. The alternating adjacent pairs of the gate interdigitates of the first FET device are connected to the corresponding upper and lower rails of the first pair of voltage rails, and the alternating adjacent pairs of the gate interdigitates of the second FET device are connected to the corresponding upper and lower rails of the second pair of voltage rails.

2. The Gilbert mixer according to claim 1, characterized in that, The plurality of gate interdigitates of each FET device are orthogonally aligned with the longitudinal axis.

3. The Gilbert mixer according to claim 1, characterized in that, In addition, including: A first drain interconnect connects a plurality of drains of the first FET device to a first output terminal; as well as The second drain interconnect connects multiple drains of the second FET device to the second output.

4. The Gilbert mixer according to claim 1, characterized in that, Each of the plurality of source terminals of the first FET device is connected to a corresponding source terminal of the plurality of source terminals of the second FET device.

5. The Gilbert mixer according to claim 1, characterized in that, Additionally, it includes a first current rail and a second current rail, wherein alternating adjacent source terminals of the first FET device are connected to the respective first current rail and the second current rail.

6. The Gilbert mixer according to claim 1, characterized in that, Each of the first gate interconnect and the second gate interconnect includes: Upper and lower arms, the upper and lower arms being connected to the respective upper and lower voltage rails of the pairs of voltage rails; and A bonding component that connects the upper arm to the lower arm and connects the gate interconnect of the first gate interconnect and the second gate interconnect to the corresponding input of the first input and the second input.

7. The Gilbert mixer according to claim 6, characterized in that, The first gate interconnect is arranged to at least partially cover the top of the second gate interconnect.

8. The Gilbert mixer according to claim 6, characterized in that, In addition, including: A third FET device is aligned along the longitudinal axis of the first FET device; A fourth FET device, which is aligned along the longitudinal axis of the second FET device; as well as A third pair of voltage rails and a fourth pair of voltage rails are arranged parallel to the longitudinal axis, spanning the third FET device and the fourth FET device respectively. Each pair of voltage rails includes an upper rail and a lower rail. The first gate interconnect connects the lower rail of the third pair of voltage rails and the upper rail of the fourth pair of voltage rails to the first input terminal, and the second gate interconnect connects the upper rail of the third pair of voltage rails and the lower rail of the fourth pair of voltage rails to the second input terminal.

9. A radar transmitter, characterized in that, Includes a Gilbert mixer, the Gilbert mixer comprising: A first multi-finger field-effect transistor (FET) device and a second multi-finger field-effect transistor (FET) device, each FET device including a plurality of gate interdigitates arranged along a longitudinal axis between alternating source and drain terminals, wherein the plurality of gate interdigitates of each FET device extend transversely to the longitudinal axis of the FET device; A first pair of voltage rails and a second pair of voltage rails are arranged parallel to the longitudinal axis, spanning the first FET device and the second FET device respectively. Each pair of voltage rails includes an upper rail and a lower rail. A first gate interconnect, wherein the first gate interconnect connects the upper rail of the first pair of voltage rails and the lower rail of the second pair of voltage rails to a first input terminal; and A second gate interconnect connects the lower rail of the first pair of voltage rails and the upper rail of the second pair of voltage rails to a second input terminal. The alternating adjacent pairs of the gate interdigitates of the first FET device are connected to the corresponding upper and lower rails of the first pair of voltage rails, and the alternating adjacent pairs of the gate interdigitates of the second FET device are connected to the corresponding upper and lower rails of the second pair of voltage rails.

10. The radar transmitter according to claim 9, characterized in that, In addition, including: A first drain interconnect connects a plurality of drains of the first FET device to a first output terminal; as well as The second drain interconnect connects multiple drains of the second FET device to the second output.

Images