Data processing method, system, apparatus, device, storage medium and program product

Abstract

This application discloses a data processing method, system, apparatus, device, storage medium, and program product. The method includes: receiving a flow table configuration management packet sent by a control plane, the flow table configuration management packet including flow table configuration mode and flow table address information; generating a first read / write signal based on the flow table configuration mode and flow table address information; monitoring the signal status of the first read / write signal, and when the signal status is idle, the first read / write signal is used to instruct a second functional module to generate a second read / write signal, the second read / write signal is used by a third functional module to perform read / write fusion processing based on the first read / write signal and / or the second read / write signal to obtain first read data and / or second read data; performing data read processing from the third functional module based on the first read / write signal to obtain first read data; generating a management response packet based on the first read data and sending the management response packet to the control plane, the management response packet being used by the control plane to perform flow table aging judgment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network communication and cloud computing, and particularly relates to a data processing method, system, device, equipment, computer storage medium and program product. BACKGROUND

[0002] In a data center network architecture, data processing and forwarding efficiency is crucial to the overall system performance. With the continuous growth of network traffic, how to efficiently manage flow table information and optimize hardware resource utilization becomes a key problem to improve the offloading capability of a data processing unit (DPU). As a core structure for realizing accurate packet matching and forwarding, a flow table will generate a large number of historical or low-heat entries due to frequent updates during operation, affecting the effective utilization of hardware resources.

[0003] In the prior art, flow table aging operation and maintenance is usually generated by a system on chip (SOC) through a line-by-line configuration method to generate a flow table management packet, and a field programmable gate array (FPGA) analyzes and reports statistical information of the corresponding flow table, and then the SOC analyzes the hit counter value and time information to determine whether to perform aging operation. Although this method can control the accumulation of invalid flow tables to a certain extent, it has problems such as read-write conflict, response delay and the like in a high-concurrency scenario, which limits the real-time performance and accuracy of flow table maintenance. SUMMARY

[0004] To solve the above technical problems, the embodiments of the present application provide a data processing method, device, equipment, computer readable storage medium and computer program product.

[0005] In a first aspect, the data processing method provided by the embodiments of the present application is applied to a first function module, and includes:

[0006] receiving a flow table configuration management packet sent by a control plane, the flow table configuration management packet including a flow table configuration mode and flow table address information;

[0007] generating a first read-write signal based on the flow table configuration mode and the flow table address information;

[0008] monitoring a signal state of the first read-write signal, when the signal state is an idle state, the first read-write signal is used to instruct a second function module to generate a second read-write signal, and the second read-write signal is used for a third function module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data;

[0009] read data from the third functional module based on the first read-write signal, to obtain the first read data;

[0010] generate a management back packet based on the first read data, and send the management back packet to the control plane, wherein the management back packet is used for the control plane to make a flow table aging decision.

[0011] In a second aspect, the data processing method provided by the embodiments of the present application is applied to a second functional module, and includes:

[0012] receive flow table hit information sent by a data plane, and perform asynchronous cache processing on the flow table hit information to obtain a hit event sequence;

[0013] generate a second read-write signal based on the hit event sequence when the first functional module monitors that the signal state of the first read-write signal is an idle state, wherein the second read-write signal is used for the third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data;

[0014] read data from the third functional module based on the second read-write signal, to obtain the second read data;

[0015] perform flow table compression processing based on the second read data and the hit event sequence, to obtain single-bit decision information, and send the single-bit decision information to the third functional module, wherein the single-bit decision information is used for the control plane to make a flow table aging decision.

[0016] In a third aspect, the data processing method provided by the embodiments of the present application is applied to a third functional module, and includes:

[0017] receive a first read-write signal and / or a second read-write signal;

[0018] perform read-write fusion processing on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data;

[0019] store the first read data and / or the second read data in parallel, wherein the first read data is used for a first functional module to generate a management back packet, and the second read data is used for a second functional module to perform flow table compression processing to obtain single-bit decision information.

[0020] In a fourth aspect, the data processing apparatus provided by the embodiments of the present application is applied to a first functional module, and includes:

[0021] a receiving unit, configured to receive a flow table configuration management packet sent by a control plane, wherein the flow table configuration management packet includes a flow table configuration mode and flow table address information;

[0022] a processing unit, configured to generate a first read-write signal based on the flow table configuration mode and the flow table address information; monitor a signal state of the first read-write signal; when the signal state is an idle state, the first read-write signal is used to instruct a second functional module to generate a second read-write signal, and the second read-write signal is used for a third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data; perform data reading processing from the third functional module based on the first read-write signal to obtain the first read data; and generate a management back packet based on the first read data;

[0023] a sending unit, configured to send the management back packet to the control plane; wherein the management back packet is used for the control plane to perform flow table aging decision.

[0024] In a fifth aspect, a data processing apparatus is provided, which is applied to a second functional module and includes:

[0025] a receiving unit, configured to receive flow table hit information generated by a data plane;

[0026] a processing unit, configured to perform asynchronous cache processing on the flow table hit information to obtain a hit event sequence; when a signal state of a first read-write signal monitored by a first functional module is an idle state, generate a second read-write signal based on the hit event sequence, and the second read-write signal is used for a third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data; perform data reading processing from the third functional module based on the second read-write signal to obtain the second read data; and perform flow table compression processing based on the second read data and the hit event sequence to obtain single-bit decision information;

[0027] a sending unit, configured to send the single-bit decision information to the third functional module; wherein the single-bit decision information is used for a control plane to perform flow table aging decision.

[0028] In a sixth aspect, a data processing apparatus is provided, which is applied to a third functional module and includes:

[0029] a receiving unit, configured to receive a first read-write signal and / or a second read-write signal;

[0030] a processing unit, configured to perform read-write fusion processing on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data;

[0031] a storage unit configured to store the first read data and / or the second read data in parallel; wherein the first read data is used by a first functional module to generate a management back packet, and the second read data is used by a second functional module to perform flow table compression processing to obtain single-bit decision information.

[0032] In a seventh aspect, a processing device is provided, which includes a processor and a memory. The memory is configured to store a computer program. The processor is configured to invoke and run the computer program stored in the memory to execute any of the data processing methods.

[0033] In an eighth aspect, a computer readable storage medium is provided, which is configured to store a computer program. The computer program causes a computer to execute any of the data processing methods.

[0034] In a ninth aspect, a computer program product is provided, which includes computer program instructions. The computer program instructions cause a computer to execute any of the data processing methods.

[0035] In the technical solution of the embodiments of the present application, the first functional module receives a flow table configuration management packet sent by a control plane. The flow table configuration management packet includes a flow table configuration mode and flow table address information. Based on the flow table configuration mode and the flow table address information, a first read-write signal is generated. The signal state of the first read-write signal is monitored. When the signal state is an idle state, the first read-write signal is used to instruct a second functional module to generate a second read-write signal. The second read-write signal is used for a third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data. Data read processing is performed from the third functional module based on the first read-write signal to obtain the first read data. A management back packet is generated based on the first read data and sent to the control plane. The management back packet is used for the control plane to make a flow table aging decision. In this way, the problems of low processing efficiency, large resource consumption, and memory access conflicts caused by the SOC obtaining flow table statistical information one by one in the prior art are solved. The efficiency, low overhead, and low latency of flow table aging operation are achieved, and the performance of the DPU in a high-concurrency network load scenario is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a structural schematic diagram of a data processing system architecture of the embodiments of the present application;

[0037] Figure 2 is a principle schematic diagram of a data processing system of the embodiments of the present application;

[0038] Figure 3 is a flowchart of a data processing method provided by the embodiments of the present application Figure 1 ;

[0039] Figure 4 is a flow diagram of a data processing method provided by an embodiment of the present application Figure 2 ;

[0040] Figure 5 is a timing diagram of a first read-write signal provided by an embodiment of the present application

[0041] Figure 6 is a flow diagram of a data processing method provided by an embodiment of the present application Figure 3 ;

[0042] Figure 7 is a timing diagram of a second read-write signal provided by an embodiment of the present application

[0043] Figure 8 is a flow diagram of a data processing method provided by an embodiment of the present application Figure 4 ;

[0044] Figure 9 is a schematic diagram of a parallel storage principle provided by an embodiment of the present application

[0045] Figure 10 is a schematic diagram of an architecture of a data processing method provided by an embodiment of the present application

[0046] Figure 11 is a schematic diagram of a structure of a data processing apparatus provided by an embodiment of the present application Figure 1 ;

[0047] Figure 12 is a schematic diagram of a structure of a data processing apparatus provided by an embodiment of the present application Figure 2 ;

[0048] Figure 13 is a schematic diagram of a structure of a data processing apparatus provided by an embodiment of the present application Figure 3 ;

[0049] Figure 14 is a schematic diagram of a structure of a data processing apparatus provided by an embodiment of the present application DETAILED DESCRIPTION

[0050] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application. All other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0051] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0052] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent the specific order of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0053] Unless otherwise defined, all technical and scientific terms used in the embodiments of the application are the same as those commonly understood by those skilled in the art. The terms used in the embodiments of the application are only for the purpose of describing the embodiments of the application and are not intended to limit the application.

[0054] Before the embodiments of the application are further described in detail, the terms and phrases involved in the embodiments of the application are explained, and the terms and phrases involved in the embodiments of the application are applicable to the following explanations.

[0055] 1) Flow table aging: The aging of the DPU flow table is an important part of the flow table state operation and maintenance, which is used for the statistical management of low-heat flow tables by the SOC, and the flow tables unloaded to the hardware FPGA are deleted in combination with the set time.

[0056] 2) Flow table aging operation and maintenance: refers to the process of deciding whether to unload it from the hardware by periodically evaluating the active state of the flow table in the DPU architecture. The core purpose is to release the resources occupied by invalid flow tables, and to improve hardware utilization and network forwarding efficiency.

[0057] 3) Flow table configuration management package: a structured data package sent by the control plane to the FPGA, used to instruct the FPGA to perform corresponding read-write operations to obtain or update flow table state information.

[0058] 4) Read-write signal: a set of logic signals used to control the read and write operations of the internal memory of the FPGA, such as block random access memory (BRAM), including read signals and write signals. These signals are controlled by timing to ensure that read and write operations are not performed simultaneously on the same address at the same time, avoiding data conflicts.

[0059] 5) Flow table hit information: refers to the situation that the flow table recorded in the data plane is actually hit by network traffic, which is used to determine whether the flow table is active.

[0060] 6) Control plane: a logical layer responsible for network policy configuration and management, used to send configuration commands to the FPGA and receive feedback information from the FPGA to complete the aging decision of the flow table.

[0061] 7) Data plane: a logical layer responsible for forwarding and matching processing of data packets, usually undertaken by FPGA, used to detect flow table hits in real time and feed relevant information back to the control plane.

[0062] In related technologies, DPU as a general processor of data center infrastructure, takes the hardware offloading way to further release the CPU resources. In network load scenarios, FPGA is limited by hardware resources and accumulates and stores a large number of historical flow tables, resulting in that the current latest flow table cannot be offloaded, so that the network data can only be forwarded to SOC for processing, thereby affecting the forwarding efficiency of DPU network traffic. The aging of DPU flow table as an important part of flow table state operation and maintenance is used for the statistical management of low-temperature flow table by SOC, and the flow table offloaded and stored to hardware FPGA is deleted in combination with the set time. The existing DPU flow table aging operation and maintenance mechanism is as follows: SOC adopts the way of configuring flow table management package by piece, FPGA receives and analyzes the flow table information in the management package, queries and reports the 64-byte statistical information of the flow table stored in DDR, SOC extracts the 8-byte flow table hit counter value after obtaining the statistical information, and combines the counter value of the flow table in the last time and the agreed time to comprehensively determine whether the flow table is aged. This method effectively avoids the accumulation of a large number of invalid flow table information on the hardware side, reduces the storage pressure of the hardware end, and further improves the offloading performance of DPU for network load.

[0063] However, in the prior art, under the current high concurrency and large traffic network load scenario, the following disadvantages exist in the flow table aging operation and maintenance: first, the SOC obtains the flow table statistical information piece by piece, so that the FPGA repeatedly parses and constructs the management packet data, occupies the FPGA processing bandwidth and causes a large amount of unnecessary time consumption, reduces the efficiency of aging operation and maintenance, and further affects the overall offloading performance of the DPU; second, after the SOC obtains the 64-byte flow table statistical information, the hit counter value needs to be extracted, stored and determined, and each flow table occupies 8 bytes of space, when a large number of flow tables are aged and maintained within a set time, valuable CPU resources and computing power are consumed; third, when the FPGA obtains the flow table statistical information according to the configuration management packet, it needs to frequently access the double data rate synchronous dynamic random access memory (DDR), which causes conflicts with other access to the DDR, and additional logic and resources are needed for arbitration, which increases the complexity of using the DDR and also reduces the efficiency of using the DDR.

[0064] To solve the above problems, the embodiments of the present application provide a data processing method, device, equipment, computer readable storage medium and computer program product, which can realize efficient, low-cost and low-delay flow table aging operation and maintenance, and significantly improve the performance of DPU in a high concurrency network load scenario.

[0065] The following describes an exemplary application of the data processing device of the embodiments of the present application. The data processing device provided by the embodiments of the present application can be implemented as a terminal or a server. In one implementation mode, the data processing device provided by the embodiments of the present application can be implemented as various types of terminals such as a notebook computer, a tablet computer, a desktop computer and a mobile device; in another implementation mode, the data processing device provided by the embodiments of the present application can also be implemented as a server, wherein the server can be a physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content distribution networks (CDNs), and basic cloud computing services such as big data and artificial intelligence platforms. The terminal and the server can be directly or indirectly connected through wired or wireless communication, which is not limited in the embodiments of the present application. In the following, an exemplary application of the data processing device implemented as a server will be described.

[0066] Referring to Figure 1 , Figure 1 is a structural schematic diagram of a data processing system architecture provided by the embodiments of the present application, for example,Figure 1 The present application relates to a server 100, a terminal device 200 and a network 300. The terminal device 200 connects the server 100 through the network 300, wherein the network 300 can be a wide area network or a local area network, or a combination of the two.

[0067] In some embodiments, please refer to Figure 1 In the data processing, the terminal device 200 sends the initiated data processing request to the server 100. The server 100 responds to the data processing request and receives the flow table configuration management package sent by the control plane, which includes the flow table configuration mode and the flow table address information. Based on the flow table configuration mode and the flow table address information, a first read-write signal is generated; the signal state of the first read-write signal is monitored, and when the signal state is an idle state, the first read-write signal is used to instruct the second functional module to generate a second read-write signal, and the second read-write signal is used for the third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data; based on the first read-write signal, data reading processing is performed from the third functional module to obtain the first read data; based on the first read data, a management return package is generated and sent to the control plane, wherein the management return package is used for the control plane to make a flow table aging decision. After the server 100 executes the data processing method provided in the present application, the management return package is sent to the terminal device 200 through the network 300, so as to realize the response to the terminal data processing request.

[0068] Please refer to Figure 2 , Figure 2 is a principle schematic diagram of a data processing system provided by the present application, which is applied to an FPGA, and the FPGA includes a first functional module, a second functional module and a third functional module; wherein the first functional module is responsible for the interaction with the flow table configuration management package, including receiving the flow table configuration management package and parsing to form a first read-write signal, and then combining the first read data to form a management return package and returning to the control plane; the second functional module is responsible for the integration and compression of the flow table information, so as to reduce the decision bit width and save CPU computing power and storage resources, including under the cache control of the first read-write signal, forming a second read-write signal according to the network flow table hit information, and then combining the second read data to form compressed single-bit decision information; the third functional module is responsible for the storage of the flow table compression decision information, including integrating the first read-write signal and / or the second read-write signal generated by the first functional module and the second functional module, and performing parallel BRAM storage read-write according to the integrated read-write address decision.

[0069] Please refer to Figure 3 , Figure 3 is a flow schematic diagram of a data processing method provided by the present application, which is applied to the first functional module, and the following will be specifically explained.

[0070] Step 301, receiving a flow table configuration management package sent by a control plane, the flow table configuration management package including a flow table configuration mode and flow table address information.

[0071] In the embodiment of the application, the first function module can also be called a management package analysis and uploading function module. The flow table configuration management package is a data structure sent by the control plane to the first function module of the FPGA, used to instruct the FPGA to perform corresponding read and write operations. The flow table configuration mode can be a single flow table configuration or a batch flow table configuration. When it is a single flow table configuration, each flow table is processed individually; when it is a batch flow table configuration, multiple flow tables can be covered by one operation, thereby improving processing efficiency. The flow table address information includes a base address and a length field, used to determine the location range of the flow table to be accessed in the memory.

[0072] In some embodiments, the control plane includes an open source distributed multi-layer virtual switch (OpenvSwitch, OVS). The OVS is an open source virtual switch supporting OpenFlow, which defines how the network should behave, such as the structure of the flow table, matching rules, actions (forwarding, modification, discarding, etc.), and tunnel encapsulation. For example, the first function module receives a flow table configuration management package sent by the OVS, i.e., an OVS function link management package, which includes header information, a configuration mode field, a flow table address information field, and a check code, etc., to ensure the reliability and integrity of data transmission. The first function module analyzes the flow table configuration management package, extracts the flow table configuration mode and the flow table address information, and uses them as the basis for generating the first read and write signal. When using a batch configuration mechanism, the FPGA does not need to repeatedly analyze the flow table configuration management package for each flow table, thereby saving processing time and bandwidth resources.

[0073] Step 302, generating a first read and write signal based on the flow table configuration mode and the flow table address information.

[0074] In the embodiment of the application, the first read and write signal is a set of logic signals used to control the read and write operations of the internal memory (such as BRAM) of the FPGA, and the first read and write signal includes a first read signal and a first write signal. The first read and write signal ensures that read and write operations cannot be performed simultaneously on the same address at the same time through timing control, thereby avoiding data conflicts. For example, in the read operation, the read signal triggers the memory to return the content of the specified address; in the write operation, the write signal triggers the memory to write data into the specified address.

[0075] In some embodiments, the generation of the first read-write signal depends on the flow table configuration mode and the flow table address information. When the batch configuration mode is used, the read address is generated according to the length information and the base address in the flow table configuration management package, and the address of up to 8192 flow tables can be supported, thereby avoiding the consumption of FPGA processing time and bandwidth caused by repeated analysis during batch flow table query. In order to prevent read-write conflict, the rising edge of the read address jump is used as the read signal in the first read-write signal, and the read signal is delayed by 1 clock cycle to be used as the write signal in the first read-write signal, thereby eliminating the situation of simultaneous read-write of an address. Therefore, not only the accuracy of read-write operation is improved, but also the stability of the overall system is improved.

[0076] For example, the first function module generates the first read-write signal according to the parsed flow table configuration mode and the flow table address information, and transmits the first read-write signal to the third function module. The first read-write signal is used to indicate the read-write operation of the memory of the third function module. By transmitting the first read-write signal to the parallel BRAM read-write function module in this way, the frequent access to the DDR can be effectively reduced, the memory access delay can be reduced, and the memory usage efficiency can be optimized.

[0077] In some embodiments, the flow table configuration mode includes a batch flow table configuration mode; and the flow table address information includes base address and length information, see Figure 4 , Figure 3 As shown in step 302, steps 401 to 404 can be implemented, which will be described in detail as follows:

[0078] In step 401, when the flow table configuration mode is the batch flow table configuration mode, the base address and the length information are operated and processed to obtain a batch read address signal, which is a continuous read address sequence.

[0079] Here, the batch flow table configuration mode refers to a mode in which multiple flow table entries are configured uniformly in one management package operation. Under the batch flow table configuration mode, a series of continuous read addresses are calculated according to the base address and the length information in the flow table address information, which are used to obtain the state information of multiple flow tables at a time. For example, in the FPGA, the base address can be used as the starting point to generate continuous addresses in an incremental manner through an adder or a counter, thereby forming a read address sequence, so as to avoid the waste of resources and time consumption caused by parsing the management package one by one. By using the address generation mechanism under the batch flow table configuration mode, the parsing burden of the FPGA in processing the flow table aging query can be significantly reduced, thereby improving the overall processing efficiency, reducing the bandwidth occupation, and enabling the system to respond to the aging operation and maintenance request of the SOC more quickly.

[0080] In step 402, the batch read address signal is subjected to jump edge detection processing to obtain a first read signal.

[0081] Here, the jump edge detection processing refers to detecting the moment of change of the address signal, and generally triggers the read operation when the address signal jumps from low to high (rising edge). This processing ensures that reading is only performed when the address changes, thereby avoiding invalid or repeated reading.

[0082] Step 403, delay processing the first read signal based on a first preset threshold to obtain a first write signal.

[0083] Here, the delay processing is to ensure that the read operation is completed before the write operation is performed, thereby avoiding read-write conflict. Specifically, the system will generate a write signal after a certain number of clock cycles (i.e. the first preset threshold) after the read signal is triggered. For example, if it takes 3 clock cycles to complete reading data, the write signal will be activated at the 4th clock cycle to ensure that the read result is ready, avoiding overwriting the read data that has not been completed during the write process. By setting reasonable delay parameters, data conflicts can be effectively avoided when reading and writing to the same address. This setting can improve the stability of the system and ensure data consistency.

[0084] Step 404, generating a first read-write signal based on the first read signal and the first write signal.

[0085] Referring to Figure 5 , Figure 5 The timing diagram of the first read-write signal provided by the embodiment of the present application. The first read-write signal is generated by integrating the batch selection signal and the batch read address signal, taking the read address jump rising edge as the first read signal, and delaying the first read signal by 1 clk as the first write signal. Here, the first read-write signal is a comprehensive signal used to coordinate read and write operations. Specifically, the system will determine whether reading, writing, or both are allowed based on the combination of the read signal and the write signal. For example, when the read signal is high and the write signal is low, only reading is performed; when the read signal is low and the write signal is high, only writing is performed; and when both the read signal and the write signal are high, it may indicate an idle state or preparation for the next operation phase. By generating a comprehensive read-write signal, the read-write process of flow table data can be accurately controlled at the hardware level, which can improve the accuracy and efficiency of data processing, and also make it easier for subsequent modules to identify and process signals.

[0086] In some other embodiments, the flow table configuration mode includes a per-flow table configuration mode; and the flow table address information includes flow table address information. In the per-flow table configuration mode, the flow table address information is mapped to obtain a per-flow read address signal, which is a discrete read address.

[0087] Step 303, monitoring the signal state of the first read-write signal, when the signal state is an idle state, the first read-write signal is used to instruct the second function module to generate a second read-write signal, and the second read-write signal is used for the third function module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data.

[0088] In the embodiments of the present application, the second function module is a flow table information compression function module, and the main task of the flow table information compression function module is to cache and compress the flow table hit information to reduce the decision bit width and save the computing power and storage resources of the control plane. The second read-write signal is a signal generated by the flow table information compression function module to control the memory read-write of the third function module, which is used to read the flow table hit information and perform compression operation.

[0089] In some embodiments, when the first read-write signal is in an idle state, it indicates that there is no read-write request from the control plane at this time, so the second function module can initiate its own read-write operation to obtain the flow table hit information and generate single-bit decision information. In order to avoid interfering with the first read-write operation initiated by the control plane, the second function module will initiate its own read-write request after the first read-write operation ends, so as to ensure that the first read-write operation initiated by the control plane and the read-write operation initiated by the second function module do not conflict with each other.

[0090] In some embodiments, read-write fusion processing refers to merging multiple signals into a unified operation sequence through a logical fusion mechanism (such as an OR operation) in the case of coexistence of multiple read-write signals, so as to realize efficient data reading and writing process. For example, when the first read-write signal and the second read-write signal exist at the same time, the system will preferentially process the first read-write signal, and then process the second read-write signal after the first read-write signal is completed, so as to ensure the orderliness and consistency of data processing.

[0091] For example, when the first read-write signal is in an idle state, the second function module generates a second read-write signal according to the flow table hit information, and transmits the second read-write signal to the third function module for read-write fusion processing. After the third function module integrates the first read-write signal and the second read-write signal, it executes the read-write operation according to the priority order, and the system ensures the correctness and efficiency of data processing through the above operation.

[0092] Step 304, performing data reading processing from the third function module based on the first read-write signal to obtain first read data.

[0093] In the embodiments of the present application, the third function module is a parallel BRAM read-write function module, and the main task of the parallel BRAM read-write function module is to integrate two-level read-write signals generated by the first function module and the second function module, and to determine the parallel BRAM read-write according to the integrated read-write address. The first function module obtains read data from the parallel BRAM read-write function module.

[0094] In some embodiments, Figure 3 After the step 304 shown, it further includes: performing zeroing processing on the first read data to obtain zeroed read data; and sending the zeroed read data to a third function module, the third function module being configured to store the zeroed read data.

[0095] Here, the zeroing processing refers to an operation of forcibly setting the data in the storage unit corresponding to the address corresponding to the zeroed read data to all zero values after the read-write operation is completed. The purpose of the zeroing processing is to avoid the influence of residual historical flow table information on subsequent data reading or writing operations. Through the zeroing processing, the old data traces can be effectively cleared, and it is ensured that each reading and writing operation is based on the latest state, thereby improving the system stability and data accuracy. In this way, by performing the zeroing processing, the historical data can be prevented from interfering with the current flow table aging operation process, and the execution of the zeroing processing can improve the reliability of data reading and writing, and can enhance the running efficiency of the DPU in a high-concurrency scenario.

[0096] Here, the third function module refers to a hardware module that undertakes a storage task in the FPGA architecture, and in specific implementation, usually a BRAM (Block RAM) or similar structure is used to implement it. The main role of the third function module is to serve as a cache or temporary storage space for storing flow table related information after compression or processing, for access and use by the SOC or other control modules. Compared with the traditional DDR storage method, the third function module has lower access delay and higher parallelism, which helps to reduce the response time of the overall system.

[0097] In the embodiments of the present application, the system sends the zeroed read data to the third function module for storage, so that the system can reduce the dependence on external storage such as DDR, and further the system can optimize the use efficiency of storage resources, and finally realize the improvement of the overall performance of the flow table aging operation.

[0098] Here, there is a close cooperative relationship between the zeroing processing and the third function module. The data generated after the zeroing processing needs to be transmitted to the third function module in time and safely for storage, so as to ensure the consistency and availability of the data. At the same time, the design of the third function module also supports fast writing and reading capability to adapt to the high-frequency data update demand.

[0099] In the embodiments of the present application, by performing zeroing processing on the first read data and storing the zeroed data in the third functional module, interference caused by residual historical data can be prevented, and frequent access to external memory can be reduced, thereby improving system stability and operation efficiency, and further significantly improving the offloading capability of the DPU in a large-scale network load scenario.

[0100] In step 305, a management back packet is generated based on the first read data, and the management back packet is sent to the control plane. The management back packet is used for the control plane to make a flow table aging decision.

[0101] In some embodiments, the management back packet is a data packet used to feed back flow table state information to the control plane. The content of the management back packet includes flow table statistical information, hit situation, decision result, etc. After receiving the management back packet, the control plane can make an aging decision of the flow table based on the content of the management back packet, and decide whether to unload the low-heat flow table from the hardware.

[0102] In some embodiments, the generation process of the management back packet is as follows: first, the first functional module reads data from the parallel BRAM of the third functional module according to the first read signal, then encapsulates the read data into a management back packet, and finally sends the management back packet to the control plane. The format of the management back packet usually includes header information, data content and check code, etc. to ensure the reliability of data transmission.

[0103] In some embodiments, the control plane includes an SOC, which is used to make a flow table aging decision according to the information in the management back packet, so as to decide whether to delete invalid flow tables and release hardware resources. This way significantly improves the efficiency of flow table aging operation and maintenance, reduces the computational burden of the control plane, and optimizes the overall performance of the DPU.

[0104] In summary, the flow table aging operation and maintenance method provided in the embodiments of the present application realizes high efficiency, low overhead and low latency in flow table aging operation and maintenance by constructing a batch flow table configuration management mechanism, a flow table information compression and single-bit decision method, and a parallel BRAM storage strategy. Specifically, the first functional module receives a flow table configuration management packet sent by the control plane and generates a first read-write signal; the second functional module generates a second read-write signal when the first read-write signal is in an idle state, which is used for read-write fusion processing by the third functional module to obtain first read data and / or second read data; and the third functional module reads data according to the first read-write signal and generates a management back packet to return to the control plane for flow table aging decision. Through the above steps, the flow table aging operation and maintenance method provided in the embodiments of the present application effectively solves the problems of low processing efficiency, large resource consumption and DDR access conflict caused by the control plane acquiring flow table statistical information one by one in the prior art, and significantly improves the performance of the DPU in a high-concurrency network load scenario.

[0105] Referring to Figure 6 , Figure 6 is a flowchart of a data processing method provided by an embodiment of the present application, and is applied to a second function module, which will be described in detail below.

[0106] Step 601: receiving flow table hit information sent by a data plane, performing asynchronous cache processing on the flow table hit information, and obtaining a hit event sequence.

[0107] In the embodiment of the present application, the second function module can also be called a flow table information compression function module. The flow table hit information refers to the state record of each flow table matched and hit when the FPGA processes network data, and usually includes fields such as a timestamp, a flow table address, and a hit frequency. The flow table hit information reflects whether the current flow table is active or low-heat, and serves as an important basis for subsequent judgment of aging.

[0108] In some embodiments, the asynchronous cache processing is a data storage mechanism that can temporarily cache the flow table hit information in a buffer queue without affecting the main data processing flow, thereby avoiding performance bottlenecks caused by frequent access to storage resources. The system can effectively prevent the loss of flow table hit information and ensure the continuity of subsequent processing logic by using the asynchronous cache processing mechanism.

[0109] For example, the second function module can use a first-in first-out buffer (FIFO) for asynchronous caching to obtain the hit event sequence. The hit event sequence is an ordered set composed of multiple flow table hit information, arranged in chronological order, for subsequent flow table aging judgment and data compression processing. The generation of the hit event sequence can provide batched flow table state information, thereby reducing the computational overhead caused by querying the flow table state one by one.

[0110] Step 602: when the signal state of the first read-write signal monitored by the first function module is an idle state, generating a second read-write signal based on the hit event sequence, and the second read-write signal is used for read-write fusion processing by the third function module based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data.

[0111] In some embodiments, the first function module can be a management packet analysis and uploading function module. The first function module is responsible for receiving and analyzing configuration management packets from the OVS, and generating the first read-write signal according to the analysis result. The first read-write signal is used to indicate the read or write operation of the internal memory (such as BRAM) of the FPGA. The active state indicates that the current first read-write signal is being activated, meaning that the first read-write signal is performing a data access operation.

[0112] In some embodiments, the first read-write signal is a read-write control signal generated by the management packet parsing and uploading module, and the main role of the first read-write signal is to coordinate the data interaction between the OVS and the FPGA. When the first read-write signal is in an idle state, it indicates that there is currently no high-priority read-write request, and at this time the system can safely perform a low-priority flow table information processing task.

[0113] In some embodiments, the second read-write signal is a read-write control signal dynamically generated by the second functional module according to the hit event sequence, and the second read-write signal is used to instruct the third functional module, i.e., the parallel BRAM read-write module, to perform data fusion read-write operations. Read-write fusion processing refers to the merging and processing of read-write requests from different sources to improve system efficiency and avoid resource conflicts.

[0114] In some embodiments, there is a cooperative relationship between the first read-write signal and the second read-write signal. Specifically, the second functional module generates the second read-write signal when it detects that the first read-write signal is in an idle state, or when there is no first read-write signal. In this way, the stability of the system and the efficiency of the operation are ensured.

[0115] For example, when it is detected that the first read-write signal is in an idle state, the second functional module generates the second read-write signal based on the hit event sequence. Another example is that when it is detected that the system does not have a first read-write signal, the second functional module generates the second read-write signal based on the hit event sequence. In this way, the collection and compression of flow table information are completed without interfering with normal business processing, thereby improving the overall response efficiency.

[0116] In some embodiments, when the first functional module monitors the signal state of the first read-write signal to be active, the second functional module performs delay processing on the flow table hit information.

[0117] Here, when the first functional module detects that the first read-write signal is in an active state, in order to prevent conflicts or interference caused by accessing the flow table hit information during the process in which the first functional module detects that the first read-write signal is in an active state, the second functional module performs delay processing on the cached flow table hit information. That is, the second functional module delays generating the second read-write signal until the first read-write signal is idle before performing the generating operation, thereby ensuring that the currently active first read-write signal can be completed smoothly, and avoiding problems such as data overwrite and address conflict.

[0118] For example, the implementation of the delay processing can be achieved by setting a FIFO cache mechanism for temporarily storing the flow table hit information to be processed. The FIFO cache mechanism then processes the information in the order of precedence. By using this FIFO cache mechanism, the consistency and integrity of the processed data can be ensured without interrupting the read and write operations in the current system. The delay processing has a logical dependence on the first read-write signal. Only when the first read-write signal is not active, the flow table hit information can be normally read and updated. Therefore, introducing the delay processing mechanism during the active period of the first read-write signal can effectively avoid data errors or performance degradation problems caused by concurrent access.

[0119] In some embodiments, Figure 6 In step 602, the second read-write signal is generated based on the hit event sequence, including: performing mapping processing on the flow table address of the hit event sequence to obtain a second read signal, the second read signal including a unit address for addressing and a bit index for positioning; performing delay processing on the second read signal based on a second preset threshold to obtain a second write signal; and generating the second read-write signal based on the second read signal and the second write signal.

[0120] Here, the mapping processing refers to converting the flow table address in the hit event sequence into the address format of a directly accessible storage unit (such as BRAM) and appending a bit index to determine the specific data bit corresponding to the flow table. For example, assuming that each flow table information occupies 32-bit storage space, the low 5 bits of the flow table address can be intercepted as the unit address, and the high bit part of the flow table address can be used to calculate the specific bit index, so as to accurately locate the bit flow table state information. In this way, by introducing the bit index, accurate reading of the flow table state information is realized, avoiding the waste of resources caused by reading the entire flow table record at a time in the traditional method. The bit mapping mode provides a basis for subsequent compression decision operations, which helps to reduce the data processing burden of the SOC end.

[0121] Here, the delay processing refers to time delaying the second read signal according to the set second preset threshold, to ensure that the write operation is performed only after the read operation is completed, preventing read-write conflict at the same address. The specific time of the delay can be adjusted according to the timing characteristics of the internal logic path of the FPGA, and is usually set to several clock cycles to ensure the timing safety between read and write operations. For example, the read signal is delayed by 3clk as the write signal to avoid reading and writing the same address. In this way, by delaying the second read signal, the problem of data overwrite or loss caused by synchronous triggering of read and write signals is effectively avoided, and the stability and reliability of the system are improved. In addition, by implementing reasonable scheduling of different read-write requests, the overall processing efficiency can be improved.

[0122] Here, refer to Figure 7 , Figure 7 indicates a timing diagram of the second read-write signal provided by the embodiments of the present application. Here, the second read-write signal is a composite control signal composed of a second read signal and a second write signal, used to uniformly coordinate the execution of read and write operations. Specifically, when the second read signal is valid, it indicates that the flow table state information needs to be read from the specified address; when the second write signal is valid, it indicates that the updated state information needs to be written back to the same address. The combination of the two signals determines whether the current operation is reading, writing, or alternating between the two. By generating the second read-write signal based on the second read signal and the second write signal, the system can efficiently manage the flow table state without increasing additional hardware resources. In particular, in the batch flow table query and update scenario, the system can significantly improve the concurrency and response speed of data processing when the second read-write signal is reasonably designed.

[0123] Step 603, performing data reading processing from the third functional module based on the second read-write signal to obtain second read data.

[0124] In the embodiments of the present application, the data reading processing is a read operation initiated by the second functional module according to the second read-write signal to obtain the corresponding flow table statistical information from the third functional module. Since the third functional module adopts a BRAM parallel storage structure, the system can read the information of multiple flow tables at a time, reducing the dependence on DDR and improving the reading speed. The second read data is the original data before flow table compression and can be used by the second functional module to generate compressed decision information.

[0125] Step 604, performing flow table compression processing based on the second read data and the hit event sequence to obtain single-bit decision information, and sending the single-bit decision information to the third functional module; wherein the single-bit decision information is used to control the plane to make flow table aging decision.

[0126] In the embodiments of the present application, the flow table compression processing is to combine the second read data and the hit event sequence to generate a decision result represented by only one bit using a bit compression algorithm. For example, if a flow table is not hit within a specified time, the corresponding decision result is 0; if the flow table is hit, the corresponding decision result is 1.

[0127] In some embodiments, after the control plane receives the single-bit decision information, it can determine whether the corresponding flow table needs to be aged according to a preset rule. Since the single-bit decision information is only one bit, the SOC does not need to additionally analyze large-width data, and the SOC can make a decision, greatly speeding up the aging operation and maintenance. The above flow table compression processing method greatly reduces the amount of data transmitted and processed, reducing the computational burden of the SOC. The single-bit decision information, as the final aging determination basis, can be directly used by the SOC without the need to extract complex 64-byte statistical data. In this way, by implementing the flow table compression processing operation, the system can save bandwidth and storage resources, while significantly improving the processing efficiency of the SOC and reducing the consumption of CPU resources.

[0128] In some embodiments, the second read data includes a history state bitmap of the hit event sequence.

[0129] Here, the history state bitmap refers to a set of binary information used to record the history state of the flow table hit event. The history state bitmap indicates whether the corresponding flow table has ever had a hit event through each bit. When a flow table hit event occurs, the system updates the value of the corresponding position in the history state bitmap. For example, if a flow table has had a hit once in the past period of time, the bit value of the corresponding position in the history state bitmap is 1; if no hit has occurred, it is 0. The length of the history state bitmap corresponds to the number of flow tables, which can be dynamically expanded or trimmed to adapt to different scales of network load scenarios.

[0130] The history state bitmap and the flow table hit event have a close data association. Whenever a new flow table hit event occurs, the system automatically maps the flow table hit event to the corresponding bit and updates the state value of the history state bitmap. The history state bitmap and the logical operation processing mechanism enable the system to quickly determine the aging state of the flow table through single-bit decision information without extracting the counter value one by one, thereby significantly reducing the CPU resource occupation and computational complexity.

[0131] In actual applications, the FPGA can generate a corresponding read address according to the configuration information after receiving the management packet, and read the history state bitmap from the parallel BRAM of the third functional module. Since the BRAM has high-speed access capability and supports parallel read and write operations, it can effectively reduce the dependence on DDR and improve the response speed and efficiency of the overall system.

[0132] In some embodiments, the flow table compression processing is performed based on the second read data and the hit event sequence to obtain single-bit decision information, including: performing logical operation processing on the history state bitmap and the hit event based on a bit index to obtain single-bit decision information, wherein the single-bit decision information is a first value or a second value; the first value represents that there is no hit event of the flow table, and the second value represents that there is a hit event of the flow table.

[0133] Here, the bit index refers to an index identifier used to locate the position of a specific flow table in the history state bitmap. The bit index is obtained by intercepting the low part of the flow table address, ensuring that each flow table has a unique bit position in the bitmap. For example, in a compression unit of 32 flow tables, the bit index can be represented by 5-bit binary coding, ranging from 0 to 31.

[0134] Here, the logical operation processing refers to performing Boolean operation (such as AND, OR, XOR, etc.) on the corresponding bit value in the history state bitmap and the current flow table hit event information to generate the final single-bit decision information. For example, if a bit in the history state bitmap is 1, indicating that a specific flow table has had a hit event in the past period of time, and the current flow table hit event information is also 1, then the logical operation result is still 1; otherwise, if the bit value in the history state bitmap and the current flow table hit event information are both 0, then the result is 0. By implementing logical operation processing, the data processing flow can be simplified, and the storage and transmission of redundant information can be avoided.

[0135] Here, the first value and the second value are respectively used to represent two states of whether the flow table has had a hit event. For example, the first value is 0, indicating that a specific flow table has not had any hit event in a specified period of time, belonging to a low-heat flow table; the second value is 1, indicating that a specific flow table has had at least one hit event in a specified period of time, belonging to a high-heat flow table. The first value and the second value can clearly express the state of the flow table through simple binary form, and using this binary form facilitates subsequent aging decision and statistical analysis of SOC.

[0136] In this way, by introducing the history state bitmap and the logical operation processing mechanism, the embodiments provided by the present application can significantly improve the data processing efficiency of the system in the flow table aging operation and maintenance process, reduce the computing power consumption of the SOC used by the system, and optimize the utilization of hardware resources. In addition, since the single-bit decision information is used, the SOC only needs to count a small number of bits to complete the aging determination of the flow table, further improving the response speed and running stability of the overall system.

[0137] To sum up, in the embodiment of the present application, the system introduces a historical state bitmap and a logical operation processing mechanism, and combines a bit index and a compression mode of single-bit decision information, to realize optimization of a data processing flow. This optimization mode can significantly reduce the calculation burden of a system chip (SOC) and improve the efficiency of flow table aging operation and maintenance, so that the flow table resource management and maintenance in a data processing unit (DPU) is more efficient.

[0138] Referring to Figure 8 , Figure 8 is a flowchart of a data processing method provided by the embodiment of the present application, applied to a third functional module, which is described in detail below.

[0139] Step 801, receiving a first read-write signal and / or a second read-write signal.

[0140] In the embodiment of the present application, the third functional module can also be called a parallel BRAM read-write functional module, which is used to be responsible for the BRAM storage of single-bit decision information, i.e., flow table compression decision information, to avoid frequent access of additional DDR; the third functional module is also used to integrate the first read-write signal and / or the second read-write signal generated by the first functional module and the second functional module, and to perform parallel BRAM read-write according to the read-write address determination of the integrated read-write signal.

[0141] For example, when the system only has the first read-write signal, i.e., only has the first read-write demand, the first functional module generates the first read-write signal; the third functional module performs read-write fusion processing, and since there is no read-write demand of the second read-write signal, the fusion result of the third functional module only has the first read-write enable, and the first read data is obtained. Then, the first functional module reads the data according to the read-write fusion result of the third functional module, and the read data is directly returned to the first functional module to form a return packet.

[0142] In some embodiments, the third functional module receives the zeroed read data sent by the first functional module. The zeroed read data is obtained by the first functional module after zeroing processing of the first read data.

[0143] For example, when the system only has the second read-write signal, i.e., only has the second read-write demand, the second functional module buffers the flow table hit information input by the data plane, and generates the second read-write signal.

[0144] The third functional module performs read-write fusion processing. Since there is no first read-write signal, the result of fusion is only the second read-write enable, and the second read data is obtained. Then, the third functional module performs read data according to the result of read-write fusion. The read data is directly returned to the second functional module as original data, and then the externally input flow table hit information is compressed and rewritten in bit, and the rewritten data is written into the third functional module again as update data.

[0145] In some embodiments, the third functional module receives single-bit decision information sent by the second functional module, and the single-bit decision information is obtained by the second functional module based on the second read data and the compressed hit event sequence.

[0146] For example, if the first read-write signal and the second read-write signal exist at the same time, that is, the first read-write demand and the second read-write demand exist at the same time, the third functional module performs read-write fusion processing. Since the first read-write signal is in an active state and the second read-write signal is forced not to be generated, the result of read-write fusion is only the first read-write enable. The third functional module performs read data according to the result of read-write fusion. The read data is directly returned to the first functional module to encapsulate the management return packet, and the read data after zero return is stored in the third functional module. When the first read-write signal response ends, the second functional module generates the second read-write signal in the order of the flow table hit event sequence. The third functional module performs read-write fusion processing. Since there is no first read-write enable, the result of fusion is only the second read-write enable. The third functional module performs read data according to the result of read-write fusion. The read data is directly returned to the flow table information compression module as original data, and then the externally input flow table hit information is compressed and rewritten in bit. The rewritten data is written into the third functional module again as update data.

[0147] Step 802, read-write fusion processing is performed on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data.

[0148] In some embodiments, read-write fusion processing refers to integrating read-write signals generated from different functional modules (such as the first functional module and the second functional module), uniformly scheduling access to parallel BRAM resources, and avoiding conflicts or resource contention caused by concurrent operation of multiple functional modules. Through read-write fusion processing, the ordered execution of multiple read-write requests can be realized, and the access efficiency of the FPGA internal memory and the overall system performance can be improved. The specific way of read-write fusion processing includes address merging, timing synchronization, priority control, etc. For example, in the case where the first read-write signal and the second read-write signal exist, the system will first process the first read-write signal and then process the second read-write signal according to the set priority rules, so as to guarantee the response speed and data consistency related to critical tasks.

[0149] The first read data is data read from the BRAM, which is used by the first functional module to generate a management back packet returned to the OVS. The management back packet usually contains flow table state information, hit counter values, etc., for the SOC to further determine whether to perform the aging operation. The second read data is data read from the BRAM, which is used by the second functional module to perform flow table information compression processing to generate single-bit decision information. The single-bit decision information indicates whether a certain flow table has network data hits within a set time. If it is 0, it means no hit, and if it is 1, it means a hit, which facilitates the SOC to quickly determine whether to perform the aging operation, thereby reducing CPU computing power consumption.

[0150] Step 803, storing the first read data and / or the second read data in parallel; wherein the first read data is used by the first functional module to generate a management back packet, and the second read data is used by the second functional module to perform flow table compression processing to obtain single-bit decision information.

[0151] Here, parallel storage refers to using multiple storage units to simultaneously perform data read and write operations, thereby improving the efficiency of data processing. Compared with the traditional serial storage method, parallel storage can significantly reduce the delay of flow table information acquisition, reduce the usage frequency of the DDR memory, and reduce the access pressure of the DDR memory.

[0152] Referring to Figure 9 , Figure 9 The principle diagram of the parallel storage mechanism provided by the embodiments of the present application is shown, which indicates that multiple BRAM storage units are used to simultaneously perform data read and write operations, flow table information is stored in groups of 32, and each group of data is mapped to different BRAM spaces, ensuring that each read and write operation is only performed on a specific storage space without traversing all storage units. The parallel storage mechanism not only improves the efficiency of data access, but also optimizes the timing characteristics of the system, making the entire flow table aging operation process more efficient and stable. When there are multiple read and write requests, the parallel storage module integrates and allocates these requests, and ensures that each request can be completed in the shortest time. For example, when the first functional module initiates a read request, the parallel storage module will respond immediately and return the read result to the first functional module for packaging a management back packet. At the same time, the second functional module may also initiate a read request to obtain original data for flow table information compression processing. Since the parallel storage module supports multiple concurrent accesses and can reasonably allocate resources, the parallel storage module can effectively avoid resource conflicts and improve the overall system throughput.

[0153] The third functional module needs to perform OR operation on the first read-write signal and the second read-write signal when integrating, so as to change two signals into one, that is, to perform fusion operation, and to fuse the read signal and the address signal. In addition, the first read-write signal and the second read-write signal each have an independent read data valid mark signal, and only the read data is sent back to the respective module to realize the corresponding subsequent function. Since a large number of BRAMs need to be instantiated, the third functional module determines the read data fusion according to the integrated high 3-bit address. The data is stored in parallel in 8 storage spaces 1 to 8 composed of BRAMs to ensure the timing optimization of engineering synthesis. In the parallel storage mode, 32 flow table information can be obtained each time, and each read-write operation is finally performed on a storage space determined by mapping, without traversing all storage spaces. The read result of the parallel storage space is fused to complete a complete parallel read-write operation. According to the size of the stored data, the number of parallel storage paths can be flexibly configured to enhance the versatility of the third functional module.

[0154] The method of the embodiment of the application effectively integrates read-write requests from different functional modules through the synergistic effect of read-write fusion processing and parallel storage mechanism, avoids FPGA internal resource contention, and improves flow table information access efficiency. The method of the embodiment of the application reduces the consumption of FPGA processing time and bandwidth, thereby speeding up the aging operation and maintenance speed of the flow table, and further significantly improving the offloading performance and overall processing efficiency of the DPU in a network high-concurrency scenario.

[0155] Next, the principle of the data processing system provided by the embodiment of the application will be described in combination with the data flow. Figure 2 The principle of the data processing system provided by the embodiment of the application will be described in combination with the data flow.

[0156] Embodiment one: if there is only the first read-write demand in the current system, that is, the read-write demand with high priority, Figure 2 The data flow is as follows:

[0157] 1) The first functional module generates the first read-write signal; 2) read-write fusion is performed in the third functional module, and since there is no second read-write signal, the fusion result here is only the first read-write enable; 3) the third functional module reads data according to the read-write fusion result, and the read data is directly returned to the management packet analysis upload module for encapsulation to form a return packet. Another data flow is to zero the read address data and re-write it into the third functional module.

[0158] Embodiment two: if there is only the second read-write demand in the current system, that is, the read-write demand with low priority, Figure 2 The data flow is as follows:

[0159] 1) the second functional module buffers the externally input flow table hit information and generates a second read-write signal; 2) read-write fusion is performed in the third functional module, and since there is no first read-write signal, the result of fusion here only has a second read-write enable; 3) the third functional module reads data according to the result of read-write fusion, the read data is directly returned to the second functional module as original data, and then the externally input flow table hit information is compressed and rewritten in bit, the rewritten data is written into the third functional module again as update data.

[0160] In the third embodiment, if the first read-write requirement and the second read-write requirement exist simultaneously in the current system, Figure 2 The data flow is as follows:

[0161] 1) the first functional module generates a first read-write signal; 2) the first read-write signal is connected to the second functional module and the third functional module simultaneously; 3) the first read-write signal controls the second functional module to force the externally input flow table hit information to be delayed, the delay refers to that the generation of the second read-write signal is performed after the first read-write signal ends; 4) at the same time, the first read-write signal performs read-write fusion in the third functional module, and since the second read-write signal is forced not to be generated in step 3), the result of fusion here only has a first read-write enable; 5) the third functional module reads data according to the result of read-write fusion, the read data is directly returned to the first functional module to be encapsulated to form a management back packet, and another data flow is to write the data of the read address into the third functional module again after being zeroed; 6) after the response of the first read-write signal ends, the second functional module buffers the flow table information in the order of priority, and generates a second read-write signal; 7) read-write fusion is performed in the third functional module, and since there is no first read-write, the result of fusion here only has a second read-write enable; 8) the third functional module reads data according to the result of read-write fusion, the read data is directly returned to the flow table information compression module as original data, and then the externally input flow table hit information is compressed and rewritten in bit, the rewritten data is written into the BRAM again as update data.

[0162] Figure 10Figure 1 is a schematic diagram of a data processing architecture provided by an embodiment of the present application, as shown, compared with the existing DPU flow table aging operation and maintenance mechanism, which configures a management packet by means of SOC and adopts a piece-by-piece configuration mode, and compared with the architecture in which the FPGA is interacted with piece by piece, the DDR is accessed, the large bit width decision is made to obtain a management return packet for aging decision operation and maintenance, the application creates a flow table information acquisition link for batch interaction, improves the hardware FPGA storage architecture, and compresses the original flow table information to form single-bit decision data, thereby accelerating the aging operation and maintenance of the flow table in a high-concurrency and large-traffic scenario, avoiding DDR, and improving the offloading performance of the DPU. Compared with the prior art, the following advantages are possessed: supporting batch flow table software and hardware management and operation and maintenance, taking 1K flow tables as an example, the efficiency of the FPGA in acquiring flow table information is improved by more than 1,000 times; according to the compressed flow table decision information, the data bit width of the aging judgment processing is reduced by 99.8%; and the hardware capture information delay is saved by 90% by using the BRAM storage in the FPGA.

[0163] Figure 11 Figure 2 is a structural composition schematic diagram of a data processing device provided by an embodiment of the present application Figure 1 , which is applied to a first functional module, as shown in Figure 11 , the data processing device 1100 comprises:

[0164] a receiving unit 1101, configured to receive a flow table configuration management packet sent by a control plane, the flow table configuration management packet comprising a flow table configuration mode and flow table address information.

[0165] a processing unit 1102, configured to generate a first read-write signal based on the flow table configuration mode and the flow table address information; monitor a signal state of the first read-write signal, when the signal state is an idle state, the first read-write signal is used to instruct a second functional module to generate a second read-write signal, the second read-write signal is used for a third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data; perform data read processing from the third functional module based on the first read-write signal, to obtain the first read data; and generate a management return packet based on the first read data.

[0166] a sending unit 1103, configured to send the management return packet to the control plane; wherein the management return packet is used for the control plane to perform flow table aging decision.

[0167] In some embodiments, the flow table configuration mode comprises a batch flow table configuration mode; and the flow table address information comprises base address and length information.

[0168] In some embodiments, when the flow table configuration mode is the batch flow table configuration mode, the processing unit 1102 is further configured to perform operation processing on the base address and the length information to obtain a batch read address signal, the batch read address signal being a continuous read address sequence; perform a transition edge detection processing on the batch read address signal to obtain a first read signal; perform a delay processing on the first read signal based on a first preset threshold to obtain a first write signal; and generate the first read-write signal based on the first read signal and the first write signal.

[0169] In some embodiments, the processing unit 1102 is further configured to perform a zeroing processing on the first read data to obtain zeroed read data; and send the zeroed read data to the third functional module, the third functional module being configured to store the zeroed read data.

[0170] Those skilled in the art should understand that, Figure 11 The implementation functions of each unit in the data processing apparatus shown can be understood with reference to the related description of the foregoing method. Figure 11 The functions of each unit in the data processing apparatus shown can be implemented by a program running on a processor, or by a specific logic circuit.

[0171] Figure 12 is a structural composition of the data processing apparatus provided by the embodiments of the present application Figure 2 applied to a second functional module, as Figure 12 shown, the data processing apparatus 1200 comprises:

[0172] A receiving unit 1201 configured to receive flow table hit information generated by a data plane.

[0173] A processing unit 1202 configured to perform asynchronous caching processing on the flow table hit information to obtain a hit event sequence; when a signal state of a first read-write signal monitored by a first functional module is an idle state, generate a second read-write signal based on the hit event sequence, the second read-write signal being used for read-write fusion processing by a third functional module based on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data; perform data reading processing from the third functional module based on the second read-write signal to obtain the second read data; and perform flow table compression processing based on the second read data and the hit event sequence to obtain single-bit decision information.

[0174] A sending unit 1203 configured to send the single-bit decision information to the third functional module; wherein the single-bit decision information is used to control a plane to make a flow table aging decision.

[0175] In some embodiments, when the signal state of the first read-write signal monitored by the first function module is active, the processing unit 1202 is further configured to perform delay processing on the flow table hit information.

[0176] In some embodiments, the processing unit 1202 is further configured to perform mapping processing on the flow table address of the hit event sequence to obtain a second read signal, the second read signal comprising a unit address for addressing and a bit index for positioning; perform delay processing on the second read signal based on a second preset threshold to obtain a second write signal; and generate the second read-write signal based on the second read signal and the second write signal.

[0177] In some embodiments, the second read data comprises a history state bitmap of the hit event sequence; and the processing unit 1202 is further configured to perform logical operation processing on the history state bitmap and the hit event based on the bit index to obtain the single-bit decision information, wherein the single-bit decision information is a first value or a second value; the first value represents no flow table hit event, and the second value represents that there is a flow table hit event.

[0178] Those skilled in the art should understand that, Figure 12 The implementation functions of each unit in the data processing apparatus shown can be understood with reference to the related description of the foregoing method. Figure 12 The functions of each unit in the data processing apparatus shown can be implemented by a program running on a processor, or by a specific logic circuit.

[0179] Figure 13 is a structural composition of the data processing apparatus provided by the embodiments of the present application Figure 3 and is applied to a third function module, as Figure 13 The data processing apparatus 1300 shown comprises:

[0180] A receiving unit 1301 is configured to receive a first read-write signal and / or a second read-write signal.

[0181] A processing unit 1302 is configured to perform read-write fusion processing on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data.

[0182] A storage unit 1303 is configured to store the first read data and / or the second read data in parallel; wherein the first read data is used by a first function module to generate a management back packet, and the second read data is used by a second function module to perform flow table compression processing to obtain single-bit decision information.

[0183] Those skilled in the art should understand that, Figure 13The implementation functions of the units in the data processing apparatus shown can be understood with reference to the related descriptions of the foregoing methods. Figure 13 The functions of the units in the data processing apparatus shown can be implemented by a program running on a processor, or by a specific logic circuit.

[0184] Figure 14 is a schematic structural diagram of a processing device 1400 provided by an embodiment of the present application. The processing device can be a terminal device or a server, Figure 14 The processing device 1400 shown includes a processor 1410, which can call and run a computer program from a memory to implement the method in the embodiments of the present application.

[0185] Optionally, as Figure 14 The processing device 1400 shown can also include a memory 1420. The processor 1410 can call and run a computer program from the memory 1420 to implement the method in the embodiments of the present application.

[0186] The memory 1420 can be a separate device independent of the processor 1410, or can be integrated in the processor 1410.

[0187] Optionally, as Figure 14 The processing device 1400 shown can also include a transceiver 1430, which the processor 1410 can control to communicate with other devices, specifically, to send information or data to other devices, or receive information or data sent by other devices.

[0188] The transceiver 1430 can include a transmitter and a receiver. The transceiver 1430 can further include an antenna, and the number of antennas can be one or more.

[0189] It should be understood that the processor of the embodiments of the present application can be an integrated circuit chip with a processing capability of signals. In the implementation process, each step of the method embodiments described above can be completed by the integrated logic circuit of hardware in the processor or the instructions in the form of software. The processor described above can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a ready programmable gate array (FPGA) or other programmable logic devices, a discrete gate or transistor logic device, a discrete hardware component. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a random memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0190] It is to be understood that the memory in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a Random Access Memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as a Static RAM (SRAM), a Dynamic RAM (DRAM), a Synchronous DRAM (SDRAM), a Double Data Rate SDRAM (DDR SDRAM), an Enhanced SDRAM (ESDRAM), a Synchlink DRAM (SLDRAM), and a Direct Rambus RAM (DR RAM). It should be noted that the memory of the system and method described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0191] It should be understood that the above-mentioned memory is exemplary but not limiting, for example, the memory in the embodiments of the present application can also be a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synch link DRAM (SLDRAM), and a direct memory bus random access memory (Direct Rambus RAM, DR RAM), etc. That is, the memory in the embodiments of the present application is intended to include, but not limited to, these and any other suitable types of memory.

[0192] The embodiment of the present application further provides a computer readable storage medium for storing the computer program.

[0193] Optionally, the computer readable storage medium can be applied to the network device in the embodiment of the present application, and the computer program makes the computer execute the corresponding process realized by the network device in the various methods of the embodiment of the present application, which will not be repeated here for the sake of brevity.

[0194] Optionally, the computer readable storage medium can be applied to the mobile terminal / terminal device in the embodiment of the present application, and the computer program makes the computer execute the corresponding process realized by the mobile terminal / terminal device in the various methods of the embodiment of the present application, which will not be repeated here for the sake of brevity.

[0195] The embodiment of the present application further provides a computer program product comprising computer program instructions.

[0196] Optionally, the computer program product can be applied to the network device in the embodiment of the present application, and the computer program instructions make the computer execute the corresponding process realized by the network device in the various methods of the embodiment of the present application, which will not be repeated here for the sake of brevity.

[0197] Optionally, the computer program product can be applied to the mobile terminal / terminal device in the embodiment of the present application, and the computer program instructions make the computer execute the corresponding process realized by the mobile terminal / terminal device in the various methods of the embodiment of the present application, which will not be repeated here for the sake of brevity.

[0198] The embodiment of the present application further provides a computer program.

[0199] Optionally, the computer program can be applied to the network device in the embodiment of the present application, and when the computer program runs on the computer, makes the computer execute the corresponding process realized by the network device in the various methods of the embodiment of the present application, which will not be repeated here for the sake of brevity.

[0200] Optionally, the computer program can be applied to the mobile terminal / terminal device in the embodiment of the present application, and when the computer program runs on the computer, makes the computer execute the corresponding process realized by the mobile terminal / terminal device in the various methods of the embodiment of the present application, which will not be repeated here for the sake of brevity.

[0201] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0202] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0203] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0204] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0205] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0206] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0207] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A data processing method, characterized by, The method applied to the first function module comprises: Receiving a flow table configuration management packet sent by a control plane, the flow table configuration management packet comprising a flow table configuration mode and flow table address information; Based on the flow table configuration mode and the flow table address information, a first read-write signal is generated; Monitoring a signal state of the first read-write signal, when the signal state is an idle state, the first read-write signal is used to instruct a second function module to generate a second read-write signal, the second read-write signal is used for a third function module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data; Based on the first read-write signal, data reading processing is performed from the third function module to obtain the first read data; Based on the first read data, a management return packet is generated and sent to the control plane, wherein the management return packet is used for the control plane to make a flow table aging decision.

2. The method of claim 1, wherein, The flow table configuration mode comprises a batch flow table configuration mode; the flow table address information comprises base address and length information; based on the flow table configuration mode and the flow table address information, the first read-write signal is generated, comprising: When the flow table configuration mode is the batch flow table configuration mode, the base address and the length information are operated and processed to obtain a batch read address signal, the batch read address signal being a continuous read address sequence; The batch read address signal is subjected to a transition edge detection process to obtain a first read signal; The first read signal is subjected to a delay processing based on a first preset threshold to obtain a first write signal; Based on the first read signal and the first write signal, the first read-write signal is generated.

3. The method of claim 1, wherein, After the data reading processing from the third function module based on the first read-write signal to obtain the first read data, the method further comprises: The first read data is subjected to a zeroing processing to obtain zeroed read data; The zeroed read data is sent to the third function module, and the third function module is used to store the zeroed read data.

4. A data processing method, characterized by, The method applied to the second function module comprises: Receiving flow table hit information sent by a data plane, and performing asynchronous cache processing on the flow table hit information to obtain a hit event sequence; When a signal state of a first read-write signal monitored by a first function module is an idle state, a second read-write signal is generated based on the hit event sequence, the second read-write signal being used for a third function module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data; Based on the second read-write signal, data reading processing is performed from the third function module to obtain the second read data; Based on the second read data and the hit event sequence, flow table compression processing is performed to obtain single-bit decision information, and the single-bit decision information is sent to the third function module; wherein the single-bit decision information is used for a control plane to make a flow table aging decision.

5. The method of claim 4, wherein, The method further comprises: When the first function module monitors that the signal state of the first read-write signal is an active state, the flow table hit information is processed with a delay.

6. The method of claim 4, wherein, The second read-write signal is generated based on the hit event sequence, including: The flow table address of the hit event sequence is mapped to obtain a second read signal, and the second read signal includes a unit address for addressing and a bit index for positioning; The second read signal is processed with a delay based on a second preset threshold to obtain a second write signal; The second read-write signal is generated based on the second read signal and the second write signal.

7. The method of claim 4, wherein, The second read data includes a history state bitmap of the hit event sequence; The flow table compression processing is performed based on the second read data and the hit event sequence to obtain single-bit decision information, including: The history state bitmap and the hit event are logically operated based on the bit index to obtain the single-bit decision information, where the single-bit decision information is a first value or a second value; the first value represents no hit event of the flow table, and the second value represents that there is a hit event of the flow table.

8. A data processing method, characterized by, The method applied to the third function module, including: receiving a first read-write signal and / or a second read-write signal; wherein the first read-write signal is generated by a first function module based on a flow table configuration mode and flow table address information, and the second read-write signal is generated by a second function module based on a hit event sequence when the signal state of the first read-write signal is an idle state; read-write fusion processing is performed on the first read-write signal and / or the second read-write signal to obtain first read data and / or second read data; the first read data and / or the second read data are stored in parallel; wherein the first read data is used by the first function module to generate a management packet, and the second read data is used by the second function module to perform flow table compression processing to obtain single-bit decision information; wherein the parallel storage includes storing the first read data and / or the second read data in different parallel storage spaces respectively, so that each read-write operation is only performed on the corresponding storage space.

9. A data processing system, characterized by The FPGA includes a first function module, a second function module and a third function module; wherein, the first function module is configured to execute the method in any one of claims 1 to 3; the second function module is configured to execute the method in any one of claims 4 to 7; the third function module is configured to execute the method in claim 8.

10. A data processing apparatus, characterized by The device applied to the first function module, including: a receiving unit configured to receive a flow table configuration management packet sent by a control plane, the flow table configuration management packet including a flow table configuration mode and flow table address information; The processing unit is configured to generate a first read-write signal based on the flow table configuration mode and the flow table address information; monitor a signal state of the first read-write signal; when the signal state is an idle state, the first read-write signal is used to instruct a second functional module to generate a second read-write signal; the second read-write signal is used for a third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data; perform data reading processing from the third functional module based on the first read-write signal, to obtain the first read data; and generate a management back packet based on the first read data. The sending unit is configured to send the management back packet to the control plane; and the management back packet is used for the control plane to perform flow table aging decision.

11. A data processing apparatus, characterized by The device applied to the second functional module comprises: The receiving unit is configured to receive flow table hit information sent by a data plane. The processing unit is configured to perform asynchronous cache processing on the flow table hit information, to obtain a hit event sequence; when a first functional module monitors a signal state of a first read-write signal to be an idle state, generate a second read-write signal based on the hit event sequence; the second read-write signal is used for a third functional module to perform read-write fusion processing based on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data; perform data reading processing from the third functional module based on the second read-write signal, to obtain the second read data; and perform flow table compression processing based on the second read data and the hit event sequence, to obtain single-bit decision information. The sending unit is configured to send the single-bit decision information to the third functional module; and the single-bit decision information is used for a control plane to perform flow table aging decision.

12. A data processing apparatus, characterized by The device applied to the third functional module comprises: The receiving unit is configured to receive a first read-write signal and / or a second read-write signal; the first read-write signal is generated by a first functional module based on a flow table configuration mode and flow table address information; and the second read-write signal is generated by a second functional module based on a hit event sequence when a signal state of the first read-write signal is an idle state. The processing unit is configured to perform read-write fusion processing on the first read-write signal and / or the second read-write signal, to obtain first read data and / or second read data. The storage unit is configured to store the first read data and / or the second read data in parallel; the first read data is used for the first functional module to generate a management back packet; the second read data is used for the second functional module to perform flow table compression processing, to obtain single-bit decision information; and the first read data and / or the second read data are respectively stored in different parallel storage spaces, to be used for each read-write operation to be performed only on a corresponding storage space.

13. A processing device, characterized by The device comprises: A processor and a memory configured to store a computer program; the processor is configured to call and run the computer program stored in the memory, to perform the method in any one of claims 1 to 8.

14. A computer-readable storage medium, characterized in that, A computer program for storing a computer program which causes a computer to perform the method of any one of claims 1 to 8.

15. A computer program product, characterised in that, A computer program comprising computer program instructions which cause a computer to perform the method of any one of claims 1 to 8.

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