Routing device, data packet transmission method and chip

Abstract

The invention discloses a routing device, a data packet transmission method and a chip. The routing device comprises at least one input unit and a control unit, each input unit is at least configured with a first buffer area and a second buffer area which are mutually independent, the first buffer area stores header information of a data packet, and the header information is at least configured with transmission priority information of the data packet; the second buffer area stores load data of the data packet; the control unit is used for receiving a data packet input from the upstream, and storing header information and load data corresponding to the data packet into the first buffer area and the second buffer area respectively; determining a downstream transmission sequence of each data packet based on the header information of each data packet; transmitting the header information based on the transmission sequence; and after the header information is sent, responding to the data transmission instruction, controlling the load data output of the corresponding input unit, and enabling the load data output sequence to be consistent with the corresponding header information output sequence.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically to a routing device, a data packet transmission method, and a chip. Background Art

[0002] Network-on-chip (NOC) routing policies are a core component of NOC, and their performance has a crucial impact on the overall performance of the NOC system. Normally, routers transmit data packets according to their priority. However, in some cases, low-priority packets can block the transmission of high-priority packets, failing to meet practical application requirements. Summary of the Invention

[0003] In view of the above, this application provides the following technical solution:

[0004] A routing device, comprising:

[0005] At least one input unit and a control unit; wherein;

[0006] Each input unit is configured with at least a first buffer area and a second buffer area that are independent of each other. The first buffer area is used to store the header information of the data packet, and the header information is configured with at least the transmission priority information of the data packet. The second buffer area is used to store the payload data of the data packet.

[0007] The control unit is configured to receive data packets input from upstream, store the header information and payload data corresponding to the data packets into a first buffer area and a second buffer area respectively; determine the transmission order of each data packet downstream based on the header information of each data packet in the first buffer area; transmit the header information in the first buffer area based on the transmission order; and after the header information is sent, control the output of the corresponding payload data in the second buffer area of ​​the corresponding input unit in response to a data transmission instruction, such that the output order of the payload data is consistent with the output order of the corresponding header information.

[0008] Optionally, it may also include: an output unit;

[0009] The output unit is configured with a data recording table, which is used to record the input unit corresponding to the header information of the data packets sent downstream by the routing device, so that the control unit can control the output of load data in the second buffer area of ​​the corresponding input unit based on the sending order of the sent header information recorded in the data recording table.

[0010] Optionally, the control unit is further configured to clear the record information corresponding to the data packet in the data record table of the output unit after the data packet transmission is completed;

[0011] In response to the completion of the data packet transmission, the buffer resources occupied by the header information of the data packet in the first buffer area are released, and the buffer resources occupied by the payload data of the data packet in the second buffer area are released.

[0012] Optionally, the data transmission indication includes a data credit signal, and the control unit includes a credit signal management subunit. The credit signal management subunit is used to independently manage the header information credit signal for the first buffer area and the load data credit signal for the second buffer area. The header information credit signal represents the downstream's ability to receive header information and is used to control the transmission frequency of header information in the first buffer area. The load data credit signal represents the downstream's ability to receive load data and is used to control the transmission frequency of load data in the second buffer area.

[0013] The control unit is also configured to control the transmission of the next header information based on the header information credit signal and the priority of the current header information when the load data credit signal is not received from the downstream node.

[0014] Optionally, the control unit is further configured to check whether there is any untransmitted payload data in the data record table after each header information is sent, and transmit the corresponding payload data in the order of records in the data record table after the downstream returns a data transmission instruction;

[0015] The control unit is also used to check in sequence through the data record table whether the load data corresponding to the transmitted header information has been transmitted completely, and when the load data credit signal is valid, to transmit the incomplete load data in accordance with the header information recording order recorded in the data record.

[0016] Optionally, when the header information of the current data packet and the header information of the subsequent data packets to be transmitted are transmitted through different output units, the control unit is further configured to copy the header information of the current data packet, so that the copied header information is transmitted to different output units respectively.

[0017] Optionally, the control unit is further configured to:

[0018] If the load data transmission is interrupted, the interrupted node of the transmitted load data is retained in the second buffer area;

[0019] In response to the data transmission instruction, the load data continues to be transmitted from the interrupted node location.

[0020] A method for transmitting data packets, comprising:

[0021] The system receives data packets from upstream and stores the header information and payload data of the data packets in a first buffer area and a second buffer area that are independent of each other in the input unit, respectively. The header information includes the transmission priority information of the data packets.

[0022] Based on the header information of each data packet in the first buffer area, the transmission order of each data packet to the downstream is determined;

[0023] The header information in the first buffer area is transmitted based on the transmission order;

[0024] After the header information is sent, in response to the data transmission instruction, the corresponding load data in the second buffer area of ​​the corresponding input unit is controlled to be output, and the output order of the load data is made consistent with the output order of the corresponding header information.

[0025] A chip includes a data transmission network, wherein each node of the data transmission network is provided with a routing device, and the routing device includes at least one input unit and a control unit; wherein;

[0026] Each input unit is configured with at least a first buffer area and a second buffer area that are independent of each other. The first buffer area is used to store the header information of the data packet, and the header information is configured with at least the transmission priority information of the data packet. The second buffer area is used to store the payload data of the data packet.

[0027] The control unit is configured to receive data packets input from upstream, store the header information and payload data corresponding to the data packets into a first buffer area and a second buffer area respectively; determine the transmission order of each data packet downstream based on the header information of each data packet in the first buffer area; transmit the header information in the first buffer area based on the transmission order; and after the header information is sent, control the output of the corresponding payload data in the second buffer area of ​​the corresponding input unit in response to a data transmission instruction, such that the output order of the payload data is consistent with the output order of the corresponding header information.

[0028] Optionally, the chip further includes: a recording unit;

[0029] The recording unit is used to update the recording information in the data recording table. The data recording table is used to record the input unit corresponding to the header information of the data packets sent downstream by the routing device, so that the control unit can control the output of load data in the second buffer area of ​​the corresponding input unit based on the sending order of the sent header information recorded in the data recording table. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a routing device provided in an embodiment of this application;

[0032] Figure 2 A schematic diagram of a buffer area provided in an embodiment of this application;

[0033] Figure 3 This is a schematic diagram illustrating an application scenario of a routing device provided in an embodiment of this application;

[0034] Figure 4 A schematic diagram of another routing device provided in the embodiments of this application;

[0035] Figure 5 A schematic diagram illustrating a cross-route on-chip network data transmission scenario provided in an embodiment of this application;

[0036] Figure 6 A schematic diagram of a data recording table provided in an embodiment of this application;

[0037] Figure 7 This is a flowchart illustrating a data packet transmission method provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The terms "first" and "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units may include steps or units not listed, but may include steps or units not listed.

[0040] This application provides a routing device, a data packet transmission method, and a chip, applied to a network on chip (NOC). NOC is a network architecture implemented at the chip level; it is a distributed, scalable, and high-performance communication architecture used to connect various modules on a chip. For example, NOC can be used for inter-core data transmission within multi-core processing chips (such as CPUs and GPUs); NOC can also be used for communication between different functional modules (such as processors, memory, and peripheral interfaces) in a system-on-a-chip; and NOC can be used in scenarios with high real-time and priority requirements for data transmission, such as high-performance computing chips and artificial intelligence chips. Typically, a NOC includes a routing device (also called a routing node), a network adapter, and network links. A routing device is a network routing node implemented on an integrated circuit and is an important component of a NOC. It can realize data transmission between multiple processors, memory, and peripherals, and can include multiple input units (i.e., input ports) and output units (i.e., output ports), capable of processing multiple data packets simultaneously. Based on the solution provided in the embodiments of this application, low-priority data packets can be prevented from blocking high-priority data packets, ensuring the transmission efficiency of high-priority data packets. This provides a reliable solution for the efficient transmission of high-priority data in on-chip networks, and is especially suitable for high-end chip scenarios with stringent requirements for the real-time and orderly transmission of data.

[0041] This application provides a routing device, see [link to relevant documentation]. Figure 1 The routing device includes at least one input unit, in Figure 1 The diagram illustrates an application scenario where the routing device includes input unit 101, input unit 102, input unit 103, and control unit 104. The specific number of input units can be determined according to actual application requirements. Figure 1 This is an example diagram to illustrate the relevant functions of the routing device. Other functional modules included in the routing device are not described in the provided text. Figure 1 Not all of them are shown in the image.

[0042] Each input unit is configured with at least two independent buffer areas: a first buffer area and a second buffer area. The first buffer area stores the header information of the data packet, and the second buffer area stores the payload data of the data packet. The data packet is the basic unit for data transmission in the on-chip network, and its structure is typically divided into two parts: header information and payload data. It may also include tail information; in some implementations, the tail information can be merged into the payload data. The header information controls the transmission path and priority of the data packet. That is, the header information at least includes transmission priority information for the data packet. For example, the header information may include routing information (target transmission node address, transmission path, etc.), Quality of Service (QoS) identification information (such as priority identifier, latency sensitivity identifier, etc.), data packet identifier (such as data packet ID, sequence number, etc.), payload length information (indicating the number of subsequent payload data), and control flags. The payload data of the data packet carries the actual transmitted data content. The payload data may include the data body (the valid data to be transmitted, such as calculation instructions, memory data, etc.), checksum information, and control flags (such as intermediate data flags), etc. In one implementation, the data packet may also include tail information, which is used to mark the end of the data packet and trigger resource release. For example, the tail information may include an end flag and status messages (such as identifiers related to successful or failed data packet transmission).

[0043] See Figure 2 This illustrates a schematic diagram of a buffer area provided in an embodiment of this application. In the routing device, the input buffer area is divided into a header buffer area (e.g., ...). Figure 2 The head buffer and load buffer areas (as shown) Figure 2 The payload buffer shown above, where the head buffer is used to store the packet header ( Figure 2 (Head in Chinese) The payload buffer is used to store the payload of data packets. Figure 2(Represented by payload in the text) Once the payload buffer is full, it will not block the head from continuing transmission. Since information such as packet priority is stored in the header, it ensures that the header of high-priority packets is not blocked, preventing low-priority packets from blocking high-priority packets. Specifically, the control unit in the routing device receives data packets from upstream and stores the corresponding header information and payload data in the first and second buffer areas, respectively. After receiving a data packet from upstream, the routing device parses the packet to obtain the header information and payload data. Then, it separates the header and payload through independent first buffer areas (for storing header information) and second buffer areas (for storing payload data). This separate storage method ensures that the header information will not be blocked due to the payload data buffer being full.

[0044] The control unit determines the downstream transmission order of each data packet based on its header information in the first buffer area, ensuring that high-priority header information participates in arbitration first. Then, after transmitting the header information in the determined order, based on the downstream data transmission indication, the load data in the second buffer area is output according to the header information transmission order, ensuring consistency between the two. The data transmission indication may include a ready signal sent by the downstream node, indicating its readiness to receive data transmitted by the routing device; it may also include link status indication signals, such as transmission start / stop control signals triggered by physical link failures or energy management; and it may include data credit signals, indicating the downstream's ability or quantity of data reception. In this embodiment, the downstream data transmission indication may be received by the routing device during data transmission or received before data transmission. Due to the dynamic nature of the downstream processing status, the downstream may provide a data transmission indication before the routing device transmits header information. For example, if the downstream node's buffer has released sufficient space during the initial transmission gap, the downstream node can send a signal indicating a data transmission instruction in advance. In this case, even if the routing device has not yet started transmitting the header information of the current data packet, it can receive this data transmission instruction beforehand, ensuring accurate transmission of subsequent header information and corresponding payload data, thereby improving the flexibility and efficiency of data transmission. Conversely, if the routing device detects that there is no available data transmission instruction before or during the transmission of the header information, or if the downstream's receiveable data capacity corresponding to the currently received data transmission instruction is insufficient to meet the needs of the subsequent payload data transmission, the routing device can transmit the header information and wait for the downstream to respond with a data transmission instruction before transmitting the corresponding payload data.

[0045] For example, the first buffer area of ​​the input unit of the routing device stores header information P0_0 (low priority) and P0_1 (high priority), while the second buffer area stores the corresponding load data. The control unit determines that P0_1 should be transmitted first based on the header priority. After the header is transmitted, based on the existence of a received downstream transmission indication, the load data of P0_1 is output in the order of the header to avoid being blocked by the load data of P0_0.

[0046] This application provides a routing device that separates the header information and payload data of data packets by setting independent first buffer areas (for storing header information) and second buffer areas (for storing payload data) in the input unit of the routing device. The transmission order is determined based on the priority of the header information, ensuring that the payload data is output in the order of the header transmission. This solves the problem of low-priority data packets blocking high-priority data packets in on-chip networks, improving the transmission efficiency of high-priority data.

[0047] The relevant functional units of the routing device in the embodiments of this application will be described below in conjunction with actual application scenarios.

[0048] To facilitate the recording and tracking of transmitted data, the routing device in this embodiment further includes an output unit for outputting data. Correspondingly, the output unit can output header information from the first buffer area and load data from the second buffer area. The output unit is configured with a data recording table, which records the input units corresponding to the header information of data packets sent downstream by the routing device. This allows the control unit of the routing device to control the output of load data from the second buffer area of ​​the corresponding input unit based on the sending order of the header information recorded in the data recording table.

[0049] The data log table records the input units (e.g., Input_unit0) corresponding to the transmitted header information. The recorded content mainly includes header identifiers and input unit numbers. Based on the header transmission order in the data log table, the payload data from the second buffer area of ​​the corresponding input unit is retrieved to ensure that the order of the payload data output by the output unit is consistent with the order of the header information. For example, if header information P0_1 (from input_unit0) is transmitted first, the data log table records this association, and subsequent payload data is output preferentially from the second buffer area of ​​Input_unit0.

[0050] See Figure 3 It illustrates an application scenario diagram of a routing device provided in an embodiment of this application, such as... Figure 3As shown, in this application scenario, the routing device is represented by "Router". This routing device includes a first input unit (represented by "input_Unit0") and a second input unit (represented by "input_Unit1"). Each of these two input units includes a first buffer area and a second buffer area. The first buffer area stores the header information of the data packets, and the second buffer area stores the payload data of the data packets. The control unit in the routing device controls the data output from the input units. Correspondingly, the routing device also includes a first output unit (represented by "Output Unit0") and a second output unit (represented by "OutputUnit1"). When the header information from input_Unit0 has a higher priority than the header information from input_Unit1, the control unit will control the header information from input_Unit0 to be transmitted first. At this time, input_Unit0 will be recorded in the data record table of Output Unit0, and then input_Unit1 will be recorded. Thus, when a downstream transmission instruction is received, the control unit calls the payload data of Input_Unit0 and Input_Unit1 in the order of the record table, avoiding order confusion. In this embodiment, a data logging table is configured in the output unit of the routing device to record the input units corresponding to the header information, ensuring that the load data is output in the order of header transmission. The data logging table enables the association and tracking of the header and load, solving the problem of disordered load order across input units.

[0051] The control unit can be an arbitrator. The header information of the data packet includes information representing the transmission priority of the data packet, such as the Quality of Service (QoS) identifier. The header information can participate in arbitration in the control unit through QoS representation; it can also be based on information including the master control unit of the sending or receiving end, and arbitration is based on the rules that different master control units correspond to different priorities; or it can be based on the task information recorded in the data to be transmitted table, and arbitration is based on the task priority corresponding to the task information, so that the control unit can determine the transmission order of the header information of the data packets to be transmitted.

[0052] In some embodiments of this application, in scenarios where header information needs to be transmitted through different output units, a header information copying processing mode can be used to ensure that the output payload data and header information are in the same order. For example, if the header information of the current data packet and the header information of subsequent data packets are transmitted through different output units, the control unit is further configured to copy the header information of the current data packet, so that the copied header information is transmitted to different output units respectively. For example, see still... Figure 3The header information transmitted by the first output unit is copied and recorded sequentially in the data record table of the second output unit, Output Unit 1. This ensures that even if the corresponding load data is subsequently output through the second output unit, the corresponding load data can be output according to the order of the transmitted header information, avoiding the problem of header and load data transmission confusion. It also supports the transmission of unified header information to multiple output ports, adapting to the multi-destination data transmission requirements in on-chip networks. For example, the header information P0_0 of the first input unit Input_unit0 of the routing device Router0 needs to be transmitted to the first output unit Output_unit0, while the header information P1_0 of the second input unit Input_unit1 needs to be transmitted to the second output unit Output_unit1. The control unit copies the header of P0_0, placing it into the transmission queues of Output_unit0 and Output_unit1 respectively, avoiding header transmission conflicts caused by different output ports and the problem of inconsistent subsequent load data transmission.

[0053] In this embodiment of the application, to reduce the storage overhead of the routing device, the corresponding record in the data record table can be cleared and buffer resources released after the data packet transmission is completed. In some embodiments, the control unit of the routing device is further configured to clear the record information of the corresponding data packet in the data record table of the output unit after the data packet transmission is completed. In response to the completion of data packet transmission, the buffer resources occupied by the header information of the data packet in the first buffer area and the buffer resources occupied by the payload data of the data packet in the second buffer area are released. When the control unit clears the record of the data packet that has been transmitted in the data record table, it can delete the corresponding input unit number and header information identifier, and then release the storage space of the header information in the first buffer area and the corresponding payload data space in the second buffer area. For example, if the header and payload of data packet P0_1 are both transmitted downstream, the control unit clears the record of the input unit Input_unit1 corresponding to P0_ in the record table, and releases the header information storage bit of P0_1 in the first buffer area and the payload data storage bit in the second buffer area of ​​Input_unit1 for use by new data packets. This can avoid resource waste, improve the reuse rate of the buffer area and the data record table, and reduce the storage overhead of the routing device.

[0054] In some embodiments of this application, the data transmission indication includes a data credit signal, such as a credit signal. When the downstream node can receive data, it sends a credit signal to the upstream node, indicating the amount of data that can be received. For example, a data unit represents the minimum amount of data to be transmitted, and the credit signal indicates the number of data units that the downstream node can receive. For instance, when the downstream node sends a credit signal containing four data units to the upstream node, it indicates that the downstream node can currently receive four data units sent by the upstream node. In this way, the amount of data that the downstream node can currently receive can be determined based on the credit signal, so as to facilitate subsequent data transmission.

[0055] The control unit of the routing device includes a credit signal management subunit, which independently manages the header information credit signal for the first buffer area and the payload data credit signal for the second buffer area. The header information credit signal (credit-head) represents the downstream's ability to receive header information and is used to control the transmission frequency of header information in the first buffer area. The payload data credit signal (credit-payload) represents the downstream's ability to receive payload data and is used to control the transmission frequency of payload data in the second buffer area.

[0056] Specifically, the credit signal indicates whether the downstream buffer is free and can receive data transmitted by the routing device. If the control unit does not receive the downstream load data credit signal (if the downstream load buffer is full), the control unit can still transmit the next high-priority header information (such as P0_1) based on the header credit signal and header priority, avoiding header blocking. For example, when the first routing device Router0 transmits data to the second routing device Router1, if Router1's load buffer is full (no load credit signal), the control unit of Router0 can still continue to transmit the high-priority header P0_1 in the input unit Input_unit1 based on the header credit signal (Router1's header buffer is free), without waiting for the load transmission to complete.

[0057] See Figure 4 It shows a schematic diagram of another routing device provided in an embodiment of this application. Figure 4 The routing device shown includes input units input_Unit0 and input_Unit1, each of which includes a first buffer area ( Figure 4 (represented by Head buffer) and the second buffer area ( Figure 4 (represented as Payload buffer in the text), control unit ( Figure 4(represented by Switch in the code) and output units Output Unit 0 and Output Unit 1. Each output unit includes a data log table ( Figure 4 In this embodiment, the header information is represented by a record table, which records the transmission order of the header information. To separate the header information and payload data (i.e., to separate the head buffer and payload buffer), the credit signals for the payload data and header information also need to be managed separately. After the data packet to be transmitted is input, it needs to be parsed, the header information of the data packet is stored in the head buffer, and the payload data is placed in the payload buffer. During output, it is necessary to choose whether to output data from the head buffer or the payload buffer. The principle for choosing between payload and head is as follows: for the same data packet, the header information is arbitrated based on its priority before outputting the payload data. When a portion of the payload data has been transmitted, if the downstream does not return a credit signal for the payload data, the header information of subsequent data packets in the head buffer can participate in the arbitration and be output downstream according to its priority.

[0058] When all Heads from multiple input units participate in arbitration, the priority information used is the highest priority from the head buffer of each input unit. A record table is added to the output unit. After a Head is sent downstream, the record table records which input unit it originated from. Once the downstream returns a credit signal for the payload data, the payload data from the corresponding input unit can be sent downstream according to the order recorded in the record table. When the end of a data packet is transmitted, the corresponding line is cleared from the record table.

[0059] In this embodiment, the control unit manages the credit signals of header information and payload data independently, ensuring that the transmission of header information is not affected by the credit signals of payload data, thereby decoupling the transmission of header information and payload data. Even if the payload data transmission is interrupted, the high-priority header can still continue to be transmitted, further reducing the problem of data transmission blockage.

[0060] See Figure 5This illustration shows a schematic diagram of a cross-router on-chip network data transmission scenario provided by an embodiment of this application. The scenario includes three-level routing devices: Router0, Router1, and Router2. Router1 and Router2 are upstream routers, transmitting data packets to the intermediate Router0. Router0 outputs integrated data packets (such as P0_0, P0_1, P0_2, etc.) downstream. Each router is configured with two input units, Input_unit0 and Input_unit1, for receiving and temporarily storing data packets. It should be noted that... Figure 5 The schematic diagrams for each routing device only show the input unit. This routing device also includes a control unit for arbitrating data packet transmission and an output unit (not shown in the diagram). Figure 5 As shown in the figure, the output unit is used to transmit the data in the input unit to the downstream, and the control unit is used to determine the transmission order of the header information according to the priority of the data packet header information, and to control the corresponding load data transmission so that the transmission order of the load data is consistent with the transmission order of the header information.

[0061] In Router1's Input_unit0, the Head field stores packet header information. Besides the empty set "Empty", the Head field stores "P1_5" (including corresponding priority information QoS) and "P1_4", indicating that it stores the header information of packets "P1_5" and "P1_4" respectively. The corresponding Payload area stores the payload data for packets "P1_5" and "P1_4". In Router1's Input_unit1, the Head field is empty, while the corresponding Payload area stores the payload data for packets "P1_3" and "P1_2" respectively. The empty set "Empty" indicates data that has already been transmitted downstream.

[0062] The Head area of ​​the input unit Input_unit0 of the routing device Router2 is empty ("Empty"), and the corresponding Payload area stores the payload data of data packets "P0_2" and "P0_1" respectively. The Head area of ​​the input unit Input_unit1 contains the header information of data packet "P0_4", and the Payload area stores the payload data corresponding to data packets "P0_4" and "P0_3" respectively.

[0063] from Figure 5As can be seen, Router1 acts as the upstream data transmission device of Router0, and the data output by Router1 enters the input unit Input_unit0 of Router0. The Head area of ​​Input_unit0 records the following packet header information: "P1_3 (header information includes priority information QoS)", "P1_2 (including priority information QoS)", "P1_1 (including priority information QoS)", and "P1_0 (including priority information QoS)". It can be seen that the input unit Input_unit0 of Router0 has received the header information of packets P1_3, P1_2, P1_1, and P1_0 sent by Router1. The Payload area of ​​Router0 stores the payload data corresponding to packets "P1_1" and "P1_0", indicating that Router0 has received the payload data corresponding to packets P1_1 and P1_0 transmitted by Router1. Since the Head of Router0's Input_unit0 also includes the header information corresponding to data packets P1_3 and P1_2, it's clear that Router0's Input_unit0's Payload is waiting to receive the load information corresponding to P1_3 and P1_2. However, because the load data corresponding to data packets P1_1 and P1_0 has not yet been transmitted to Router0's downstream receiver, Router0's Input_unit0's Payload temporarily lacks the ability to receive load data. Once the load data corresponding to P1_1 and P1_0 has been transmitted to Router0's downstream receiver, Router0 can send a load data credit signal to Router1, enabling Router1 to transmit the load information corresponding to data packets P1_3 and P1_2 from Input_unit1's Payload to Router0. Figure 5 As shown, the header of Router0 is full. After transmitting the header information of the corresponding data packets P1_1 and P1_0 to the downstream receiver, it can send a credit signal of the header information back to Router1, enabling Router1 to transmit the header information of the corresponding data packets P1_5 and P1_4 from Input_unit0 to Router0. Therefore, in this embodiment, the header and payload information of the data packets are transmitted separately, and even if the payload area is full, it will not block the continued transmission of the header.

[0064] exist Figure 5In this example, the upstream data sender of Router0's input unit Input_unit1 is Router2. The Head of Input_unit1 stores the header information of data packets P0_3, P0_2, P0_1, and P0_0, while the Payload of Input_unit1 stores the payload information of data packets P0_1 and P0_0. Figure 5 The payload data of packet P0_1 is also stored in the payload of Router2's Input_unit0, but the header information of packet P0_1 is not stored in the header of Router2's Input_unit0. This indicates that Router2 has sent the header information of packet P0_1 to Router0, but due to the data reception capacity limitation of the payload area of ​​Router0's Input_unit1, only a portion of the payload information of P0_1 has been transmitted to Router0. After Router0 sends a payload data acceptance signal back to Router2, indicating that Router0 has room to continue receiving payload data, Router2 can continue to transmit the payload data of P0_1 to Router0. However, this does not affect the fact that the Head of Router0's Input_unit1 continues to receive the header information of the corresponding data packets transmitted by Router2. Figure 5 As shown in Router2, after transmitting the header information of data packet P0_1, Router2 continued to transmit the header information of data packets P0_2 and P0_3 to the Head of Input_unit1 of Router0. This enables the Head of subsequent data packets in the Head to participate in arbitration and be output downstream when the payload is halfway transmitted and no Payload Credit is returned downstream.

[0065] Correspondingly, the payload area of ​​Router2 stores the payload data of data packets P0_2 and P0_3 in a pending transmission state. Router2 can only transmit the payload data of data packets P0_2 and P0_3 to Router0 after the payload data of P0_1 has been completely transmitted to Router0 and a payload data verification signal has been received from Router0, indicating that Router0 has free space to continue storing payload data. Meanwhile, the Head area of ​​Router0's Input_unit1 is currently full. After Router0 continues to transmit the header information of the corresponding data packets in its Head area to its downstream receiver, creating free space in its Head area, it will send a header information verification signal back to Router2. At this point, Router2 can transmit the header information of data packet P0_4 to Router0.

[0066] Furthermore, Router0 can continue to send the header information of high-priority data packets to the downstream receiver based on the priority of the header information of the data packets stored in the Head area of ​​its input unit. For example, the header information of data packets P0_0, P0_1, and P0_2 can be sent to the downstream receiver first. Based on the load data credit signal of the downstream receiver and the transmission order of the header information of the corresponding data packets, the load information of the corresponding data packets can be sent in sequence. This realizes the logic of controlling the transmission order based on the priority of header information and ensuring the orderly output of data.

[0067] In some embodiments of this application, the control unit is further configured to check whether there is any untransmitted payload data in the data record table after each header information is sent, and continue to transmit the corresponding payload data in the order of records in the data record table after the downstream returns a data transmission instruction.

[0068] After each header message is sent, the control unit immediately checks for any untransmitted payload data (such as the payload corresponding to a previously transmitted header) according to the transmission order of the header messages recorded in the data log table. Upon receiving a downstream transmission instruction (such as a payload credit signal), the corresponding payload data is transmitted according to the header message transmission order recorded in the data log table. For example, see [link to previous section]. Figure 5After Router2 sends the header information of corresponding data packets P0_1 (from Router2 input_unit0) and P0_2 (from Router2 input_unit0), the data log table records both in sequence. Each time a new header is sent, the control unit checks the log table. If it finds that the load for P0_1 has not been fully transmitted, upon receiving a downstream credit signal, it prioritizes transmitting the load data corresponding to data packet P0_1, and then transmits the load data for data packet P0_2. This process of checking the data log table for untransmitted load data after each header transmission and transmitting it sequentially ensures timely transmission of load data, reduces backlog, and improves overall data throughput.

[0069] In another embodiment of this application, the control unit is further configured to sequentially check whether the payload data corresponding to the transmitted header information has been transmitted through the data record table, and when the payload data credit signal is valid, transmit the incomplete payload data in accordance with the header information recording order recorded in the data record.

[0070] For example, suppose the routing device Router-A first transmits the header information of the high-priority data packet Pa_1 from the input unit Input_Unit-a, and then transmits the header information of the low-priority data packet Pb_1 from the input unit Input_Unit-b.

[0071] See Figure 6 The illustration shows a schematic diagram of a data recording table provided in an embodiment of this application. The data recording table includes fields such as Head_ID (header identifier), input unit, and load data transmission status (Status). After the header information of data packet Pa_1 is transmitted, a new record is added to the data recording table, including: Head_ID = Pa_1, the corresponding input unit is Input_Unit-a, and the load data status (Status) is not transmitted. After the header information of data packet Pb_1 is transmitted, another record is added to the data recording table, such as Head_ID = Pb_1, the input unit is Input_Unit-b, and the load data status (Status) is not transmitted.

[0072] When the timed polling cycle is reached, the control unit traverses the data record table and finds two records with Status = Not Transmitted; simultaneously, the downstream node, having processed part of the load, returns a valid load data credit signal. The control unit processes the record in the order it was recorded, first retrieving the load data for data packet Pa_1 from the second buffer area of ​​Input_Unit-a and sending it to the output port; after completion, it processes the record for data packet Pb_1, retrieving the load data for Pb_1 from the second buffer area of ​​Input_Unit-b and sending it.

[0073] If, during the transmission of load Pa_1, the downstream buffer suddenly becomes full, returning an invalid credit signal, the transmission is forcibly interrupted. The control unit marks the load data status Status of the corresponding record for Pa_1 as transmission interrupted and stores the interruption node information. During subsequent periodic polling, when the control unit detects this record, it waits for a valid credit signal to return from the downstream, and then continues transmitting the load Pa_1 from the interruption node until completion, updating the record status to complete.

[0074] In this embodiment, the control unit systematically checks the load transmission status corresponding to the transmitted headers, and, in conjunction with the valid load data credit signal, schedules the transmission of incomplete loads according to the header recording order. This enables precise control of the load transmission rhythm, ensuring that the load is output strictly following the header transmission order, adapting to complex on-chip network scenarios with multiple concurrent data packets, avoiding load backlog and out-of-order transmission, improving data transmission integrity and efficiency, and guaranteeing the end-to-end transmission quality of high-priority data.

[0075] In this embodiment, interrupted nodes can be retained during load data transmission, allowing subsequent continuation from those nodes. This solves the load data retransmission problem, saves bandwidth and time, and improves transmission efficiency. Specifically, in one implementation, if load data transmission is interrupted, the interrupted node of the transmitted load data is retained in the second buffer area. In response to a data transmission instruction, the load data continues transmission from the interrupted node location. Specifically, if load data transmission is interrupted due to a lack of downstream signal (e.g., interrupted when transmitting to the 5th load data unit), the control unit records the interrupted node (e.g., the 5th data unit) in the second buffer area. Upon receiving a transmission instruction, transmission continues from the 5th data unit, without starting from the beginning. For example, the load data of P0_1 includes 10 data units, and transmission is interrupted due to a lack of downstream signal when transmitting to the 3rd data unit. The second buffer area records the interrupted node as "3". When the transmission instruction is restored, the control unit directly starts transmission from the 4th data unit until all 10 data units are transmitted, solving the load data retransmission problem and improving load data transmission efficiency.

[0076] Another embodiment of this application also provides a data packet transmission method, see [link to relevant documentation]. Figure 7The method may include the following steps:

[0077] S201. Receive the data packet input from the upstream and store the header information and payload data of the data packet into the first buffer area and the second buffer area, which are independent of each other, in the input unit.

[0078] The header information includes the data packet transmission priority information.

[0079] S202. Based on the header information of each data packet in the first buffer area, determine the transmission order of each data packet downstream.

[0080] S203. Transmit the header information in the first buffer area based on the transmission order.

[0081] S204. After the header information is sent, in response to the data transmission instruction, the corresponding load data in the second buffer area of ​​the corresponding input unit is controlled to be output, and the output order of the load data is consistent with the output order of the corresponding header information.

[0082] Optionally, after sending the header information, the input unit corresponding to the header information is recorded in the data record table of the output unit;

[0083] The step of responding to a data transmission instruction and controlling the output of the corresponding load data in the second buffer area of ​​the corresponding input unit specifically includes: controlling the output of the load data in the second buffer area of ​​the corresponding input unit based on the transmission order of the sent header information recorded in the data record table.

[0084] Optionally, it also includes:

[0085] Once the header and payload data of a data packet have been transmitted, the record information corresponding to that data packet in the data record table is cleared.

[0086] Release the storage resources occupied by the header information of the data packet in the first buffer area, and release the storage resources occupied by the payload data of the data packet in the second buffer area.

[0087] Optionally, the data transmission indication includes a header information credit signal and a payload data credit signal; the method further includes:

[0088] The header information credit signal and the load data credit signal are managed independently, wherein the header information credit signal represents the downstream's ability to receive header information, and the load data credit signal represents the downstream's ability to receive load data.

[0089] When no load data credit signal is received from downstream, the next header information is transmitted based on the header information credit signal and the priority of the current header information.

[0090] Optionally, it also includes:

[0091] After each header message is sent, check if there is any untransmitted payload data in the data record table; upon receiving a data transmission instruction from the downstream, transmit the corresponding payload data according to the record order in the data record table.

[0092] The data record table is used to check in turn whether the payload data corresponding to the transmitted header information has been transmitted completely. When the payload data credit signal is valid, the unfinished payload data is transmitted in the order of the header information recorded in the data record.

[0093] Optionally, when the header information of the current data packet and the header information of subsequent data packets to be transmitted are transmitted through different output units, the method further includes:

[0094] The header information of the current data packet is copied, and the copied header information is transmitted to different output units.

[0095] Optionally, it also includes:

[0096] If the load data transmission is interrupted, the interruption point of the transmitted load data is recorded in the second buffer area;

[0097] Upon receiving a data transmission instruction, the load data continues to be transmitted from the interrupted node location.

[0098] It should be noted that the specific implementation of the data packet transmission method in this embodiment can refer to the corresponding content of the function of the control unit in the routing device mentioned above, and will not be described in detail here.

[0099] In another embodiment of this application, a chip is also provided, including a data transmission network, wherein each node of the data transmission network is provided with a routing device, the routing device including at least one input unit and a control unit; wherein;

[0100] Each input unit is configured with at least a first buffer area and a second buffer area that are independent of each other. The first buffer area is used to store the header information of the data packet, and the header information is configured with at least the transmission priority information of the data packet. The second buffer area is used to store the payload data of the data packet.

[0101] The control unit is configured to receive data packets input from upstream, store the header information and payload data corresponding to the data packets into a first buffer area and a second buffer area respectively; determine the transmission order of each data packet downstream based on the header information of each data packet in the first buffer area; transmit the header information in the first buffer area based on the transmission order; and after the header information is sent, control the output of the corresponding payload data in the second buffer area of ​​the corresponding input unit in response to a data transmission instruction, such that the output order of the payload data is consistent with the output order of the corresponding header information.

[0102] Optionally, the chip further includes: a recording unit;

[0103] The recording unit is used to update the recording information in the data recording table. The data recording table is used to record the input unit corresponding to the header information of the data packets sent downstream by the routing device, so that the control unit can control the output of load data in the second buffer area of ​​the corresponding input unit based on the sending order of the sent header information recorded in the data recording table.

[0104] In this embodiment, the data transmission network in the chip can be an on-chip network.

[0105] It should be noted that the routing devices set up at each node of the data transmission network described in this embodiment can refer to the corresponding content above, and will not be described in detail here.

[0106] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0107] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0109] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A routing device, comprising: At least one input unit and one control unit; in; Each input unit is configured with at least a first buffer area and a second buffer area that are independent of each other. The first buffer area is used to store the header information of the data packet, and the header information is configured with at least the transmission priority information of the data packet. The second buffer area is used to store the payload data of the data packet. The control unit is used to receive data packets input from upstream and store the header information and payload data corresponding to the data packets into the first buffer area and the second buffer area, respectively. Based on the header information of each data packet in the first buffer area, the transmission order of each data packet to the downstream is determined; The header information in the first buffer area is transmitted based on the transmission order; after the header information is sent, in response to the data transmission instruction, the corresponding load data in the second buffer area of ​​the corresponding input unit is controlled to be output, and the output order of the load data is consistent with the output order of the corresponding header information.

2. The routing device according to claim 1, further comprising: Output unit; The output unit is configured with a data recording table, which is used to record the input unit corresponding to the header information of the data packets sent downstream by the routing device, so that the control unit can control the output of load data in the second buffer area of ​​the corresponding input unit based on the sending order of the sent header information recorded in the data recording table.

3. The routing device according to claim 2, wherein the control unit is further configured to clear the record information corresponding to the data packet in the data record table of the output unit after the data packet transmission is completed; In response to the completion of the data packet transmission, the buffer resources occupied by the header information of the data packet in the first buffer area are released, and the buffer resources occupied by the payload data of the data packet in the second buffer area are released.

4. The routing apparatus according to claim 1, wherein the data transmission indication includes a data credit signal, and the control unit includes a credit signal management subunit, the credit signal management subunit being used to independently manage the header information credit signal for the first buffer area and the load data credit signal for the second buffer area; the header information credit signal characterizes the downstream receiving capability for header information and is used to control the transmission frequency of header information in the first buffer area; the load data credit signal characterizes the downstream receiving capability for load data and is used to control the transmission frequency of load data in the second buffer area; The control unit is also configured to control the transmission of the next header information based on the header information credit signal and the priority of the current header information when the load data credit signal is not received from the downstream node.

5. The routing device according to claim 2, wherein the control unit is further configured to check whether there is any untransmitted load data in the data record table after each header information is sent, and transmit the corresponding load data in the order of records in the data record table after the downstream returns a data transmission instruction; The control unit is also used to check in sequence through the data record table whether the load data corresponding to the transmitted header information has been transmitted completely, and when the load data credit signal is valid, to transmit the incomplete load data in accordance with the header information recording order recorded in the data record.

6. In the routing device according to claim 2, when the header information of the current data packet and the header information of the subsequent data packet to be transmitted are transmitted through different output units, the control unit is further configured to copy the header information of the current data packet, so that the copied header information is transmitted to different output units respectively.

7. The routing device according to claim 1, wherein the control unit is further configured to: If the load data transmission is interrupted, the interrupted node of the transmitted load data is retained in the second buffer area; In response to the data transmission instruction, the load data continues to be transmitted from the interrupted node location.

8. A method for transmitting data packets, comprising: The system receives data packets from upstream and stores the header information and payload data of the data packets in a first buffer area and a second buffer area that are independent of each other in the input unit, respectively. The header information includes the transmission priority information of the data packets. Based on the header information of each data packet in the first buffer area, the transmission order of each data packet to the downstream is determined; The header information in the first buffer area is transmitted based on the transmission order; After the header information is sent, in response to the data transmission instruction, the corresponding load data in the second buffer area of ​​the corresponding input unit is controlled to be output, and the output order of the load data is made consistent with the output order of the corresponding header information.

9. A chip comprising a data transmission network, wherein each node of the data transmission network is provided with a routing device, the routing device comprising at least one input unit and a control unit; in; Each input unit is configured with at least a first buffer area and a second buffer area that are independent of each other. The first buffer area is used to store the header information of the data packet, and the header information is configured with at least the transmission priority information of the data packet. The second buffer area is used to store the payload data of the data packet. The control unit is used to receive data packets input from upstream and store the header information and payload data corresponding to the data packets into the first buffer area and the second buffer area, respectively. Based on the header information of each data packet in the first buffer area, the transmission order of each data packet to the downstream is determined; The header information in the first buffer area is transmitted based on the transmission order; after the header information is sent, in response to the data transmission instruction, the corresponding load data in the second buffer area of ​​the corresponding input unit is controlled to be output, and the output order of the load data is consistent with the output order of the corresponding header information.

10. The chip according to claim 9, further comprising: Recording unit; The recording unit is used to update the recording information in the data recording table. The data recording table is used to record the input unit corresponding to the header information of the data packets sent downstream by the routing device, so that the control unit can control the output of load data in the second buffer area of ​​the corresponding input unit based on the sending order of the sent header information recorded in the data recording table.

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