Three-dimensional memory device and manufacturing method thereof

Abstract

A memory device includes: a memory array structure having a plurality of memory banks, each memory bank including a plurality of memory banks, each memory bank having at least one memory block; and a peripheral structure stacked with the memory array structure in a vertical direction and having a plurality of memory bank driver circuits, each corresponding to one of the plurality of memory banks, respectively, each memory bank driver circuit is coupled with a word line of at least one memory block of a corresponding one of the memory banks, and overlaps one of the at least one memory block in a vertical direction. Each memory bank driver circuit may include a pre-charge voltage driver circuit configured to provide a pre-charge voltage to the word line, and a discharge voltage driver circuit configured to provide a discharge voltage to the word line.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods of fabrication thereof. Background Art

[0002] The semiconductor memory market is highly competitive. The ability to reduce the cost of manufacturing semiconductor memory products increases manufacturers' profitability. Furthermore, the ability to manufacture semiconductor memory products at a lower price than competitors allows manufacturers to increase their market share.

[0003] One way to reduce the cost of semiconductor memory products is to reduce the amount of area required to implement them. Summary of the Invention

[0004] According to one aspect of this disclosure, a memory device includes: a memory array structure including a plurality of memory banks, each of the memory banks including a plurality of memory groups, each memory group having at least one memory block; and a peripheral structure stacked vertically with the memory array structure and including a plurality of memory-group-driver circuits, each of the plurality of memory-group-driver circuits corresponding to one of the plurality of memory groups, wherein each memory-group-driver circuit is coupled to a word line of the at least one memory block corresponding to one of the plurality of memory groups and overlaps with one of the at least one memory block in the vertical direction.

[0005] In some implementations, each memory group driver circuitry includes a precharge voltage driver circuitry configured to provide a precharge voltage to the word line of at least one memory block corresponding to one of the plurality of memory groups.

[0006] In some embodiments, each memory group driver circuitry further includes a discharge voltage driver circuitry configured to provide a discharge voltage to the word line of the at least one memory block corresponding to one of the plurality of memory groups.

[0007] In some embodiments, one of the memory group driver circuits includes a buffer circuit configured to buffer control signals from the precharge voltage driver circuit or the discharge voltage driver circuit.

[0008] In some embodiments, the peripheral structure further includes: multiple memory group driver interconnects coupled to only odd or only even number lines in the corresponding memory group driver circuitry and word lines.

[0009] In some embodiments, subsets of the plurality of memory groups are arranged in rows along a first lateral direction; memory group driver interconnects coupled to the memory group driver circuitry of the subsets of the plurality of memory groups are arranged in the same horizontal wiring channel subset along the first lateral direction.

[0010] In some implementations, the number of horizontal routing channels in the same subset of horizontal routing channels depends on the number of word lines in each memory block and is independent of the number of memory groups in the subset of the plurality of memory groups.

[0011] In some embodiments, the peripheral structure further includes: a first word line driver circuit and a second word line driver circuit, the first word line driver circuit being located on a first side of a memory block and coupled to even-number lines, and the second word line driver circuit being located on a second side of the memory block opposite to the first side and coupled to odd-number lines; a Y decoder circuit overlapping the memory block in the vertical direction; and a sense amplifier circuit at least partially overlapping the memory block in the vertical direction.

[0012] In some embodiments, the sense amplifier circuit, the Y decoder circuit, and a memory group driver circuit are arranged in a first lateral direction between the first word line driver circuit and the second word line driver circuit, and the memory group driver circuit is arranged in a second lateral direction perpendicular to the first lateral direction between the sense amplifier circuit and the Y decoder circuit.

[0013] In some embodiments, the sense amplifier circuit, the Y decoder circuit, and a memory bank driver circuit are arranged in a first lateral direction between the first word line driver circuit and the second word line driver circuit, and the memory bank driver circuit and the Y decoder circuit are arranged in a second lateral direction perpendicular to the first lateral direction between a first portion of the sense amplifier circuit and a second portion of the sense amplifier circuit.

[0014] In some embodiments, the Y decoder circuit and a memory group driver circuit are arranged in a first lateral direction between the first word line driver circuit and the second word line driver circuit, and the first word line driver circuit, the second word line driver circuit, the memory group driver circuit, and the Y decoder circuit are arranged in a second lateral direction perpendicular to the first lateral direction between the first portion of the sense amplifier circuit and the second portion of the sense amplifier circuit.

[0015] In some embodiments, the peripheral structure further includes at least one X decoder circuit coupled to the buffer circuit, wherein a first X decoder circuit of the at least one X decoder circuit is located on the peripheral structure and is vertically offset relative to a region of the memory array structure located between two laterally adjacent memory cells.

[0016] In some implementations, each memory block includes multiple memory cells, and each memory cell includes at least one vertical transistor and at least one vertical capacitor.

[0017] Another aspect of this disclosure provides a method for forming a memory device, comprising: forming a memory array structure including a plurality of memory banks, each memory bank including a plurality of memory groups, each memory group having at least one memory block; forming a peripheral structure including forming a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups; and bonding the memory array structure and the peripheral structure such that each memory group driver circuit is coupled to a word line of the at least one memory block corresponding to one of the plurality of memory groups and overlaps with one of the at least one memory block in a vertical direction.

[0018] In some embodiments, forming each memory group driver circuitry includes forming a precharge voltage driver circuitry configured to provide a precharge voltage to the word lines of at least one memory block corresponding to one of the plurality of memory groups.

[0019] In some embodiments, forming each memory group driver circuitry further includes forming a discharge voltage driver circuitry configured to provide a discharge voltage to the word line of the at least one memory block corresponding to one of the plurality of memory groups.

[0020] In some embodiments, a memory bank driver circuit forming a memory bank driver circuit includes forming a buffer circuit, the buffer circuit being configured to buffer control signals of the precharge voltage driver circuit or the discharge voltage driver circuit.

[0021] In some implementations, forming the peripheral structure further includes forming a plurality of memory group driver interconnects configured to couple only odd or only even number lines in the corresponding memory group driver circuitry and word lines.

[0022] In some embodiments, forming a memory array structure includes arranging subsets of a plurality of memory groups in a row along a first lateral direction; and forming a peripheral structure further includes arranging memory group driver interconnects coupled to the memory group driver circuitry of the subsets of the plurality of memory groups in a subset of horizontal wiring channels along the first lateral direction.

[0023] In some implementations, the number of horizontal routing channels in the same subset of horizontal routing channels depends on the number of word lines in each memory block and is independent of the number of memory groups in the subset of the plurality of memory groups.

[0024] In some embodiments, forming the peripheral structure further includes forming a plurality of word line driver circuits, a plurality of Y decoder circuits, and a plurality of sense amplifier circuits, wherein, after the memory array structure and the peripheral structure are bonded, the plurality of word line driver circuits are located between adjacent memory blocks, each Y decoder circuit overlaps with a corresponding memory block in the vertical direction, and each sense amplifier circuit at least partially overlaps with a corresponding memory block in the vertical direction.

[0025] In some embodiments, forming the peripheral structure further includes: arranging at least one of the plurality of sense amplifier circuits, a first Y decoder circuit of the plurality of Y decoder circuits, and a memory group driver circuit in a first lateral direction between a first word line driver circuit and a second word line driver circuit; and arranging the memory group driver circuit in a second lateral direction perpendicular to the first lateral direction between the at least one sense amplifier circuit and the first Y decoder circuit.

[0026] In some embodiments, forming the peripheral structure further includes: arranging at least one of the plurality of sense amplifier circuits, a first Y decoder circuit of the plurality of Y decoder circuits, and a memory bank driver circuit in a first lateral direction between a first word line driver circuit and a second word line driver circuit; and arranging the memory bank driver circuit and the first Y decoder circuit in a second lateral direction perpendicular to the first lateral direction between a first portion of the at least one sense amplifier circuit and a second portion of the at least one sense amplifier circuit.

[0027] In some embodiments, forming the peripheral structure further includes: arranging a first Y decoder circuit and a memory group driver circuit in the plurality of Y decoder circuits between a first word line driver circuit and a second word line driver circuit in a first lateral direction; and arranging the first word line driver circuit and the second word line driver circuit, the memory group driver circuit, and the first Y decoder circuit between a first portion of the sense amplifier circuit and a second portion of the sense amplifier circuit in a second lateral direction perpendicular to the first lateral direction.

[0028] In some embodiments, forming the peripheral structure further includes forming at least one X decoder circuit coupled to the buffer circuit, wherein, after the memory array structure and the peripheral structure are bonded, a first X decoder circuit of the at least one X decoder circuit is located on the peripheral structure and is vertically offset relative to a region of the memory array structure located between two laterally adjacent memory cells.

[0029] In some implementations, forming each memory block includes forming a plurality of memory cells, each memory cell including at least one vertical transistor and at least one vertical capacitor.

[0030] Another aspect of this disclosure provides a memory system comprising: a memory device including: a memory array structure including a plurality of memory banks, each memory bank including a plurality of memory groups, each memory group having at least one memory block; and a peripheral structure stacked vertically with the memory array structure and including a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups, wherein each memory group driver circuit is coupled to a word line of the at least one memory block of the plurality of memory groups and overlaps with one of the at least one memory blocks in the vertical direction; and a memory controller coupled to the memory device and configured to control the memory device.

[0031] Another aspect of this disclosure provides a memory device, comprising: a memory array structure including memory cells, each memory cell including a memory block; and a peripheral structure stacked vertically with the memory array structure, and including: a discharge voltage driver circuit coupled to a word line of the memory block; and a precharge voltage driver circuit, wherein both the precharge voltage driver circuit and the discharge voltage driver circuit are coupled to word line drivers, and wherein the precharge voltage driver circuit and the discharge voltage driver circuit overlap with the memory block in the vertical direction.

[0032] These illustrative embodiments are mentioned not to limit or restrict the scope of this disclosure, but to provide examples to aid in understanding it. Further embodiments are discussed in the detailed description, and further description is provided therein. Attached Figure Description

[0033] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use embodiments of the present disclosure.

[0034] Figure 1A This is a block diagram showing the first and second semiconductor structures before they are bonded together to form a 3D memory device.

[0035] Figure 1B This is a block diagram showing a first semiconductor structure and a second semiconductor structure bonded together in a face-to-face orientation to form a 3D memory device.

[0036] Figure 1C The bonding layers of the first semiconductor structure and the second semiconductor structure are shown before being aligned for face-to-face bonding to form a 3D memory device.

[0037] Figure 1D The bonding layers of the first semiconductor structure and the second semiconductor structure are shown after being bonded face-to-face to form a 3D memory device.

[0038] Figure 1E This is a schematic diagram of a part of the memory array structure and a part of the peripheral structure, wherein the memory array structure is shown above the peripheral structure.

[0039] Figure 1F This is a schematic diagram of a part of the memory array structure and a part of the peripheral structure, wherein the memory array structure is shown below the peripheral structure.

[0040] Figure 2 It is a high-level block diagram of a memory array structure including illustrative memory cells with vertically oriented transistors.

[0041] Figure 3 This is a schematic diagram illustrating a dynamic random access memory (DRAM) array.

[0042] Figure 4 A schematic plan view of a memory device according to the present disclosure is shown.

[0043] Figure 5 A schematic diagram of the arrangement of a memory device according to the present disclosure is shown.

[0044] Figure 6 A schematic diagram of a word line driver circuit for a memory device according to the present disclosure is shown.

[0045] Figure 7 A schematic plan view of a memory device according to the present disclosure is shown.

[0046] Figure 8 A schematic plan view of a memory device according to the present disclosure is shown.

[0047] Figure 9 It is a plan view of an array of memory banks and associated X-decoder circuitry, the associated X-decoder circuitry including circuitry for generating voltages for commonly driving word lines of the memory banks.

[0048] Figure 10A This is a plan view of an illustrative array of memory banks according to the present disclosure.

[0049] Figure 10BThis is a plan view of an illustrative memory bank based on the contents of this disclosure.

[0050] Figure 10C This is a plan view of another illustrative memory group based on the present disclosure.

[0051] Figure 10D This is a plan view of another illustrative memory group based on the present disclosure.

[0052] Figure 11 The configuration of the Y decoder circuit, the sense amplifier circuit, the word line driver circuit, and the memory bank driver circuit according to this disclosure is shown.

[0053] Figure 12 Another configuration of the Y decoder circuit, sense amplifier circuit, word line driver circuit, and memory group driver circuit according to this disclosure is shown.

[0054] Figure 13 Another configuration of the Y decoder circuit, sense amplifier circuit, word line driver circuit, and memory group driver circuit according to this disclosure is shown.

[0055] Figure 14 Similar to Figure 10A However, a buffer circuit is shown in addition.

[0056] Figure 15 This is a flowchart of a method for forming a memory device according to the present disclosure.

[0057] Figure 16 This is a block diagram of a memory system containing a memory device according to the present disclosure.

[0058] Figures 17A-17B This is a flowchart of a method for forming a peripheral structure for a memory device according to the present disclosure.

[0059] Figures 18A-18B This is a flowchart of a method for forming an alternative peripheral structure for a memory device according to the present disclosure.

[0060] Figures 19A-19B This is a flowchart of a method for forming an alternative peripheral structure for a memory device according to the present disclosure.

[0061] The contents of this disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0062] The semiconductor memory market is highly competitive. The ability to reduce the cost of manufacturing semiconductor memory products increases manufacturers' profitability. Furthermore, the ability to manufacture semiconductor memory products at a lower price than competitors allows manufacturers to increase their market share.

[0063] One way to reduce the cost of semiconductor memory products is by reducing the area required to implement them. Various embodiments of this disclosure can reduce the area required to implement semiconductor memory products by reducing the amount of wiring required. That is, by reducing the number of interconnects, a more area-efficient layout can be implemented, thereby reducing the required area. In semiconductor memory products, reducing the number of interconnects above memory cells in a memory array can provide the area-efficient layout required to reduce the area needed to implement the semiconductor memory product.

[0064] Many types of memory devices (e.g., semiconductor memory devices) use a physical arrangement that includes word lines and bit lines. Word lines and bit lines are coupled to a memory cell array, referred to herein as a memory array. Additionally, word lines and bit lines are coupled to circuitry external to the memory array. For example, bit lines may be connected to a sense amplifier, while word lines may be connected to a word line driver, and the sense amplifier circuitry and word line driver circuitry can be located external to the memory array, either laterally or vertically separated from it.

[0065] This document provides various illustrative examples and implementations to facilitate understanding of the structure of a memory device (e.g., a semiconductor memory product) and methods for manufacturing such a memory device, wherein the memory device has an area-efficient layout that produces smaller area requirements and thus smaller, higher-yield chips.

[0066] It should be noted that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0067] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0068] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with intermediate features or layers, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without intermediate features or layers (i.e., directly on).

[0069] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the figures and one or more other elements or features. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0070] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0071] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0072] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process operation, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. Unless otherwise specifically stated, terms used herein to describe various shapes, dimensions, distances, or orientations affected by manufacturing tolerances should be understood as nominal.

[0073] As used herein, the term “vertical / perpendicular” refers to the lateral surface of a substrate that is orthogonal to the lateral orientation.

[0074] As used herein, the acronym "CMOS" stands for Complementary Metal-Oxide-Semiconductor. "CMOS process" refers to the semiconductor manufacturing process that produces both n-channel and p-channel field-effect transistors on the same substrate. "CMOS circuit" refers to a circuit that includes both n-channel and p-channel field-effect transistors.

[0075] Various embodiments of this disclosure utilize a memory array formed on a first wafer and peripheral structures formed on a second wafer. The peripheral structures, including circuitry and interconnects, are bonded to the memory array in a face-to-face configuration. Figure 1A-1F Semiconductor memories with unbonded, bonded, and differently oriented memory arrays and peripheral structures are shown.

[0076] Figure 1A This is a block diagram illustrating a pair of semiconductor structures, including a first semiconductor structure 102 (also referred to herein as memory array structure 102) and a second semiconductor structure 114 (also referred to herein as peripheral structure 114) prior to bonding together to form a memory device (e.g., but not limited to dynamic random access memory (DRAM)). The first semiconductor structure 102 and the second semiconductor structure 114 may be formed on different wafers. The first semiconductor structure 102 may be a wafer-separated die, and the second semiconductor structure 114 may be a wafer-separated die.

[0077] refer to Figure 1AThe first semiconductor structure 102 includes a substrate 104, a memory array 106, an interconnect layer 108 disposed above the memory array 106, and a hybrid bonding layer 112 disposed above the interconnect layer 108. In some embodiments, the substrate 104 may be (but is not limited to) a silicon substrate, and the memory array 106 may be (but is not limited to) a DRAM array. It should be noted that in some, but not all, cases, the substrate 104 may be thinned or removed. The interconnect layer 108 may include multiple levels of interconnects, and each level may be electrically connected to a vertically adjacent level via one or more vias. The hybrid bonding layer 112 may be a dielectric layer having a plurality of first bonding contacts disposed therein.

[0078] Still refer to Figure 1A The second semiconductor structure 114 includes a substrate 116, peripheral circuitry 118, an interconnect layer 120 disposed above the peripheral circuitry 118, and a hybrid bonding layer 122 disposed above the interconnect layer 120. In some embodiments, the peripheral circuitry 118 may be (but is not limited to) a CMOS circuit. The interconnect layer 120 may include interconnects of multiple levels, and each level may be electrically connected to a vertically adjacent level via one or more vias. The hybrid bonding layer 122 may be a dielectric layer having a plurality of second bonding contacts disposed therein. The first semiconductor structure 102 and the second semiconductor structure 114 are configured to be bonded together in a face-to-face orientation such that the hybrid bonding layer 122 and the hybrid bonding layer 112 are bonded to each other, and at least a portion of the first bonding contacts is in electrical contact with at least a portion of the second bonding contacts.

[0079] Figure 1B This is a block diagram illustrating a first semiconductor structure 102 and a second semiconductor structure 114 after being hybrid-bonded together in a face-to-face orientation to form a semiconductor memory device 100B. In this bonding configuration, one or more first bonding contacts of the hybrid bonding layer 112 are in electrical contact with one or more corresponding second bonding contacts of the hybrid bonding layer 122. It should be noted that in the bonding configuration, the hybrid bonding layers 112 and 122 may be referred to herein as hybrid bonding interface 113.

[0080] Still referencing Figure 1BIt should be understood that the orientation of the semiconductor memory device 100B (where the first semiconductor structure 102 is on the bottom and the second semiconductor structure 114 is on the top) is illustrative and not limiting. That is, the semiconductor memory device 100B can be oriented such that the second semiconductor structure 114 is on the bottom, with its hybrid bonding layer 122 as its top layer, and the first semiconductor structure 102 is on the top, with its hybrid bonding layer 112 as its bottom layer. In this alternative orientation, the memory array 106 is in the top portion of the semiconductor memory device 100b. In various manufacturing processes after the first semiconductor structure 102 and the second semiconductor structure 114 are bonded together, the substrate 104 / 116 can be removed from at least partially or completely from the semiconductor structure, and a new semiconductor layer can be formed thereon. The following is in conjunction with... Figure 1C and Figure 1D Describe additional details of the first and second bonding contacts.

[0081] Figure 1C A more detailed representation of a first semiconductor structure 102 having a hybrid bonding layer 112 and a more detailed representation of a second semiconductor structure 114 having a hybrid bonding layer 122 are shown prior to alignment for face-to-face bonding to form a semiconductor memory device. Figure 1C As shown, the hybrid bonding layer 112 includes a plurality of first bonding contacts 124 disposed therein. Interconnects from the interconnect layer 108 are also shown. In this illustrative embodiment, one or more first bonding contacts 124 may make electrical contact with the interconnects of the interconnect layer 108. The interconnects from the interconnect layer 108 provide electrical pathways from at least the memory array 106 of the first semiconductor structure 102 to one or more first bonding contacts 124.

[0082] Still refer to Figure 1C The hybrid bonding layer 122 of the second semiconductor structure 114 includes a plurality of second bonding contacts 126 disposed therein. The second semiconductor structure 114 also includes interconnects from the interconnect layer 120. In this illustrative embodiment, one or more second bonding contacts 126 may be electrically contacted with the interconnects of the interconnect layer 120. The interconnects from the interconnect layer 120 provide electrical pathways from at least the peripheral circuitry 118 of the second semiconductor structure 114 to one or more second bonding contacts 126.

[0083] Figure 1D Similar to Figure 1CHowever, a hybrid bonding layer 112 of the first semiconductor structure 102 and a hybrid bonding layer 122 of the second semiconductor structure 114 are shown after face-to-face bonding to form a semiconductor memory device. In this way, the first bonding contact 124 can make electrical contact with a corresponding second bonding contact in the second bonding contact 126. The electrical connection between the first bonding contact 124 and the second bonding contact 126 allows electrical signals to be transmitted between the first semiconductor structure 102 and the second semiconductor structure 114.

[0084] Figure 1E This is a block diagram of a bonded semiconductor structure 100 including a portion of a memory array structure 102 and a portion of a peripheral structure 114, wherein the memory array structure 102 is shown above the peripheral structure 114.

[0085] Figure 1F It is a block diagram of a bonded semiconductor structure 101 including a portion of a memory array structure 102 and a portion of a peripheral structure 114, wherein the memory array structure 102 is shown below the peripheral structure 114.

[0086] Figure 2 This is a block diagram of the memory array 201 coupled to the peripheral circuitry of the peripheral structure 202, and further shows an expanded structure diagram of the memory cells. The memory array 201 includes multiple word lines 204, multiple bit lines 206, and multiple memory cells 208. As shown, each memory cell 208 is coupled to one bit line and one word line.

[0087] Still refer to Figure 2 The diagram 210 shows the structure of memory cell 208. Memory cell 212, typically implemented as a capacitor, is connected to the first source / drain (S / D) terminal of FET 214. FET 214 includes pillars of vertically oriented semiconductor material 216, a gate dielectric 218 disposed around a portion of the semiconductor material 216, and a gate electrode 220 disposed on the gate dielectric 218. FET 214 may be referred to herein as a vertical transistor.

[0088] Figure 3 This is a schematic diagram of an illustrative memory array 201 of dynamic memory cells, and further illustrates the memory array with peripheral circuitry coupled to peripheral structure 202. Each dynamic memory cell 302 in array 201 includes a field-effect transistor (FET) 304 and a capacitor 306. Figure 3 In the illustrative embodiment, FET 304 is an n-channel FET. Dynamic memory cells 302 are arranged in rows and columns to form a two-dimensional array, namely memory array 201. Figure 3In the example, memory array 201 has four rows and four columns. Therefore, the 4x4 arrangement of the illustrative memory array 201 provides sixteen dynamic storage cells 302. Various arrays according to this disclosure can be constructed from any combination of rows and columns, and Figure 3 The illustrative four-by-four array shown does not limit the size of the memory array 201 according to this disclosure.

[0089] Still refer to Figure 3 The gate terminal of FET 304 is coupled to word line 204, the first source / drain (S / D) terminal of FET 304 is coupled to bit line 206, the second S / D terminal of FET 304 is coupled to the first terminal of capacitor 306, and the second terminal of capacitor 306 is coupled to ground. This arrangement is sometimes referred to as a "1T1C" memory cell, or a 1 transistor 1 capacitor memory cell. In a 1T1C memory cell, each memory cell contains one transistor and one capacitor. The transistor acts as an access device, controlling the flow of charge into and out of the capacitor. The capacitor is used to store and retain charge, which represents the data stored in the memory cell. The basic operation of a 1T1C memory cell involves two main states: a charging state and a discharging state. The charging state can represent a bit "1", and the discharging state can represent a bit "0". During a write operation, FET 304 is used to couple capacitor 306 to a voltage source or ground via bit line 206, thereby allowing charge to transfer to or discharge from capacitor 306. The write operation modifies the charge stored in the capacitor, thereby storing the desired data. During the read operation, FET 304 couples capacitor 306 to a sense amplifier (not shown) via bit line 206, which detects and amplifies the charge stored in the capacitor. The amplified signal is then interpreted as the stored data.

[0090] Those skilled in the art will understand that alternative dynamic memory cell circuit arrangements are possible, and embodiments of this disclosure are not limited to 1T1C memory cells.

[0091] Figure 4 A schematic plan view of a memory device 400 according to some aspects of this disclosure is shown. For example... Figure 4 As shown, the memory device 400 may include one or more memory array structures 402, such as memory dies. Each memory array structure 402 may include multiple memory banks 404. For example, as Figure 4 As shown, the memory array structure 402 may include eight memory banks 404. Each memory bank 404 may include multiple memory blocks 406. For example, as Figure 4 As shown, the storage body 404 may include (m×n) storage blocks 406.

[0092] In some embodiments, the memory device 400 may further include a plurality of peripheral structures 412. In some embodiments, each peripheral structure 412 may include at least one word line driver circuit (WLD circuit) 414 and at least one sense amplifier circuit (SA circuit) 416. In some embodiments, such as Figure 4 As shown, the peripheral structure 412 may include a WLD circuit 414 and two SA circuits 416. It should be noted that... Figure 4 In the diagram, memory block 406 and peripheral structure 412 are shown side-by-side to illustrate the size of the area covered by memory block 406 and peripheral structure 412. However, in the actual structure, in the plan view of memory device 400, memory block 406 and peripheral structure 412 may at least partially overlap each other. In some embodiments, memory block 406 and peripheral structure 412 are formed separately on two different wafers or substrates and bonded to each other with at least partial overlap. In some embodiments, memory block 406 and peripheral structure 412 may completely overlap each other.

[0093] In some embodiments, a peripheral structure 412 is formed on a first wafer, and a peripheral structure 412 occupies a first region on the first wafer in a plan view of the first wafer. In some embodiments, a memory block 406 is formed on a second wafer, and a memory block 406 occupies a second region on the second wafer in a plan view of the second wafer. After the first wafer and the second wafer are bonded, in a plan view of the memory device 400, the first region including the WLD circuit 414 and the SA circuit 416 at least partially overlaps with the second region including the memory block 406. In some embodiments, the first region may include a first sub-region having a WLD circuit 414 and two second sub-regions each having an SA circuit 416. In some embodiments, the two second sub-regions may be disposed on both sides of the first sub-region. In other words, the two SA circuits 416 may be disposed on both sides of a WLD circuit 414, such as... Figure 4 As shown.

[0094] In some embodiments, when a memory block 406 includes M word lines and N bit lines, the WLD circuit 414 can be used to control the M word lines in the corresponding memory block 406, and each SA circuit 416 disposed on one side of the WLD circuit 414 can be used to control N / 2 bit lines in the corresponding memory block 406. In some embodiments, the SA circuit 416 can be shared by two adjacent memory blocks 406, and one SA circuit 416 can be used to control an odd or even number of bit lines in two adjacent memory blocks 406.

[0095] Figure 5A schematic diagram showing the arrangement of a memory device 500 according to the present disclosure is provided. Figure 5 As shown, the SA circuit includes SA circuit 516a and SA circuit 516b. SA circuit 516a can be used to control the even-numbered bit lines in memory blocks 506a and 506b. Figure 5 As shown, the SA circuit 516a includes two outputs: one output is connected to the even-numbered bit lines of memory block 506a, and the other output is connected to the even-numbered bit lines of memory block 506b, which is located above and adjacent to memory block 506a in the X direction. Similarly, in some embodiments, the SA circuit 516b includes two outputs: one output is connected to the odd-numbered bit lines of memory block 506a, and the other output is connected to the odd-numbered bit lines of memory block 506c, which is located below and adjacent to memory block 506a in the X direction.

[0096] In some embodiments, the WLD circuit may further include WLD circuit 514a and WLD circuit 514b. In some embodiments, WLD circuit 514a can be used to control even-number lines in memory block 506a, and WLD circuit 514b can be used to control odd-number lines in memory block 506a. In some embodiments, WLD circuit 514a can be shared by memory block 506a and an adjacent memory block (not shown) located to the left of memory block 506a, and WLD circuit 514b can be shared by memory block 506a and another adjacent memory block (not shown) located to the right of memory block 506a. In some embodiments, WLD circuit 514a can be used to control even-number lines in memory block 506a and even-number lines in adjacent memory blocks, and WLD circuit 514b can be used to control odd-number lines in memory block 506a and odd-number lines in another adjacent memory block.

[0097] In other words, the SA circuit, including SA circuits 516a and 516b, and the WLD circuit, including WLD circuits 514a and 514b, can be configured to at least partially overlap with memory block 506a, or completely overlap with memory block 506a. Furthermore, the SA circuit and WLD circuit can control only memory block 506a, or they can jointly control memory block 506a and adjacent memory blocks in the X and / or Y directions.

[0098] Figure 5 Further schematic diagrams of word line routing and bit line routing are shown. For example... Figure 5 As shown, word line routing can include the horizontal direction ( Figure 5 (in the Y direction) and vertical direction ( Figure 5Both the X-direction and the bit line routing may include only the vertical direction. In some implementations, even-numbered lines (e.g., WL0, WL2, WL4, WL6) may be connected to even-numbered WLD circuits 514a, and odd-numbered lines (e.g., WL1, WL3, WL5, WL7) may be connected to odd-numbered WLD circuits 514b.

[0099] Figure 6 A schematic diagram of the WLD circuit 614 according to some aspects of this disclosure is shown. It should be understood that... Figure 6 The WLD circuit 614 shown is for illustrative purposes only, and other designs or structures of the WLD circuit 614 can also be applied to this application. In this example, the WLD circuit 614 is a CMOS circuit having an input terminal configured to receive a signal labeled MWL and an output terminal configured to provide an output signal labeled WL. The WLD circuit 614 is coupled to a first voltage supply node labeled X+ and further coupled to a second voltage supply node labeled VWLN. In this example, the voltage at the first voltage supply node X+ is positive relative to the voltage at the second voltage supply node VWLN.

[0100] Still refer to Figure 6 Multiple WLD circuits 614 can be used for word lines of one or more memory blocks. Figure 6 In the illustrated embodiment, a plurality of WLD circuits 614 may be arranged such that they are positioned between the first set of sense amplifier (SA) circuits and the second set of SA circuits.

[0101] Figure 7 A schematic plan view of a memory device 700 according to some aspects of this disclosure is shown. For example... Figure 7 As shown, the memory device 700 may include one or more memory array structures 702, such as memory dies. Each memory array structure 702 may include multiple memory banks 704. For example, as Figure 7 As shown, the memory array structure 702 may include eight memory banks 704. Each memory bank 704 may include multiple memory blocks 706. For example, as Figure 7 As shown, the storage body 704 may include (m×n) storage blocks 706.

[0102] In some embodiments, the memory device 700 may further include a plurality of peripheral structures 712. In some embodiments, each peripheral structure 712 may include at least one word line driver circuit (WLD circuit) 714 and at least one sense amplifier circuit (SA circuit) 716. In some embodiments, such as Figure 7As shown, the peripheral structure 712 may include a WLD circuit 714 and two SA circuits 716. In some embodiments, the peripheral structure 712 may include a region 718 in which circuitry (e.g., but not limited to voltage generation circuitry) may be disposed.

[0103] It should be noted that, Figure 7 In the diagram, memory block 706 and peripheral structure 712 are shown side-by-side to illustrate the size of the area covered by memory block 706 and peripheral structure 712. However, in practical applications and structures, in the plan view of memory device 700, memory block 706 and peripheral structure 712 may at least partially overlap each other. In some embodiments, memory block 706 and peripheral structure 712 are formed separately on two different wafers or substrates and bonded to each other with at least partial overlap.

[0104] In some embodiments, a peripheral structure 712 is formed on a first wafer, and a peripheral structure 712 occupies a first region on the first wafer in a plan view. In some embodiments, a memory block 706 is formed on a second wafer, and a memory block 706 occupies a second region on the second wafer in a plan view. After the first wafer and the second wafer are bonded, in a plan view of the memory device 700, the first region including WLD circuitry 714 and SA circuitry 716 at least partially overlaps with the second region including memory block 706, i.e., the overlap of the first region and the second region is in the vertical direction. In some embodiments, the first region may include a first sub-region having a WLD circuitry 714 and two second sub-regions each having an SA circuitry 716. In some embodiments, when viewed with the peripheral circuitry and memory blocks stacked in the vertical direction, the first sub-region having a WLD circuitry 714 may be located between two adjacent memory blocks 706. In some embodiments, when viewed with the peripheral circuitry and memory blocks stacked vertically, a second sub-region, each having an SA circuit 716, may at least partially overlap with a second region having a memory block 706. In some embodiments, the second sub-region may completely overlap with the second region having a memory block 706. In some embodiments, the SA circuit 716 may be shared by two adjacent memory blocks 706, and one SA circuit 716 may be used to control the odd or even bit lines in the two adjacent memory blocks 706. For example, the SA circuit 716 may include two outputs: one output connected to the even bit line of the memory block 706, and the other output connected to... Figure 7 The even-numbered bit lines of the memory block adjacent to memory block 706 in the X direction. It should be noted that in some embodiments, the peripheral structure 712 includes a region 718 in which additional circuitry can be disposed.

[0105] In some embodiments, the WLD circuit 714 is located on a peripheral wafer (e.g., a CMOS wafer), corresponding to a position between two memory blocks 706 on the memory array wafer in the planar view (i.e., perpendicular to the stacking direction of the memory array structure and the peripheral structure). In some embodiments, the WLD circuit 714 provides corresponding signals to the odd-number lines or even-number lines of two adjacent memory blocks 706. For example, the WLD circuit 714 may provide corresponding signals to the odd-number lines of two adjacent memory blocks 706.

[0106] Figure 8 A schematic plan view of a memory device 800 according to some aspects of this disclosure is shown. For example... Figure 8 As shown, the memory device 800 may include one or more memory array structures 802, such as memory dies. Each memory array structure 802 may include multiple memory banks 804. For example, as Figure 8 As shown, the memory array structure 802 may include eight memory banks 804. Each memory bank 804 may include multiple memory blocks 806. For example, as Figure 8 As shown, the storage body 804 may include (m×n) storage blocks 806.

[0107] In some embodiments, the memory device 800 may further include a plurality of peripheral structures 812. In some embodiments, each peripheral structure 812 may include at least one word line driver circuit (WLD circuit) 814 and at least one sense amplifier circuit (SA circuit) 816. In some embodiments, such as Figure 8 As shown, the peripheral structure 812 may include a WLD circuit 814 and an SA circuit 816. It should be noted that... Figure 8 In the diagram, memory block 806 and peripheral structure 812 are shown side-by-side to illustrate the size of the area covered by memory block 806 and peripheral structure 812. However, in practical applications and structures, in the plan view of memory device 800, memory block 806 and peripheral structure 812 may at least partially overlap each other. In some embodiments, memory block 806 and peripheral structure 812 are formed separately on two different wafers or substrates and bonded to each other in at least a partially overlapping relationship. It should be noted that in some embodiments, peripheral structure 812 includes a region 818 in which additional circuitry can be disposed. It should also be noted that peripheral structure 812 may include circuitry for Y decoder 820.

[0108] In some embodiments, a peripheral structure 812 is formed on a first wafer, and a peripheral structure 812 occupies a first region on the first wafer in a plan view of the first wafer. In some embodiments, a memory block 806 is formed on a second wafer, and a memory block 806 occupies a second region on the second wafer in a plan view of the second wafer. After the first wafer and the second wafer are bonded, in a plan view of the memory device 800, the first region including WLD circuitry 814 and SA circuitry 816 at least partially overlaps with the second region including memory block 806, i.e., the overlap of the first region and the second region is in the vertical direction. In some embodiments, the first region may include a first sub-region having a WLD circuitry 814 and a second sub-region each having an SA circuitry 816. In some embodiments, when viewed with the peripheral circuitry and memory blocks stacked in the vertical direction, the first sub-region having a WLD circuitry 814 may be located between two adjacent memory blocks 806. In some embodiments, the first sub-region may not overlap with the second region having memory block 806. In some embodiments, when viewed with the peripheral circuitry and memory blocks stacked vertically, the second sub-region having an SA circuit 816 may at least partially overlap with the second region having the memory block 806. In some embodiments, the second sub-region may completely overlap with the second region having the memory block 806.

[0109] Figure 9 This is a plan view of a portion of a memory device 900, including the memory structure and the peripheral circuitry stacked on the memory structure. The memory structure may include multiple memory banks, and each memory bank may include an array of memory groups 908. Figure 9 A pair of first memory groups 910, a pair of second memory groups 912, and a pair of third memory groups 914 are shown.

[0110] The peripheral circuit structure may include an X-decoder circuit 902 located between adjacent memory banks, and may include a pre-charge voltage driver circuit 904 and a discharge voltage driver circuit 906 coupled to the memory bank 908. Since both the pre-charge voltage driver circuit 904 and the discharge voltage driver circuit 906 are located in the space between adjacent memory banks, the X-decoder circuit 902 can occupy a relatively large area. It should be noted that... Figure 9Interconnects extending continuously from the X decoder circuit 902 through rows having memory groups 910, 912, and 914 are shown. In some embodiments, each precharge voltage driver circuit 904 is configured to provide a precharge voltage to a word line corresponding to at least one memory block in one of the plurality of memory groups. In some embodiments, each discharge voltage driver circuit 906 is configured to provide a discharge voltage to a word line corresponding to at least one memory block in one of the plurality of memory groups. By distributing the functions of the precharge voltage driver circuit 904 and the discharge voltage driver circuit 906 across the available space in the memory group according to various embodiments of this disclosure, the area consumed by the X decoder circuit is reduced. This efficient area arrangement can reduce the size of the memory array structure.

[0111] Figure 10A This is a plan view of a portion of a memory device 1000. The memory device 1000 includes a memory array structure and peripheral structures bonded thereto, such that they are stacked vertically on top of each other. The memory array structure includes memory blocks, which in turn include memory cells. The peripheral structures include circuitry (e.g., but not limited to CMOS circuitry) and interconnects. Electrical signals pass through bonding contacts (see...). Figure 1A-1D It is passed between the peripheral structure and the memory array structure.

[0112] According to this disclosure, the memory device 1000 includes an X decoder circuit 1002 and an array of memory groups 1004. It should be noted that... Figure 10A A single-row memory group 1004 in an array is shown for simple illustrative implementation and description. Although in Figure 10A A single row is shown and described herein, but various other embodiments according to this disclosure are not limited to any particular number of rows. The array 1004 of memory groups includes a first memory group 1006, a second memory group 1008, and a third memory group 1010. Each memory group includes at least one memory block. Embodiments according to this disclosure are not limited to having three memory groups, and various embodiments may have more or fewer memory groups. Furthermore, memory groups in any particular embodiment may have the same or different numbers of memory blocks.

[0113] Still refer to Figure 10AThe first memory group 1006 may be coupled to WLD circuits 100-O, 100-E, 101-O, and 101-E, and to a first memory group driver circuit. In some embodiments, the first memory group driver circuit may include a precharge voltage driver circuit 1012 and a discharge voltage driver circuit 1014 coupled to WLD circuit 614, and may be located between column_0 (including odd WLD circuits 100-O and even WLD circuits 100-E) and column_1 (including odd WLD circuits 101-O and even WLD circuits 101-E) of the WLD circuit.

[0114] The second memory bank 1008 may be coupled to column 2 of the WLD circuit (including odd WLD circuit 102-0 and even WLD circuit 102-E) and to the second memory bank driver circuit. In some embodiments, the second memory bank driver circuit may include a precharge voltage driver circuit 1020 and a discharge voltage driver circuit 1022, and may be located between the odd WLD circuit 102-0 and the even WLD circuit 102-E.

[0115] The third memory bank 1010 may be coupled to WLD circuits 103-O, 103-E, 104-O, and 104-E, and may also be coupled to a third memory bank driver circuit. In some embodiments, the third memory bank driver circuit may include a precharge voltage driver circuit 1026 and a discharge voltage driver circuit 1028, and may be located between column 3 (including odd WLD circuits 103-O and even WLD circuits 103-E) and column 4 (including odd WLD circuits 104-O and even WLD circuits 104-E) of the WLD circuit.

[0116] like Figure 10A As shown, the precharge voltage driver circuits 1012, 1020, and 1026 are positioned vertically overlapping the memory bank, rather than as... Figure 9 The setup shown is within the X decoder circuitry. Similarly, the discharge voltage driver circuits 1014, 1022, and 1028 are positioned vertically overlapping the memory bank, rather than as shown... Figure 9The circuit is shown to be located within the X decoder circuit. In other words, the projection of the first memory group driver circuit, including the precharge voltage driver circuit 1012 and the discharge voltage driver circuit 1014, can partially overlap with the first memory group 1006 in the lateral plane; the projection of the second memory group driver circuit, including the precharge voltage driver circuit 1020 and the discharge voltage driver circuit 1022, can partially overlap with the second memory group 1008 in the lateral plane; and the projection of the third memory group driver circuit, including the precharge voltage driver circuit 1026 and the discharge voltage driver circuit 1028, can partially overlap with the third memory group 1010 in the lateral plane.

[0117] Figure 10B This is an enlarged plan view of the first memory bank 1006 according to the present disclosure. In this illustrative embodiment, the first memory bank 1006 includes a first memory block (memory block 0), a second memory block (memory block 1), a third memory block (memory block 2), and a first portion of a fourth memory block (i.e., the first portion of memory block 3). According to the present disclosure, memory bank driver interconnects 1016a, 1016b, 1018a, and 1018b coupled to the first memory bank driver circuitry including a pre-charge voltage driver circuitry 1012 and a discharge voltage driver circuitry 1014 can be connected to only odd-numbered or only even-numbered word lines (i.e., only odd-numbered or only even-numbered word lines), while memory bank driver interconnects coupled to adjacent group driver circuitry of adjacent rows of memory banks can be connected to only the opposite only even-numbered or only odd-numbered word lines. It should be noted that with Figure 9 The configuration shown is different; memory group driver interconnects 1016a, 1016b, 1018a, and 1018b do not extend beyond the boundary of memory group 1006 to other memory groups. Memory group driver interconnects 1016a, 1016b, 1018a, and 1018b occupy a set of horizontal wiring channels.

[0118] Figure 10C This is an enlarged plan view of the second memory bank 1008 according to the present disclosure. The second memory bank 1008 includes a second portion of a fourth memory block (i.e., the second portion of memory block 3), a fifth memory block (memory block 4), and a first portion of a sixth memory block (i.e., the first portion of memory block 5). According to the present disclosure, memory bank driver interconnects 1022a, 1022b, 1024a, and 1024b coupled to the second memory bank driver circuitry including precharge voltage driver circuitry 1020 and discharge voltage driver circuitry 1022 can be connected to only odd-numbered or only even-numbered word lines (i.e., only odd-numbered or only even-numbered word lines), while memory bank driver interconnects coupled to adjacent group driver circuitry of adjacent rows of memory banks can be connected to only the opposite only even-numbered or only odd-numbered word lines. It should be noted that with Figure 9 The configuration shown is different; memory group driver interconnects 1022a, 1022b, 1024a, and 1024b do not extend beyond the boundary of memory group 1008 to other memory groups. Memory group driver interconnects 1022a, 1022b, 1024a, and 1024b occupy a set of horizontal wiring channels.

[0119] Figure 10D This is an enlarged plan view of the third memory bank 1010 according to the present disclosure. The third memory bank 1010 includes a second portion of a sixth memory block (i.e., the second portion of memory block 5), a seventh memory block (memory block 6), an eighth memory block (memory block 7), and a ninth memory block (memory block 8). According to the present disclosure, memory bank driver interconnects 1030a, 1030b, 1032a, and 1032b coupled to the third memory bank driver circuitry including a pre-charge voltage driver circuitry 1026 and a discharge voltage driver circuitry 1028 are coupled to WLD circuitry that can be connected to only odd-numbered or only even-numbered lines (i.e., only odd-numbered lines or only even-numbered lines) in the word lines, while memory bank driver interconnects coupled to adjacent group driver circuitry of adjacent rows of memory banks can be connected to only the opposite only even-numbered or only odd-numbered lines. It should be noted that with Figure 9 The configuration shown is different; memory group driver interconnects 1030a, 1030b, 1032a, and 1032b do not extend beyond the boundary of memory group 1010 to other memory groups. Memory group driver interconnects 1030a, 1030b, 1032a, and 1032b occupy a set of horizontal wiring channels.

[0120] refer to Figure 10B-10D The memory group driver interconnects of the first memory group 1006 occupy the same horizontal routing path as the memory group driver interconnects of the second memory group 1008, and also occupy the same horizontal routing path as the memory group driver interconnects of the third memory group 1010. Even though the memory group driver interconnects of the first, second, and third memory groups occupy the same horizontal routing path, they are not connected to each other. That is, each set of memory group driver interconnects is contained within the boundary of its respective memory group (see [link to relevant documentation]). Figure 10A Therefore, the number of horizontal wiring channels required per row of memory can be reduced.

[0121] Figure 11-13 Various configurations of the Y decoder circuitry, sense amplifier circuitry, word line driver circuitry, and regions (referred to herein as junction areas) for implementing memory group driver circuitry (e.g., precharge voltage driver circuitry and discharge voltage driver circuitry) are shown according to this disclosure. Figure 11A configuration 1100 is shown, including a Y decoder 1101, a first subset 1102a of word line driver circuitry, a second subset 1102b of word line driver circuitry, a memory bank driver 1103, and a sense amplifier circuit 1104. In configuration 1100, the Y decoder 1101, the memory bank driver 1103, and the sense amplifier circuit 1104 are sandwiched between the first subset 1102a and the second subset 1102b of word line driver circuitry. Furthermore, in configuration 1100, the memory bank driver 1103 is sandwiched between the sense amplifier circuit 1104 and the Y decoder 1101. In some embodiments, the Y decoder 1101, the memory bank driver 1103, and the sense amplifier circuit 1104 overlap with the corresponding memory blocks in the vertical direction. That is, in the lateral plane, the projections of the Y decoder 1101, the memory bank driver 1103, and the sense amplifier circuit 1104 can be completely covered by the projections of the corresponding memory blocks. In some embodiments, word line driver circuits 1102a and 1102b may be located between adjacent memory blocks in a vertical view. That is, in a horizontal plane, the projections of word line driver circuits 1102a and 1102b do not overlap with the projections of the memory blocks.

[0122] Figure 12 An alternative configuration 1200 is shown, comprising a Y decoder 1101, a first subset 1102a of word line driver circuitry, a second subset 1102b of word line driver circuitry, a memory bank driver 1103, and a first portion 1204a and a second portion 1204b of sense amplifier circuitry. In configuration 1200, the Y decoder 1101, the memory bank driver 1103, the first portion 1204a of sense amplifier circuitry, and the second portion 1204b of sense amplifier circuitry are sandwiched between the first subset 1102a and the second subset 1102b of word line driver circuitry. Furthermore, in configuration 1200, the Y decoder 1101 and the memory bank driver 1103 are sandwiched between the first portion 1204a of sense amplifier circuitry and the second portion 1204b of sense amplifier circuitry. In some embodiments, the Y decoder 1101, memory group driver 1103, and sense amplifier circuits 1204a and 1204b overlap with the corresponding memory blocks in the vertical direction. That is, in the lateral plane, the projections of the Y decoder 1101, memory group driver 1103, and sense amplifier circuits 1204a and 1204b can be completely covered by the projection of the corresponding memory blocks. In some embodiments, word line driver circuits 1102a and 1102b can be located between adjacent memory blocks in a vertical view. That is, in the lateral plane, the projections of word line driver circuits 1102a and 1102b do not overlap with the projection of the memory blocks.

[0123] Figure 13 An alternative configuration 1300 is shown, including a Y decoder 1101, a first subset 1304a of word line driver circuitry, a second subset 1304b of word line driver circuitry, a first portion 1302a of sense amplifier circuitry, and a second portion 1302b of sense amplifier circuitry. In configuration 1300, the Y decoder 1101 and the memory bank driver 1103 are sandwiched between the first subset 1304a and the second subset 1304b of word line driver circuitry. Furthermore, in configuration 1300, the Y decoder 1101 and the memory bank driver 1103, the first subset 1304a and the second subset 1304b of word line driver circuitry are sandwiched between the first portion 1302a and the second portion 1302b of sense amplifier circuitry. In some embodiments, the Y decoder 1101, the memory bank driver 1103, and portions 1302a and 1302b of the sense amplifier circuitry overlap with corresponding memory blocks in a vertical direction. Some other portions of the sense amplifier circuits 1302a and 1302b may be located between memory blocks in a vertical view. That is, in a horizontal plane, the projections of the Y decoder 1101 and the memory bank driver 1103 can be completely covered by the projections of the corresponding memory blocks. In a horizontal plane, the projections of the first portion 1302a and the second portion 1302b of the sense amplifier circuits may be partially covered by the projections of the corresponding memory blocks. In some embodiments, when viewed vertically, the word line driver circuits 1304a and 1304b may be located between adjacent memory blocks. That is, in a horizontal plane, the projections of the word line driver circuits 1304a and 1304b do not overlap with the projections of the memory blocks.

[0124] Figure 14 It shows something similar to Figure 10A The memory device 1400 is shown, but buffers 1402 and 1404, and interconnects 1401, 1403, and 1405 for the inputs and outputs of those buffer circuits are also shown. More specifically, interconnect 1401 provides an input to buffer 1402; interconnect 1403 couples the output of buffer 1402 to the input of buffer 1404; and interconnect 1405 carries the output of buffer 1404. In this illustrative example, buffers 1402 and 1404 are added at predetermined intervals to ensure that the timing of control signals arrives at each memory bank in a timely manner.

[0125] Figure 15This is a flowchart of a method 1500 for manufacturing a memory device. Method 1500 includes forming a memory array structure 1502 comprising a plurality of memory banks, each memory bank comprising a plurality of memory groups, each memory group having at least one memory block. Each memory block comprises a plurality of memory cells. Many well-known memory cell circuits and a wide variety of physical layouts for memory cell circuits exist. Various embodiments of this disclosure can correspondingly utilize various memory cell circuit designs and physical layouts for those memory cell circuits. The design choices regarding memory cell circuits and layouts can depend on many factors, including but not limited to the manufacturing processes available for producing the memory array structure. Memory cells according to this disclosure are not limited to any particular circuit design, physical layout, or manufacturing process. In some embodiments, the memory cell is a DRAM cell. In some embodiments, the memory cell is a 1T1C memory cell.

[0126] Still refer to Figure 15 Method 1500 further includes forming a peripheral structure 1504. The peripheral structure can be fabricated using the same or a different process than that used to fabricate the memory array structure. In some embodiments, the peripheral structure is fabricated using a CMOS process. Forming the peripheral structure includes forming a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups.

[0127] Still refer to Figure 15 Method 1500 further includes bonding 1506 the memory array structure and the peripheral structure such that each memory group driver circuit is coupled to the word line of at least one memory block corresponding to one of the multiple memory groups, and overlaps with one of the memory blocks in the vertical direction. In some embodiments, the memory array structure and the peripheral structure are bonded to each other by hybrid bonding.

[0128] Figure 16This is a block diagram of illustrative system 1600. System 1600 includes a memory system 1602, which includes one or more memory devices 1604 and a memory controller 1606 coupled to the memory devices 1604. System 1600 also includes a host 1608. Host 1608 can be a computing resource, such as, but not limited to, a computer, personal computer, server, microprocessor system, microcontroller system, multiprocessor system, industrial control system, computer-based consumer electronics system, artificial intelligence (AI) system, automotive electronics system, avionics system, entertainment system, etc. In illustrative system 1600, memory controller 1606 communicates with both memory devices 1604 and host 1608. Memory controller 1606 provides control signals to memory devices 1604, transfers data to be written from host 1608 to memory devices 1604, and transfers data to be read from memory devices 1604 to host 1608. In some systems, the transfer of data from memory device 1604 to host 1608 is referred to as a "load" operation, and the transfer of data from host 1608 to memory device 1604 is referred to as a "store" operation. Memory controller 1606 can be configured to control memory operations such as read, write, and refresh operations. Memory controller 1606 can also be configured to manage various functions regarding data stored or to be stored in memory device 1604, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, memory controller 1606 is also configured to determine the maximum memory capacity available to host 1608, the number of memory banks, the memory type and speed, and other parameters. Any other suitable functions may also be performed by memory controller 1606. Memory controller 1606 can communicate with external devices (e.g., host 1608) according to specific communication protocols. For example, the memory controller 1606 can communicate with external devices through at least one of various interface protocols, such as, but not limited to, Universal Serial Bus (USB) protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0129] Figures 17A-17B This is a flowchart of a method 1700 for forming a memory device according to the present disclosure. More specifically, method 1700 provides a peripheral structure for a memory device according to the present disclosure. Figure 17AAs shown, method 1700 includes forming 1702 a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups. Method 1700 further includes forming 1704 a plurality of first memory group driver interconnects, the plurality of first memory group driver interconnects being configured to couple between even-numbered lines of at least one memory block corresponding to one of the plurality of memory groups on a first side of each memory group driver circuit. Method 1700 further includes forming 1706 a plurality of second memory group driver interconnects, the plurality of second memory group driver interconnects being configured to couple between odd-numbered lines of at least one memory block corresponding to one of the plurality of memory groups on a second side of each memory group driver circuit. Method 1700 further includes arranging 1708 subsets of the plurality of memory groups in a row along a first lateral direction. Method 1700 further includes arranging 1710 the plurality of first memory group driver interconnects and the plurality of second memory group driver interconnects in a subset of the same horizontal wiring channels along the first lateral direction.

[0130] like Figure 17B As shown, method 1700 further includes forming 1712 a plurality of word line driver circuits, a plurality of Y decoder circuits, and a plurality of sense amplifier circuits, such that after the memory array structure and the peripheral structure are bonded together, the plurality of word line driver circuits are located between adjacent memory blocks, a first subset of the word line driver circuits are connected to even number lines, a second subset of the word line driver circuits are connected to odd number lines, each Y decoder circuit overlaps with a corresponding memory block in the vertical direction, and each sense amplifier circuit overlaps at least partially with a corresponding memory block in the vertical direction.

[0131] Still refer to Figure 17B Method 1700 further includes arranging at least one of the plurality of sense amplifier circuits, a first Y decoder circuit of the plurality of Y decoder circuits, and a memory bank driver circuit 1714 in a first lateral direction sandwiched between a first subset of word line driver circuits and a second subset of word line driver circuits. Furthermore, method 1700 further includes arranging a memory bank driver circuit 1716 in a second lateral direction perpendicular to the first lateral direction sandwiched between at least one sense amplifier circuit and the first Y decoder circuit.

[0132] Figures 18A-18B This is a flowchart of a method 1800 for forming a memory device according to the present disclosure. More specifically, method 1800 provides an alternative layout for the peripheral structure of a memory device according to the present disclosure. Figure 18AAs shown, method 1800 includes forming 1802 a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups. Method 1800 further includes forming 1804 a plurality of first memory group driver interconnects, the plurality of first memory group driver interconnects being configured to couple between even-numbered lines of at least one memory block corresponding to one of the plurality of memory groups on a first side of each memory group driver circuit. Method 1800 further includes forming 1806 a plurality of second memory group driver interconnects, the plurality of second memory group driver interconnects being configured to couple between odd-numbered lines of at least one memory block corresponding to one of the plurality of memory groups on a second side of each memory group driver circuit. Method 1800 further includes arranging 1808 subsets of the plurality of memory groups in a row along a first lateral direction. Method 1800 further includes arranging 1810 the plurality of first memory group driver interconnects and the plurality of second memory group driver interconnects along the first lateral direction in a subset of the same horizontal wiring channels.

[0133] like Figure 18B As shown, method 1800 further includes forming 1812 a plurality of word line driver circuits, a plurality of Y decoder circuits, and a plurality of sense amplifier circuits, such that after the memory array structure and the peripheral structure are bonded together, the plurality of word line driver circuits are located between adjacent memory blocks, a first subset of the word line driver circuits are connected to even-number lines, a second subset of the word line driver circuits are connected to odd-number lines, each Y decoder circuit overlaps with a corresponding memory block in the vertical direction, and each sense amplifier circuit at least partially overlaps with a corresponding memory block in the vertical direction. Method 1800 further includes arranging at least one sense amplifier circuit of the plurality of sense amplifier circuits, a first Y decoder circuit of the plurality of Y decoder circuits, and a memory group driver circuit 1814 sandwiched between the first subset and the second subset of the word line driver circuits in a first lateral direction. Moreover, method 1800 further includes arranging a memory group driver circuit and a first Y decoder circuit 1816 sandwiched between a first portion and a second portion of at least one sense amplifier circuit in a second lateral direction perpendicular to the first lateral direction.

[0134] Figures 19A-19B This is a flowchart of a method 1900 for forming a memory device according to the present disclosure. More specifically, method 1900 provides another alternative layout for the peripheral structure of a memory device according to the present disclosure. Figure 19AAs shown, method 1900 includes forming 1902 a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups. Method 1900 further includes forming 1904 a plurality of first memory group driver interconnects, the plurality of first memory group driver interconnects being configured to couple between even-numbered lines of at least one memory block corresponding to one of the plurality of memory groups on a first side of each memory group driver circuit. Method 1900 further includes forming 1906 a plurality of second memory group driver interconnects, the plurality of second memory group driver interconnects being configured to couple between odd-numbered lines of at least one memory block corresponding to one of the plurality of memory groups on a second side of each memory group driver circuit. Method 1900 further includes arranging subsets of the plurality of memory groups in a row 1908 along a first lateral direction. Method 1900 further includes arranging the plurality of first memory group driver interconnects and the plurality of second memory group driver interconnects in the same horizontal routing channel subset 1910 along the first lateral direction. Method 1900 further includes forming 1912 multiple word line driver circuits, multiple Y decoder circuits, and multiple sense amplifier circuits, such that after the memory array structure and the peripheral structure are bonded together, the multiple word line driver circuits are located between adjacent memory blocks, a first subset of the word line driver circuits are connected to even number lines, a second subset of the word line driver circuits are connected to odd number lines, each Y decoder circuit overlaps with a corresponding memory block in the vertical direction, and each sense amplifier circuit overlaps at least partially with a corresponding memory block in the vertical direction.

[0135] refer to Figure 19B Method 1900 further includes arranging a first Y decoder circuit and a memory bank driver circuit in a plurality of Y decoder circuits, 1914, sandwiched in a first lateral direction between a first subset of word line driver circuits and a second subset of word line driver circuits. Furthermore, method 1900 further includes arranging the plurality of word line driver circuits, a memory bank driver circuit, and the first Y decoder circuit in a plurality of word line driver circuits, 1916, sandwiched in a second lateral direction perpendicular to the first lateral direction between a first portion of a sense amplifier circuit and a second portion of a sense amplifier circuit.

[0136] The foregoing description of specific embodiments is intended to reveal the general nature of this disclosure so that others may readily modify and / or adapt these specific embodiments to various applications by applying knowledge of the art, without excessive experimentation and without departing from the overall conception of this disclosure. Therefore, such adaptations and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments, based on the teachings and guidance provided herein. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on these teachings and guidance.

[0137] The embodiments of this disclosure have been described above using functional building blocks, which illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries can be defined as long as the specific functions and their relationships are properly implemented.

[0138] The summary and abstract may set forth one or more, but not all, embodiments of this disclosure conceived by one or more inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0139] The scope and extent of this disclosure should not be limited by any of the illustrative embodiments described above, but should be defined solely by the appended claims and their equivalents.

[0140] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged with each other and in a manner consistent with the scope of this disclosure.

Claims

1. A memory device, comprising: A memory array structure, the memory array structure comprising multiple memory cells, each memory cell comprising multiple memory groups, each memory group having at least one memory block; as well as The peripheral structure is stacked vertically with the memory array structure and includes multiple memory group driver circuits, each corresponding to one of the multiple memory groups. Each memory group driver circuit is coupled to the word line of at least one memory block in one of the plurality of memory groups, and overlaps with one of the memory blocks in the vertical direction.

2. The memory device according to claim 1, wherein, Each memory bank driver circuit includes: A precharge voltage driver circuit configured to provide a precharge voltage to the word line of at least one memory block corresponding to one of the plurality of memory groups.

3. The memory device according to claim 2, wherein, Each memory bank driver circuit also includes: A discharge voltage driver circuit configured to provide a discharge voltage to the word line of at least one memory block corresponding to one of the plurality of memory groups.

4. The memory device according to claim 3, wherein, One of the memory bank driver circuits in the memory bank driver circuit includes: A buffer circuit is configured to buffer the control signals of the precharge voltage driver circuit or the discharge voltage driver circuit.

5. The memory device according to claim 4, wherein, The peripheral structure also includes: Multiple memory group driver interconnects, wherein the multiple memory group driver interconnects are coupled to only odd-numbered or only even-numbered lines in the corresponding memory group driver circuits and word lines.

6. The memory device according to claim 5, wherein: Subsets of the plurality of memory groups are arranged in rows along a first lateral direction; and The memory group driver interconnects coupled to the memory group driver circuitry of the subset of the plurality of memory groups are arranged along the first lateral direction in the same horizontal wiring channel subset.

7. The memory device according to claim 6, wherein, The number of horizontal routing channels in the subset of identical horizontal routing channels depends on the number of word lines in each memory block and is independent of the number of memory groups in the subset of the plurality of memory groups.

8. The memory device according to claim 6, wherein, The peripheral structure also includes: A first word line driver circuit and a second word line driver circuit, wherein the first word line driver circuit is located on a first side of a memory block and coupled to even-number lines, and the second word line driver circuit is located on a second side of the memory block opposite to the first side and coupled to odd-number lines. A Y-decoder circuit, the Y-decoder circuit overlapping the one memory block in the vertical direction; and A readout amplifier circuit that at least partially overlaps with one of the memory blocks in the vertical direction.

9. The memory device according to claim 8, wherein: The sense amplifier circuit, the Y decoder circuit, and a memory group driver circuit are arranged in the first lateral direction between the first word line driver circuit and the second word line driver circuit, and The memory group driver circuit is arranged between the sense amplifier circuit and the Y decoder circuit in a second lateral direction perpendicular to the first lateral direction.

10. The memory device according to claim 8, wherein: The sense amplifier circuit, the Y decoder circuit, and a memory group driver circuit are arranged in the first lateral direction between the first word line driver circuit and the second word line driver circuit, and The memory bank driver circuit and the Y decoder circuit are arranged in a second lateral direction perpendicular to the first lateral direction between the first portion of the sense amplifier circuit and the second portion of the sense amplifier circuit.

11. The memory device according to claim 8, wherein: The Y decoder circuit and a memory group driver circuit are arranged in the first lateral direction between the first word line driver circuit and the second word line driver circuit, and The first word line driver circuit and the second word line driver circuit, the memory group driver circuit, and the Y decoder circuit are arranged in a second lateral direction perpendicular to the first lateral direction between the first portion of the sense amplifier circuit and the second portion of the sense amplifier circuit.

12. The memory device according to claim 6, wherein, The peripheral structure also includes at least one X decoder circuit coupled to the buffer circuit. The first X decoder circuit in the at least one X decoder circuit is located on the peripheral structure and is vertically offset relative to the region of the memory array structure located between two laterally adjacent memory cells.

13. The memory device according to claim 1, wherein, Each memory block comprises multiple memory cells, and each memory cell comprises at least one vertical transistor and at least one vertical capacitor.

14. A method of forming a memory device, comprising: A memory array structure comprising multiple memory cells is formed, wherein each memory cell comprises multiple memory groups, and each memory group has at least one memory block; Forming a peripheral structure, the peripheral structure includes forming a plurality of memory group driver circuits, each of the plurality of memory group driver circuits corresponding to one of the plurality of memory groups; as well as The memory array structure and the peripheral structure are bonded such that each memory group driver circuit is coupled to the word line of at least one memory block of a corresponding memory group in the plurality of memory groups, and overlaps with one of the memory blocks in the vertical direction.

15. The method according to claim 14, wherein, The circuitry forming each memory bank driver includes: A precharge voltage driver circuit is formed, the precharge voltage driver circuit being configured to provide a precharge voltage to the word line of at least one memory block corresponding to one of the plurality of memory groups.

16. The method according to claim 15, wherein, The circuitry forming each memory bank driver also includes: A discharge voltage driver circuit is formed, the discharge voltage driver circuit being configured to provide a discharge voltage to the word line of at least one memory block corresponding to one of the plurality of memory groups.

17. The method according to claim 16, wherein, One of the memory bank driver circuits forming the memory bank driver circuit includes: A buffer circuit is formed, which is configured to buffer the control signals of the precharge voltage driver circuit or the discharge voltage driver circuit.

18. The method according to claim 17, wherein, The formation of the peripheral structure also includes: Multiple memory group driver interconnects are formed, and the multiple memory group driver interconnects are coupled to only odd-numbered or only even-numbered word lines in the corresponding memory group driver circuits and word lines.

19. The method of claim 18, wherein: Forming the memory array structure includes arranging a subset of the plurality of memory groups in a row along a first lateral direction; and The peripheral structure also includes the memory group driver interconnects coupled to the memory group driver circuitry of the subset of the plurality of memory groups, which are arranged along the first lateral direction in the same horizontal wiring channel subset.

20. The method according to claim 19, wherein, The number of horizontal routing channels in the subset of identical horizontal routing channels depends on the number of word lines in each memory block and is independent of the number of memory groups in the subset of the plurality of memory groups.

21. The method according to claim 19, wherein, The formation of the peripheral structure also includes: This forms multiple word line driver circuits, multiple Y decoder circuits, and multiple sense amplifier circuits. In this configuration, after the memory array structure and the peripheral structure are bonded, the plurality of word line driver circuits are located between adjacent memory blocks, each Y decoder circuit overlaps with a corresponding memory block in the vertical direction, and each sense amplifier circuit at least partially overlaps with a corresponding memory block in the vertical direction.

22. The method according to claim 21, wherein, The formation of the peripheral structure also includes: At least one of the plurality of sense amplifier circuits, a first Y decoder circuit of the plurality of Y decoder circuits, and a memory group driver circuit are arranged in the first lateral direction between the first word line driver circuit and the second word line driver circuit; and The memory group driver circuit is arranged in a second lateral direction perpendicular to the first lateral direction, between the at least one sense amplifier circuit and the first Y decoder circuit.

23. The method according to claim 21, wherein, The formation of the peripheral structure also includes: At least one of the plurality of sense amplifier circuits, a first Y decoder circuit of the plurality of Y decoder circuits, and a memory group driver circuit are arranged in the first lateral direction between the first word line driver circuit and the second word line driver circuit; and The memory group driver circuit and the first Y decoder circuit are arranged in a second lateral direction perpendicular to the first lateral direction, between the first portion of the at least one sense amplifier circuit and the second portion of the at least one sense amplifier circuit.

24. The method according to claim 21, wherein, The formation of the outer structure also includes: The first Y decoder circuit and a memory group driver circuit of the plurality of Y decoder circuits are arranged in the first lateral direction between the first word line driver circuit and the second word line driver circuit; and The first word line driver circuit and the second word line driver circuit, the memory group driver circuit, and the first Y decoder circuit are arranged in a second lateral direction perpendicular to the first lateral direction, between the first portion of the sense amplifier circuit and the second portion of the sense amplifier circuit.

25. The method according to claim 19, wherein, The formation of the peripheral structure also includes: Form at least one X decoder circuit coupled to the buffer circuit. Wherein, after the memory array structure and the peripheral structure are bonded, the first X decoder circuit in the at least one X decoder circuit is located on the peripheral structure and is vertically offset relative to the region of the memory array structure located between two laterally adjacent memory cells.

26. The method according to claim 14, wherein, Each storage block is formed by: Multiple memory cells are formed, each memory cell including at least one vertical transistor and at least one vertical capacitor.

27. A memory system comprising: The memory device includes: A memory array structure, the memory array structure comprising multiple memory cells, each memory cell comprising multiple memory groups, each memory group having at least one memory block; and The peripheral structure is stacked vertically with the memory array structure and includes multiple memory group driver circuits, each corresponding to one of the multiple memory groups. Each memory group driver circuit is coupled to the word line of at least one memory block in one of the plurality of memory groups, and overlaps with one of the memory blocks in the vertical direction; and A memory controller, which is coupled to the memory device and configured to control the memory device.

28. A memory device, comprising: A memory array structure, the memory array structure comprising memory blocks, each memory block comprising a memory cell; as well as A peripheral structure, which is stacked with the memory array structure in the vertical direction, and the peripheral structure includes: A discharge voltage driver circuit, the discharge voltage driver circuit being coupled to the word line of the memory block; and A pre-charge voltage driver circuit, wherein both the pre-charge voltage driver circuit and the discharge voltage driver circuit are coupled to a word line driver. The pre-charge voltage driver circuit and the discharge voltage driver circuit overlap with the storage block in the vertical direction.

Images