Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a semiconductor substrate; an active region including an isolation layer formed in the semiconductor substrate and a protrusion defined by the isolation layer, the protrusion disposed at a higher level than an upper surface of the isolation layer; a first pad and a second pad adapted to cover the protrusion of the active region; a first contact formed in an upper portion of the first pad and a conductive structure in an upper portion of the first contact; and a second contact formed in an upper portion of the second pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0054562, filed on April 24, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of the present invention generally relate to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a buried gate and a method for manufacturing the semiconductor device. Background Technology

[0004] As the integration density of semiconductor devices increases, their active areas also shrink, leading to a decrease in contact margin. Therefore, new solutions are needed to enhance performance characteristics and reliability. Summary of the Invention

[0005] Embodiments of the present invention relate to a semiconductor device capable of ensuring contact margin, and a method for manufacturing the semiconductor device.

[0006] Embodiments of the present invention relate to a semiconductor device capable of improving the electrical characteristics of the device, and a method for manufacturing the semiconductor device.

[0007] According to an embodiment of the present invention, a semiconductor device includes: a semiconductor substrate; an active region including an isolation layer formed in the semiconductor substrate and a protrusion defined by the isolation layer, the protrusion being disposed at a level higher than the upper surface of the isolation layer; a first pad and a second pad adapted to cover the protrusion of the active region; a first contact formed in the upper portion of the first pad and a conductive structure formed in the upper portion of the first contact; and a second contact formed in the upper portion of the second pad.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a semiconductor substrate; an active region including an isolation layer formed in the semiconductor substrate and a protrusion defined by the isolation layer, the protrusion being spaced apart from another protrusion by the isolation layer and disposed at a level higher than the upper surface of the isolation layer; a buried gate structure formed in the semiconductor substrate to pass through the isolation layer and the active region and having an upper surface located at a level lower than the protrusion of the active region; a first pad and a second pad adapted to cover the protrusion of the active region; a first contact formed in the upper portion of the first pad and a conductive structure formed in the upper portion of the first contact; and a second contact formed in the upper portion of the second pad.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a semiconductor substrate; bit line contacts and bit line structures formed in an upper portion of the substrate; bit line pads disposed between the substrate and the bit line contacts; storage node contacts configured to be spaced apart from the bit line structures in the upper portion of the substrate; and storage node pads disposed between the substrate and the storage node contacts.

[0010] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: defining an active region in a substrate, the active region including an isolation layer and a protrusion configured to be spaced apart from another protrusion by the isolation layer at a level higher than the upper surface of the isolation layer; forming a first pad and a second pad adapted to cover the protrusion of the active region; forming an isolation layer between the first pad and the second pad, and forming a low-k layer over the first pad and the second pad; forming a first contact hole exposing the first pad by penetrating the low-k layer over the first pad; sequentially forming a first contact and a conductive structure over the first pad in the first contact hole; forming a second contact hole exposing the second pad by penetrating the low-k layer over the second pad; and forming a second contact adapted to gap-fill the second contact hole.

[0011] These and other features and advantages will become better understood from the following detailed description of the embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0013] Figure 2A and Figure 2B These are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention.

[0014] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A This illustrates a method for manufacturing according to an embodiment of the present invention. Figure 2A A cross-sectional view of the method for the semiconductor device shown.

[0015] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B This illustrates a method for manufacturing according to an embodiment of the present invention. Figure 2B A cross-sectional view of the method for the semiconductor device shown.

[0016] Figure 17A and Figure 17B This is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

[0017] Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A and Figure 31A This illustrates another embodiment of the invention for manufacturing... Figure 17A A cross-sectional view of the method for the semiconductor device shown.

[0018] Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B and Figure 31B This illustrates a method for manufacturing according to yet another embodiment of the invention. Figure 17B A cross-sectional view of the method for the semiconductor device shown.

[0019] Figure 32 This is a plan view illustrating a semiconductor device according to another embodiment of the present invention.

[0020] Figure 33 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Detailed Implementation

[0021] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in various figures and embodiments of the invention.

[0022] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When the first layer is referred to as "on the second layer" or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that there is a third layer between the first layer and the second layer or the substrate.

[0023] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 2A and Figure 2B This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Figure 2A It is along Figure 1 The cross-sectional view taken by line A-A' shown in the figure. Figure 2B It is along Figure 1 The cross-sectional view taken by line B-B' shown in the figure.

[0024] refer to Figure 1 , Figure 2A and Figure 2B The semiconductor device may include multiple memory cells. Each memory cell may include conductive structures disposed at different levels. For example, each memory cell may include a cell transistor that includes a buried word line WL, a bit line BL 133, and a memory element 141 (see [link to documentation]). Figure 2A and Figure 2B ).

[0025] An isolation layer 102 and active regions 103 may be formed in a substrate 101. A plurality of active regions 103 may be defined by the isolation layer 102. Each active region 103 may have a strip shape with a major axis and a minor axis. The active regions 103 may be spaced apart from each other at predetermined intervals. Each active region 103 may have an upper surface located at a level higher than the upper surface of the isolation layer 102. Each active region 103 may include a protrusion 103P disposed at a level higher than the upper surface of the isolation layer 102.

[0026] Substrate 101 may include a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 101 may also include another semiconductor material, such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 may also include a silicon-on-insulator (SOI) substrate.

[0027] A linear buried word line WL extending along a first direction D1 can be formed in the substrate 101. The buried word line WL can be formed by a buried gate structure. The buried gate structure may include a gate electrode 112 and a gate capping layer 113, which are formed on a gate dielectric layer 111 formed on the surface of the gate trench 110 to fill the gate trench 110.

[0028] Specifically, a linear gate trench 110 can be formed in the substrate 101 along a first direction D1 to pass through the active region 103 and the isolation layer 102. The lower surface of the gate trench 110 can be disposed at a level higher than the lower surface of the isolation layer 102. The depth of the gate trench 110 can be shallower than the isolation layer 102. According to another embodiment of the invention, the lower portion of the gate trench 110 can have a curvature. According to another embodiment of the invention, the isolation layer 102 formed along the direction extending from the gate trench 110 can be etched to a predetermined depth to form fins in the active region 103.

[0029] A gate dielectric layer 111 may be formed on the surface of the gate trench 110. A gate electrode 112, filling a portion of the gate trench 110, may be formed on the gate dielectric layer 111. A gate capping layer 113 may be formed on the gate electrode 112 to fill the remaining portion of the gate trench 110. The upper surface of the gate capping layer 113 may be disposed at a level higher than the upper surface of the isolation layer 102.

[0030] The gate dielectric layer 111 may be conformally formed on the lower surface and inner surface of the gate trench 110. The gate dielectric layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include a material with a dielectric constant greater than that of silicon oxide. For example, the high-k material may include a material with a dielectric constant greater than about 3.9. Another example is that the high-k material may include a material with a dielectric constant greater than about 10. Yet another example is that the high-k material may include a material with a dielectric constant of about 10 to 30. The high-k material may include at least one metallic element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be selectively used as high-k materials. The gate dielectric layer 111 may include a metal oxide.

[0031] The gate electrode 112 may have a shape that fills the lower portion of the gate trench 110. The gate electrode 112 may be a low-resistance material to reduce the gate sheet resistance. The gate electrode 112 may include a semiconductor material, a metal-based material, or a combination thereof. The gate electrode 112 may include polysilicon, a metal, a metal nitride, or a combination thereof. For example, the gate electrode 112 may include N-type doped polysilicon, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), ruthenium (Ru), or a combination thereof. According to another embodiment of the invention, the gate electrode 112 may be formed solely of titanium nitride or solely of molybdenum. According to yet another embodiment of the invention, the gate electrode 112 may be formed by a stack of titanium nitride and tungsten (i.e., TiN / W) or a stack of titanium nitride and polysilicon (i.e., TiN / polysilicon).

[0032] According to another embodiment of the present invention, the gate electrode 112 may adopt a dual-gate structure including an upper gate and a lower gate. According to yet another embodiment of the present invention, the gate electrode 112 may adopt a tri-gate structure including an upper gate, a middle gate, and a lower gate.

[0033] According to another embodiment of the present invention, the gate electrode 112 may have a high work function. Here, a high work function may refer to a work function greater than the mid-bandgap work function of silicon. A low work function may refer to a work function less than the mid-bandgap work function of silicon. Specifically, a high work function may have a work function greater than about 4.5 eV, while a low work function may have a work function less than about 4.5 eV. The gate electrode 112 may comprise p-type polycrystalline silicon or nitrogen-rich titanium nitride (TiN).

[0034] According to another embodiment of the present invention, the gate electrode 112 may have an increased high work function. The gate electrode 112 may include metal silicon nitride. The metal silicon nitride may be a silicon-doped metal nitride. The gate electrode 112 may include metal silicon nitride with controlled silicon content. For example, the gate electrode 112 may include tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function, and silicon may be included in titanium nitride to further increase its work function. Titanium silicon nitride may have a controlled silicon content to have an increased high work function. According to another embodiment of the present invention, the gate electrode 112 may include titanium aluminum nitride (TiAlN).

[0035] Gate capping layer 113 can be used to protect gate electrode 112. Gate capping layer 113 can fill the upper portion of gate trench 110 above gate electrode 112. Gate capping layer 113 may include a dielectric material. Gate capping layer 113 may include silicon nitride, silicon oxynitride, or a combination thereof. According to another embodiment of the invention, gate capping layer 113 may include a combination of silicon nitride and silicon oxide. Gate capping layer 113 may include a silicon nitride pad and spin-on dielectric (SOD) material.

[0036] A first impurity region 104 and a second impurity region 105 can be formed on the substrate 101. The first impurity region 104 and the second impurity region 105 can be referred to as the "first source / drain region and the second source / drain region". The first impurity region 104 and the second impurity region 105 can be formed in the protrusion 103P of the active region. The lower portion of the first impurity region 104 and the second impurity region 105 can be disposed at a level higher than the upper surface of the gate electrode 112, but embodiments of the present invention are not limited thereto. The gate electrode 112 and the first impurity region 104 and the second impurity region 105 can constitute a single-cell transistor. The single-cell transistor can improve the short-channel effect through the gate electrode 112 having a buried gate structure.

[0037] First pad 120B and second pad 120S can be formed in the upper part of the first impurity region 104 and the second impurity region 105. First pad 120B and second pad 120S can be used to ensure contact margin with the substrate during subsequent contact processes. First pad 120B can be disposed in the upper part of the first impurity region 104. Second pad 120S can be disposed in the upper part of the second impurity region 105.

[0038] The first pad 120B and the second pad 120S may include semiconductor material. The first pad 120B and the second pad 120S may be selective epitaxial growth (SEG) layers. The first pad 120B and the second pad 120S may be doped SEG material. The first pad 120B and the second pad 120S can be formed simultaneously in a single process.

[0039] A low-k layer 121 may be disposed between the first pad 120B and the second pad 120S. The low-k layer 121 may have a lower dielectric constant than silicon nitride (Si3N4). The low-k layer 121 may include a material layer with a dielectric constant lower than about 3.9. For example, the low-k layer 121 may include SiCO (silicon oxide bonded with carbon). The low-k layer 121 may also be disposed above the first pad 120B and the second pad 120S. The upper surface of the low-k layer 121 may be disposed at a level higher than the upper surfaces of the first pad 120B and the second pad 120S.

[0040] A hard mask 130 can be formed on the low-k layer 121. The hard mask 130 can be used as an etching mask for forming the first contact hole 131. The hard mask 130 may include a material having etching selectivity relative to the low-k layer 121. The hard mask 130 may be disposed below the first conductor 133 disposed between the second contacts 140.

[0041] A first contact 132 may be formed on a first pad 120B. The first contact 132 may be coupled to a first impurity region 104 via the first pad 120B. The first pad 120B may improve the contact margin between the first contact 132 and the first impurity region 104. The first pad 120B may have the same linewidth as the first contact 132 and may have two sidewalls aligned in a direction perpendicular to the substrate. The first contact 132 may be disposed in a first contact hole 131, the lower surface of which is lower than the upper surface of the active region 103. A portion of the first contact 132 may have a linewidth smaller than the diameter of the first contact hole 131. The first contact 132 may include a conductive material. For example, the first contact 132 may be formed of polysilicon or a metallic material. The first contact 132 may be referred to as a 'bit line contact 132'. The first pad 120B may be referred to as a 'bit line contact pad 120B'.

[0042] A conductive structure may be formed on the upper part of the first contact 132. This conductive structure may be referred to as a 'bitline structure'. The conductive structure may include a stacked structure of wires 133 and wire hard masks 134. The wires 133 can be coupled to the first impurity region 104 via the first contact 132 and the first pad 120B.

[0043] Wire 133 and wire hard mask 134 can be along Figure 1The line shape extends in the second direction D2 as shown. Conductive structures can be spaced apart from each other in the first direction D1. A portion of the conductor 133 can be coupled to the first contact 132. The linewidth of the conductor 133 can be the same as the linewidth of the first contact 132. Therefore, the conductor 133 can cover the upper surface of the first contact 132 and extend in one direction. The conductor 133 can include a metallic material. The conductor hard mask 134 can include a dielectric material. The conductor 133 and the conductor hard mask 134 can be referred to as "bit line 133" and "bit line hard mask 134," respectively. The conductor 133 can correspond to... Figure 1 The bit line BL is shown in the diagram.

[0044] Spacer 135 may be formed on the sidewalls of the first pad 120B, the first contact 132, and the conductive structures 133 and 134. Spacer 135 may gap-fill the first contact hole 131, i.e., on the sidewalls of the first pad 120B and the first contact 132, and spacer 135 may also be formed on the sidewalls of the conductor 133 and the conductor hard mask 134. Spacer 135 may be formed as a continuous monolayer. Spacer 135 may include, for example, silicon nitride.

[0045] According to another embodiment of the present invention, spacer 135 may include a spacer structure. For example, the spacer structure may include one selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, low-k materials, and combinations thereof. The spacer structure may include a spacer 135 that gap-fills the first contact hole 131, and spacers 135 disposed on the sidewalls of the conductor 133 and the conductor hard mask 134. The spacer 135 that gap-fills the first contact hole 131 may be referred to as a 'gap-filling spacer'. The spacer 135 disposed on the sidewalls of the conductor 133 and the conductor hard mask 134 may be referred to as a 'bitline spacer'. The bitline spacer 134 may be a single layer or multiple layers. According to another embodiment of the present invention, spacer 135 may further include a low-k material or an air gap.

[0046] A second contact 140 may be disposed between adjacent conductive structures. The second contact 140 may be columnar. The second contact 140 may be disposed on a second pad 120S. The second contact 140 may be coupled to a second impurity region 105 via the second pad 120S. The second pad 120S may improve the contact margin between the second contact 140 and the second impurity region 105. The second contact 140 may include a conductive material, such as, for example, a semiconductor material or a metal material. For example, the semiconductor material may include polysilicon. For example, the metal material may include tungsten (W). According to another embodiment of the invention, the second contact 140 may include a stacked structure of semiconductor material and metal material. According to yet another embodiment of the invention, the second contact 140 may include a stacked structure of semiconductor material, an ohmic contact layer, and metal material. The second contact 140 may be referred to as 'storage node contact 140'.

[0047] refer to Figure 2A A spacer 135 and a low-k layer 121 can be provided between the first pad 120B and the second pad 120S. Therefore, parasitic capacitance and leakage current can be prevented between the conductive structure coupled to the first pad 120B and the second contact 140 coupled to the second pad 120S.

[0048] As described above, according to an embodiment of the present invention, by disposing the first pad 120B and the second pad 120S below the first contact 132 and the second contact 140, a contact margin (or landing margin) between each contact and the substrate 101 can be ensured. By forming the first pad 120B and the second pad 120S above the active region protrusion 130P to cover the active region protrusion 130P, the linewidth of the active region is increased. Therefore, an overlap margin between the first contact 132 and the second contact 140 and the substrate can be ensured. Furthermore, since the etching height of the contact hole used to form each contact can be reduced to the same amount as the height of the first pad 120B and the second pad 120S, the phenomenon of unopened contact holes can be prevented and process margins can be ensured.

[0049] Furthermore, according to an embodiment of the present invention, by applying a low-k layer 121 between the active region protrusion 130P and the first pad 120B and the second pad 120S, parasitic capacitance and leakage current between contacts can be prevented and short circuits between contacts can be prevented.

[0050] Storage element 141 may be formed on second contact 140. Storage element 141 may include a capacitor containing a storage node. The storage node may be columnar, but embodiments of the invention are not limited thereto. Although not shown, dielectric layers and board nodes may be further formed on the storage node. The storage node may also have a cylindrical shape other than columnar. According to another embodiment of the invention, landing pads may be provided between second contact 140 and storage element 141. The landing pads may be spaced apart from each other by interlayer dielectric layers.

[0051] According to another embodiment of the invention, different storage elements may be coupled to the second contact 140.

[0052] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A This illustrates a method for manufacturing according to an embodiment of the present invention. Figure 2A A cross-sectional view of the method for the semiconductor device shown. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B This illustrates a method for manufacturing according to an embodiment of the present invention. Figure 2B A cross-sectional view of the method for the semiconductor device shown. Figure 3A and Figure 3B The same process is shown, only the orientation of the cross-sectional view is different. Similarly, Figure 4A and Figures 4B to 16A The same process is shown in Figure 16B, only the orientation of the cross-sectional view differs. For ease of understanding, the cross-section of the same process is shown below. Figure 1 Let's begin with a description.

[0053] refer to Figure 3A and Figure 3B An isolation layer 12 can be formed on the substrate 11. The active region 13 can be defined by the isolation layer 12. (See reference...) Figure 1Each active region 13 may have a strip with a major axis and a minor axis. The active regions 13 may be set to be spaced apart from each other at predetermined intervals.

[0054] The isolation layer 12 can be formed using a shallow trench isolation (STI) process. The STI process can be performed as follows: The substrate 11 can be etched to form isolation trenches (reference numerals omitted). The isolation trenches can be filled with a dielectric material, thus forming the isolation layer 12. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or another deposition process can be performed to fill the isolation trenches with the dielectric material. A planarization process, such as chemical mechanical polishing (CMP), can also be performed.

[0055] Subsequently, a buried gate structure can be formed on the substrate 11. The buried gate structure can correspond to... Figure 1 The letter line WL is shown in the image. (Reference) Figure 1 The buried gate structure may have a linear shape extending along a first direction D1. The buried gate structure may include a gate trench 15, a gate dielectric layer 16 covering the lower surface and sidewalls of the gate trench 15, a gate electrode 17 filling the lower portion of the gate trench 15 above the gate dielectric layer 16, and a gate capping layer 18 formed above the gate electrode 17 (see [link to documentation]). Figure 4A and Figure 4B ).

[0056] The following methods can be used to form a buried grid structure.

[0057] First, a gate trench 15 can be formed in the substrate 11. The gate trench 15 can have a linear shape passing through the active region 13 and the isolation layer 12. The gate trench 15 can be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. The gate trench 15 can be formed by using a hard mask layer 14 as an etch barrier. The hard mask layer 14 can include silicon oxide. The gate trench 15 can be formed to be shallower than the isolation trench. The lower surface of the gate trench 15 can be disposed at a level higher than the lower surface of the isolation layer 12. The depth of the gate trench 15 can be sufficient to increase the average cross-sectional area of ​​the gate electrode 17. Therefore, the resistance of the gate electrode 17 can be reduced. According to another embodiment of the invention, the bottom edge of the gate trench 15 can be curved. By forming the bottom edge of the gate trench 15 to be curved, the unevenness of the lower part of the gate trench 15 can be minimized, and therefore the gate electrode 17 can be easily filled.

[0058] Although not shown, a fin region can be formed after the gate trench 15 is formed. The fin region can be formed by recessing a portion of the isolation layer 12.

[0059] Subsequently, a gate dielectric layer 16 can be formed on the lower surface and sidewalls of the gate trench 15. Before the formation of the gate dielectric layer 16, etching damage on the surface of the gate trench 15 can be repaired. For example, a sacrificial oxide can be formed by a thermal oxidation process, and then the sacrificial oxide can be removed.

[0060] The gate dielectric layer 16 can be formed by a thermal oxidation process. For example, the bottom and sidewalls of the gate trench 15 can be oxidized to form the gate dielectric layer 16.

[0061] According to another embodiment of the present invention, the gate dielectric layer 16 can be formed by a deposition method. For example, the gate dielectric layer 16 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be selectively used as high-k materials.

[0062] According to another embodiment of the invention, the gate dielectric layer 16 can be formed by depositing a pad polysilicon layer and then completely oxidizing the pad polysilicon layer.

[0063] According to another embodiment of the present invention, the gate dielectric layer 16 can be formed by forming a pad silicon nitride layer and then completely oxidizing the pad silicon nitride layer.

[0064] Subsequently, a gate electrode 17 can be formed on the gate dielectric layer 16. The gate electrode 17 can be formed by forming a conductive layer (not shown) to fill the gate trench 15 and then performing a recess process. The recess process can be performed by performing an etch-back process, or by sequentially performing a chemical mechanical polishing (CMP) process and an etch-back process. The gate electrode 17 can have a recessed shape that fills a portion of the gate trench 15. The upper surface of the gate electrode 17 can be disposed at a level lower than the upper surface of the substrate 11. The gate electrode 17 can include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 17 can include a stack of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). The titanium nitride / tungsten (TiN / W) stack can have a structure formed by conformally forming titanium nitride and then filling a portion of the gate trench 15 with tungsten. According to another embodiment of the invention, the gate electrode 17 can be formed as a single structure of titanium nitride or a stacked structure of titanium nitride. According to another embodiment of the present invention, the gate electrode 17 may further include a work function control layer or a dipole-induced layer located between the gate dielectric layer 16 and the gate electrode 17. According to yet another embodiment of the present invention, the gate electrode 17 may be formed as a stacked structure of heterogeneous materials. According to yet another embodiment of the present invention, the gate electrode 17 may be formed as a stacked structure of heterogeneous materials, but the gate electrode 17 may further include a barrier layer located between the upper gate electrode and the lower gate electrode.

[0065] Subsequently, a cover dielectric material 18A can be formed over the gate electrode 17. The cover dielectric material 18A can be formed to have sufficient height to fill the remaining portion of the gate trench 15 over the gate electrode 17. The cover dielectric material 18A can be formed over the gate electrode 17 and over the first hard mask layer 14. For example, the cover dielectric material 18A may comprise silicon nitride. According to another embodiment of the invention, the cover dielectric material 18A may comprise a NON (nitride-oxide-nitride) multilayer structure.

[0066] refer to Figure 4A and Figure 4B A gate capping layer 18 can be formed on the gate electrode 17 to fill the remaining portion of the gate trench 15. For this purpose, a chemical mechanical polishing (CMP) process or a cleaning process can be performed using the upper surface of the first hard mask layer 14 as an etch stop target.

[0067] Subsequently, a first impurity region 19 and a second impurity region 20 can be formed. The first impurity region 19 and the second impurity region 20 can be formed by a doping process (such as an implantation process). Hereinafter, the first impurity region 19 and the second impurity region 20 may be referred to as "first source / drain region 19 and second source / drain region 20". The first source / drain region 19 and the second source / drain region 20 may have the same depth. According to another embodiment of the invention, the first source / drain region 19 may be deeper than the second source / drain region 20. The first source / drain region 19 may be a region coupled to a bit line contact. The second source / drain region 20 may be a region coupled to a storage contact.

[0068] The unit transistor of the memory cell can be formed by a gate electrode 17, a first source / drain region 19, and a second source / drain region 20.

[0069] refer to Figure 5A and Figure 5B The first hard mask layer 14 can be removed. Subsequently, a recess process 21 can be performed on the isolation layer 13.

[0070] The removal of the first hard mask layer 14 and the recessing process 21 of the isolation layer 13 can be performed as a cleaning process. For example, the cleaning process may include a wet cleaning process or a dry cleaning process. For example, a wet cleaning process can be performed using a hydrofluoric acid (HF) solution.

[0071] Because the isolation layer 13 is recessed to a predetermined depth, the upper surface of the active region 13 can be positioned at a level higher than the upper surface of the isolation layer 12. The active region 13 positioned at a level higher than the upper surface of the isolation layer 12 can be referred to as an active region protrusion 13P. The active region protrusion 13P may include a first source / drain region 19 and a second source / drain region 20. Furthermore, the upper surface of the gate capping layer 18 can also be positioned at a level higher than the upper surface of the isolation layer 12.

[0072] refer to Figure 6A and Figure 6B The first pad 22B and the second pad 22S covering the active region protrusion 13P can be formed on the active region protrusion 13P. The first pad 22B and the second pad 22S can be SEG materials formed by selective epitaxial growth (SEG) process. For example, the first pad 22B and the second pad 22S can be doped SEG materials.

[0073] Since the first pad 22B and the second pad 22S are formed to cover the active region protrusion 13P, the linewidth of the active region protrusion 13P can be increased. Because the first pad 22B and the second pad 22S respectively cover the sidewall and top surface of the active region protrusion 13P, the linewidth can be increased to twice the thickness of each pad 22B and 22S, and the height can be increased to the same extent as the thickness of each pad 22B and 22S.

[0074] Therefore, contact margin (or landing margin) between the contact and the substrate 11 can be ensured during subsequent processes for forming the contact. Furthermore, since the contact etching depth is reduced by the same amount as the height of each pad 22B and 22S during the process of etching the contact holes for subsequently formed contact, reduction in process margin and failure of contact holes to open can be prevented.

[0075] refer to Figure 7A and Figure 7B A low-k layer 23 can be formed between the first pad 22B and the second pad 22S. The low-k layer 23 can fill the gaps between adjacent buried gate structures above the first pad 22B. The low-k layer 23 can have an upper surface at the same level as the upper surface of the gate cover layer 18. The upper surface of the low-k layer 23 can be disposed at a level higher than the upper surfaces of the first pad 22B and the second pad 22S.

[0076] The low-k layer 23 can have a lower dielectric constant than silicon nitride (Si3N4). The low-k layer 23 can include a material layer with a dielectric constant less than about 3.9. For example, the low-k layer 23 can include SiCO.

[0077] refer to Figure 8A and Figure 8B A second hard mask layer 24 can be formed over the low-k layer 23 and the gate capping layer 18. The second hard mask layer 24 can serve as an interlayer dielectric layer. The second hard mask layer 24 may include a dielectric material. For example, the second hard mask layer 24 may include silicon oxide, but embodiments of the invention are not limited thereto. The second hard mask layer 24 may be patterned to define a first contact hole region.

[0078] refer to Figure 9A and Figure 9B The low-k layer 23 exposed through the second hard mask layer 24 can be etched to form the first contact hole 25. When the low-k layer 23 is etched, the first pad 22B can remain intact or substantially unchanged without loss due to the selective etching.

[0079] refer to Figure 10A and Figure 10B This can form a gap to fill the first contact hole 25 (see...) Figure 9A and Figure 9BThe preliminary first contact 26A can be formed by a selective epitaxial growth (SEG) process. For example, the preliminary first contact 26A may include SEG SiP. In this way, the preliminary first contact 26A can be formed by a selective epitaxial growth process without voids. According to another embodiment of the invention, the preliminary first contact 26A can be formed by depositing a polysilicon deposit and performing a chemical mechanical polishing (CMP) process. The preliminary first contact 26A may fill the first contact hole 25 (see...). Figure 9A and Figure 9B The upper surface of the initial first contact 26A can be positioned at the same level as the upper surface of the second hard mask layer 24.

[0080] refer to Figure 11A and Figure 11B The conductive layer 27A and the hard mask material layer 28A can be sequentially stacked on the initial first contact 26A and the second hard mask layer 24. The conductive layer 27A can include a metal-containing material. The conductive layer 27A can include a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment of the invention, the conductive layer 27A can include tungsten (W). According to another embodiment of the invention, the conductive layer 27A can include a stack of titanium nitride and tungsten (TiN / W). In this case, titanium nitride can be used as a barrier. The hard mask material layer 28A can be formed of a dielectric material having etching selectivity relative to the conductive layer 27A and the initial first contact 26A. The hard mask material layer 28A can include silicon oxide or silicon nitride.

[0081] refer to Figure 12A and Figure 12B This can form the first contact 26, the wire 27, and the wire hard mask 28.

[0082] Therefore, a mask pattern can be formed on the hard mask material layer 28A (see...). Figure 11A and Figure 11B Then, the hard mask material layer 28A and the conductive layer 27A can be sequentially etched using this mask pattern (see...). Figure 11A and Figure 11B ) and preliminary first contact 26A (see Figure 11A and Figure 11B When the first contact 26A is initially etched, the first pad 22B can also be etched at the same time.

[0083] The first pad 22B, the first contact 26, the conductor 27, and the conductor hard mask 28 may have the same linewidth. The first pad 22B, the first contact 26, the conductor 27, and the conductor hard mask 28 may be referred to as 'bit line pad 22B', 'bit line contact 26', 'bit line 27', and 'bit line hard mask 28', respectively. The bit line 27 and the bit line hard mask 28 may be referred to as a bit line structure.

[0084] The linewidth of the bit line structure can be smaller than the diameter of the first contact hole 25, and a gap G is left around the first contact member 26. The gap G does not need to be formed in a surrounding shape around the first contact member 26, but can be formed independently on the two sidewalls of the bit line contact member 21. Therefore, a first contact member 26 and a pair of gaps G can be provided in the first contact hole 25. The pair of gaps G can be separated from each other by the first contact member 26.

[0085] refer to Figure 13A and Figure 13B This can form a spacer layer 29A. The spacer layer 29A can fill the gaps G (see...). Figure 12A and Figure 12B It covers the two sidewalls and the top of the bitline structure. The spacer layer 29A may be a single layer. The spacer layer 29A may include, for example, silicon nitride.

[0086] According to another embodiment of the invention, the spacer layer 29A may include a multilayer structure comprising two or more layers made of a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, low-k materials and combinations thereof.

[0087] refer to Figure 14A and Figure 14B Spacers 29 can be formed. Spacers 29 may include spacers 29 that fill the gap of the first contact hole 25 and spacers 29 disposed on the sidewalls of the conductor 27 and the conductor hard mask 28. The spacer 29 that fills the gap of the first contact hole 25 may be referred to as a 'gap-filling spacer'. The spacer 29 disposed on the sidewalls of the conductor 27 and the conductor hard mask 28 may be referred to as a 'bitline spacer'. Bitline spacers may be formed as a single layer or multiple layers. According to another embodiment of the invention, spacers 29 may further include a low-k material or an air gap.

[0088] Subsequently, a second contact hole 30 can be formed. The second contact hole 30 can be disposed between adjacent conductive structures. The second contact hole 30 exposing the second pad 22S can be formed by etching the second hard mask layer 24 and the low-k layer 23 between the spacers 29 (i.e., between adjacent conductive structures). By pre-forming the second pad 22S before forming the second contact hole 30, the contact etching height can be reduced to be as much as the thickness of the second pad 22S, and furthermore, the contact margin (or landing margin) between the second impurity region 20 and the subsequent second contact can be ensured to be as much as the thickness of the second pad 22S.

[0089] The second contact hole 30 may have a linear shape extending along the second direction D2. The second contact holes 30 may be spaced apart from each other by conductive structures.

[0090] refer to Figure 15A and Figure 15B This can form a second contact 31 that fills the gap in the second contact hole 30. The second contact 31 can be coupled to the second impurity region 20 via the second pad 22S.

[0091] The second contact 31 can be formed by the following series of processes: forming a plug material layer that fills the gap in the second contact hole 30, performing an etching process in a manner in which the plug material layers are separated and spaced apart from each other in the second direction D2 (see...). Figure 1 To form a plug isolation portion, and then form an isolation layer that fills the gap of the plug isolation portion.

[0092] The second contact 31 may be columnar. The second contact 31 may be disposed on the second pad 22S. The second contact 31 may be coupled to the second impurity region 20 via the second pad 22S. The second pad 22S may improve the contact margin between the second contact 31 and the second impurity region 20. The second contact 31 may include a conductive material. For example, the conductive material may include a semiconductor material or a metallic material. For example, the semiconductor material may include polysilicon. For example, the metallic material may include tungsten (W). According to another embodiment of the invention, the second contact 31 may include a stacked structure of semiconductor material and metallic material. According to yet another embodiment of the invention, the second contact 31 may include a stacked structure of semiconductor material, an ohmic contact layer, and metallic material. The second contact 31 may be referred to as a "storage node contact 31".

[0093] refer to Figure 16A and Figure 16BA storage element 32 can be formed on the second contact 31. The storage element 32 may include a capacitor containing a storage node. The storage node may be columnar, but embodiments of the invention are not limited thereto. Although not shown, a dielectric layer and board nodes may be further formed on the storage node. The storage node may have a cylindrical shape other than a columnar shape. According to another embodiment of the invention, a landing pad may be provided between the second contact 31 and the storage element 32. The landing pads may be spaced apart from each other by an interlayer dielectric layer.

[0094] According to another embodiment of the present invention, different storage elements can be coupled to the second contact 31.

[0095] Figure 17A and Figure 17B This is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Figure 17A and Figure 17B Besides the structure of the gate capping layer and the low-k layer, and with Figure 2A and Figure 2B Most of them are the same. The same reference numerals are given the same structure, and for ease of description, the description of the same structure may be omitted or simplified.

[0096] like Figure 1 , Figure 17A and Figure 17B As shown, for reference Figure 1 , Figure 2A and Figure 2B The semiconductor device may include multiple memory cells. Each memory cell may include conductive structures disposed at different levels. For example, each memory cell may include a cell transistor that includes a buried word line WL, a bit line BL 133, and a storage element 141 (see [link to documentation]). Figure 17A and Figure 17B ).

[0097] An isolation layer 102 and an active region 103 may be formed in the substrate 101. A plurality of active regions 103 may be defined by the isolation layer 102. Each active region 103 may include a protrusion 103P disposed at a level above the upper surface of the isolation layer 102.

[0098] A linear buried word line WL extending along a first direction D1 can be formed on the substrate 101. The buried word line WL can be formed as a buried gate structure. The buried gate structure may include a gate electrode 112 and a gate capping layer 113 formed on the gate dielectric layer 111. The buried gate structure can be formed by filling a gate trench 110 on the surface of the gate dielectric layer 111.

[0099] A gate dielectric layer 111 may be formed on the surface of the gate trench 110. A gate electrode 112 may be formed on top of the gate dielectric layer 111 to fill the lower portion of the gate trench 110. A gate capping layer 113 may be formed on top of the gate electrode 112 to fill the remaining portion of the gate trench 110. The upper surface of the gate capping layer 113 may be disposed at the same level as the upper surface of the isolation layer 102.

[0100] The first impurity region 104 and the second impurity region 105 can be formed on the substrate 101. The first impurity region 104 and the second impurity region 105 can be referred to as the 'first source / drain region' and the 'second source / drain region'. The first impurity region 104 and the second impurity region 105 can be formed in the active region protrusion 103P.

[0101] First pad 120B and second pad 120S can be formed on first impurity region 104 and second impurity region 105, respectively. First pad 120B and second pad 120S can be used to ensure contact margin with the substrate during subsequent contact processes. First pad 120B can be disposed on first impurity region 104. Second pad 120S can be disposed on second impurity region 105.

[0102] The first pad 120B and the second pad 120S may include semiconductor material. The first pad 120B and the second pad 120S may be selectively epitaxial (SEG) layers. The first pad 120B and the second pad 120S may be doped SEG material. The first pad 120B and the second pad 120S can be formed simultaneously in a single process.

[0103] A low-k layer 121 may be disposed above the isolation layer between the first pad 120B and the second pad 120S, and above the gate capping layer 113 between adjacent first pads 120B. The low-k layer 121 may have a dielectric constant less than that of silicon nitride (Si3N4). The low-k layer 121 may include a material layer with a dielectric constant less than about 3.9. For example, the low-k layer 121 may include SiCO. The low-k layer 121 may also be disposed above the first pad 120B and the second pad 120S. The upper surface of the low-k layer 121 may be disposed at a level higher than the upper surfaces of the first pad 120B and the second pad 120S.

[0104] A hard mask 130 can be formed on the low-k layer 121 between the first pad 120B and the second pad 120S. The hard mask 130 can be used as an etching mask for forming the first contact hole 131. The hard mask 130 may include a material with etching selectivity relative to the low-k layer 121. The hard mask 130 may be disposed below the first conductor 133 disposed between the second contacts 140.

[0105] A first contact 132 may be formed on a first pad 120B. The first contact 132 may be coupled to a first impurity region 104 via the first pad 120B. The first pad 120B may improve the contact margin between the first contact 132 and the first impurity region 104. The first pad 120B may have the same linewidth as the first contact 132 and have two sidewalls aligned in a direction perpendicular to the substrate. The first contact 132 may be disposed in a first contact hole 131, the lower surface of which is located at a level lower than the upper surface of the active region 103. A portion of the first contact 132 may have a linewidth smaller than the diameter of the first contact hole 131. The first contact 132 may include a conductive material. For example, the first contact 132 may be formed of polysilicon or a metallic material. The first contact 132 may be referred to as a "bit line contact 132". The first pad 120B may be referred to as a "bit line contact pad 120B".

[0106] A conductive structure can be formed on the first contact 132. This conductive structure can be referred to as a "bitline structure." The conductive structure may include a stacked structure of wires 133 and wire hard masks 134. The wires 133 can be coupled to the first impurity region 104 via the first contact 132 and the first pad 120B.

[0107] The conductor 133 and the conductor hard mask 134 can be referred to as "bit line 133" and "bit line hard mask 134," respectively. The conductor 133 can correspond to... Figure 1 The bit line BL is shown in the diagram.

[0108] Spacer 135 may be formed on the sidewalls of the first pad 120B, the first contact 132, and the conductive structure. Spacer 135 may gap-fill the first contact hole 131, i.e., on the sidewalls of the first pad 120B and the first contact 132, and may also be formed on the sidewalls of the conductor 133 and the conductor hard mask 134. Spacer 135 may be formed as a continuous monolayer. Spacer 135 may include, for example, silicon nitride.

[0109] The second contact 140 can be disposed between adjacent conductive structures. The second contact 140 can be columnar. The second contact 140 can be disposed on the second pad 120S. The second contact 140 can be coupled to the second impurity region 105 through the second pad 120S. The second pad 120S can improve the contact margin between the second contact 140 and the second impurity region 105. The second contact 140 can be referred to as "storage node contact 140".

[0110] Spacer 135 and low-k layer 121 can be disposed between first pad 120B and second pad 120S, and between first pad 120B. Therefore, parasitic capacitance and leakage current can be prevented between the conductive structure coupled to first pad 120B and the second contact 140 coupled to second pad 120S.

[0111] As described above, according to an embodiment of the present invention, by disposing the first pad 120B and the second pad 120S below the first contact 132 and the second contact 140, contact margin (or landing margin) between each contact and the substrate 101 can be ensured. By forming the first pad 120B and the second pad 120S above the active region protrusion 130P to cover the active region protrusion 130P, the linewidth of the active region can be increased. Therefore, the overlap margin between the first contact 132 and the second contact 140 and the substrate can ultimately be ensured. In addition, since the etching height of the contact hole used to form each contact can be reduced to the same amount as the height of the first pad 120B and the second pads 120B and 120S, the phenomenon of unopened contact holes can be prevented and process margin can be ensured.

[0112] In addition, according to an embodiment of the present invention, by applying a low-k layer 121 between the active region protrusion 130P and the first pad 120B and the second pad 120S, and between the first pad 120B, parasitic capacitance and leakage current between contacts and short circuit between contacts can be prevented.

[0113] A storage element 141 may be formed on the second contact 140.

[0114] Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A and Figure 31A This illustrates a method for manufacturing according to another embodiment of the invention. Figure 17A A cross-sectional view of the method for the semiconductor device shown. Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B and Figure 31B This illustrates a method for manufacturing according to another embodiment of the invention. Figure 17B A cross-sectional view of the method for the semiconductor device shown. Figure 18A and Figure 18B The same process is shown, differing only in the orientation of the cross-sectional view. Similarly, Figure 19A and Figures 19B to 31A and Figure 31B The same process is also shown, differing only in the orientation of the cross-sectional view. To aid understanding, cross-sections of the same process are shown. Figure 1 Start describing. Figure 18A and Figures 18B to 31A and Figure 31B The process can be combined with Figure 3A and Figures 3B to 16A and Figure 16B The processes are similar, except for the gate capping layer and the low-k layer. The same structures are given the same reference numerals, and for ease of description, descriptions of the same structures and processes will be omitted or briefly provided.

[0115] refer to Figure 18A and Figure 18B An isolation layer 12 can be formed in the substrate 11. The active region 13 can be defined by the isolation layer 12.

[0116] Subsequently, a buried gate structure can be formed on the substrate 11. The buried gate structure can correspond to... Figure 1 The word line WL is shown in the diagram. The buried gate structure may include a gate trench 15, a gate dielectric layer 16 covering the lower surface and sidewalls of the gate trench 15, a gate electrode 17 filling a portion of the gate trench 15 over the gate dielectric layer 16, and a gate capping layer 18 formed over the gate electrode 17 (see [reference]). Figure 19B ).

[0117] A method for forming a buried gate structure includes first forming a gate trench 15 in a substrate 11. The gate trench 15 may have a linear shape passing through the active region 13 and the isolation layer 12. The gate trench 15 can be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. To form the gate trench 15, a hard mask layer 14 can be used as an etch barrier.

[0118] Although not shown, a fin region can be formed after the gate trench 15 is formed. The fin region can be formed by recessing a portion of the isolation layer 12.

[0119] Subsequently, a gate dielectric layer 16 can be formed on the lower surface and sidewalls of the gate trench 15. Etching damage on the surface of the gate trench 15 can be recovered before the formation of the gate dielectric layer 16. For example, the sacrificial oxide can be removed after forming it via a thermal oxidation process.

[0120] The gate dielectric layer 16 can be formed by a thermal oxidation process. For example, the lower surface and sidewalls of the gate trench 15 can be oxidized to form the gate dielectric layer 16.

[0121] Subsequently, a gate electrode 17 can be formed on the gate dielectric layer 16. The gate electrode 17 can be formed by forming a conductive layer (not shown) to fill the gate trench 15 and then performing a recess process. The recess process can be performed by performing an etch-back process, or by sequentially performing a chemical mechanical polishing (CMP) process and an etch-back process. The gate electrode 17 can have a recessed shape that fills a portion of the gate trench 15. The upper surface of the gate electrode 17 can be disposed at a level lower than the upper surface of the substrate 11. The gate electrode 17 can include a metal, a metal nitride, or a combination thereof.

[0122] Subsequently, a cover dielectric material 18A can be formed over the gate electrode 17. The cover dielectric material 18A can be formed to have sufficient height to fill the remaining portion of the gate trench 15 over the gate electrode 17. The cover dielectric material 18A can be formed over the gate electrode 17 and over the first hard mask layer 14.

[0123] refer to Figure 19A and Figure 19B A gate capping layer 18 can be formed on the gate electrode 17 to fill a portion of the gate trench 15. For this purpose, an etch-back process or a cleaning process can be performed on the capping dielectric material 18A (see [link to documentation]). Figure 18A and Figure 18B ).

[0124] The upper surface of the gate capping layer 18 can be disposed at a lower level than the upper surface of the isolation layer 12 and the upper surface of the active region (i.e., the first impurity region 19 and the second impurity region 20).

[0125] Subsequently, a first impurity region 19 and a second impurity region 20 can be formed. The first and second impurity regions 19 and 20 can be formed by a doping process (e.g., implantation). Hereinafter, the first impurity region 19 and the second impurity region 20 may be referred to as "first source / drain region 19 and second source / drain region 20". The first source / drain region 19 can be the region to which bit line contacts are to be coupled. The second source / drain region 20 can be the region to which storage contacts are to be coupled.

[0126] The unit transistor of the memory cell can be formed by a gate electrode 17, a first source / drain region 19, and a second source / drain region 20.

[0127] refer to Figure 20A and Figure 20B The first hard mask layer 14 can be removed. Subsequently, the isolation layer 13 can be subjected to a recess process 21.

[0128] The removal of the first hard mask layer 14 and the recessing process 21 of the isolation layer 13 can be performed as a cleaning process. For example, the cleaning process may include a wet cleaning process or a dry cleaning process. For example, a hydrogen fluoride (HF) solution can be used to perform a wet cleaning process.

[0129] Because the isolation layer 13 is recessed to a predetermined depth, the upper surface of the active region 13 can be positioned at a level higher than the upper surface of the isolation layer 13. The active region 13 positioned at a level higher than the upper surface of the isolation layer 13 can be referred to as an active region protrusion 13P. The active region protrusion 13P may include a first source / drain region 19 and a second source / drain region 20. Furthermore, the upper surface of the gate capping layer 18 can be positioned at a level higher than the upper surface of the isolation layer 13, but embodiments of the present invention are not limited thereto.

[0130] refer to Figure 21A and Figure 21B A first pad 22B and a second pad 22S can be formed on the active region protrusion 13P, covering the active region protrusion 13P. The first pad 22B and the second pad 22S can be SEG materials formed by selective epitaxial growth (SEG) process. For example, the first pad 22B and the second pad 22S can be doped SEG materials.

[0131] Since the first pad 22B and the second pad 22S are formed to cover the active region protrusion 13P, the linewidth of the active region protrusion 13P can be increased. Because the first pad 22B and the second pad 22S respectively cover the sidewall and top surface of the active region protrusion 13P, the linewidth can be increased to twice the thickness of each pad 22B and 22S, and the height can be increased by the same amount as the thickness of each pad 22B and 22S.

[0132] Therefore, during subsequent processes for forming the contacts, contact margin (or landing margin) between the contacts and the substrate 11 can be ensured. Furthermore, since the contact etching depth is reduced to the same amount as the height of each pad 22B and 22S during the contact hole etching process for subsequent contacts, reduced process margin and the absence of contact holes can be prevented.

[0133] refer to Figure 22A and Figure 22BA low-k layer 23 may be formed between the first pad 22B and the second pad 22S, and between the first pad 22B. The upper surface of the low-k layer 23 may be positioned at a level higher than the upper surfaces of the first pad 22B and the second pad 22S.

[0134] The dielectric constant of the low-k layer 23 can be less than that of silicon nitride (Si3N4). The low-k layer 23 may include a material layer with a dielectric constant less than about 3.9. For example, the low-k layer 23 may include SiCO.

[0135] refer to Figure 23A and Figure 23B A second hard mask layer 24 can be formed over the low-k layer 23 and the gate capping layer 18. The second hard mask layer 24 can be used as an interlayer dielectric layer. The second hard mask layer 24 can be patterned to define the first contact hole region.

[0136] Reference 24A and Figure 24B The low-k layer 23 exposed by the second hard mask layer 24 can be etched to form the first contact hole 25. When the low-k layer 23 is etched, the first pad 22B can remain intact without loss due to the selective etching.

[0137] refer to Figure 25A and Figure 25B This can form a gap to fill the first contact hole 25 (see...) Figure 24A and Figure 24B The initial first contact 26A.

[0138] refer to Figure 26A and Figure 26B The conductive layer 27A and the hard mask material layer 28A can be sequentially stacked on the initial first contact 26A and the second hard mask layer 24.

[0139] refer to Figure 27A and Figure 27B This can form the first contact 26, the wire 27, and the wire hard mask 28.

[0140] Therefore, a mask pattern can be formed on the hard mask material layer 28A (see...). Figure 11A and Figure 11B Furthermore, the hard mask material layer 28A and the conductive layer 27A can be sequentially etched using this mask pattern (see...). Figure 11A and Figure 11B ) and preliminary first contact 26A (see Figure 11A and Figure 11B When the first contact 26A is initially etched, the first pad 22B can also be etched at the same time.

[0141] The first pad 22B, the first contact 26, the conductor 27, and the conductor hard mask 28 may have the same linewidth. The first pad 22B, the first contact 26, the conductor 27, and the conductor hard mask 28 may be referred to as 'bit line pad 22B', 'bit line contact 26', 'bit line 27', and 'bit line hard mask 28', respectively. The bit line 27 and the bit line hard mask 28 may be referred to as a bit line structure.

[0142] The linewidth of the bitline structure can be smaller than the diameter of the first contact hole 25. Therefore, a gap G can be formed on the sidewall of the first contact 26. The gap G may not have a surrounding shape around the first contact 26. The gap G may include two separate gaps formed on the two sidewalls of the bitline contact 21. In each contact hole 25, a first contact 26 and a pair of gaps G can be formed, the pair of gaps G being spaced apart from each other by the first contact 26.

[0143] refer to Figure 28A and Figure 28B This can form a spacer layer 29A. The spacer layer 29A can fill the gaps G (see...). Figure 27A and Figure 27B It covers the two sidewalls and the top of the bitline structure. The spacer layer 29A may be a single layer. The spacer layer 29A may include, for example, silicon nitride.

[0144] According to another embodiment of the present invention, the spacer layer 29A may include a multilayer structure, the multilayer structure including one selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, low-k materials and combinations thereof.

[0145] refer to Figure 29A and Figure 29B Spacers 29 can be formed. Spacers 29 may include spacers 29 that gap-fill the first contact hole 25, and spacers 29 disposed on the sidewalls of the conductor 27 and the conductor hard mask 28. The spacer 29 that gap-fills the first contact hole 25 may be referred to as a "gap-filling spacer." The spacer 29 disposed on the sidewalls of the conductor 27 and the conductor hard mask 28 may be referred to as a "bitline spacer."

[0146] Subsequently, a second contact hole 30 can be formed. The second contact hole 30 can be disposed between adjacent conductive structures. The second contact hole 30 can expose the second pad 22S. The second contact hole 30 can be formed by etching the second hard mask layer 24 and the low-k layer 23 between the spacers 29 (i.e., between adjacent conductive structures). According to the illustrated embodiment of the invention, by pre-forming the second pad 22S before forming the second contact hole 30, the contact etching height can be reduced to the same amount as the thickness of the second pad 22S, and similarly, the second impurity region 20 and the subsequently formed second contact 31 (see Figure 30A and Figure 30BThe contact margin (or landing margin) between the two pads can be ensured to be as much as the thickness of the second pad 22S.

[0147] The second contact hole 30 may have a linear shape extending along the second direction D2. The second contact holes 30 may be spaced apart from each other by conductive structures.

[0148] refer to Figure 30A and Figure 30B This can form a second contact 31 that fills the gap in the second contact hole 30. The second contact 31 can be coupled to the second impurity region 20 via the second pad 22S.

[0149] The second contact 31 can be formed by a series of processes, including forming a plug material layer that fills the gap in the second contact hole 30, and performing an etching process in such a way that the plug material layers are separated and spaced apart from each other in the second direction D2 (see...). Figure 1 To form a plug isolation portion, and then form an isolation layer that fills the gap of the plug isolation portion.

[0150] The second contact 31 may be columnar. The second contact 31 may be disposed on the second pad 22S. The second contact 31 may be coupled to the second impurity region 20 through the second pad 22S. The second pad 22S may improve the contact margin between the second contact 31 and the second impurity region 20. The second contact 31 may be referred to as "storage node contact 31".

[0151] refer to Figure 31A and Figure 31B A storage element 32 can be formed on the second contact 31. The storage element 32 may include a capacitor containing a storage node. The storage node may be columnar, but embodiments of the invention are not limited thereto. Although not shown, a dielectric layer and board nodes may be further formed on the storage node. The storage node may have a cylindrical shape other than a columnar shape. According to another embodiment of the invention, a landing pad may be provided between the second contact 31 and the storage element 32. The landing pads may be spaced apart from each other by an interlayer dielectric layer.

[0152] According to another embodiment of the present invention, different storage elements can be coupled to the second contact 31.

[0153] Figure 32 This is a plan view illustrating a semiconductor device according to another embodiment of the present invention. Figure 33 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Figure 33 It is along Figure 32 The cross-sectional view shown is taken by line I-I'.

[0154] refer to Figure 32 and Figure 33The semiconductor device may include a substrate 101, a buried gate structure 100G, a first doped region 104, and a second doped region 105. The buried gate structure 100G, the first doped region 104, and the second doped region 105 may be embedded in the substrate 101.

[0155] The semiconductor device may be part of a memory cell. For example, the semiconductor device may be part of a memory cell in a dynamic random access memory (DRAM). The semiconductor device may include bit lines 133 electrically connected to substrate 101 (see...). Figure 33 ) and memory storage element 141 (see Figure 33 Bit line 133 can be electrically connected to the first doped region 104 via first contact 132. Memory storage element 141 can be electrically connected to the second doped region 105 via second contact 140. First contact 132 and second contact 140 can be referred to as "bit line contact" and "storage node contact," respectively. Bit line 133 and memory storage element 141 can be disposed at a level higher than the buried gate structure 100G. Bit line 133 and memory storage element 141 can be disposed at different levels. Memory storage element 141 can be disposed at a level higher than bit line 133. Memory storage element 141 may include a capacitor. According to another embodiment of the present invention, memory storage element 141 may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0156] An isolation layer 102 and active regions 103 may be formed on a substrate 101. Multiple active regions 103 may be defined by the isolation layer 102. The isolation layer 102 may be a shallow trench isolation (STI) region formed by a trench etching process. The isolation layer 102 may include silicon oxide, silicon nitride, or a combination thereof.

[0157] The active region 103 may include strips arranged in an array. The array of active regions 103 may include a row array and / or a column array. The row array of active regions 103 may include active regions 103 arranged along a first direction D1. The column array of active regions 103 may include active regions 103 arranged along a second direction D2. From a top viewpoint, the cross-section of each active region 103 may be a parallelogram, such as a parallelogram with rounded edges.

[0158] Each active region 103 may have an upper surface located at a level higher than the upper surface of the isolation layer 102. Each active region 103 may include a protrusion 103P disposed at a level higher than the upper surface of the isolation layer 102.

[0159] Substrate 101 may include a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 101 may also include another semiconductor material, such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0160] A linear gate trench 110 can be formed in the substrate 101 along a first direction D1 to pass through the active region 103 and the isolation layer 102. The gate trench 110 can pass through the center of each active region 103. Therefore, the areas on both sides of the gate trench 110 in each active region 103 (i.e., the areas of the first doped region 104 and the second doped region 110) can be the same, but embodiments of the present invention are not limited thereto.

[0161] The lower surface of the gate trench 110 can be positioned at a level higher than the lower surface of the isolation layer 102. The depth of the gate trench 110 can be shallower than the depth of the isolation layer 102. The lower portion of the gate trench 110 can have a curvature. According to another embodiment of the invention, the isolation layer 102 in the direction in which the gate trench 110 extends can be etched to a predetermined depth to form fins in the active region 103.

[0162] A gate dielectric layer 111 may be conformally formed on the surface of the gate trench 110. A gate electrode 112 filling a portion of the gate trench 110 may be formed on the gate dielectric layer 111. A gate capping layer 113 filling the remaining portion of the gate trench 110 may be formed on the gate electrode 112. The upper surface of the gate capping layer 113 may be disposed at a level higher than the upper surface of the isolation layer 102.

[0163] A gate dielectric layer 111 may be conformally formed on the lower and inner surfaces of the gate trench 110. The gate dielectric layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include a material with a dielectric constant greater than that of silicon oxide. For example, the high-k material may include a material with a dielectric constant greater than about 3.9. Another example is that the high-k material may include a material with a dielectric constant greater than about 10. Yet another example is that the high-k material may include a material with a dielectric constant of about 10 to 30. The high-k material may include at least one metallic element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the invention, the high-k material may include lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be selectively used as the high-k material. The gate dielectric layer 111 may include a metal oxide.

[0164] The gate electrode 112 may have a shape that fills the lower portion of the gate trench 110. The gate electrode 112 may be a low-resistance material to reduce the gate sheet resistance. The gate electrode 112 may include a semiconductor material, a metal-based material, or a combination thereof. The gate electrode 112 may include polysilicon, a metal, a metal nitride, or a combination thereof. For example, the gate electrode 112 may include N-type doped polysilicon, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), ruthenium (Ru), or a combination thereof. According to another embodiment of the invention, the gate electrode 112 may be formed solely of titanium nitride or solely of molybdenum. According to yet another embodiment of the invention, the gate electrode 112 may include a stack of titanium nitride and tungsten (i.e., TiN / W) or a stack of titanium nitride and polysilicon (i.e., TiN / polysilicon).

[0165] According to another embodiment of the present invention, the gate electrode 112 may have a dual-gate structure including an upper gate and a lower gate. According to yet another embodiment of the present invention, the gate electrode 112 may have a tri-gate structure including an upper gate, a middle gate, and a lower gate.

[0166] According to one embodiment of the present invention, the gate electrode 112 may have a high work function. A high work function can refer to a work function higher than the mid-bandgap work function of silicon. A low work function can refer to a work function lower than the mid-bandgap work function of silicon. For example, a high work function may have a work function higher than about 4.5 eV, while a low work function may have a work function lower than about 4.5 eV. The gate electrode 112 may comprise p-type polycrystalline silicon or nitrogen-rich titanium nitride (TiN).

[0167] According to one embodiment of the present invention, the gate electrode 112 may have an increased high work function. The gate electrode 112 may include metal silicon nitride. The metal silicon nitride may be a silicon-doped metal nitride. The gate electrode 112 may include metal silicon nitride with a controlled silicon content. For example, the gate electrode 112 may include tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function, and silicon may be included in titanium nitride to further increase its work function. The silicon content of titanium silicon nitride can be adjusted to have an increased high work function. In one embodiment, the gate electrode 112 may include aluminum titanium nitride (TiAlN).

[0168] Gate capping layer 113 can be used to protect gate electrode 112. Gate capping layer 113 can fill the upper portion of gate trench 110 above gate electrode 112. Gate capping layer 113 may include a dielectric material. Gate capping layer 113 may include silicon nitride, silicon oxynitride, or a combination thereof. According to another embodiment of the invention, gate capping layer 113 may include a combination of silicon nitride and silicon oxide. Gate capping layer 113 may include a silicon nitride pad and spin-on dielectric (SOD) material.

[0169] A first impurity region 104 and a second impurity region 105 can be formed in the active region 103. The first impurity region 104 can be formed in the active region 103 on the first side of the buried gate structure 100G, while the second impurity region 105 can be formed in the active region 103 on the second side of the buried gate structure 100G. The first impurity region 104 and the second impurity region 105 can be regions doped with conductive dopants. For example, the dopants can include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first impurity region 104 and the second impurity region 105 can be respectively disposed in the active regions 103 on both sides of the gate trench 110. The first impurity region 104 and the second impurity region 105 can be separated from each other by the gate trench 110. The first impurity region 104 and the second impurity region 105 can be referred to as the "first source / drain region and the second source / drain region". The first impurity region 104 and the second impurity region 105 can be formed in the active region protrusion 103P. The lower portions of the first impurity region 104 and the second impurity region 105 may be positioned at a level higher than the upper surface of the gate electrode 112, but embodiments of the present invention are not limited thereto. The gate electrode 112 and the first impurity region 104 and the second impurity region 105 may constitute a unit transistor. The unit transistor can improve the short-channel effect by using a gate electrode 112 with a buried gate structure.

[0170] First pad 120B and second pad 120S can be formed on first impurity region 104 and second impurity region 105, respectively. First pad 120B and second pad 120S can be used to ensure contact margin with the substrate during the formation of first contact 132 and second contact 140. First pad 120B can be disposed on first impurity region 104. Second pad 120S can be disposed on second impurity region 105.

[0171] The first pad 120B and the second pad 120S may include semiconductor material. The first pad 120B and the second pad 120S may be selectively epitaxial (SEG) layers. The first pad 120B and the second pad 120S may be doped SEG material. The first pad 120B and the second pad 120S can be formed simultaneously in a single process.

[0172] A first contact 132 may be formed on a first pad 120B. The first contact 132 may be coupled to a first impurity region 104 via the first pad 120B. The first pad 120B may improve the contact margin between the first contact 132 and the first impurity region 104. The first contact 132 may include a conductive material. For example, the first contact 132 may be formed of polysilicon or a metallic material. The first contact 132 may be referred to as a 'bit line contact 132'. The first pad 120B may be referred to as a 'bit line contact pad 120B'.

[0173] The second contact 140 may be formed on the second pad 120S. The second contact 140 may be coupled to the second impurity region 105 via the second pad 120S. The second pad 120S may improve the contact margin between the second contact 140 and the second impurity region 105. The second contact 140 may include a conductive material. For example, the conductive material may include a semiconductor material or a metallic material. For example, the semiconductor material may include polysilicon. For example, the metallic material may include tungsten (W). According to another embodiment of the present invention, the second contact 140 may include a stacked structure of semiconductor material and metallic material. According to yet another embodiment of the present invention, the second contact 140 may include a stacked structure of semiconductor material, ohmic contact layer and metallic material. The second contact 140 may be referred to as 'storage node contact 140'. The second pad 120S may be referred to as 'storage node contact pad 120S'.

[0174] As described above, according to an embodiment of the present invention, by disposing the first pad 120B and the second pad 120S below the first contact 132 and the second contact 140, contact margin (or landing margin) between each contact and the substrate 101 can be ensured. By forming the first pad 120B and the second pad 120S above the active region protrusion 130P to cover the active region protrusion 130P, the linewidth of the active region can be increased. Therefore, overlap margin between the first contact 132 and the second contact 140 and the substrate can be ensured. Furthermore, since the etching height of the contact hole used to form each contact can be reduced to the same amount as the height of the first pad 120B and the second pad 120S, the phenomenon of unopened contact holes can be prevented and process margin can be ensured.

[0175] See Figure 32 and Figure 33 The semiconductor device may include multiple memory cells, and adjacent memory cells may be separated from each other by an isolation layer 102. A memory cell may be formed on an active region 103, and this may be referred to as a "1G1A (one gate-one active) structure" memory cell. In a 1G1A structure memory cell, a bit line 133 may be coupled to an active region 103. Therefore, a memory cell may be coupled to a bit line 133. A 1G1A structure memory cell may include a 1T1C (one transistor-one capacitor). As a comparative example, in a typical DRAM, two memory cells may be formed in an active region, and two gate electrodes may be formed in an active region, and two adjacent memory cells may share a bit line.

[0176] According to embodiments of the present invention, by applying free pads to the bit line contacts and storage node contact areas, it is possible to ensure contact margin.

[0177] According to embodiments of the present invention, by using the low-k layer as a gap-filling material between free pads, the electrical characteristics of the device can be improved.

[0178] Although the invention has been described with reference to specific embodiments, those skilled in the art will understand that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; An active region includes an isolation layer formed in the semiconductor substrate and a protrusion defined by the isolation layer, the protrusion being disposed at a level higher than the upper surface of the isolation layer; First and second pads, which are adapted to cover the protrusion of the active region; A first contact formed in the upper part of the first pad and a conductive structure formed in the upper part of the first contact; as well as The second contact is formed in the upper part of the second pad.

2. The semiconductor device according to claim 1, further comprising: A low-k layer, which is adapted to fill the upper part of the isolation layer in the gap between the first pad and the second pad.

3. The semiconductor device according to claim 2, wherein, The upper surface of the low-k layer is located at a level higher than the upper surfaces of the first pad and the second pad.

4. The semiconductor device according to claim 2, wherein, The low-k layer includes Materials with a dielectric constant less than that of silicon nitride.

5. The semiconductor device according to claim 2, wherein, The low-k layer comprises SiCO.

6. The semiconductor device according to claim 1, wherein, The first pad and the second pad are selectively epitaxial growth layers.

7. The semiconductor device according to claim 1, wherein, Each of the first pad and the second pad covers the side and top surfaces of the protrusion of the active region.

8. The semiconductor device according to claim 1, further comprising: A buried gate structure, which is formed in the substrate and includes a stacked structure of gate electrode and gate capping layer.

9. The semiconductor device according to claim 1, wherein, The protrusions in the active region include a first impurity region and a second impurity region.

10. The semiconductor device according to claim 1, wherein, The first pad covers the first impurity region, while the second pad covers the second impurity region.

11. The semiconductor device according to claim 1, wherein, The first pad, the first contact, and the conductive structure have the same linewidth.

12. The semiconductor device according to claim 1, wherein, The first contact includes a bit line contact, and the conductive structure includes a bit line structure.

13. The semiconductor device according to claim 1, wherein, The second contact includes a storage node contact.

14. The semiconductor device according to claim 1, further comprising: The storage element is located on top of the second contact.

15. A semiconductor device, comprising: Semiconductor substrate; An active region includes an isolation layer formed in the semiconductor substrate and a protrusion defined by the isolation layer, the protrusion being spaced apart from another protrusion by the isolation layer and disposed at a level higher than the upper surface of the isolation layer; A buried gate structure is formed in the semiconductor substrate to pass through the isolation layer and the active region, and has an upper surface located at a level lower than the protrusion of the active region; First and second pads, which are adapted to cover the protrusion of the active region; A first contact formed in the upper part of the first pad and a conductive structure formed in the upper part of the first contact; as well as The second contact is formed in the upper part of the second pad.

16. The semiconductor device of claim 15, further comprising: A low-k layer, which is adapted to fill the upper portion of the isolation layer in the gap between the first pad and the second pad, and to fill the upper portion of the buried gate structure in the gap between the first pads.

17. The semiconductor device according to claim 16, wherein, The upper surface of the low-k layer is located at a level higher than the upper surfaces of the first pad and the second pad.

18. The semiconductor device according to claim 15, wherein, The first pad and the second pad include doped SEG material, where SEG stands for Selective Epitaxial Growth.

19. The semiconductor device according to claim 15, wherein, Each of the first pad and the second pad covers the side and top surfaces of the protrusion of the active region.

20. The semiconductor device according to claim 15, wherein, The protrusions in the active region include a first impurity region and a second impurity region.

21. The semiconductor device according to claim 15, wherein, The first pad covers the first impurity region, and the second pad covers the second impurity region.

22. A method for manufacturing a semiconductor device, the method comprising: An active region is defined in a substrate, the active region including an isolation layer and a protrusion, the protrusion being disposed at a level higher than the upper surface of the isolation layer; Form a first pad and a second pad for covering the protrusion of the active region; An isolation layer is formed between the first pad and the second pad, and a low-k layer is formed above the first pad and the second pad; A first contact hole is formed by penetrating the low-k layer above the first pad to expose the first pad; A first contact and a conductive structure are sequentially formed on the first pad in the first contact hole; A second contact hole is formed by penetrating the low-k layer above the second pad to expose the second pad; as well as A second contact element is formed to fill the gap of the second contact hole.

23. The method according to claim 22, wherein, The active region defining the isolation layer and the protrusion in the substrate includes: The active region is defined as being separated from another active region by the isolation layer; and The isolation layer is recessed to a predetermined depth so that a portion of the active region protrudes.

24. The method according to claim 22, wherein, Forming the first pad and the second pad includes performing a SEG process on the protrusion in the active region, where SEG stands for Selective Epitaxial Growth.

25. The method according to claim 22, wherein, The first pad and the second pad include doped SEG material.

26. The method according to claim 22, wherein, The low-k layer includes Materials with a dielectric constant less than that of silicon nitride.

27. The method according to claim 22, wherein, The low-k layer comprises SiCO.

28. The method according to claim 22, wherein, The protrusions in the active region include a first impurity region and a second impurity region.

29. The method according to claim 28, wherein, The first pad covers the first impurity region, and the second pad covers the second impurity region.

30. The method according to claim 22, wherein, The first contact and the conductive structure are sequentially formed in the first contact hole above the first pad, including: Forming a preliminary first contact suitable for gap filling the first contact hole; A conductive layer and a hard mask material are sequentially stacked on top of the initial first contact; and The hard mask material, the conductive layer, the preliminary first contact, and the first pad are etched sequentially.

31. The method of claim 22, further comprising: After the first contact and the conductive structure are sequentially formed in the first contact hole on the first pad, A spacer is formed to cover the side and top surfaces of the first contact and the conductive structure.

32. The method of claim 22, further comprising: After the second contact element is formed A storage element is formed in the upper part of the second contact.

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