Semiconductor element and manufacturing method thereof

Abstract

The invention provides a semiconductor element which comprises a substrate, a conductive contact, a metal plate, an array structure and a plurality of circuit structures. The substrate includes an array portion and a plurality of circuit portions adjacent to the array portion, where the array portion is located in an array region, and the circuit portions are located in a plurality of circuit regions. The conductive contact is disposed over the substrate. The metal plate is arranged above the conductive contact. The array structure is arranged above the metal plate. The plurality of circuit structures are disposed adjacent to the array structure. A method of manufacturing a semiconductor device is also provided. The semiconductor element releases more space for the bottom electrode connection structure, the voltage is more stable, and the structure and the process of the bottom electrode connection structure are simplified.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] Semiconductor components are widely used in the electronics industry due to their relatively small size, diverse functions, and relatively low manufacturing cost. However, as the size of semiconductor components shrinks, the space for the electrode connection structure used to connect to the power supply becomes limited, the manufacturing process becomes cumbersome, and the limited number of contacts for connecting to the power supply leads to voltage instability.

[0003] For the reasons mentioned above, there is a need for a semiconductor device with an improved electrode connection structure (for connecting a power supply) to solve the aforementioned problems. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor element, including a substrate, conductive contacts, a metal plate, an array structure, and multiple circuit structures. The substrate includes an array portion and multiple circuit portions adjacent to the array portion, wherein the array portion is located in an array region, and the circuit portions are located in multiple circuit regions. Conductive contacts are disposed above the substrate. The metal plate is disposed above the conductive contacts. The array structure is disposed above the metal plate. Multiple circuit structures are disposed adjacent to the array structure.

[0005] In some implementations, the array structure includes a central array structure and a plurality of peripheral array structures, wherein the peripheral array structures include a first array structure, a second array structure, a third array structure, and a fourth array structure surrounding the central array structure.

[0006] In some embodiments, the conductive contacts include a plurality of first conductive contacts located below a first array structure, a plurality of second conductive contacts located below a second array structure, a plurality of third conductive contacts located below a third array structure, and a plurality of fourth conductive contacts located below a fourth array structure.

[0007] In some embodiments, the first conductive contacts, the second conductive contacts, the third conductive contacts, and the fourth conductive contacts are aligned in a single row.

[0008] In some embodiments, at least one of the first conductive contacts, the second conductive contacts, the third conductive contacts, and the fourth conductive contacts is aligned in multiple rows.

[0009] In some implementations, when the array structure, the circuit structures, and the metal plate are projected onto the substrate, the projection of the metal plate covers the projection of the array structure.

[0010] In some implementations, the semiconductor element also includes a metal connector located below the conductive contact.

[0011] In some implementations, the semiconductor element also includes a power supply that electrically connects to the metal interconnect.

[0012] In some implementations, the power supply is disposed between the metal connector and the substrate.

[0013] In some embodiments, the power supply is located outside the vertical projection area of ​​the array structure projected onto the plane, wherein the plane is parallel to the substrate.

[0014] Some embodiments of the present invention provide a method for manufacturing a semiconductor element, comprising: forming an array structure and forming a plurality of circuit structures adjacent to the array structure; providing a substrate including an array portion and a plurality of circuit portions adjacent to the array portion, wherein the array portion is located in an array region corresponding to the array structure, and the circuit portions are located in a plurality of circuit regions corresponding to the circuit structures; forming conductive contacts above the array portion; and disposing a metal plate below the array structure and above the conductive contacts.

[0015] In some implementations, the steps of forming the array structure and forming these circuit structures are performed together.

[0016] In some implementations, the steps of forming these circuit structures and forming conductive contacts are performed separately.

[0017] In some implementations, the array structure includes a central array structure and a plurality of peripheral array structures, wherein the peripheral array structures include a first array structure, a second array structure, a third array structure, and a fourth array structure surrounding the central array structure.

[0018] In some embodiments, the conductive contacts include a plurality of first conductive contacts located below a first array structure, a plurality of second conductive contacts located below a second array structure, a plurality of third conductive contacts located below a third array structure, and a plurality of fourth conductive contacts located below a fourth array structure.

[0019] In some embodiments, the first conductive contacts, the second conductive contacts, the third conductive contacts, and the fourth conductive contacts are aligned in a single row.

[0020] In some embodiments, at least one of the first conductive contacts, the second conductive contacts, the third conductive contacts, and the fourth conductive contacts is aligned in multiple rows.

[0021] In some implementations, when the array structure, the circuit structures, and the metal plate are projected onto the substrate, the projection of the metal plate covers the projection of the array structure.

[0022] In some embodiments, the method further includes forming a metal connector over the array portion prior to the step of forming conductive contacts, and the step of forming conductive contacts includes forming conductive contacts over the metal connector.

[0023] In some implementations, the method further includes electrically connecting a power supply to a metal connector.

[0024] It is understood that the above general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0025] The spirit of the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the preferred embodiments of the present invention, those skilled in the art can make changes and modifications based on the techniques taught in the present invention without departing from the spirit and scope of the present invention.

[0026] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0027] Figure 2A This is a top view of the array structure and the distribution of multiple circuit structures during step S110 of manufacturing a semiconductor element according to some embodiments of the present invention.

[0028] Figures 2B to 2F This is a cross-sectional view of several intermediate stages (steps S120 to S150) in the manufacture of a semiconductor device according to some embodiments of the present invention, wherein Figure 2B For along Figure 2A A cross-sectional view of line A-A'.

[0029] Figure 2G According to some embodiments of the present invention Figure 1 The view below during step S150 of manufacturing a semiconductor element shows the intermediate connection structure and substrate omitted to more clearly illustrate the positions of the conductive contacts and the metal plate.

[0030] Figure 2H as well as Figure 2I For some other embodiments of the present invention Figure 1 The figure shows a lower view of the intermediate stage of step S150 in the manufacturing of a semiconductor device, in which the intermediate connection structure and the substrate are omitted from the figure to more clearly show the positions of the conductive contacts and the metal plate.

[0031] Figure 3AThis is a cross-sectional view of step S160 of manufacturing a semiconductor element according to some embodiments of the present invention.

[0032] Figure 3B This is a cross-sectional view of step S160 of manufacturing a semiconductor element according to some other embodiments of the present invention. Detailed Implementation

[0033] The following detailed reference is made to embodiments of the present invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0034] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit this disclosure. The singular forms such as “a,” “the,” etc., as used herein include the plural forms such as “at least one”; unless explicitly stated otherwise, “or” means “and / or.” In this document, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising,” “including,” and / or “having” specify the presence of the stated features, regions, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0035] Embodiments of the invention are described herein with reference to the top drawing, which serves as an idealized embodiment of the invention. Therefore, variations in the shape of the drawing are expected due to factors such as manufacturing techniques and / or tolerances. Consequently, embodiments of the invention should not be construed as limited to the specific shapes of the areas shown herein, but rather include shape deviations, for example, caused by manufacturing processes. For instance, areas depicted in the drawing or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles in the drawing may also be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the areas and are not intended to limit the scope of the invention.

[0036] Reference will now be made in detail to embodiments of the invention, examples of which are described herein and illustrated in the accompanying drawings. Although the invention will be described in conjunction with embodiments, it should be understood that they are not intended to limit the invention to these embodiments. Therefore, the scope of the invention is limited only by the appended claims.

[0037] Please see Figure 1 The present invention illustrates a method 100 for manufacturing a semiconductor device, and the method 100 includes steps S110, S120, S130, S140, S150 and S160. Figure 1Steps S110 to S160 are described in detail in conjunction with the following figures, providing a semiconductor element having a bottom electrode connection structure (including at least a metal plate and conductive contacts) located below the array structure. This arrangement frees up more space for the bottom electrode connection structure, allows for more conductive contacts, enables more stable voltage, and simplifies the structure and fabrication process of the bottom electrode connection structure by eliminating the need to consider the location and fabrication process of the array structure and circuit structure.

[0038] Please see Figure 1 Step S110 Figure 2A as well as Figure 2B ,in Figure 2A A top view showing the distribution of the array structure 210 and the plurality of circuit structures 220 during step S110 of manufacturing a semiconductor element according to some embodiments of the present invention, and Figure 2B For along Figure 2A A cross-sectional view along line A-A'. In step S110, an array structure 210 is formed and a plurality of circuit structures 220 adjacent to the array structure 210 are formed.

[0039] It is worth noting that, Figure 2B The multiple circuit structures 220 and array structure 210 have been simplified for ease of explanation. Depending on actual needs, the array structure 210 and the multiple circuit structures 220 may also include other components.

[0040] In some implementations, the steps of forming the array structure 210 and forming multiple circuit structures 220 can be performed simultaneously to simplify and speed up the process.

[0041] In some embodiments, the array structure 210 includes a plurality of peripheral array structures 214 and a central array structure 212, wherein the plurality of peripheral array structures 214 include a first array structure 214A, a second array structure 214B, a third array structure 214C and a fourth array structure 214D, and the first array structure 214A, the second array structure 214B, the third array structure 214C and the fourth array structure 214D surround the central array structure 212.

[0042] In some embodiments, the plurality of circuit structures 220 include a first circuit structure 221, a second circuit structure 222, a third circuit structure 223, and a fourth circuit structure 224 surrounding the array structure 210, wherein the first circuit structure 221 is adjacent to the first array structure 214A, the second circuit structure 222 is adjacent to the second array structure 214B, the third circuit structure 223 is adjacent to the third array structure 214C, and the fourth circuit structure 224 is adjacent to the fourth array structure 214D. In some embodiments, the plurality of circuit structures 220 are directly connected to a plurality of circuit portions SUS1 of the substrate SUS (see details). Figure 2C ).

[0043] In some implementations, please refer to Figure 2B The array structure 210 includes capacitors, transistors, or combinations thereof. In some embodiments, the first array structure 214A includes conductors 215 (e.g., word lines) and capacitors 216 located below the conductors 215. In some embodiments, the bit lines perpendicular to the conductors 215 ( Figure 2B (Not shown) Electrically connected channel, wherein the channel is electrically connected to capacitor 216, and the gate dielectric layer ( Figure 2B (Not shown) is located between the channel and the conductor 215 (word line). In some embodiments, multiple circuit structures 220 (e.g., Figure 2B The first circuit structure 221) can be used as a sense amplifier or a sub-word line driver.

[0044] In some embodiments, the array structure 210 is projected onto the vertical projection area of ​​the XY plane, and the multiple circuit structures 220 are projected onto the vertical projection area of ​​the XY plane, respectively defining multiple circuit areas A1 and array areas A2.

[0045] Please see Figure 1 Step S120 and Figure 2C ,in Figure 2C This is a cross-sectional view of step S120 of manufacturing a semiconductor device according to some embodiments of the present invention. In step S120, a substrate SUS is provided, including an array portion SUS2 and a plurality of circuit portions SUS1 adjacent to the array portion SUS2, wherein the array portion SUS2 is located in the array region A2 corresponding to the array structure 210. Figure 2B ), and multiple circuit portions SUS1 are located in multiple circuit regions A1 corresponding to multiple circuit structures 220. Figure 2B ).

[0046] In some implementations, the multiple circuit portions SUS1 and the array portion SUS2 are each separate substrate boards. That is, the multiple circuit portions SUS1 and the array portion SUS2 are not integrally formed.

[0047] In some embodiments, the substrate SUS includes a base material or a structure on which the base material is formed. In some embodiments, the substrate SUS may include a single material, multiple layers of different materials, one or more layers with different materials or different structural regions, or other similar configurations. These materials may include semiconductors, insulators, conductors, or combinations thereof. In some embodiments, the substrate SUS may be a silicon substrate, a silicon-germanium (GaAs) substrate, a ceramic substrate, a quartz substrate, a glass substrate, a silicon-on-insulator (SOI) substrate, etc. In some embodiments, the substrate SUS may include compound semiconductors (e.g., SiC, GaAs, GaP, InP, InAs, or InSb) or alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP). In some embodiments, the substrate SUS includes a metal layer. In some embodiments, the substrate SUS is a multilayer structure, including a polycrystalline silicon layer and metal layers sequentially stacked on the polycrystalline silicon layer.

[0048] Please see Figure 1 Step S130 and Figure 2D ,in Figure 2D This is a cross-sectional view of step S130 of manufacturing a semiconductor element according to some embodiments of the present invention. In step S130, a metal connector 250 is formed above the array portion SUS2.

[0049] In some implementations, the metal connector 250 is formed only in the array region A2 and does not extend to the multiple circuit regions A1.

[0050] In some embodiments, the metal connector 250 includes tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, tin, gold, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0051] In some embodiments, an intermediate connection structure MC is disposed between the metal connector 250 and the substrate SUS. Specifically, the intermediate connection structure MC is disposed between the metal connector 250 and the array portion SUS2. In some embodiments, the intermediate connection structure MC can be a single layer or multiple layers, such that the metal connector 250 is separated from the substrate SUS via the intermediate connection structure MC.

[0052] Please see Figure 1Step S140 and Figure 2E ,in Figure 2E This is a cross-sectional view of step S140 of manufacturing a semiconductor element according to some embodiments of the present invention. In step S140, conductive contacts 240 are formed above the metal connector 250.

[0053] In some embodiments, the conductive contact 240 includes a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, tin, gold, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0054] In some implementations, please refer to Figure 1 , Figure 2B as well as Figure 2E The steps of forming the array structure 210 and forming multiple circuit structures 220 (step S110) and forming conductive contacts 240 above the metal connector 250 (step S140) are performed separately.

[0055] Please see Figure 2B as well as Figure 2E It should be noted that the manufacturing process of the conductive contact 240 is independent of the manufacturing processes of the multiple circuit structures 220 and the array structure 210, and they do not interfere with each other. Furthermore, the structure and manufacturing process of the conductive contact 240 are independent of the circuit structures 220 and the array structure 210. Therefore, the structure and manufacturing process of the conductive contact 240 are simplified.

[0056] Please see Figure 1 Step S150 and Figure 2F ,in Figure 2F This is a cross-sectional view of step S150 of manufacturing a semiconductor element according to some embodiments of the present invention. In step S150, a metal plate 230 is disposed below the array structure 210 and above the conductive contacts 240.

[0057] Therefore, a semiconductor device 200 including a bottom electrode connection structure (BEC) (including a metal plate 230, conductive contacts 240, and metal connectors 250) is provided. The bottom electrode connection structure (BEC) is disposed below the array structure 210 to connect the bottom electrode to the capacitor 216. In some embodiments, the bottom electrode connection structure (BEC) can be used for dynamic random access memory (DRAM), such as oxide-semiconductor channel transistor dynamic random access memory (OCTRAM).

[0058] In some embodiments, the metal plate 230 includes tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, tin, gold, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. Through the arrangement of the metal plate 230, the bottom electrode connection structure BEC can be formed individually, and the manufacturing process is not limited to the arrangement of multiple circuit structures 220 and array structures 210.

[0059] In some embodiments, the metal plate 230 covers the entire array structure 210 but does not cover the multiple circuit structures 220. That is, when the array structure 210, the multiple circuit structures 220, and the metal plate 230 are projected onto the substrate SUS, the projection of the metal plate 230 covers the projection of the array structure 210, thereby defining the position of the bottom electrode connection structure BEC.

[0060] In some embodiments, the metal plate 230 is separated from the substrate SUS at least via conductive contacts 240 and metal connectors 250, and the conductive contacts 240 are separated from the array portion SUS2 via the metal plate 230.

[0061] It is worth noting that in the prior art, the contacts used to connect power supplies are typically located in the remaining space (e.g., corner space) of an array structure between adjacent circuit structures. Therefore, a series of stacked contacts and manufacturing processes are required to match the circuit structure, which limits the space available for contact placement, the maximum number of contacts that can be accommodated, and the cumbersome process.

[0062] With the provision of conductive contacts 240, the bottom electrode connection structure BEC can be formed below the array structure 210, and will not be limited by the remaining space released by the arrangement of multiple circuit structures 220 (e.g., the space in the corner of the array structure 210 between adjacent circuit structures 220). Therefore, the space and number that the conductive contacts 240 can accommodate can be increased, thereby improving voltage stability.

[0063] In some embodiments, a semiconductor element 200 is provided, comprising, from bottom to top, a substrate SUS, an intermediate connection structure MC, a metal connector 250, conductive contacts 240, a metal plate 230, and an array structure 210, wherein a plurality of circuit structures 220 are adjacent to the array structure 210. The metal connector 250 is disposed above the substrate SUS. The conductive contacts 240 are disposed above the metal connector 250. The metal plate 230 is disposed above the conductive contacts 240. The array structure 210 is disposed above the metal plate 230.

[0064] In some implementations, a metal connector 250 directly contacts multiple conductive contacts 240, rather than a single conductive contact 240, to simplify the manufacturing process of the bottom electrode connection structure (BEC) and define the current conduction path. For example, see [link to example description]. Figure 2G , Figure 2H as well as Figure 2I .

[0065] In some embodiments, the thickness of the metal plate 230 is the same as the thickness of the components in the same layer of the circuit structure 220.

[0066] Please see Figure 2G Presenting some embodiments of the present invention Figure 1 Manufacturing semiconductor devices 200 ( Figure 2F The lower view during step S150 shows the intermediate connection structure MC and the substrate SUS (see [link]). Figure 2F (Unshown parts are omitted to more clearly show the positions of conductive contact 240 and metal plate 230.)

[0067] In some implementations, please also refer to Figure 2A as well as Figure 2GThe conductive contacts 240 include a plurality of first conductive contacts 242 located below the first array structure 214A, a plurality of second conductive contacts 244 located below the second array structure 214B, a plurality of third conductive contacts 246 located below the third array structure 214C, and a plurality of fourth conductive contacts 248 located below the fourth array structure 214D. Therefore, the plurality of first conductive contacts 242, the plurality of second conductive contacts 244, the plurality of third conductive contacts 246, and the plurality of fourth conductive contacts 248 can be disposed below the entire array structure 210, providing more space for the conductive contacts 240 and thereby improving voltage stability.

[0068] exist Figure 2G In this configuration, a plurality of first conductive contacts 242, a plurality of second conductive contacts 244, a plurality of third conductive contacts 246, and a plurality of fourth conductive contacts 248 are aligned in a single row, with each row extending along the direction corresponding to one of the peripheral array structures 214. Specifically, the plurality of first conductive contacts 242 and the plurality of second conductive contacts 244 are aligned along the Y-axis, and the plurality of third conductive contacts 246 and the plurality of fourth conductive contacts 248 are aligned along the X-axis.

[0069] It is worth noting that different configurations can be provided according to actual needs. In some other embodiments, at least one of the first conductive contact 242, the second conductive contact 244, the third conductive contact 246, and the fourth conductive contact 248 is aligned in a multi-row configuration.

[0070] In some embodiments, the conductive contact 240 is not located below the circuit structure 220. For example, the conductive contact 240 is not located below any of the first circuit structure 221, the second circuit structure 222, the third circuit structure 223, and the fourth circuit structure 224, thereby avoiding interference with the circuit structure 220.

[0071] Please see Figure 2H Presented according to some other embodiments of the present invention Figure 1 The bottom view is taken during an intermediate stage of step S150 in the manufacturing of a semiconductor device. Figure 2H In this configuration, multiple first conductive contacts 242 and multiple second conductive contacts 244 are aligned in a double-row configuration along the Y-axis, and multiple third conductive contacts 246 and multiple fourth conductive contacts 248 are aligned in a single-row configuration along the X-axis. Specifically, two first conductive contacts 242 and two second conductive contacts 244 are aligned along the X-axis, and more than two first conductive contacts 242 and more than two second conductive contacts 244 are aligned along the Y-axis.

[0072] Please see Figure 2IThe plurality of first conductive contacts 242, a plurality of second conductive contacts 244, a plurality of third conductive contacts 246, and a plurality of fourth conductive contacts 248 are arranged in a double-row configuration. In some other embodiments, a multi-row configuration, such as three rows, four rows, etc., may be provided.

[0073] Specifically, two first conductive contacts 242 and two second conductive contacts 244 are aligned along the X-axis, and more than two first conductive contacts 242 and more than two second conductive contacts 244 are aligned along the Y-axis. Two third conductive contacts 246 and two fourth conductive contacts 248 are aligned along the Y-axis, and more than two third conductive contacts 246 and more than two fourth conductive contacts 248 are aligned along the X-axis.

[0074] In some other implementations, please refer to the same document. Figure 2A as well as Figure 2I The conductive contact 240 is not located throughout the entire peripheral array structure 214. Figure 2A Below. For example, depending on actual needs, conductive contacts 240 may be located below any one to any three of the first array structure 214A, the second array structure 214B, the third array structure 214C, and the fourth array structure 214D.

[0075] Please see Figure 1 Step S160 and Figure 3A ,in Figure 3A This is a cross-sectional view of step S160 of manufacturing a semiconductor element 200 according to some embodiments of the present invention. In step S160, a power supply 260 is electrically connected to a metal connector 250.

[0076] In some implementations, power supply 260 includes a variety of internal power supply elements, such as conventional storage electrode power supplies (e.g., supplying voltage of photoelectric device (VPLT)).

[0077] In some embodiments, the power supply 260 is not located in the array region A2. That is, the power supply 260 is substantially located outside the vertical projection area of ​​the array structure 210 onto a plane parallel to the substrate SUS. In some embodiments, the power supply 260 is substantially located outside the vertical projection area of ​​the metal plate 230 onto a plane parallel to the substrate SUS.

[0078] It should be emphasized that different types of power supply configurations 260 can be provided. For some other implementations, please refer to... Figure 3BThe power supply 260 is disposed between the metal plate 230 and the substrate SUS (or more precisely, between the metal plate 230 and the intermediate connection structure MC) to save space occupied by the power supply 260 in the working area and to avoid interference from the array structure 210 and the circuit structure 220. For example, the power supply 260 is disposed in the array area A2 or the circuit area A1.

[0079] While the invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0080] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the invention is intended to encompass any modifications and variations falling within the scope of the appended claims and their equivalents.

[0081] [Symbol Explanation]

[0082] 100: Method

[0083] 200: Semiconductor components

[0084] 210: Array Structure

[0085] 212: Central Array Structure

[0086] 214: Peripheral Array Structure

[0087] 214A: First array structure

[0088] 214B: Second array structure

[0089] 214C: Third Array Structure

[0090] 214D: Fourth Array Structure

[0091] 215: Conductor

[0092] 216: Capacitor

[0093] 220: Circuit Structure

[0094] 221: First Circuit Structure

[0095] 222: Second Circuit Structure

[0096] 223: Third Circuit Structure

[0097] 224: Fourth Circuit Structure

[0098] 230: Metal plate

[0099] 240: Conductive contact

[0100] 242: First conductive contact

[0101] 244: Second conductive contact

[0102] 246: Third conductive contact

[0103] 248: Fourth conductive contact

[0104] 250: Metal connectors

[0105] 260: Power Supply

[0106] BEC: Bottom Electrode Connection Structure

[0107] MC: Intermediate connection structure

[0108] SUS: Substrate; SUS1: Circuit section; SUS2: Array section; S110, S120, S130, S140, S150, S160: Step A1: Circuit area

[0109] A2: Array area A-A': Line A-A'

[0110] X: X-axis

[0111] Y: Y-axis

[0112] Z: Z-axis.

Claims

1. A semiconductor element, characterized in that, Include: A substrate includes an array portion and a plurality of circuit portions adjacent to the array portion, wherein the array portion is located in an array region and the plurality of circuit portions are located in a plurality of circuit regions. Conductive contacts are disposed above the substrate; A metal plate is disposed above the conductive contact; An array structure is disposed above the metal plate; as well as Multiple circuit structures are arranged adjacent to the array structure.

2. The semiconductor device according to claim 1, wherein the array structure comprises a central array structure and a plurality of peripheral array structures, wherein the plurality of peripheral array structures comprises a first array structure, a second array structure, a third array structure and a fourth array structure surrounding the central array structure.

3. The semiconductor element according to claim 2, wherein the conductive contacts include a plurality of first conductive contacts located below the first array structure, a plurality of second conductive contacts located below the second array structure, a plurality of third conductive contacts located below the third array structure, and a plurality of fourth conductive contacts located below the fourth array structure.

4. The semiconductor element according to claim 3, wherein the plurality of first conductive contacts, the plurality of second conductive contacts, the plurality of third conductive contacts, and the plurality of fourth conductive contacts are respectively aligned in a single row.

5. The semiconductor element of claim 3, wherein at least one of the plurality of first conductive contacts, the plurality of second conductive contacts, the plurality of third conductive contacts, and the plurality of fourth conductive contacts is aligned in a multi-row configuration.

6. The semiconductor device according to claim 1, wherein when the array structure, the plurality of circuit structures and the metal plate are projected onto the substrate, the projection of the metal plate covers the projection of the array structure.

7. The semiconductor device according to claim 1, wherein, It also includes a metal connector located below the conductive contact.

8. The semiconductor element according to claim 7, wherein, It also includes a power supply that electrically connects the metal connector.

9. The semiconductor device of claim 8, wherein the power supply is disposed between the metal connector and the substrate.

10. The semiconductor device of claim 8, wherein the power supply is disposed outside the vertical projection area of ​​the array structure projected onto the plane, wherein the plane is parallel to the substrate.

11. A method for manufacturing a semiconductor device, characterized in that, Include: Forming an array structure and forming multiple circuit structures adjacent to the array structure; A substrate is provided, comprising an array portion and a plurality of circuit portions adjacent to the array portion, wherein the array portion is located in an array region corresponding to the array structure, and the plurality of circuit portions are located in a plurality of circuit regions corresponding to the plurality of circuit structures. Conductive contacts are formed above the array portion; as well as A metal plate is positioned below the array structure and above the conductive contacts.

12. The method of claim 11, wherein the steps of forming the array structure and forming the plurality of circuit structures are performed together.

13. The method of claim 11, wherein the steps of forming the plurality of circuit structures and forming the conductive contacts are performed separately.

14. The method of claim 11, wherein the array structure comprises a central array structure and a plurality of peripheral array structures, wherein the plurality of peripheral array structures comprises a first array structure, a second array structure, a third array structure, and a fourth array structure surrounding the central array structure.

15. The method of claim 14, wherein the conductive contacts comprise a plurality of first conductive contacts located below the first array structure, a plurality of second conductive contacts located below the second array structure, a plurality of third conductive contacts located below the third array structure, and a plurality of fourth conductive contacts located below the fourth array structure.

16. The method of claim 15, wherein the plurality of first conductive contacts, the plurality of second conductive contacts, the plurality of third conductive contacts, and the plurality of fourth conductive contacts are respectively aligned in a single row.

17. The method of claim 15, wherein at least one of the plurality of first conductive contacts, the plurality of second conductive contacts, the plurality of third conductive contacts, and the plurality of fourth conductive contacts is aligned in a multi-row configuration.

18. The method of claim 11, wherein when the array structure, the plurality of circuit structures and the metal plate are projected onto the substrate, the projection of the metal plate covers the projection of the array structure.

19. The method according to claim 11, wherein, It also includes forming a metal connector above the array portion before the step of forming the conductive contact, and the step of forming the conductive contact includes forming the conductive contact above the metal connector.

20. The method according to claim 19, wherein, It also includes an electrical connection between the power supply and the metal connector.

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