Semiconductor device and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, and a memory system. The semiconductor device comprises a first laminated structure, a second laminated structure, a first contact structure and a second contact structure. The first laminated structure comprises first gate layers stacked in the first direction, and the second laminated structure is located on one side of the first laminated structure in the first direction and comprises second gate layers stacked in the first direction. The first contact structure extends in the first laminated structure along a direction opposite to the first direction and is connected with a first gate layer. The second contact structure extends in the second laminated structure along the first direction and is connected with a second gate layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor device, a method for fabricating a semiconductor device, and a memory system. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for storage density of semiconductor devices such as 3D memory are also increasing. However, due to limitations in processes, equipment and materials, increasing the storage density of semiconductor devices has become quite difficult.

[0003] Furthermore, with the increase in the number of stacked layers and the improvement in storage density per unit area in semiconductor devices such as 3D memory, the process steps in semiconductor device fabrication have become more complex and lengthy, and the fabrication cost of semiconductor devices is also gradually increasing.

[0004] Therefore, as the number of stacked layers in semiconductor devices increases, how to simplify the fabrication process and reduce the fabrication cost of semiconductor devices while taking into account both the reliability and overall performance of semiconductor devices is an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of this application provide semiconductor devices and methods for fabricating the same, as well as memory systems, that can at least partially solve the aforementioned technical problems or other problems.

[0006] This application provides a semiconductor device comprising: a first stacked structure including a first gate layer stacked along a first direction; a second stacked structure located on one side of the first stacked structure along the first direction and including a second gate layer stacked along the first direction; a first contact structure extending in the first stacked structure along the first direction and connected to a first gate layer; and a second contact structure extending in the second stacked structure along a direction opposite to the first direction and connected to a second gate layer.

[0007] In one embodiment of this application, the first contact structure and the second contact structure are symmetrically arranged along a direction intersecting the first direction.

[0008] In one embodiment of this application, the first contact structure extends from a first side of the first stacked structure in a direction opposite to the first direction and is connected to a first gate layer; and the second contact structure extends from a second side of the second stacked structure in the first direction and is connected to a second gate layer, wherein the first side and the second side are opposite to each other in the first direction.

[0009] In one embodiment of this application, a first gate layer extends in the first stacked structure along the second direction; the semiconductor device further includes a first dielectric layer disposed in the same layer as the first gate layer; and the first contact structure extends in the opposite direction to the first direction, passes through at least one of the first dielectric layers, and is connected to the first gate layer.

[0010] In one embodiment of this application, the first contact structure includes a first end and a second end opposite to each other along the first direction, wherein the second end is connected to a first gate layer; and in a direction intersecting the first direction, the size of the first end is smaller than the size of the second end.

[0011] In one embodiment of this application, the second gate layer extends in the second stacked structure along the second direction; the semiconductor device further includes a second dielectric layer disposed in the same layer as the second gate layer; and the second contact structure extends in a direction opposite to the first direction, passes through at least one of the second dielectric layers, and is connected to the second gate layer.

[0012] In one embodiment of this application, the second contact structure includes a third end and a fourth end opposite to each other along the first direction, wherein the fourth end is connected to a second gate layer; and in a direction intersecting the first direction, the size of the third end is smaller than the size of the fourth end.

[0013] In one embodiment of this application, a peripheral circuit is located on one side of the second stacked structure along the first direction; a first interconnection structure extends in the first stacked structure and the second stacked structure in a direction opposite to the first direction and connects the peripheral circuit and the first contact structure; and a second interconnection structure is located between the peripheral circuit and the second contact structure and connects the peripheral circuit and the second contact structure.

[0014] In one embodiment of this application, the semiconductor device further includes: a semiconductor layer located between the first stacked structure and the second stacked structure along the first direction, and extending along a direction intersecting the first direction.

[0015] In one embodiment of this application, the semiconductor device further includes: a channel structure including a channel layer and a functional layer located on the surface of the channel layer, wherein the channel layer extends in a direction opposite to the first direction and is connected to the semiconductor layer; and the functional layer includes a first functional layer and a second functional layer, wherein the first functional layer extends in the first stacked structure and the second functional layer extends in the second stacked structure in a direction opposite to the first direction.

[0016] In one embodiment of this application, the channel layer and the semiconductor layer have the same doping type.

[0017] In one embodiment of this application, the doping concentration of conductive impurities in the semiconductor layer is greater than the doping concentration of conductive impurities in the channel layer.

[0018] In one embodiment of this application, a plurality of first contact structures are arranged along a direction intersecting the first direction, and have different extension lengths in a direction opposite to the first direction; or a plurality of second contact structures are arranged along a direction intersecting the first direction, and have different extension lengths in the first direction.

[0019] In one embodiment of this application, a plurality of the first contact structures are arranged along a direction intersecting the first direction, and their extension length in the direction opposite to the first direction increases or decreases.

[0020] In one embodiment of this application, a plurality of second contact structures are arranged along a direction intersecting the first direction, and their extension length in the first direction increases or decreases.

[0021] In one embodiment of this application, the first contact structure includes a first conductive structure and a first dielectric filling layer surrounded by the first conductive structure.

[0022] In one embodiment of this application, the second contact structure includes a second conductive structure and a second dielectric filling layer surrounded by the second conductive structure.

[0023] This application, in another aspect, provides a method for fabricating a semiconductor device, the method comprising: forming a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction, wherein the first stacked structure includes a first gate layer stacked along the first direction, and the second stacked structure includes a second gate layer stacked along the first direction; and forming a first contact structure and a second contact structure, wherein the first contact structure extends in a direction opposite to the first direction and is connected to a first gate layer, and the second contact structure extends in the first direction and is connected to a second gate layer.

[0024] In one embodiment of this application, forming a first contact structure and a second contact structure includes: forming a first contact hole and a second contact hole, wherein the first contact hole extends from a first side of the first stacked structure in a direction opposite to the first direction to a first gate layer, and the second contact hole extends from a second side of the second stacked structure in the first direction to a second gate layer, the first side and the second side being opposite to each other in the first direction; and filling the first contact hole and the second contact hole to form the first contact structure and the second contact structure.

[0025] In one embodiment of this application, forming a first contact hole and a second contact hole includes: forming the second contact hole; and flipping an intermediate body having the second contact hole formed thereon, and forming the first contact hole in the flipped intermediate body.

[0026] In one embodiment of this application, forming the second contact hole includes: forming a first opening extending along the first direction; and forming a second opening communicating with the first opening via the first opening, the second opening extending to a second gate layer in a direction intersecting the first direction, wherein, in the direction intersecting the first direction, the size of the second opening is larger than the size of the first opening.

[0027] In one embodiment of this application, a plurality of the first openings are arranged along the second direction and have different extension lengths in the first direction.

[0028] In one embodiment of this application, forming a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction includes: alternately stacking a first isolation layer and a first gate sacrificial layer to form a first stacked structure; forming a semiconductor layer on one side of the first stacked structure along the first direction; alternately stacking a second isolation layer and a second gate sacrificial layer on one side of the semiconductor layer along the first direction to form a second stacked structure; and replacing a portion of the first gate sacrificial layer and a portion of the second gate sacrificial layer with the first gate layer and the second gate layer, respectively, to form the first stacked structure and the second stacked structure.

[0029] In one embodiment of this application, the semiconductor device further includes a channel structure, forming the channel structure by: forming a channel via extending in a first stacked structure and a second stacked structure in a direction opposite to the first direction, wherein the channel via exposes a portion of the semiconductor layer; forming an initial functional layer in the channel via; removing a portion of the initial functional layer on the exposed semiconductor layer to form a first functional layer and a second functional layer, wherein the first functional layer extends in the first stacked structure and the second functional layer extends in the second stacked structure in a direction opposite to the first direction; and forming a channel layer on the surfaces of the first functional layer, the semiconductor layer, and the second functional layer.

[0030] In another aspect, this application provides a memory system comprising: a controller; and the semiconductor device provided in any one aspect of this application, wherein the controller is coupled to the memory and is used to control the semiconductor device to store data.

[0031] According to at least one embodiment of the semiconductor device and its fabrication method, and memory system provided in this application, the semiconductor device includes a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction. A plurality of first contact structures connected to the first stacked structure extend in the first stacked structure along a direction opposite to the first direction and are connected to a first gate layer of the first stacked structure. A plurality of second contact structures connected to the second stacked structure extend in the second stacked structure along the first direction and are connected to a second gate layer of the second stacked structure. This achieves good connectivity between the gate layer and the contact structures. By introducing contact structures connected to the upper and lower sub-stacked structures (e.g., the first and second stacked structures) of the stacked structure from both sides of the stacked structure along the stacking direction into the corresponding gate layers, the first and second contact structures corresponding to the upper and lower sub-stacked structures can be independently configured without interference, simplifying the process of forming the contact structures. Furthermore, while improving the reliability and storage density of the semiconductor device, it also reduces the fabrication cost of the semiconductor device. Attached Figure Description

[0032] Other features, objects, and beneficial effects of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0033] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application;

[0034] Figure 2 This is a top view schematic diagram of a semiconductor device according to one embodiment of this application;

[0035] Figure 3 This is a top view of the second region according to one embodiment of this application;

[0036] Figure 4 This is a top view of the second region according to another embodiment of this application;

[0037] Figure 5 It will Figure 4 The diagram shows a cross-section of the second region along line A-A'.

[0038] Figure 6 One implementation method is Figure 4 The diagram shows a cross-section of the second region along line B-B'.

[0039] Figure 7 Another implementation method is to Figure 4 The diagram shows a cross-section of the second region along line B-B'.

[0040] Figure 8 This is a flowchart of a method for fabricating a semiconductor device according to one embodiment of this application;

[0041] Figures 9-37 These are schematic diagrams illustrating a method for fabricating a semiconductor device according to one embodiment of this application; and

[0042] Figure 38 This is a schematic diagram of a memory system structure according to one embodiment of this application. Detailed Implementation

[0043] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements.

[0044] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation rather than degree and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0045] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "having," and / or "having have" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. When describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0046] In addition, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0047] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formalized sense.

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 1000 according to one embodiment of this application. Figure 2 This is a top view schematic diagram of a semiconductor device 1000 according to one embodiment of this application. Figure 3 This is a top view of the second region 12 according to one embodiment of this application. Figure 4 This is a top view of the second region 12 according to another embodiment of this application. Figure 5 It will Figure 4 The diagram shows a cross-section of the second region 12 taken along line A-A'. Figure 6 One implementation method is Figure 4 The diagram shows a cross-section of the second region 12 along line B-B'. Figure 7Another implementation method is to Figure 4 The diagram shows a cross-section of the second region 12 along line B-B'.

[0050] like Figures 1-7 As shown, the semiconductor device 1000 includes: a first stacked structure 201, a second stacked structure 202, a first contact structure 501, and a second contact structure 502. The first stacked structure 201 includes a first gate layer 210 stacked along a first direction (z+ direction). The second stacked structure 202 is located on one side of the first stacked structure 201 along the z+ direction and includes a second gate layer 220 stacked along the z+ direction. The first contact structure 501 extends in the first stacked structure 201 along the z+ direction and is connected to a first gate layer 210. The second contact structure 502 extends in the second stacked structure 202 along the z- direction, which is opposite to the z+ direction, and is connected to a second gate layer 220.

[0051] A semiconductor device according to at least one embodiment of this application includes a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction. A plurality of first contact structures connected to the first stacked structure extend in the first stacked structure along a direction opposite to the first direction and are connected to a first gate layer of the first stacked structure. A plurality of second contact structures connected to the second stacked structure extend in the second stacked structure along the first direction and are connected to a second gate layer of the second stacked structure. This achieves good connectivity between the gate layer and the contact structures. By introducing contact structures connected to the upper and lower sub-stacked structures (e.g., the first and second stacked structures) of the stacked structure from both sides of the stacked structure along the stacking direction into the corresponding gate layers, the first and second contact structures corresponding to the upper and lower sub-stacked structures can be independently configured without interference, simplifying the process of forming the contact structures. Furthermore, while improving the reliability and storage density of the semiconductor device, it also reduces the fabrication cost of the semiconductor device.

[0052] Taking three-dimensional memory as an example, some semiconductor devices include a stacked structure formed by alternating gate layers and dielectric layers, wherein word line contacts located in the step region of the stacked structure can enable the gate layer to connect with external circuits.

[0053] However, as the number of stacked layers increases, forming word line contacts in the step region requires multiple processes such as photolithography and etching to create the stepped morphology of the steps, which significantly increases the manufacturing cost of semiconductor devices. Simultaneously, the more steps there are, the larger the area of ​​the step region needs to be formed, which is detrimental to improving the integration density of semiconductor devices. Furthermore, the more stacked layers there are, the more severe the wafer warpage becomes, making alignment between the word line contacts and the step surfaces in the step region more difficult. This leads to decreased reliability or low electrical test yield of the semiconductor device, ultimately affecting its reliability and overall performance.

[0054] The semiconductor device provided in this application does not require the formation of steps and word line contacts corresponding to the steps. By using multiple contact structures with different extension lengths, the gate layer located at different stacking heights can be connected to the external circuit. Therefore, while simplifying the semiconductor device fabrication process and reducing the production cost, the area required for the semiconductor device can be reduced, and the storage density, reliability and overall performance of the semiconductor device per unit area can be improved.

[0055] Specifically, such as Figures 2-5 As shown, the second stacked structure 202 may be disposed on one side of the first stacked structure 201. The stacked structure formed by the two may include a first region 11 and a second region 12 that are adjacently distributed in the x direction intersecting the z+ direction. The first region 11 may include alternately stacked dielectric and gate layers, such as a first gate layer 210 and a third dielectric layer 250, and a second gate layer 220 and a fourth dielectric layer 260. The second region 12 may include alternately stacked dielectric layer pairs, such as a first dielectric layer 230 and a third dielectric layer 250, and a second dielectric layer 240 and a fourth dielectric layer 260.

[0056] Both the first gate layer 210 and the second gate layer 220 may include conductive materials, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides. Furthermore, the first gate layer 210 and the second gate layer 220 may include conductive material layers of the same material or conductive material layers of different materials; this application does not limit this.

[0057] The third dielectric layer 250 and the fourth dielectric layer 260 can be used as isolation stack layers in the first stacked structure 201 and the second stacked structure 202, respectively, and both can include an insulating dielectric material layer. Exemplarily, both the third dielectric layer 250 and the fourth dielectric layer 260 can include an insulating dielectric material layer such as silicon oxide. Furthermore, the third dielectric layer 250 and the fourth dielectric layer 260 can include insulating dielectric material layers of the same material or insulating dielectric material layers of different materials; this application does not limit this.

[0058] The first dielectric layer 230 and the third dielectric layer 250 are two different insulating dielectric material layers, and the second dielectric layer 240 and the fourth dielectric layer 260 are also two different insulating dielectric material layers. For example, the first dielectric layer 230 and the second dielectric layer 240 may include, but are not limited to, insulating dielectric material layers such as silicon nitride layers.

[0059] Furthermore, the plurality of first dielectric layers 230 and the plurality of first gate layers 210 may have the same stacking height. The plurality of second dielectric layers 240 and the plurality of second gate layers 220 may have the same stacking height. The number of layers in the stacked structure formed by the first stacked structure 201 and the second stacked structure 202 is not limited to the number of layers shown in the figure, and can be set as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0060] In other words, reference Figure 1 and Figure 2 Both the first stacked structure 201 and the second stacked structure 202 may include alternately stacked dielectric layers and composite layers. Taking the first stacked structure 201 as an example, the composite layer may include a first gate layer 210 and a first dielectric layer 230 disposed in the same layer. For example, the first gate layer 210 and the first dielectric layer 230 may be connected to each other in an xy plane intersecting the z+ direction. The first gate layer 210 extends from the first region 11 of the stacked structure along the x direction to the second region 12 and is connected to the first dielectric layer 230 disposed in the same layer, wherein the first dielectric layer 230 is located in the second region 12. Taking the second stacked structure 202 as an example, the composite layer includes a second gate layer 220 and a second dielectric layer 240 disposed in the same layer. For example, the second gate layer 220 and the second dielectric layer 240 can be connected to each other in an xy plane intersecting the z+ direction. The second gate layer 220 extends from the first region 11 of the stacked structure to the second region 12 along the x direction and is connected to the second dielectric layer 240 disposed in the same layer, wherein the second dielectric layer 240 is located in the second region 12.

[0061] However, with the increasing demand for storage capacity in semiconductor devices, the number of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack technologies can be used to form a stacked structure by sequentially stacking multiple sub-stacked structures in the stacking direction of the stacked structure. Each sub-stacked structure may include multiple alternating gate layers and dielectric layers. The number of layers in each sub-stacked structure may be the same or different. The content, structure, and beneficial effects of the semiconductor devices with two sub-stacked structures (e.g., the first stacked structure and the second stacked structure) described in this application are wholly or partially applicable to semiconductor devices including multiple sub-stacked structures, therefore, related or similar content will not be repeated.

[0062] Continue to refer Figure 1 , Figure 2 and Figure 5 Contact structures such as the first contact structure 501 and the second contact structure 502 can be formed in contact holes (not shown) with a predetermined depth along the z+ direction, formed by processes such as photolithography and etching, to facilitate connection with gate layers at different stacking heights (e.g., the first gate layer 210 and the second gate layer 220). However, with the increase in the integration density of semiconductor devices and the increase in the number of stacked layers, the depth of contact holes connecting to gate layers at lower stacking heights is becoming increasingly deeper. During the formation of contact holes, gate layer breakdown is easily caused, leading to short circuits between different gate layers.

[0063] In at least one embodiment of this application, the stacked structure including the first stacked structure 201 and the second stacked structure 202 may include a first region 11 and a second region 12. The first sub-region 01 of the second region 12 includes an insulating dielectric material stack layer, such as a first insulating dielectric material stack layer formed by alternating stacking of a first dielectric layer 230 and a third dielectric layer 250, and a second insulating dielectric material stack layer formed by alternating stacking of a second dielectric layer 240 and a fourth dielectric layer 260.

[0064] Optionally, the first contact structure 501 extends along the z+ direction, passes through at least one first dielectric layer 230, and connects to a first gate layer 210. Furthermore, the second contact structure 502 extends along the z- direction, passes through at least one second dielectric layer 240, and connects to a second gate layer 220. In other words, by placing the first contact structure 501 and the second contact structure 502 within a stack of insulating dielectric materials, for example, by placing the first contact structure 501 and the second contact structure 502 within the first sub-region 01, effective communication between the contact structure and the corresponding gate layer can be achieved while reducing the possibility of short circuits between different gate layers.

[0065] like Figure 3 As shown, as an option, multiple first contact structures 501 are located in the first sub-region 01 and can be staggered along the y-direction, wherein the y-direction is staggered with the x-direction and the z+ direction (e.g., Figure 1 As shown, all of them intersect. Alternatively, multiple second contact structures 502 are located in the first sub-region 01 and can be staggered along the y-direction. As yet another option, multiple first contact structures 501 and multiple second contact structures 502 are located in the first sub-region 01 and can all be staggered along the y-direction.

[0066] like Figure 4As shown, as one option, multiple first contact structures 501 are located in the first sub-region 01 and can be spaced apart along the x-direction. As another option, multiple second contact structures 502 are located in the first sub-region 01 and can be spaced apart along the x-direction. As yet another option, multiple first contact structures 501 and multiple second contact structures 502 are located in the first sub-region 01 and can all be spaced apart along the x-direction.

[0067] Alternatively, a plurality of first contact structures 501 and a plurality of second contact structures 502 are located in a first sub-region 01, wherein the plurality of first contact structures 501 are spaced apart along the x-direction, and the plurality of second contact structures 502 are staggered along the y-direction. Alternatively, a plurality of first contact structures 501 and a plurality of second contact structures 502 are located in the first sub-region 01, wherein the plurality of first contact structures 501 are staggered along the y-direction, and the plurality of second contact structures 502 are spaced apart along the x-direction.

[0068] Optionally, in some embodiments of this application, the first contact structure 501 and the second contact structure 502 may be symmetrically arranged along a direction intersecting the z+ direction (e.g., the x or y direction). By symmetrically arranging the first and second contact structures, the storage density of the semiconductor device can be improved while achieving a good connection between the gate layer and the contact structure.

[0069] In other words, those skilled in the art should understand that, without departing from the teachings of this application, the layout of the contact structures connected to different stacked structures in the plane (xy plane) intersecting the z+ direction can be selected according to the different semiconductor device architectures.

[0070] like Figure 1 As shown, in some embodiments of this application, the stacked structure including the first stacked structure 201 and the second stacked structure 202 may include two opposite sides along the z+ direction, a first side 200-1 and a second side 200-2. A first contact structure 501 extends from the first side 200-1 along the z+ direction in the first stacked structure 201 and connects to a first gate layer 210. A second contact structure 502 extends from the second side 200-2 along the z- direction in the second stacked structure 202 and connects to a second gate layer 220. In other words, the contact structures connected to different stacked structures may be located on opposite sides of the overall structure formed by the multiple stacked structures along the stacking direction of the stacked structures.

[0071] In addition, such as Figure 1As shown, in some embodiments of this application, the semiconductor device 1000 further includes a peripheral circuit layer 600, which includes peripheral circuits 601 connected to the first gate layer 210 or the second gate layer 220. Optionally, a plurality of peripheral circuits 601 are located on the second side 200-2 along the z+ direction. In this case, the semiconductor device 1000 further includes a first interconnect structure 710, which extends along the z- direction in the first stacked structure 201 and the second stacked structure 202, and connects the peripheral circuits 601 and the first contact structure 501.

[0072] In other words, the first interconnect structure 710 can be disposed on one side of the plurality of first contact structures 501 along the y-direction, and the first interconnect structure 710 extends along the z-direction, and can be connected to the first contact structure 501 through the connection structure 800 extending along the y-direction. The connection between the peripheral circuit 601 and the first contact structure 501 is realized by means of the first interconnect structure 710 and the connection structure 800.

[0073] In addition, the semiconductor device 1000 also includes a second interconnect structure 720, which is located between the peripheral circuit 601 and the second contact structure 502. The second interconnect structure 720 can be located on the second side 200-2, just like the peripheral circuit 601, which simplifies the circuitry of the second interconnect structure between the multiple second contact structures and the peripheral circuit.

[0074] refer to Figure 6 and Figure 7 Alternatively, multiple first contact structures 501 can be arranged along the x-direction with different extension lengths in the z+ direction; alternatively, multiple second contact structures 502 can be arranged along the x-direction with different extension lengths in the z- direction. Yet another option is that multiple first contact structures 501 can be arranged along the x-direction with different extension lengths in the z+ direction, and multiple second contact structures 502 can be arranged along the x-direction with different extension lengths in the z- direction. It should be noted that the number of first contact structures 501 and second contact structures 502 in the semiconductor device 1000 is not limited to the number of layers shown in the figure, and can be set separately as needed.

[0075] Specifically, multiple first contact structures 501 are arranged along the x-direction, and their extension lengths in the z+ direction increase or decrease. The multiple first contact structures 501 may include a first sub-contact structure 501-1, a second sub-contact structure 501-2, and a third sub-contact structure 501-3, wherein the extension length of the first sub-contact structure 501-1 in the z+ direction is h4, the extension length of the second sub-contact structure 501-2 in the z+ direction is h5, and the extension length of the third sub-contact structure 501-3 in the z+ direction is h6. Optionally, the first sub-contact structures 501-1, the second sub-contact structure 501-2, and the third sub-contact structure 501-3 are arranged along the x-direction, and their extension lengths h4, h5, and h6 in the z+ direction increase or decrease.

[0076] Furthermore, the plurality of first contact structures 501 are arranged along the x-direction, and their extension length in the z+ direction can gradually increase or gradually decrease, wherein "gradually" can be understood as the extension length of the plurality of first contact structures 501 arranged along the x-direction in the z+ direction increasing or decreasing by a predetermined size.

[0077] Similarly, multiple second contact structures 502 are arranged along the x-direction, and their extension lengths in the z-direction may increase or decrease. The multiple second contact structures 502 may include a fourth sub-contact structure 502-1, a fifth sub-contact structure 502-2, and a sixth sub-contact structure 502-3, wherein the fourth sub-contact structure 502-1 has an extension length of h1 in the z-direction, the fifth sub-contact structure 502-2 has an extension length of h2 in the z-direction, and the sixth sub-contact structure 502-3 has an extension length of h3 in the z-direction. Optionally, the fourth sub-contact structure 502-1, the fifth sub-contact structure 502-2, and the sixth sub-contact structure 502-3 are arranged along the x-direction, and their extension lengths h1, h2, and h3 in the z-direction may decrease or increase.

[0078] Furthermore, the plurality of second contact structures 502 are arranged along the x-direction, and their extension length in the z-direction can gradually increase or decrease. For example, the extension length of the plurality of second contact structures 502 arranged along the x-direction in the z-direction can increase or decrease by a predetermined size.

[0079] In some embodiments of this application, a plurality of first contact structures 501 are arranged along the x-direction and their extension length in the z+ direction increases or decreases, and a plurality of second contact structures 502 are arranged along the x-direction and their extension length in the z+ direction increases or decreases.

[0080] By reasonably setting the extension length of multiple contact structures arranged along the x-direction in the above embodiments, the etching process of the contact holes forming multiple contact structures can be changed, and the etching amount can be precisely changed along the x-direction. For example, the etching amount can gradually increase or decrease along the x-direction. By accurately determining the etching amount, the damage of etching to semiconductor intermediates can be reduced, and the product yield of the final semiconductor device can be improved.

[0081] refer to Figure 1 The semiconductor device 1000 further includes a semiconductor layer 203, which is located between the first stacked structure 201 and the second stacked structure 202 along the z+ direction and extends along a direction intersecting the z+ direction (e.g., the x direction or the y direction).

[0082] In the fabrication process of semiconductor device 1000, the first contact hole (not shown) accommodating the first contact structure 501 only needs to extend along the z+ direction in the first stacked structure 201 to the stacking height of the corresponding first gate layer 210. The second contact hole (not shown) accommodating the second contact structure 502 only needs to extend along the z- direction in the second stacked structure 202 to the stacking height of the corresponding second gate layer 220. Therefore, the contact structures connected to different stacked structures are introduced into the corresponding gate layers from both sides of the overall structure formed by the stacked structures. Multiple first contact holes and multiple second contact holes do not require etching of the semiconductor layer 203; the contact holes only extend within their respective corresponding stacked structures. This facilitates the rational arrangement of the etching process for forming multiple contact holes and reduces damage to the semiconductor intermediates by accurately determining the etching amount, thereby improving the yield of the final semiconductor device. Furthermore, this ensures that the fabrication processes of contact structures connected to different stacked structures do not interfere with each other and simplifies the fabrication process of the contact structures.

[0083] Furthermore, the semiconductor device 1000 also includes a channel structure 300, which includes a channel layer 330 and a functional layer 320 located on the surface of the channel layer 330. The channel layer 330 extends along the z-direction and is connected to the semiconductor layer 203. The functional layer 320 includes a first functional layer 320-1 and a second functional layer 320-2. The first functional layer 320-1 extends along the z-direction in the first stacked structure 201, and the second functional layer 320-2 extends along the z-direction in the second stacked structure 202.

[0084] Taking a three-dimensional memory as an example, the channel layer extends along the stacking direction in the stacked structure. The distance between the source layer and the drain layer located on both sides of the channel layer along the stacking direction is lengthened as the number of stacked layers in the stacked structure increases. This leads to a decrease in the open-circuit current of the channel during the operation of the semiconductor device, which affects the execution of the read operation of the semiconductor device.

[0085] In the above-described embodiments of this application, the semiconductor layer 203 is located between the first stacked structure 201 and the second stacked structure 202, and is connected to the channel layer 330. Therefore, the portion of the channel layer 330 located in the first stacked structure 201 (hereinafter referred to as the first channel layer) and the portion of the channel layer 330 located in the second stacked structure 202 (hereinafter referred to as the second channel layer) can be connected in parallel. In other words, the semiconductor layer 203 can serve as the drain (or source) of the first channel layer and the second channel layer in the upper and lower stacked structures (first stacked structure 201 and second stacked structure 202). By connecting the first channel layer and the second channel layer in the upper and lower stacked structures in parallel, the channel open-circuit current of the semiconductor device can be increased.

[0086] Optionally, both the first functional layer 320-1 and the second functional layer 320-2 may include a barrier layer formed on the inner wall of the channel hole (not shown) to block the outflow of charge; a charge trapping layer formed on the surface of the barrier layer to store charge during operation of the semiconductor device; and a tunneling layer formed on the surface of the charge trapping layer.

[0087] In some embodiments, both the first functional layer 320-1 and the second functional layer 320-2 may comprise an oxide-nitride-oxide (ONO) structure. However, in other embodiments, both the first functional layer 320-1 and the second functional layer 320-2 may have a structure different from that of an ONO configuration. The channel layer 330 may be formed on the surface of the tunneling layer and may be used to transport the required charge (electrons or holes).

[0088] Optionally, the channel layer 330 may be fabricated from a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and may contain conductive impurities. For example, the channel layer 330 may include an N-type doped or P-type doped polycrystalline silicon layer. The channel layer 330 may have a cylindrical or columnar shape extending along the z+ direction.

[0089] Alternatively, the channel layer 330 and the semiconductor layer 203 can have the same doping type. Furthermore, the doping concentration of conductive impurities in the semiconductor layer 203 can be greater than that in the channel layer 330. In other words, a drain or source with a relatively high concentration of conductive impurities can improve the mobility of electrons or holes in the channel, thereby improving the response speed of the semiconductor device.

[0090] Additionally, refer to Figure 1 and Figure 2In some embodiments of this application, the channel structure 300 may include a first channel structure 301 and a second channel structure 302. Optionally, a plurality of first channel structures 301 may be located in a first region 11 and pass through portions of a plurality of first gate layers 210 and a plurality of second gate layers 220 located in the first region 11 along the z-direction. A plurality of second channel structures 302 may be located in a second region 12 and pass through portions of a plurality of first gate layers 210 and a plurality of second gate layers 220 located in the second region 12 along the z-direction.

[0091] Alternatively, the second channel structure 302 may include the same layer structure as the first channel structure 301. For example, the first channel structure 301 may include a functional layer 320 located on the inner wall of the first channel hole (not shown) and a channel layer 330 located on the surface of the functional layer 320. The functional layer 320 may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially disposed on the inner wall of the channel hole. The channel layer 330 may be located on the surface of the tunneling layer, and the channel layer 330 may be made of a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and may have conductive impurities. In addition, the first channel structure 301 may also include a channel-filling dielectric layer filling the remaining space of the first channel hole after the functional layer 320 and the channel layer 330 have been formed. The channel-filling dielectric layer includes an insulating dielectric material layer such as a silicon oxide layer.

[0092] Alternatively, the second channel structure 302 may have a different layer structure than the first channel structure 301, and this application does not limit this.

[0093] Refer again Figure 1 In some embodiments of this application, the first contact structure 501 includes a first conductive structure 510 and a first dielectric filling layer 520 surrounded by the first conductive structure 510, wherein the first conductive structure 510 is connected to the first gate layer 210. Optionally, the second contact structure 502 includes a second conductive structure 530 and a second dielectric filling layer 540 surrounded by the second conductive structure 530, wherein the second conductive structure 530 is connected to the second gate layer 230.

[0094] Alternatively, the materials of the first conductive structure 510 and the second conductive structure 530 may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal materials may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor materials may be, for example, doped crystalline silicon or silicides, etc. This application does not limit the specific materials used.

[0095] Furthermore, in one embodiment of this application, both the first dielectric filling layer 520 and the second dielectric filling layer 540 can be dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. The contact structure includes a dielectric filling layer surrounded by a contact conductive structure, which can reduce the use of conductive materials in the contact structure and achieve the effects of reducing the fabrication cost of semiconductor devices and reducing stress deformation on the first and second stacked structures.

[0096] In addition, refer to Figure 1 and Figure 5 In some embodiments of this application, the first contact structure 501 includes a first end 5011 and a second end 5012 opposite to each other along the z+ direction, wherein the second end 5012 is connected to a first gate layer 210, and in the direction intersecting the z+ direction (x direction or y direction), the size d1 of the first end 5011 is smaller than the size d2 of the second end 5012.

[0097] In some embodiments of this application, the second contact structure 502 includes a third end 5021 and a fourth end 5022 opposite to each other along the z+ direction, wherein the fourth end 5022 is connected to a second gate layer 220, and in the direction intersecting the z+ direction (x direction or y direction), the dimension d3 of the third end 5021 is smaller than the dimension d4 of the fourth end 5022.

[0098] In other words, both the first contact structure 501 and the second contact structure 502 can include two interconnected portions: a first portion (not shown) and a second portion (not shown). Taking the first contact structure 501 as an example, the first portion of the first contact structure 501 extends along the z+ direction and extends to the stack height of the first gate layer 210 corresponding to the first contact structure 501. The second portion of the first contact structure 501 extends at the stack height of the corresponding first gate layer 210 along a direction intersecting the z+ direction (e.g., the x or y direction) to connect to the corresponding first gate layer 210.

[0099] Optionally, the second portion of the first contact structure 501 and the first gate layer 210 may have the same thickness in the z+ direction. The first portion of the first contact structure 501 may include a first dielectric filling layer 520.

[0100] In addition, such as Figures 1-4As shown, in some embodiments of this application, the semiconductor device 1000 further includes a gate line isolation structure 400. The gate line isolation structure 400 may extend along the z-direction through the second stacked structure 202, the semiconductor layer 203, and the first stacked structure 201. Furthermore, at least one of the plurality of gate line isolation structures 400 may extend along the x-direction from the first region 11 into the second region 12. Alternatively, at least one of the plurality of gate line isolation structures 400 may extend only along the x-direction in the first region 11. Alternatively, at least one of the plurality of gate line isolation structures 400 may extend only along the x-direction in the second region 12; in this embodiment, the gate line isolation structure 400 located in the second region 12 may be located in a second sub-region 02 of the second region 12. The second sub-region 02 may include two partitions disposed opposite each other in the y-direction.

[0101] Optionally, the second channel structure 302 may be located in the second sub-region 02 of the second region 12. In addition, both the first gate layer 210 and the second gate layer 220 may extend from the first region 11 into the second sub-region 02 of the second region 12 along the x-direction.

[0102] Optionally, such as Figure 5 As shown, the gate isolation structure 400 may include a gate isolation layer 111 and a gate filling layer 112 located on the surface of the gate isolation layer 111. Optionally, the material of the gate isolation layer 111 may include at least one of a high dielectric constant dielectric layer and an insulating dielectric material layer such as a silicon oxide layer. Furthermore, the material of the gate filling layer 112 may include at least one of a semiconductor material such as polysilicon and an insulating dielectric material layer such as silicon oxide, silicon nitride, or silicon oxynitride. Optionally, the material of the gate filling layer 112 may also include a conductive material layer. This application does not limit the internal filling material of the gate isolation structure 400.

[0103] Therefore, according to at least one embodiment of the present application, the semiconductor device includes a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction. A plurality of first contact structures connected to the first stacked structure extend in the first stacked structure along a direction opposite to the first direction and are connected to a first gate layer of the first stacked structure. A plurality of second contact structures connected to the second stacked structure extend in the second stacked structure along the first direction and are connected to a second gate layer of the second stacked structure. This achieves good connection between the gate layer and the contact structures. By introducing contact structures connected to the upper and lower sub-stacked structures (e.g., the first and second stacked structures) of the stacked structure from both sides of the stacked structure along the stacking direction into the corresponding gate layers, the first and second contact structures corresponding to the upper and lower sub-stacked structures can be independently configured without interference, and the process of forming the contact structures is simplified. Furthermore, while improving the reliability and storage density of the semiconductor device, the fabrication cost of the semiconductor device is also reduced.

[0104] Figure 8 This is a flowchart of a method for fabricating a semiconductor device according to one embodiment of this application, 2000. Figures 9-37 These are schematic diagrams of a semiconductor device fabrication method 2000 according to one embodiment of this application.

[0105] like Figure 8 As shown, the semiconductor device fabrication method 2000 may include:

[0106] S1, forming a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction, wherein the first stacked structure includes a first gate layer stacked along the first direction, and the second stacked structure includes a second gate layer stacked along the first direction.

[0107] S2, forming a first contact structure and a second contact structure, wherein the first contact structure extends along a first direction and is connected to a first gate layer, and the second contact structure extends along a direction opposite to the first direction and is connected to a second gate layer.

[0108] The following will combine Figures 8-37 The specific processes of each step of the above preparation method 2000 in the embodiments of this application are described in detail.

[0109] Step S1

[0110] Figure 9 This is a top view schematic diagram of the structure formed after forming the second stacked structure 202' according to a preparation method of one embodiment of this application. Figure 10 This is a cross-sectional schematic diagram of the structure formed after forming the second stacked structure 202' according to a preparation method of one embodiment of this application.

[0111] like Figure 1 , Figures 8-10 As shown, step S1, forming the first stacked structure and the second stacked structure located on one side of the first stacked structure along the first direction, may include, for example, providing an initial substrate 100'; forming the first stacked structure 201 and the second stacked structure 202 located on one side of the first stacked structure 201 along the z+ direction on one side of the initial substrate 100'.

[0112] Specifically, such as Figure 10 As shown, in one embodiment of this application, the material used to fabricate the initial substrate 100' can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, etc., which are III-V compounds. Further, the initial substrate 100' can be selected as single-crystal silicon.

[0113] In one embodiment of this application, the initial substrate 100' may be, for example, a composite substrate for supporting a device structure thereon. Multiple layers made of different materials may be sequentially deposited using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the initial substrate 100'.

[0114] The initial substrate 100' may include a substrate sacrificial layer for subsequent formation of a semiconductor interconnect layer of a connection channel structure. The substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer; alternatively, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Alternatively, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be monocrystalline silicon or polycrystalline silicon; specifically, in one embodiment of this application, an exemplary material forming the sacrificial layer may be polycrystalline silicon.

[0115] A portion of the initial substrate 100' may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion processes. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of this application, the well regions may be prepared using the same or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this application does not limit this.

[0116] like Figure 9 and Figure 10 As shown, in some embodiments of this application, forming a first stacked structure 201 and a second stacked structure 202 located on one side of the first stacked structure 201 along the z+ direction may include: alternately stacking a third dielectric layer 250 and a first gate sacrificial layer 270 to form a first stacked structure 201'; forming a semiconductor layer 203 on one side of the first stacked structure 201' along the z+ direction; alternately stacking a fourth dielectric layer 260 and a second gate sacrificial layer 280 on one side of the semiconductor layer 203 along the z+ direction to form a second stacked structure 202'; and replacing a portion of the first gate sacrificial layer 270 and a portion of the second gate sacrificial layer 280 with a first gate layer 210 (see reference). Figure 3 and Figure 4 ) and second gate layer 220 (reference) Figure 3 and Figure 4 ).

[0117] Specifically, after the initial substrate 100' is formed, a first stacked structure 201' can be formed on one side of the initial substrate 100' by one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and this application does not limit them.

[0118] The first stack structure 201' may include multiple pairs of third dielectric layers 250 and first gate sacrificial layers 270 that are stacked alternately on top of each other. For example, the first stack structure 201' may include multiple pairs of dielectric layers, such as 64 pairs, 128 pairs, or more than 128 pairs of third dielectric layers 250 and first gate sacrificial layers 270.

[0119] In some embodiments, the third dielectric layer 250 and the first gate sacrificial layer 270 may each comprise a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form the third dielectric layer 250 and the first gate sacrificial layer 270 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. Subsequently, a portion of the sacrificial stack layer may be etched away, and the etched portion of the sacrificial stack layer may be replaced with a conductive layer comprising a conductive material to form the first gate layer of the semiconductor device.

[0120] After forming the first stacked structure 201', a double-stack or multi-stack technique can be used to form a stacked structure by sequentially stacking multiple sub-stacked structures in the z+ direction. Each sub-stacked structure may include multiple stacked dielectric layer pairs. The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process of the single stacked structure described above is wholly or partially applicable to the stacked structure formed by multiple sub-stacked structures described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on the double-stacked structure or the multi-stacked structure, wherein the number of sub-stacked structures in the multi-stacked structure is greater than or equal to 3.

[0121] refer to Figure 10 A second stacked structure 202' can be formed on one side of the first stacked structure 201' through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0122] The second stacked structure 202' may include multiple pairs of fourth dielectric layers 260 and second gate sacrificial layers 280 that are stacked alternately with each other. For example, the second stacked structure 202' may include multiple pairs of dielectric layers, such as 64 pairs, 128 pairs, or more than 128 pairs of fourth dielectric layers 260 and second gate sacrificial layers 280.

[0123] It should be noted that the dimension of the fourth dielectric layer 261 that is farthest from the initial substrate 100' among the multiple fourth dielectric layers 260 in the z+ direction may be greater than or equal to the dimension of any of the other fourth dielectric layers 260 in the z+ direction.

[0124] Furthermore, in some embodiments of this application, a semiconductor layer 203 may be formed on the side of the first stacked structure 201' away from the initial substrate 100' before the second stacked structure 202' is formed.

[0125] Specifically, a semiconductor layer 203 can be formed through one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the semiconductor layer 203 includes semiconductor materials such as polycrystalline silicon or monocrystalline silicon. Furthermore, the semiconductor layer 203 may include N-type or P-type doped conductive impurities. The semiconductor layer 203 may extend along a direction intersecting the z+ direction (e.g., the x-direction or the y-direction).

[0126] After forming the semiconductor layer 203, the second stacked structure 202' can be formed using the method described above. In other words, the semiconductor layer 203 is located between the first stacked structure 201' and the second stacked structure 202' along the z+ direction.

[0127] The stacked structure having a first stacked structure 201' and a second stacked structure 202' may include a first region 11 and a second region 12 distributed adjacently along the x direction intersecting the z+ direction, wherein the first region 11 can be used to form a channel structure with storage function, and the second region 12 can be used to form a contact structure, which can be connected to a gate layer subsequently formed.

[0128] Figure 11 This is a top view schematic diagram of the structure formed after forming the channel hole 310 according to a preparation method of one embodiment of this application. Figure 12 This is a cross-sectional schematic diagram of the structure formed after forming the channel hole 310 according to a preparation method according to one embodiment of this application. Figure 13 This is a top view schematic diagram of the structure formed after forming the initial functional layer 320' according to a preparation method of one embodiment of this application. Figure 14This is a cross-sectional schematic diagram of the structure formed after forming the initial functional layer 320' according to a preparation method of one embodiment of this application.

[0129] Figure 15 This is a top view schematic diagram of the structure formed after forming the channel structure 300 according to a preparation method of one embodiment of this application. Figure 16 This is a cross-sectional schematic diagram of the structure formed after forming the channel structure 300 according to a preparation method according to one embodiment of this application.

[0130] like Figures 11-16 As shown, in some embodiments of this application, the semiconductor device fabrication method 2000 further includes forming a channel structure 300. Forming the channel structure 300 may include, for example,: forming a channel hole 310, the channel hole 310 extending along the z-direction in a first stacked structure 201' and a second stacked structure 202', wherein the channel hole 310 exposes a portion of the semiconductor layer 203; forming an initial functional layer 320' in the channel hole 310; removing the portion of the initial functional layer 320' located on the exposed semiconductor layer 203 to form a first functional layer 320-1 and a second functional layer 320-2, wherein the first functional layer 320-1 extends along the z-direction in the first stacked structure 201' and the second functional layer 320-2 extends along the z-direction in the second stacked structure 202'; and forming a channel layer 330 on the surfaces of the first functional layer 320-1, the semiconductor layer 203, and the second functional layer 320-2.

[0131] The channel structure 300 may include a semiconductor layer and a composite dielectric layer filled within the channel via 310. For example, the channel structure 300 may include a functional layer 320 and a channel layer 330 located on the surface of the functional layer 320. In addition, the plurality of channel structures 300 may include a plurality of first channel structures 301 located in the first region 11 and having storage functions, and a plurality of second channel structures 302 located in the second region 12.

[0132] Specifically, such as Figures 10-12 As shown, a plurality of channel holes 310 are formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., wherein the plurality of channel holes 310 may include a plurality of first channel holes 310-1 located in the first region 11 and a plurality of second channel holes 310-2 located in the second region 12. The channel holes 310 may expose a portion of the semiconductor layer 203.

[0133] Alternatively, the channel hole 310 passes through the second stacked structure 202', the semiconductor layer 203 and the first stacked structure 201' along the z-direction and extends into the initial substrate 100'.

[0134] Optionally, the multiple channel holes 310 may have the same depth in the z-direction to reduce the difficulty and cost of fabricating semiconductor devices. Optionally, the aperture size of the second channel hole 310-2 may be larger than the aperture size of the first channel hole 310-1.

[0135] like Figures 11-14 As shown, after forming multiple channel holes 310, an initial functional layer 320' can be formed on the inner wall of the channel holes 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0136] The initial functional layer 320' may include a barrier layer formed on the inner wall of the channel via 310 and on the exposed semiconductor layer 203 to prevent charge outflow; a charge trapping layer formed on the surface of the barrier layer to store charge during operation of the semiconductor device; and a tunneling layer formed on the surface of the charge trapping layer.

[0137] In some embodiments of this application, the initial functional layer 320' may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the initial functional layer 320' may have a structure different from the ONO configuration.

[0138] Furthermore, those skilled in the art should understand that, without departing from the teachings of this application, the initial functional layer may be formed on the sidewalls and bottom surface of the channel hole, or on the sidewalls of the channel hole, depending on the different semiconductor device architectures, and this application does not limit this.

[0139] like Figures 13-16 As shown, by means of, for example, dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove the portion of the initial functional layer 320' located on the exposed semiconductor layer 203, forming a first functional layer 320-1 and a second functional layer 320-2, wherein the first functional layer 320-1 extends along the z-direction in the first stacked structure 201', and the second functional layer 320-2 extends along the z-direction in the second stacked structure 202'.

[0140] Optionally, after removing the portion of the initial functional layer 320' located on the exposed semiconductor layer 203 and re-exposing a portion of the semiconductor layer 203, a new semiconductor material layer can be formed on the surface of the re-exposed semiconductor layer 203 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, in order to reduce the damage to the semiconductor layer 203 caused by the aforementioned process of "removing the portion of the initial functional layer 320' located on the exposed semiconductor layer 203".

[0141] After the formation of the first functional layer 320-1 and the second functional layer 320-2, a channel layer 330 can be formed on the surfaces of the first functional layer 320-1, the semiconductor layer 203, and the second functional layer 320-2 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other words, the surface of the channel layer 330 is in direct contact with the surface of the semiconductor layer 203, thereby connecting the two.

[0142] Optionally, the channel layer 330 can be used to transport the required charge (electrons or holes). The channel layer 330 can be fabricated from a semiconductor material such as polycrystalline silicon or monocrystalline silicon and can have conductive impurities. For example, the channel layer 330 can be an N-type doped or P-type doped polycrystalline silicon layer. Similar to the channel via 310, the channel layer 330 can also have a cylindrical or columnar shape extending along the z-direction. Alternatively, the channel layer 330 can also extend into the initial substrate 100'.

[0143] In addition, such as Figure 16 As shown, the channel structure 300 also includes a channel plug formed at the end of the channel hole 310 away from the initial substrate 100' (which can be understood as the top end of the channel structure 300). Specifically, after forming the channel layer 330, the channel hole 310 can be filled with a channel-filling dielectric layer (such as...). Figure 14 (As shown). The channel-filling dielectric layer may include an oxide dielectric layer, such as silicon oxide. Furthermore, during the filling process, multiple insulating gaps can be formed in the channel-filling dielectric layer to alleviate structural stress by controlling the channel filling process. Then, a channel plug is formed in the portion of the channel-filling dielectric layer located at the top of the channel via 310. The channel plug can be made of the same material as the channel layer 330, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer 330.

[0144] In addition, such as Figures 11-16As shown, as an alternative, since the second channel structure 302 does not have a storage function, the second channel hole 310-2 can also be filled only with an insulating dielectric material layer, such as a silicon oxide layer, using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Similarly, by controlling the channel filling process, multiple insulating gaps can be formed in the insulating dielectric material layer to reduce the structural stress of the second channel structure 302.

[0145] Figure 17 This is a top view schematic diagram of the structure formed after exposing the gate gap 401, according to a preparation method of one embodiment of this application. Figure 18 This is a perspective view of the structure formed after forming the gate isolation structure 400 according to a preparation method of one embodiment of this application. Figure 19 yes Figure 18 The diagram shown is an enlarged view of the structure at point S. Figure 20 yes Figure 19 The diagram shows a cross-sectional view of the structure taken along line D-D'. Figure 21 yes Figure 19 The diagram shows a cross-sectional view of the structure taken along line E-E'.

[0146] In addition, refer to Figures 11-21 In some embodiments of this application, the semiconductor device fabrication method 2000 further includes forming a gate isolation structure 400.

[0147] The gate gap 401 generated during the formation of the gate isolation structure 400 can serve as a pathway for providing etchant, thereby allowing the removal of a portion of the first gate sacrificial layer 270 and a portion of the second gate sacrificial layer 280 using processes such as wet etching. The first gate layer 210 (see reference) is then formed in the void (not shown) formed after the removal of the portion of the first gate sacrificial layer 270 and the portion of the second gate sacrificial layer 280. Figure 1 ) and second gate layer 220 (reference) Figure 1 ).

[0148] Specifically, such as Figures 11-12As shown, the gate line gap 401 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. At least one of the plurality of gate line gaps 401 can extend from the first region 11 into the second region 12 along the x-direction; or, at least one of the plurality of gate line gaps 401 can extend along the x-direction in the first region 11; or, at least one of the plurality of gate line gaps 401 can extend along the x-direction in the second region 12. In addition, the gate line gap 401 can pass through the second stacked structure 202', the semiconductor layer 203, and the first stacked structure 201' along the z+ direction and extend into the initial substrate 100'.

[0149] Optionally, such as Figures 11-16 As shown, during the formation of the channel structure 300, a gate gap sacrificial layer 113 can be filled into the gate gap 401. The gate gap sacrificial layer 113 may include a carbon-containing material layer, a polysilicon material layer, etc. The gate gap sacrificial layer 113 can be formed of a material with a high deposition rate to facilitate rapid filling of the gate gap 401, and the gate gap sacrificial layer 113 should be any material with high dry etching selectivity relative to the third dielectric layer 250, the fourth dielectric layer 260, the first gate sacrificial layer 270, and the second gate sacrificial layer 280 to facilitate removal in subsequent steps.

[0150] like Figures 15-17 As shown, the gate gap sacrificial layer can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to expose the gate gap 401, and by means of the gate gap 401, a portion of the first gate sacrificial layer 270 and a portion of the second gate sacrificial layer 280 can be removed.

[0151] refer to Figure 16 and Figure 17 At least one of the plurality of gate line gaps 401 may extend from the first region 11 into the second region 12 along the x-direction; or, at least one of the plurality of gate line gaps 401 may extend along the x-direction in the first region 11; or, at least one of the plurality of gate line gaps 401 may extend along the x-direction in the second region 12. Therefore, the portions of the first gate sacrificial layer 270 and the second gate sacrificial layer 280 located in the first region 11 can be removed by means of the portions of the plurality of gate line gaps 401 located in the first region 11, and the portions of the first gate sacrificial layer 270 and the second gate sacrificial layer 280 located in the second region 12 adjacent to the gate line gaps 401 can be removed by means of the portions of the plurality of gate line gaps 401 located in the second region 12.

[0152] Specifically, during the process of removing part of the first gate sacrificial layer 270 and part of the second gate sacrificial layer 280 using processes such as wet etching, the etchant and chemical precursor can be made to contact part of the first gate sacrificial layer 270 and part of the second gate sacrificial layer 280 through the gate line gap 401, thereby removing part of the first gate sacrificial layer 270 and part of the second gate sacrificial layer 280 and forming sacrificial voids (not shown).

[0153] Furthermore, in at least one embodiment of this application, the layout of the gate gap 401 in the xy plane can be selected according to different settings of the final semiconductor device architecture, so as to optimize the process window of the above-mentioned gate sacrificial layer removal step, reduce the size of the gate isolation structure formed based on the gate gap 401, and increase the storage density of the final semiconductor device.

[0154] like Figures 17-21 As shown, the first gate layer 210 and the second gate layer 220 can be formed in the sacrificial voids using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. By removing a portion of the first gate sacrificial layer 270, the first gate layer 210 can be formed in the space formed by removing the portion of the first gate sacrificial layer 270; by removing a portion of the second gate sacrificial layer 280, the second gate layer 220 can be formed in the space formed by removing the portion of the second gate sacrificial layer 280.

[0155] Both the first gate layer 210 and the second gate layer 220 may include conductive materials. The conductive materials may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal materials may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor materials may be, for example, doped crystalline silicon or silicides, etc. This application does not limit the specific materials used.

[0156] Furthermore, in some embodiments of this application, after forming the first gate layer 210 and the second gate layer 220, a gate line isolation structure 400 can also be formed by filling the gate line gap 401. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a gate line isolation layer 111 and a gate line filling layer 112 located on the surface of the gate line isolation layer 111 within the gate line gap 401.

[0157] Optionally, the material of the gate isolation layer 111 may include at least one of a high dielectric constant dielectric layer and an insulating dielectric material layer such as a silicon oxide layer. Furthermore, the material of the gate filling layer 112 may include at least one of a semiconductor material such as polysilicon and an insulating dielectric material layer such as silicon oxide, silicon nitride, or silicon oxynitride. Optionally, the material of the gate filling layer 112 may also include a conductive material layer. This application does not limit the internal filling material of the gate isolation structure 400.

[0158] In addition, such as Figure 16 and Figure 20 , Figure 21 As shown, after the gate isolation structure 400, the first gate layer 210 and the second gate layer 220 are formed in the first stacked structure 201' and the second stacked structure 202', the first stacked structure 201' and the second stacked structure 202' are formed as the first stacked structure 201 and the second stacked structure 202, wherein the remaining first gate sacrificial layer 270 and the remaining second gate sacrificial layer 280 are formed as the first dielectric layer 230 and the second dielectric layer 240, respectively.

[0159] like Figures 18-21 As shown, both the first gate layer 210 and the second gate layer 220 extend from the first region 11 into the second region 12 along the x-direction, and can be connected to the first dielectric layer 230 and the second dielectric layer 240 located in the second region 12, respectively. The portions of the first gate layer 210 and the second gate layer 220 in the second region 12 are located at the edge of the gate isolation structure 400. In the following text, contact structures can be formed in the regions where the first dielectric layer 230 and the second dielectric layer 240 are located, wherein the contact structures may include a first contact structure connected to the first gate layer 210 and a second contact structure connected to the second gate layer 220. The fabrication process of the contact structures will be described in detail below with reference to the accompanying drawings. It should be noted that... Figure 19 For ease of observation, the first gate layer 210, the second gate layer 220, the first dielectric layer 230, and the second dielectric layer 240 are omitted in the subsequent top view.

[0160] Step S2

[0161] Figure 22 This is a top view schematic diagram of the structure formed after forming the first opening 102, according to a preparation method according to one embodiment of this application. Figure 23 yes Figure 21 The diagram shows a cross-sectional view of the structure taken along line G-G'. Figure 24 yes Figure 24 The diagram shows a cross-sectional view of the structure taken along line F-F'. Figure 25 This is a cross-sectional schematic diagram of the structure formed after forming the first mask layer 204 according to a preparation method of one embodiment of this application. Figure 26This is a cross-sectional schematic diagram of the structure formed after forming the first process opening 2 according to a preparation method of one embodiment of this application. Figure 27 This is a cross-sectional schematic diagram of the structure formed after forming the first filling layer 205 according to a preparation method of one embodiment of this application. Figure 28 This is a cross-sectional schematic diagram of the structure formed after forming the second process opening 3 according to a preparation method of one embodiment of this application. Figure 29 This is a cross-sectional schematic diagram of the structure formed after forming the second filling layer 206 according to a preparation method of one embodiment of this application. Figure 30 This is a cross-sectional schematic diagram of the structure formed after forming the third process opening 4 according to a preparation method of one embodiment of this application. Figure 31 This is a cross-sectional schematic diagram of the structure formed after forming the second contact hole 521 according to a preparation method of one embodiment of this application. Figure 32 This is a cross-sectional schematic diagram of the structure formed after forming the second contact structure 502 according to a preparation method according to one embodiment of this application. Figure 33 This is a cross-sectional schematic diagram of the structure formed by flipping an intermediate having a first interconnect structure 710 by 180° according to a preparation method of one embodiment of this application. Figure 34 This is a top view schematic diagram of the structure formed after forming the third opening 101 according to a preparation method of one embodiment of this application. Figure 35 This is a cross-sectional schematic diagram of the structure formed after forming the first contact hole 511 according to a preparation method of one embodiment of this application. Figure 36 This is a cross-sectional schematic diagram of the structure formed after forming the first contact structure 501 according to a preparation method of one embodiment of this application. Figure 37 This is a cross-sectional schematic diagram of the structure formed after forming the connecting structure 800 according to a preparation method of one embodiment of this application.

[0162] like Figures 22-37 As shown, step S2 forms a first contact structure and a second contact structure, wherein the first contact structure extends along a first direction and is connected to a first gate layer, and the second contact structure extends along a direction opposite to the first direction and is connected to a second gate layer. This may include, for example, forming a first contact hole 511 and a second contact hole 521, wherein the first contact hole 511 extends from a first side 200-1 of the first stacked structure 201 along the z+ direction to a first gate layer 210, and the second contact hole 521 extends from a second side 200-2 of the second stacked structure 202 along the z- direction to a second gate layer 220, with the first side 200-1 and the second side 200-2 opposite each other in the z+ direction; and filling the first contact hole 511 and the second contact hole 521 to form a first contact structure 501 and a second contact structure 502.

[0163] Optionally, the first contact hole 511 and the second contact hole 521 can be formed in stages. For example, the second contact hole 521 can be formed first, and then the intermediate body with the second contact hole 521 formed can be flipped, and the first contact hole 511 can be formed in the flipped intermediate body. Alternatively, the first contact hole 511 can be formed first, and then the intermediate body with the first contact hole 511 formed can be flipped, and the second contact hole 521 can be formed in the flipped intermediate body. The process of forming the first contact hole 511 and the second contact hole 521 will be described below with reference to the accompanying drawings, taking the example of forming the second contact hole 521 first and then the first contact hole 511.

[0164] like Figures 22-31 As shown, forming the second contact hole 521 may include: forming a first opening 102 extending along the z- direction; and forming a second opening 104 communicating with the first opening 102 via the first opening 102, the second opening 104 extending to a second gate layer 220 in a direction intersecting the z+ direction (e.g., the x direction or the y direction), wherein, in the direction intersecting the z+ direction, the size d2 of the second opening 104 is larger than the size d1 of the first opening 102.

[0165] Specifically, the following will combine Figures 24-30 The process of forming a plurality of first openings 102 according to one embodiment of the present application is described in detail.

[0166] like Figure 25 As shown, the second stacked structure 202 may include a plurality of alternately stacked second dielectric layers 240 and a plurality of fourth dielectric layers 260. Figure 25 The plurality of second dielectric layers 240 shown may include a first layer 241, a second layer 242, a third layer 243, and a fourth layer 244. It should be noted that in this embodiment, only a second stacked structure including four second dielectric layers is used as an example to describe the process of forming a plurality of first openings; however, this application does not limit the number of second dielectric layers.

[0167] Combination Figure 23 and Figure 25The second dielectric layer 240 is disposed on the same layer as the second gate layer 220. In other words, the first layer 241, the second layer 242, the third layer 243, and the fourth layer 244 all have a second gate layer 220 disposed on the same layer as them. For example, the second gate layer 221 is disposed on the same layer as the first layer 241, the second gate layer 222 is disposed on the same layer as the second layer 242, the second gate layer 223 is disposed on the same layer as the third layer 243, and the second gate layer 224 is disposed on the same layer as the fourth layer 244. In this embodiment, a plurality of first openings 102 are formed in the insulating dielectric material stack layer including the second dielectric layer 240 and the fourth dielectric layer 260, and each of the plurality of first openings 102 extends along the z-direction to a different stack height.

[0168] like Figure 25 As shown, a patterned first mask layer 204 can be formed on the surface of the second stacked structure 202 away from the first stacked structure 201, wherein the shape and size of the pattern 1 in the first mask layer 204 can be consistent with the pre-formed plurality of first openings 102 (e.g., Figure 24 (As shown) has the same shape and size.

[0169] For example, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a first mask layer 204 on the surface of the second stacked structure 202 away from the first stacked structure 201. Subsequently, a photolithography process can be used to transfer the mask pattern in a photomask (not shown) to the first mask layer 204 to form a first mask layer 204 having pattern 1.

[0170] like Figure 25 and Figure 26 As shown, using a patterned first mask layer 204 as a mask, a dry etching process or a combination of dry and wet etching processes can be performed. Other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be executed to form a first process opening 2 in the second stacked structure 202. It should be noted that, limited by the etching process, the top dimension of the first process opening 2 and the subsequent multiple process openings can be larger than their bottom dimension, and the error range between the two can be between -10% and 10%.

[0171] The first process opening 2 can extend along the z-direction to between the third layer 243 and the fourth layer 244. In addition, a plurality of first process openings 2 can be distributed at intervals along the x-direction, wherein the plurality of first process openings 2 include a first branch opening 21, a second branch opening 22 and a third branch opening 23 distributed at intervals along the x-direction.

[0172] like Figure 26 and Figure 27As shown, the third opening 23 can be configured to form a second contact hole 521 extending to the third layer 243. The etching depth of the third opening 23 formed in the above process already meets the requirements of the second contact hole 521 extending to the third layer 243. Therefore, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a first filling layer 205. The first filling layer 205 fills the third opening 23.

[0173] like Figure 27 and Figure 28 As shown, after filling the third opening 23, a dry etching process or a combination of dry and wet etching processes can be used, or other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form a second process opening 3 in the second stacked structure 202. The second process opening 3 can extend along the z-direction between the second layer 242 and the third layer 243. In addition, a plurality of second process openings 3 can be spaced apart along the x-direction, wherein the plurality of second process openings 3 includes a fourth opening 31 and a fifth opening 32 spaced apart along the x-direction.

[0174] like Figure 28 and Figure 29 As shown, the fifth opening 32 can be configured to form a second contact hole 521 extending to the second layer 242. The etching depth of the fifth opening 32 formed in the above process already meets the requirement of the second contact hole 521 extending to the second layer 242. Therefore, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a second filling layer 206. The second filling layer 206 fills the fifth opening 32 and the third opening 23.

[0175] like Figure 29 and Figure 30 As shown, after forming the second filling layer 206, a dry etching process or a combination of dry and wet etching processes can be used, or other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form a third process opening 4 in the second stacked structure 202. The third process opening 4 can extend along the z-direction between the first layer 241 and the second layer 242. Figure 30 Only one third process opening 4 is shown, however, the number of third process openings 4 may include multiple ones. In addition, multiple second process openings 4 may be distributed at intervals along the x-direction.

[0176] like Figure 24 and Figure 30 As shown, it can be set Figure 30The third process opening 4 shown is used to form a second contact hole 521 extending into the first layer 241. The etching depth of the third process opening 4 formed in the above process already meets the requirements of the second contact hole 521 in the first layer 241. A plurality of first openings 102 are spaced apart along the x-direction and include a first opening 1021 extending between the first layer 241 and the second layer 242, a first opening 1022 extending between the second layer 242 and the third layer 243, and a first opening 1021 extending between the third layer 243 and the fourth layer 244. A first opening 1023 can be formed from one of the plurality of first process openings 2, a first opening 1022 can be formed from one of the plurality of second process openings 3, and a first opening 1021 can be formed from one of the plurality of third process openings 4. In other words, through multiple etching processes, a plurality of first openings 102 distributed along the x-direction can be formed, wherein the extension length of the plurality of first openings 102 in the z-direction can be different; for example, the extension length of the plurality of first openings 102 along the x-direction can be larger or smaller in the z-direction.

[0177] refer to Figures 30-31 In some embodiments of this application, after forming a plurality of first openings 102, a dry etching process or a combination of dry and wet etching processes can be used, or other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form a second opening 104 communicating with the first openings 102. The communicating first openings 102 and second openings 104 are formed as a second contact hole 521. The second opening 104 extends to a second gate layer 220 in a direction intersecting the z-direction (e.g., the x-direction or the y-direction), and in the direction intersecting the z-direction, the size d2 of the second opening 104 is larger than the size d1 of the first opening 102.

[0178] refer to Figures 31-32 In some embodiments of this application, after the second contact hole 521 is formed, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to form a second conductive structure 530 and a second dielectric filling layer 540 surrounded by the second conductive structure 530 in the second contact hole 521, wherein the second conductive structure 530 is connected to the second gate layer 220.

[0179] Alternatively, the material of the second conductive structure 530 may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal materials may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor materials may be, for example, doped crystalline silicon or silicides, etc. This application does not limit the specific materials used.

[0180] Furthermore, in one embodiment of this application, the second dielectric filling layer 540 may be, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The contact structure includes a dielectric filling layer surrounded by a conductive contact structure, which can reduce the use of conductive materials in the contact structure and achieve the effects of reducing the fabrication cost of semiconductor devices and reducing stress deformation of the second stacked structure.

[0181] like Figures 32-37 As shown, prior to forming the first contact structure 501, the semiconductor device fabrication method 2000 may further include forming a first interconnect structure 710 connected to the first contact structure 501. The first interconnect structure 710 may extend along the z-direction in the first stacked structure 201 and the second stacked structure 202, and connect the first contact structure 501 to the peripheral circuit 601 (e.g., ...). Figure 1 (As shown).

[0182] Specifically, a dry etching process or a combination of dry and wet etching processes can be used, or other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form a first interconnect hole (not shown) extending along the z-direction in the first stacked structure 201 and the second stacked structure 202. A thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, is then used to fill the first interconnect hole to form a first interconnect structure 710. The first interconnect structure 710 may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicides, etc., which are not limited in this application.

[0183] like Figures 33-35 As shown, after the first interconnect structure 710 is formed, the intermediate body can be flipped 180° and a plurality of first contact holes 511 can be formed from the first side 200-1 away from the second stacked structure 202 from the first stacked structure 201.

[0184] Specifically, forming the first contact hole 511 may include: forming a third opening 101 extending along the z+ direction; and forming a fourth opening 103 communicating with the third opening 101 via the third opening 101, the fourth opening 103 extending to a first gate layer 210 in a direction intersecting the z+ direction (e.g., the x direction or the y direction), wherein, in the direction intersecting the z+ direction, the size of the fourth opening 103 is larger than the size of the third opening 101.

[0185] Alternatively, the following can be adopted: Figures 24-30The process of forming the first opening 102 shown is used to form a plurality of third openings 101. Through multiple etching processes, a plurality of third openings 101 distributed along the x-direction can be formed, wherein the extension length of the plurality of third openings 101 in the z+ direction can be different, for example, the extension length of the plurality of third openings 101 in the z+ direction along the x-direction can be increased or decreased.

[0186] like Figure 31 and Figure 35 As shown, in the process of forming the first contact hole 511 and the second contact hole 512, the first contact hole 511 extends only along the z+ direction in the first stacked structure 201, and the second contact hole 512 extends only along the z- direction in the second stacked structure 202. Neither of them needs to extend through the semiconductor 203. This allows the fabrication process of the contact structure connected to different stacked structures to not affect each other and simplifies the fabrication process of the contact structure.

[0187] like Figures 35-36 As shown, in one embodiment of this application, after forming the first contact hole 511, a first contact structure 501 can be formed in the first contact hole 511 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first contact structure 501 includes a first conductive structure 510 and a first dielectric filling layer 520 surrounded by the first conductive structure 510, wherein the first conductive structure 510 is connected to the first gate layer 210.

[0188] Alternatively, the material of the first conductive structure 510 may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal materials may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor materials may be, for example, doped crystalline silicon or silicides, etc. This application does not limit the specific materials used.

[0189] Furthermore, in one embodiment of this application, the first dielectric filling layer 520 may be, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The contact structure includes a dielectric filling layer surrounded by a contact conductive structure, which can reduce the use of conductive materials in the contact structure and achieve the effects of reducing the fabrication cost of semiconductor devices and reducing stress deformation of the first stacked structure.

[0190] like Figure 36 and Figure 37 As shown, after forming the first contact structure 501, a connection structure 800 can be formed. The connection structure 800 extends along the y-direction on a first side 200-1 of the first stacked structure 201 and connects the first interconnect structure 710 and the first contact structure 501. The first contact structure 501, through the first interconnect structure 710 and the connection structure 800, can achieve connection with the peripheral circuit 601 (such as...). Figure 1 The connection shown is shown.

[0191] Optionally, the interconnect structure 800 can be formed using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the interconnect structure 800 may include any one or a combination of conductive metal materials and doped semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicides, etc., and this application does not limit the specific materials used.

[0192] like Figure 1 and Figure 37 As shown, a semiconductor device 1000 can be formed by combining the peripheral circuit layer 600, which includes the peripheral circuit 601, with the overall structure including the first stacked structure 201 and the second stacked structure 202 through processes such as bonding.

[0193] Therefore, according to at least one embodiment of the semiconductor device fabrication method provided in this application, the semiconductor device includes a first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction. A plurality of first contact structures connected to the first stacked structure extend in the first stacked structure along a direction opposite to the first direction and are connected to a first gate layer of the first stacked structure. A plurality of second contact structures connected to the second stacked structure extend in the second stacked structure along the first direction and are connected to a second gate layer of the second stacked structure. This achieves good connection between the gate layer and the contact structures. By introducing contact structures connected to the upper and lower sub-stacked structures (e.g., the first and second stacked structures) of the stacked structure from both sides of the stacked structure along the stacking direction into the corresponding gate layers, the first and second contact structures corresponding to the upper and lower sub-stacked structures can be independently configured without interference, and the process of forming the contact structures is simplified. Furthermore, while improving the reliability and storage density of the semiconductor device, the fabrication cost of the semiconductor device is also reduced.

[0194] Figure 38 This is a schematic diagram of a memory system 30000 according to one embodiment of this application.

[0195] like Figure 38As shown, at least one embodiment of another aspect of this application also provides a memory system 30000. The memory system 30000 may include a semiconductor device 32100 and a controller 32200. The semiconductor device 32100 may be the same as the semiconductor device described in any of the embodiments above, and will not be repeated here. The semiconductor device 32100 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following description will use a three-dimensional semiconductor device as an example.

[0196] Alternatively, a three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0197] The memory system 30000 may include a semiconductor device 32100 and a controller 32200. The semiconductor device 32100 may be the same as the semiconductor device described in any of the embodiments above, and will not be repeated here. The controller 32200 can control the semiconductor device 32100 via a channel CH, and the semiconductor device 32100 can perform operations based on the control of the controller 32200 in response to a request from the host 31000. The semiconductor device 32100 can receive a command CMD and an address ADDR from the controller 32200 via the channel CH and access a region selected from the memory cell array in response to that address. In other words, the semiconductor device 32100 can perform internal operations corresponding to the command on the region selected by the address.

[0198] In some implementations, the three-dimensional storage system can be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. The storage system provided in this application, due to the incorporation of the semiconductor device provided in this application, has the same beneficial effects as the described semiconductor device, and will not be elaborated upon here.

[0199] Although exemplary fabrication methods and structures of semiconductor devices are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor device. Furthermore, the materials of the exemplified layers are merely exemplary.

[0200] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that, include: The first stacked structure includes a first gate layer stacked along a first direction; The second stacked structure is located on one side of the first stacked structure along the first direction and includes a second gate layer stacked along the first direction; as well as A first contact structure extends along the first direction in the first stacked structure and is connected to a first gate layer; as well as The second contact structure extends in the second stacked structure in a direction opposite to the first direction and is connected to a second gate layer.

2. The semiconductor device according to claim 1, wherein, The first contact structure and the second contact structure are symmetrically arranged along a direction intersecting the first direction.

3. The semiconductor device according to claim 1, wherein, The first contact structure extends along the first direction from the first side of the first stacked structure and is connected to a first gate layer. as well as The second contact structure extends from the second side of the second stacked structure in a direction opposite to the first direction and is connected to a second gate layer. The first side and the second side are opposite each other in the first direction.

4. The semiconductor device according to claim 1, wherein, The first gate layer extends in the first stacked structure along a second direction intersecting the first direction; The semiconductor device further includes a first dielectric layer disposed on the same layer as the first gate layer; and The first contact structure extends along the first direction, passes through at least one of the first dielectric layers, and is connected to a first gate layer.

5. The semiconductor device according to claim 4, wherein, The first contact structure includes a first end and a second end opposite to each other along the first direction. Wherein, the second end is connected to the first gate layer; and in the direction intersecting the first direction, the size of the first end is smaller than the size of the second end.

6. The semiconductor device according to claim 1, wherein, The second gate layer extends in the second stacked structure along a second direction intersecting the first direction; The semiconductor device further includes a second dielectric layer disposed on the same layer as the second gate layer; as well as The second contact structure extends in a direction opposite to the first direction, passes through at least one of the second dielectric layers, and is connected to a second gate layer.

7. The semiconductor device according to claim 6, wherein, The second contact structure includes a third end and a fourth end opposite to each other along the first direction. The fourth end is connected to a second gate layer; and in a direction intersecting the first direction, the size of the third end is smaller than the size of the fourth end.

8. The semiconductor device according to claim 1, wherein, Also includes: The peripheral circuit is located on one side of the second stacked structure along the first direction; A first interconnection structure extends in the first stacked structure and the second stacked structure in a direction opposite to the first direction, and connects the peripheral circuit and the first contact structure; as well as The second interconnection structure is located between the peripheral circuit and the second contact structure, and connects the peripheral circuit and the second contact structure.

9. The semiconductor device according to claim 1, wherein, Also includes: A semiconductor layer is located between the first stacked structure and the second stacked structure along the first direction and extends along a direction intersecting the first direction.

10. The semiconductor device according to claim 9, wherein, Also includes: The channel structure includes a channel layer and a functional layer located on the surface of the channel layer. The channel layer extends in a direction opposite to the first direction and is connected to the semiconductor layer; and The functional layer includes a first functional layer and a second functional layer. The first functional layer extends in the first stacked structure along a direction opposite to the first direction, and the second functional layer extends in the second stacked structure.

11. The semiconductor device according to claim 10, wherein, The channel layer and the semiconductor layer have the same doping type.

12. The semiconductor device according to claim 11, wherein, The doping concentration of conductive impurities in the semiconductor layer is greater than that of conductive impurities in the channel layer.

13. The semiconductor device according to claim 1, wherein, Multiple first contact structures are arranged along a direction intersecting the first direction, and have different extension lengths in the first direction; or Multiple second contact structures are arranged along a direction intersecting the first direction, and have different extension lengths in the direction opposite to the first direction.

14. The semiconductor device according to claim 1, wherein, Multiple first contact structures are arranged along a direction intersecting the first direction, and their extension length in the first direction increases or decreases.

15. The semiconductor device according to claim 1, wherein, Multiple second contact structures are arranged along a direction intersecting the first direction, and their extension length in the opposite direction to the first direction increases or decreases.

16. The semiconductor device according to claim 1, wherein, The first contact structure includes a first conductive structure and a first dielectric filling layer surrounded by the first conductive structure.

17. The semiconductor device according to claim 1, wherein, The second contact structure includes a second conductive structure and a second dielectric filling layer surrounded by the second conductive structure.

18. A method for fabricating a semiconductor device, characterized in that, include: A first stacked structure and a second stacked structure located on one side of the first stacked structure along a first direction are formed, wherein the first stacked structure includes a first gate layer stacked along the first direction, and the second stacked structure includes a second gate layer stacked along the first direction; and A first contact structure and a second contact structure are formed, wherein the first contact structure extends along the first direction and is connected to a first gate layer, and the second contact structure extends along a direction opposite to the first direction and is connected to a second gate layer.

19. The method according to claim 18, wherein, The formation of the first contact structure and the second contact structure includes: A first contact hole and a second contact hole are formed, wherein the first contact hole extends from a first side of the first stacked structure along the first direction to a first gate layer, and the second contact hole extends from a second side of the second stacked structure along a direction opposite to the first direction to a second gate layer, the first side and the second side being opposite to each other in the first direction; and The first contact hole and the second contact hole are filled to form the first contact structure and the second contact structure.

20. The method according to claim 19, wherein, Forming the first contact hole and the second contact hole includes: Forming the second contact hole; and The intermediate body with the second contact hole is flipped over, and the first contact hole is formed in the flipped intermediate body.

21. The method according to claim 19, wherein, Forming the second contact hole includes: Forming a first opening extending in a direction opposite to the first direction; and A second opening communicating with the first opening is formed through the first opening, and the second opening extends to a second gate layer in a direction intersecting the first direction. In the direction intersecting the first direction, the size of the second opening is larger than the size of the first opening.

22. The method according to claim 21, wherein, The plurality of first openings are arranged along a second direction intersecting the first direction, and have different lengths of extension in the direction opposite to the first direction.

23. The method according to claim 18, wherein, The formation of the first stacked structure and the second stacked structure located on one side of the first stacked structure along the first direction include: Alternating stacking of a first isolation layer and a first gate sacrificial layer forms a first stacked structure; A semiconductor layer is formed on one side of the first stacked structure along the first direction; Along the first direction, on one side of the semiconductor layer, a second isolation layer and a second gate sacrificial layer are alternately stacked to form a second stacked structure; and A portion of the first gate sacrificial layer and a portion of the second gate sacrificial layer are replaced with the first gate layer and the second gate layer, respectively, to form the first stacked structure and the second stacked structure.

24. The method according to claim 23, wherein, The semiconductor device further includes a channel structure, wherein forming the channel structure includes: A channel hole is formed, the channel hole extending in the first stacked structure and the second stacked structure in a direction opposite to the first direction, wherein the channel hole exposes a portion of the semiconductor layer; An initial functional layer is formed in the channel holes; The portion of the initial functional layer located on the exposed semiconductor layer is removed to form a first functional layer and a second functional layer, wherein the first functional layer extends in the first stacked structure in a direction opposite to the first direction, and the second functional layer extends in the second stacked structure; and A channel layer is formed on the surface of the first functional layer, the semiconductor layer, and the second functional layer.

25. A memory system, characterized in that, include: At least one semiconductor device as described in any one of claims 1-17; as well as A controller, coupled to the semiconductor device, is used to control the semiconductor device to store data.

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