Three-state content addressable memory based on molybdenum disulfide memristor transistor and read-write method thereof

Abstract

The invention discloses a molybdenum disulfide (MoS2) memristor transistor-based three-state content addressable memory and a read-write method thereof, the molybdenum disulfide (MoS2) memristor transistor-based three-state content addressable memory comprises a three-state content addressable memory unit respectively connected with two bit lines and a single row matching line, and the three-state content addressable memory unit comprises a first MoS2 three-terminal memristor transistor, a second MoS2 three-terminal memristor transistor and a third MoS2 three-terminal memristor transistor, the drain electrode is connected with the row matching line, and the source electrode is grounded; the grid electrode of the second MoS2 three-terminal memristive transistor is connected with the other bit line, the drain electrode of the second MoS2 three-terminal memristive transistor is connected with the row matching line, the source electrode of the second MoS2 three-terminal memristive transistor is grounded, each MoS2 three-terminal memristive transistor works in a high-resistance state or a low-resistance state, and storage representation of three-state logic coding is achieved by combining the conduction states of the two MoS2 three-terminal memristive transistors. Compared with the prior art, the device has the advantages of simple structure, good regulation and control performance, high stability in the read-write process and the like.

Description

Technical Field

[0001] This invention relates to the field of semiconductors and integrated circuits, and in particular to a three-state content-addressable memory based on molybdenum disulfide memristor transistors and its read / write method. Background Technology

[0002] Existing tri-state content-addressable memories (TCAMs) suffer from the following drawbacks in data search and matching applications: Traditional TCAM storage units must support three states (0, 1, and X), resulting in complex hardware structures, low storage density, and large chip area. During large-scale data retrieval, the complex tri-state matching logic leads to exponentially increasing search power consumption with storage capacity, especially when a large number of "X" bits are present, resulting in significant wasted power. Furthermore, the search speed of existing TCAMs is limited by the cascading of multi-level matching circuits, making it difficult to meet the demands of high-speed real-time retrieval. Insufficient parallel processing capability for "X" bits also increases latency during complex condition matching. Although some solutions mitigate these problems by optimizing the storage array architecture or introducing power control circuits, technical bottlenecks such as the difficulty in balancing search efficiency and power consumption control, and high hardware costs remain.

[0003] Chinese patent application publication number CN108615812A discloses a tri-state content-addressable memory (TRM) based on memory diodes. By employing germanium oxide, aluminum oxide, and hafnium oxide memory diodes and complementary search signal lines in the TRM, it solves the problems of large chip size, high power consumption, and process incompatibility in existing technologies, achieving a smaller, lower-power, and more compatible TRM. However, in this application, both writing and searching are performed via top electrode pressure, i.e., sharing the search signal line (SL). This can easily lead to control signal conflicts, crosstalk, or write errors when the array size is increased.

[0004] In summary, there is currently a lack of a three-state content-addressable memory to solve or partially solve the aforementioned problems. Summary of the Invention

[0005] The purpose of this invention is to overcome the defects of the prior art by providing a three-state content-addressable memory based on molybdenum disulfide memristor transistors and its read / write method, so as to solve or partially solve the problems of complex device structure and unsatisfactory stability of read / write process.

[0006] The objective of this invention can be achieved through the following technical solutions:

[0007] One aspect of the present invention provides a tri-state content-addressable memory based on a molybdenum disulfide memristor transistor, comprising tri-state content-addressable memory cells respectively connected to two bit lines and a single row match line, wherein the tri-state content-addressable memory cells include:

[0008] The first MoS2 three-terminal memristor transistor has its gate connected to a bit line, its drain connected to the row matching line, and its source grounded.

[0009] The second MoS2 three-terminal memristor transistor has its gate connected to another bit line, its drain connected to the row matching line, and its source grounded.

[0010] Each MoS2 three-terminal memristor transistor operates in either a high-resistance or low-resistance state. By combining the conduction states of two MoS2 three-terminal memristor transistors, a three-state logic encoding storage representation is achieved.

[0011] As a preferred technical solution, it includes multiple tri-state content-addressable storage units, arranged in an array in rows, with each column of tri-state content-addressable storage units sharing two bit lines, and each row corresponding to an independent row matching line.

[0012] As a preferred technical solution, for any MoS2 three-terminal memristor transistor, it includes the following components arranged sequentially along the vertical direction of the device:

[0013] The substrate is made of Si / SiO2.

[0014] The gate material is Ti / Au;

[0015] Alumina layer;

[0016] Source / drain / MoS2 channel layer, with the source / drain material being Ti / Au;

[0017] Isolation layer.

[0018] As a preferred technical solution, the thickness of the source, gate, and drain is 5 / 45nm, and the thickness of the alumina layer is 30nm.

[0019] As a preferred technical solution, for the tri-state content-addressable memory unit, when the first MoS2 three-terminal memristor transistor is in a high-resistance state and the second MoS2 three-terminal memristor transistor is in a low-resistance state, the tri-state content-addressable memory unit is logic 0; when the first MoS2 three-terminal memristor transistor is in a low-resistance state and the second MoS2 three-terminal memristor transistor is in a high-resistance state, the tri-state content-addressable memory unit is logic 1; when the first MoS2 three-terminal memristor transistor is in a high-resistance state and the second MoS2 three-terminal memristor transistor is in a high-resistance state, the tri-state content-addressable memory unit is logic X.

[0020] Another aspect of the present invention provides a read / write method for a tri-state content-addressable memory based on a molybdenum disulfide memristor transistor, applied to the aforementioned tri-state content-addressable memory, the read / write method comprising the following steps:

[0021] Writing steps: Apply a voltage to the drain of the two MoS2 three-terminal memristor transistors through the matching line to form a programming voltage of the target polarity between the drain and source, and configure the two MoS2 three-terminal memristor transistors to a high-resistance state or a low-resistance state to achieve writing;

[0022] Reading steps: Search data is applied to the gates of two MoS2 three-terminal memristor transistors through two bit lines. When the search data matches the storage state, the matching line maintains a low current, achieving matching. When the search data does not match the storage state, the MoS2 three-terminal memristor transistors are turned on, the matching line current increases, and mismatch occurs.

[0023] As a preferred technical solution, the programming voltage includes a 0V→-4V→0V voltage for writing a high-resistivity state and a 0V→4V→0V voltage for writing a low-resistivity state.

[0024] As a preferred technical solution, the search data includes 0V level and 1V level, which respectively turn the active MoS2 three-terminal memristor transistor off and on.

[0025] In another aspect, an electronic device is provided, characterized in that it includes one or more processors, a memory, and one or more programs stored in the memory, said one or more programs including instructions for executing the aforementioned read / write method of a tri-state content-addressable memory based on a molybdenum disulfide memristor transistor.

[0026] In another aspect, the present invention provides a method for fabricating a molybdenum disulfide memristor transistor for the aforementioned three-state content-addressable memory (MoS2 memristor transistor), the method comprising the following steps:

[0027] Patterning of the gate of a molybdenum disulfide memristor transistor was achieved using electron beam lithography.

[0028] Ti / Au metal deposition was achieved on a Si / SiO2 substrate by electron beam evaporation.

[0029] Al2O3 dielectric layer is achieved by atomic layer deposition;

[0030] MoS2 thin films are formed by transfer;

[0031] Patterned etching of MoS2 thin films was achieved through reactive ion etching.

[0032] Molybdenum disulfide memristor transistors (MoD2) were deposited with Ti / Au source and drain metals via electron beam lithography and electron beam evaporation.

[0033] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0034] (1) Simple device structure: The three-state content addressing memory cell of the present invention includes only two MoS2 three-terminal memristor transistors, bit lines connected to the gates of the two memristor transistors respectively, and a matching line connected to the drains of the two memristor transistors. By controlling the combination of the conduction states of the two memristor transistors, the storage representation of the three-state logic encoding can be realized. It has the characteristics of simple structure, small area, and strong compatibility, and is suitable for large-scale scalable array design.

[0035] (2) Good controllability: The memristor transistor based on MoS2 in this invention has obvious resistance state change characteristics, and can achieve stable switching between high resistance state and low resistance state at low voltage. It has excellent non-volatility, reprogrammability and good controllability, and has long-term stable operation and reliable data retention capability.

[0036] (3) High stability of read and write process: In the writing process, the present invention applies a voltage of specific polarity and amplitude between the matching line and the source and drain terminals, while the search data is applied to the gate of the two memristor transistors through the bit line to achieve physical path separation. Compared with the scheme of completing the read and write by applying pressure to the top electrode, the switch control does not need to rely on applying voltage to the top electrode, which overcomes the risk of control signal conflict, crosstalk or miswriting when the array scale is increased, and significantly improves the reliability and operational stability of large-scale arrays. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the three-state content-addressable storage unit in the embodiment;

[0038] Figure 2 This is a schematic diagram of the structure of the MoS2 three-terminal memristor transistor in the embodiment;

[0039] Figure 3 This is a resistance switching diagram of the memristor transistor device in the embodiment;

[0040] Figure 4 This is a circuit endurance diagram of the memristor transistor conductance in the embodiment;

[0041] Figure 5 This is a multi-conductance diagram of the gate modulation of the memristor transistor in the embodiment;

[0042] Figure 6 This is a schematic diagram of the matching logic in the three states of the three-state content addressing storage unit in the embodiment;

[0043] Figure 7 This is a diagram of a two-dimensional TCAM array structure composed of multiple units in the embodiment;

[0044] Figure 8 This is a diagram showing the matching results of a 1×1 TCAM array in the embodiment;

[0045] Figure 9 This is a diagram showing the matching results of a 2×2 TCAM array in the embodiment;

[0046] Figure 10 This is a flowchart illustrating the read / write method of a three-state content-addressable memory based on a molybdenum disulfide memristor transistor in this embodiment.

[0047] Figure 11 This is a flowchart illustrating the fabrication method of the molybdenum disulfide memristor transistor in the embodiments;

[0048] Figure 12 This is a schematic diagram of the electronic device in the embodiment. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0050] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0051] Example 1

[0052] To address the problems existing in the prior art, this embodiment provides a three-state content-addressable memory based on molybdenum disulfide memristor transistors, including... Figure 1 The three-state content-addressable memory (TCAM) cell comprises two three-terminal memristor transistors (mem1 and mem2) based on a single layer of molybdenum disulfide material. Each memristor transistor has a three-terminal structure, including a source, drain, and gate. Its conduction states exhibit two stable states: a high-resistivity state (HRS) and a low-resistivity state (LRS), and reversible and controllable state switching can be achieved under specific amplitude voltages, demonstrating good non-volatility and write reconfigurability. By combining the conduction states of mem1 and mem2, three-state logic encoding (logic "0", "1", and "X" wildcards) can be implemented for storage representation. This design features simple structure, small area, and strong compatibility, making it suitable for large-scale scalable array designs.

[0053] Three-state logic expression and matching mechanism: Using the combination encoding of the conductance states of mem1 and mem2, the three-state logic of the TCAM unit is defined as follows:

[0054] Logical "0": mem1 = HRS, mem2 = LRS;

[0055] Logical "1": mem1 = LRS, mem2 = HRS;

[0056] Logical “X”: mem1 = HRS, mem2 = HRS.

[0057] See Figure 2 This is a schematic diagram of the structure of a three-terminal memristor transistor based on a single layer of molybdenum disulfide material in this embodiment. The transistor consists of a substrate, a gate, an aluminum oxide layer, a source / drain / MoS2 channel layer, and an isolation layer arranged sequentially along the vertical direction. The substrate material is Si / SiO2, the gate / source / drain material is Ti / Au, the thickness of the source, gate, and drain is 5 / 45nm, and the thickness of the aluminum oxide layer is 30nm.

[0058] Preferably, the three content-addressable memories include multiple TCAM units, such as Figure 7 As shown, multiple TCAM units form a two-dimensional array structure in rows, with each row equipped with an independent ML matching line, enabling multi-row parallel matching. The system can quickly read the matching results through simple current detection logic, possessing high-throughput fuzzy search capabilities. Each column shares SL1 / SL2 input lines, and the matching results are output through an independent ML for each row. It supports multi-row parallel matching and can quickly read the matching results by combining current discrimination or voltage holding methods. The array structure supports multi-bit width expansion, thereby adapting to data retrieval tasks of different precision and complexity, possessing high scalability and neuromorphic computing adaptability.

[0059] This embodiment uses a combination of mem1 and mem2 dual memristor transistors to achieve three logic states: "0", "1" and "X". The X state supports matching all search inputs and is suitable for fuzzy matching tasks. Only two memristor transistors are needed to construct the three-state logic. The array has strong scalability and supports multi-row parallel matching and priority selection.

[0060] The memristor transistor employs a three-terminal structure, consisting of a bottom gate, a high-k dielectric layer, a MoS2 channel, and top metal source / drain electrodes. Its overall structure is thin and compact, which is beneficial for increasing array integration density. Compared to most existing two-terminal memristor devices based on MoS2, this embodiment realizes a three-terminal gate-controlled memristor transistor suitable for TCAM applications, possessing excellent conductivity regulation capability and good process compatibility.

[0061] Example 2

[0062] Based on Example 1, see Figure 10This embodiment provides a read / write method for a tri-state content-addressable memory based on a molybdenum disulfide memristor transistor, used in the tri-state content-addressable memory of Embodiment 1. The read / write method includes writing and reading steps.

[0063] Writing steps: Apply a voltage to the drain of the two MoS2 three-terminal memristor transistors through the matching line to form a programming voltage of the target polarity between the drain and source, and configure the two MoS2 three-terminal memristor transistors to a high-resistance state or a low-resistance state to achieve writing.

[0064] Specifically, data is written by applying a voltage via ML, which acts on the drain of mem1 / mem2. By applying a programming voltage of specific polarity between the source and drain, mem1 and mem2 can be written to either the HRS or LRS state, respectively. For example, applying a voltage of 0V→-4V→0V to mem1 writes HRS, and applying a voltage of 0V→4V→0V to mem2 writes LRS; the combination represents logic "0". This process requires no additional control transistors; the state setting is achieved directly through the voltage polarity and amplitude.

[0065] Reading steps: Search data is applied to the gates of two MoS2 three-terminal memristor transistors through two bit lines. When the search data matches the storage state, the matching line maintains a low current, achieving matching. When the search data does not match the storage state, the MoS2 three-terminal memristor transistors are turned on, the matching line current increases, and mismatch occurs.

[0066] Specifically, search data is input through SL1 / SL2, which act on the gates of mem1 and mem2 respectively. mem1 is on at 1V and off at 0V. A logic input of "0" indicates SL1 = 1V and SL2 = 0V, while a logic input of "1" indicates SL1 = 0V and SL2 = 1V. When the input matches the storage state (e.g., writing 0), mem1 is on but in HRS mode, while mem2 is off. No current is conducted, and ML maintains a low current (matching). Conversely, if the storage state does not match the input, at least one channel is on, and the ML current increases (mismatch). The entire matching process does not require the participation of control transistors, achieving efficient and low-power three-state fuzzy matching based on analog current judgment.

[0067] Search data is connected to the gates of mem1 and mem2 via two bit lines (SL1 and SL2) and input in parallel to all columns. The matching result is determined by the current state of the match line (ML) in each row: if all cells in the row match the input data, ML maintains a low current, indicating a "perfect match"; if any cell does not match and is turned on, the ML current rises, indicating a "mismatch". This process is an analog matching mechanism, requiring no complex digital logic assistance, and has advantages such as speed, low power consumption, and strong parallelism.

[0068] This embodiment achieves three-state logic mapping by combining the conduction states of mem1 and mem2. The matching result is naturally reflected by the current state of the matching line, eliminating the need for complex digital judgment circuits required in traditional TCAMs, significantly simplifying the peripheral logic structure and reducing power consumption. In particular, the wildcard "X" state is achieved by having mem1 and mem2 simultaneously in a high-impedance state. The structure itself supports wildcard matching, further simplifying the peripheral circuit design and making it suitable for high-concurrency fuzzy matching scenarios.

[0069] like Figure 3 As shown, the conductance switching of the memristor transistor from HRS to LRS can be achieved by programming voltage, exhibiting clear bistable characteristics; Figure 4 The conductivity retention characteristics of the device under repeated write / erase cycles were demonstrated, verifying its good rewrite capability and cycle stability.

[0070] like Figure 5 As shown, different conductance states can be achieved by adjusting the gate voltage, exhibiting multi-conductance state control capability.

[0071] This invention defines three logical states using the combined conduction states of mem1 and mem2, such as Figure 6 As shown. Each column of search data is input through two bit lines (SL1 and SL2), and the matching result of each row is detected by the Match Line (ML). Only when all cells are off-center, the ML current remains low, indicating a perfect match; if any cell is on-center, the ML current rises, indicating a mismatch.

[0072] like Figure 8 and Figure 9 As shown, both the matching logic of a single unit and the parallel matching process under a 2×2 array can intuitively demonstrate the effectiveness and scalability of this mechanism.

[0073] In summary, the device in this embodiment possesses multi-level conductance states with adjustable gates, and has the potential to be further extended into a multi-valued storage unit or a weighted matching mechanism, providing device-level hardware support for tasks such as fuzzy recognition and approximate search in neuromorphic computing systems. It eliminates the need for complex logic gates, determining matching solely through the ML current, significantly reducing power consumption.

[0074] Example 3

[0075] Based on the foregoing embodiments, this embodiment provides a method for fabricating a molybdenum disulfide memristor transistor, used to fabricate the MoS2 memristor transistor of the tri-state content-addressable memory in Embodiment 1. See [link to documentation]. Figure 11 The preparation method includes the following steps:

[0076] Patterning of the gate of a molybdenum disulfide memristor transistor was achieved using electron beam lithography.

[0077] Ti / Au metal deposition was achieved on a Si / SiO2 substrate by electron beam evaporation.

[0078] Al2O3 dielectric layer is achieved by atomic layer deposition;

[0079] MoS2 thin films are formed by transfer;

[0080] Patterned etching of MoS2 thin films was achieved through reactive ion etching.

[0081] Molybdenum disulfide memristor transistors (MoD2) were deposited with Ti / Au source and drain metals via electron beam lithography and electron beam evaporation.

[0082] The device in this embodiment can be fabricated using standard micro-nano fabrication processes, and has good manufacturing compatibility and practical application potential.

[0083] Example 4

[0084] This embodiment provides an electronic device, including: one or more processors and a memory, wherein the memory stores one or more programs, the one or more programs including instructions for executing the read / write method as described in Embodiment 2.

[0085] like Figure 12 At the hardware level, the electronic device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for the business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to achieve the above-mentioned functions. Figure 10 The method described herein. Of course, in addition to software implementation, this invention does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0086] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0087] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A three-state content-addressable memory based on a molybdenum disulfide memristor transistor, characterized in that, The storage unit includes a tri-state content-addressable memory unit connected to two bit lines and a single row match line, the tri-state content-addressable memory unit comprising: The first MoS2 three-terminal memristor transistor has its gate connected to a bit line, its drain connected to the row matching line, and its source grounded. The second MoS2 three-terminal memristor transistor has its gate connected to another bit line, its drain connected to the row matching line, and its source grounded. Each MoS2 three-terminal memristor transistor operates in either a high-resistance or low-resistance state. By combining the conduction states of two MoS2 three-terminal memristor transistors, a three-state logic encoding storage representation is achieved.

2. The three-state content-addressable memory based on a molybdenum disulfide memristor transistor according to claim 1, characterized in that, It includes multiple tri-state content-addressable storage units, arranged in an array in rows. Each column of tri-state content-addressable storage units shares two bit lines, and each row corresponds to an independent row matching line.

3. A three-state content-addressable memory based on a molybdenum disulfide memristor transistor according to claim 1, characterized in that, For any MoS2 three-terminal memristor transistor, it includes the following components arranged sequentially along the vertical direction of the device: The substrate is made of Si / SiO2. The gate material is Ti / Au; Alumina layer; Source / drain / MoS2 channel layer, with the source / drain material being Ti / Au; Isolation layer.

4. A three-state content-addressable memory based on a molybdenum disulfide memristor transistor according to claim 3, characterized in that, The thickness of the source, gate, and drain electrodes is 5 / 45nm, and the thickness of the aluminum oxide layer is 30nm.

5. A three-state content-addressable memory based on a molybdenum disulfide memristor transistor according to claim 1, characterized in that, For the aforementioned tri-state content-addressable memory cell, when the first MoS2 three-terminal memristor transistor is in a high-resistance state and the second MoS2 three-terminal memristor transistor is in a low-resistance state, the tri-state content-addressable memory cell is logic 0; when the first MoS2 three-terminal memristor transistor is in a low-resistance state and the second MoS2 three-terminal memristor transistor is in a high-resistance state, the tri-state content-addressable memory cell is logic 1; when the first MoS2 three-terminal memristor transistor is in a high-resistance state and the second MoS2 three-terminal memristor transistor is in a high-resistance state, the tri-state content-addressable memory cell is logic X.

6. A method for reading and writing a three-state content-addressable memory based on a molybdenum disulfide memristor transistor, characterized in that, Applied to the tri-state content-addressable memory as described in any one of claims 1-5, the read / write method includes the following steps: Writing steps: Apply a voltage to the drain of the two MoS2 three-terminal memristor transistors through the matching line to form a programming voltage of the target polarity between the drain and source, and configure the two MoS2 three-terminal memristor transistors to a high-resistance state or a low-resistance state to achieve writing; Reading steps: Search data is applied to the gates of two MoS2 three-terminal memristor transistors through two bit lines. When the search data matches the storage state, the matching line maintains a low current, achieving matching. When the search data does not match the storage state, the MoS2 three-terminal memristor transistors are turned on, the matching line current increases, and mismatch occurs.

7. The read / write method for a three-state content-addressable memory based on a molybdenum disulfide memristor transistor according to claim 6, characterized in that, The programming voltages include a 0V→-4V→0V voltage for writing the high-resistivity state and a 0V→4V→0V voltage for writing the low-resistivity state.

8. The read / write method for a three-state content-addressable memory based on a molybdenum disulfide memristor transistor according to claim 6, characterized in that, The search data includes 0V and 1V levels, which respectively turn the active MoS2 three-terminal memristor transistor off and on.

9. An electronic device, characterized in that, It includes one or more processors, memory, and one or more programs stored in the memory, said one or more programs including instructions for performing the read / write method of the tri-state content-addressable memory based on molybdenum disulfide memristor transistors as described in claim 6.

10. A method for fabricating a molybdenum disulfide memristor transistor, characterized in that, The method for fabricating a MoS2 memristor transistor for a tri-state content-addressable memory as described in any one of claims 1-5 includes the following steps: Patterning of the gate of a molybdenum disulfide memristor transistor was achieved using electron beam lithography. Ti / Au metal deposition was achieved on a Si / SiO2 substrate by electron beam evaporation. Al2O3 dielectric layer is achieved by atomic layer deposition; MoS2 thin films are formed by transfer; Patterned etching of MoS2 thin films was achieved through reactive ion etching. Molybdenum disulfide memristor transistors (MoD2) were deposited with Ti / Au source and drain metals via electron beam lithography and electron beam evaporation.

Images