Semiconductor device based on SiC material and manufacturing process thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device based on a SiC material and a manufacturing process of the semiconductor device. The device comprises an N + type SiC substrate, an N-type composite buffer layer which is arranged on the substrate and has a concentration gradient, an N-type drift region which is arranged on the buffer layer, and an active region which is composed of a first conduction type region and a second conduction type ion implantation region. The innovation lies in that a composite buffer layer structure is adopted to effectively suppress dynamic avalanche and optimize the reverse recovery characteristic, and meanwhile, a composite structure of a junction termination extension region and a field limiting ring with shallower junction depth is integrated in a terminal region, so that the process complexity is simplified on the premise of ensuring high breakdown voltage. According to the manufacturing process, impurity activation of the active region and the terminal region is synchronously completed through two times of ion implantation and one time of high-temperature annealing, and the manufacturing process is completely compatible with an existing SiC plane process platform. The device realizes excellent compromise between reverse recovery charge and forward voltage drop, and has the characteristics of superspeed, soft recovery, low loss and high reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a semiconductor device based on SiC material and its manufacturing process. Background Technology

[0002] In power electronic systems such as inverters, rectifiers, and choppers, freewheeling diodes are key components. Their switching performance, especially their reverse recovery characteristics, directly determines the system's switching losses, electromagnetic interference (EMI) levels, and reliability. Due to inherent material limitations, silicon (Si)-based fast recovery diodes (FRDs) have approached their performance limits in high-temperature, high-frequency, and high-efficiency applications.

[0003] Silicon carbide (SiC) materials, due to their superior properties such as high critical breakdown electric field, high saturated electron drift velocity, and high thermal conductivity, have become an ideal choice for fabricating next-generation high-performance power devices. Silicon carbide JBS diodes combine the advantages of Schottky diodes (low turn-on voltage and ultrafast switching speed) and PN junction diodes (low leakage current), making them a research hotspot.

[0004] However, traditional planar silicon carbide devices still face challenges: "Hard" recovery characteristic: During the reverse recovery process, if the current change rate (di / dt) is too high, it can easily cause severe voltage overshoot and oscillation, generating EMI and threatening system safety.

[0005] The trade-off between Qrr and VF: To reduce the on-state voltage drop (VF), it is usually necessary to reduce the proportion of the Schottky contact area, but this leads to more minority carrier injection, increasing the reverse recovery charge (Qrr), and thus increasing switching losses.

[0006] Termination protection: Complex termination structures (such as JTE, field limiting ring) are required to alleviate edge electric field crowding and improve breakdown voltage, but this increases process complexity and cost. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor device based on SiC material and its manufacturing process. By introducing a composite buffer layer and an integrated composite terminal structure, the electric field distribution is effectively optimized, achieving an excellent trade-off between on-state voltage drop (VF) and reverse recovery charge (Qrr), and obtaining superior soft recovery characteristics, thereby solving the problems mentioned in the background art.

[0008] To achieve the above objectives, in one aspect, the present invention provides a semiconductor device based on SiC material, comprising, from top to bottom: Cathode metal layer.

[0009] N+ type SiC substrate.

[0010] The N-type drift region located on an N+ type SiC substrate.

[0011] The N-type drift region is equipped with: The second type of conductivity ion implantation region forms a periodic array structure, and the junction depth of the second type of conductivity ion implantation region is Xj; A composite buffer layer is located between the N-type drift region and the N+ type SiC substrate; the composite buffer layer consists of at least two N-type SiC epitaxial layers with different doping concentrations, with the doping concentration decreasing stepwise or gradually from bottom to top.

[0012] Active regions include: A second conductivity type ohmic contact region on the surface of the second conductivity type ion implantation region; The first conductivity type region on the surface of the N-type drift region.

[0013] An anode metal layer covers the second conductivity type ohmic contact region and the first conductivity type region, forming an ohmic contact with the second conductivity type region and a Schottky contact with the N-type drift region.

[0014] An integrated composite termination structure is located outside the active region. The termination structure is composed of a field limiting ring (FLR) and a shallow junction termination extension region (S-JTE). The junction depth of the S-JTE is smaller than the junction depth Xj of the second conductivity type ion implantation region in the active region, and the junction depth ratio is 1:1.5 to 1:3. The semiconductor device is configured as a dual-terminal power device with ultra-high speed recovery characteristics.

[0015] Preferably, the composite buffer layer has a three-layer structure: the first layer (closest to the N+ type SiC substrate) has the highest doping concentration, smoothly transitioning to the N+ type SiC substrate concentration; the second layer has an intermediate concentration; and the third layer (closest to the N-type drift region) has the lowest doping concentration, smoothly transitioning to the drift layer concentration. This structure can effectively suppress electric field penetration, reduce device switching overshoot, and optimize the reverse recovery waveform.

[0016] Preferably, the junction depth Xj of the ion implantation region of the second conductivity type is 0.3 μm-0.8 μm, and the junction depth of the S-JTE is 0.1 μm-0.4 μm. The combination of the shallow junction S-JTE and FLR greatly simplifies the complex ion implantation and annealing process of traditional deep junction JTEs while ensuring the terminal protection effect.

[0017] On the other hand, the present invention provides a manufacturing process for semiconductor devices based on SiC material, including the following steps: S1. Epitaxial growth: A composite buffer layer and an N-type drift layer are epitaxially grown sequentially on an N+ type SiC substrate.

[0018] S2. Termination Area Photolithography and Ion Implantation: Using the first photoresist mask, second conductivity type ion implantation is performed in the chip termination area to form the shallow junction S-JTE region and field confinement ring (FLR) region.

[0019] S3. Active region photolithography and ion implantation: Using a second photoresist mask, second conductivity type ion implantation is performed in the active region of the chip to form a second conductivity type ion implantation region with a deeper junction.

[0020] S4. High-temperature annealing: Under the protection of inert gas, high-temperature annealing is performed to activate all implanted ions and repair lattice damage.

[0021] S5. Surface passivation: A layer of silicon dioxide (SiO2) or silicon nitride (Si3N4) is grown as a passivation layer.

[0022] S6. Contact hole photolithography and etching: Using a third photoresist mask, the passivation layer is etched to expose the anode contact area of ​​the active region and part of the terminal region.

[0023] S7. Ohmic contact region ion implantation: Using the fourth photoresist mask, high-dose second conductivity type ion implantation is performed on the exposed second conductivity type ion implantation region to form a second conductivity type ohmic contact region.

[0024] S8. Secondary annealing: Perform rapid thermal annealing to activate the second conductivity type ohmic contact region by implanting ions.

[0025] S9. Metallization: Anode metal (such as Ti / Ni / Ag or Al-based alloy) is deposited on the front side of the device, and the anode pattern is formed by lift-off or etching; cathode metal is deposited on the back side of the device after grinding and thinning.

[0026] S10, Alloying: Alloying is carried out under a specific atmosphere to form good ohmic and Schottky contacts.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows: In this SiC-based semiconductor device and its manufacturing process, the composite buffer layer effectively modulates the electric field distribution, suppresses dynamic avalanche, significantly softens the reverse recovery waveform (reducing di / dt), reduces voltage overshoot and oscillation, and lowers switching losses and EMI. By optimizing the second conductivity type region array design and the composite buffer layer, extremely low Qrr and ultrafast recovery speed are achieved while maintaining a low forward voltage drop (VF). The integrated composite termination structure (FLR+S-JTE) provides excellent termination protection, ensuring a high and stable breakdown voltage. The shallow junction S-JTE design reduces the requirements for injection and annealing processes, improving the process window and yield.

[0028] By ensuring compatibility with existing SiC planar process platforms through manufacturing processes, and without the need for expensive or special equipment, it can be achieved simply through ion implantation mask design and process optimization, thus possessing the potential for large-scale mass production. Attached Figure Description

[0029] Figure 1 This is a flowchart illustrating the overall process of the present invention. Detailed Implementation

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1: This embodiment of the invention provides a SiC-based semiconductor device for medium-voltage, high-frequency applications such as industrial motor drives and photovoltaic inverters. It is a SiC JBS diode with a rated voltage of 1200V and a rated current of 20A. Its core innovation lies in the use of a triple-layer composite buffer layer and a shallow-junction FLR-SJTE composite terminal to achieve excellent switching performance. Specifically, it includes: Substrate: 4H-SiC crystal form, N+ type conductive, 350 μm thick, doping concentration >1e19 cm⁻¹ -3 .

[0032] Composite buffer layer: Three N-type SiC layers are epitaxially grown sequentially on the substrate.

[0033] First layer (close to the substrate): 0.8 μm thick, doping concentration 2.5e18 cm⁻¹ -3 It forms a smooth concentration transition with the substrate, reducing series resistance.

[0034] Second layer (intermediate layer): 1.5 μm thick, doping concentration 8e17 cm⁻¹ -3 Its main function is as a buffer layer, effectively suppressing the expansion rate of the space charge region.

[0035] Third layer (connecting drift regions): 0.7 μm thick, doping concentration 3e17 cm⁻¹ -3 It smoothly connects with the drift region, further optimizing the electric field distribution.

[0036] N-type drift region: 12 μm thickness, doping concentration 8e15 cm⁻¹ -3 Theoretically, the unipolar breakdown voltage exceeds 1500V, providing ample margin for the design.

[0037] The active region second conductivity type array: adopts a hexagonal arrangement, implanted ions are aluminum (Al), junction depth Xj = 0.6μm, surface concentration 1e18 cm⁻¹ -3 The ratio of the width of the first conductivity type region to the width of the second conductivity type region is 3:2.

[0038] Integrated composite terminal: Field limiting ring (FLR): It consists of 6 rings, with a ring width of 10μm and a ring spacing of 8μm.

[0039] Shallow junction termination extension region (S-JTE): implanted ions are aluminum (Al), junction depth is 0.3 μm (only half the depth of the second conductivity type region of the active region), and surface concentration is adjusted to 5e17 cm⁻¹ through multiple implantations. -3 .

[0040] Anode metal: adopts a Ti / Ni / Ag stacked structure, in which Ti forms Schottky and Ohmic contacts with SiC.

[0041] The manufacturing process is as follows: (1) After all epitaxial growth is completed, terminal region implantation is performed first. Using the first mask, ion implantation of the S-JTE region and all FLRs is completed in one go. Due to the shallow junction depth, the implantation energy is low (e.g., 200 keV for Al), avoiding severe lattice damage caused by high-energy implantation.

[0042] (2) Then, the active region second conductivity type region implantation is performed. A second mask is used, and a higher implantation energy (350 keV for Al) is used to form a deep junction of 0.6 μm.

[0043] (3) Perform a high-temperature annealing (1700°C, 5min, Ar atmosphere) to activate all implanted ions in the terminal region and the active region.

[0044] (4) The subsequent second conductivity type ohmic contact implantation uses a self-aligned process, with the anode metal as a mask for shallow high-concentration implantation, which greatly simplifies the process steps.

[0045] In this embodiment, the composite buffer layer serves to remove the charge stored in the drift region during reverse recovery, when the diode switches from the on state to the off state. In traditional uniformly doped drift regions, the electric field expands rapidly, causing a sharp drop in current (large di / dt), resulting in hard recovery. The composite buffer layer in this embodiment has a concentration gradient, establishing an additional built-in electric field at the moment of turn-off. This electric field is aligned with the applied electric field, allowing for a more "gentle" and efficient extraction of charge carriers, acting like an "electron deceleration ramp," thus achieving a smooth decrease in current, i.e., soft recovery.

[0046] The role of integrated termination: Due to its shallow depth and precisely controlled concentration, shallow junction S-JTE can effectively disperse the electric field lines at the termination edge, preventing electric field concentration. FLR, as an auxiliary step, further ensures a uniform electric field distribution. The combination of these two methods achieves a near-ideal breakdown voltage with almost no increase in process complexity, and exhibits better stability than traditional deep junction JTE.

[0047] Example 2: This embodiment of the invention provides a SiC-based semiconductor device for high-voltage, high-power applications such as rail transit and smart grids. It is a 3300V / 50A diode. Electric field management is crucial for high-voltage devices, and this embodiment addresses this issue through a thicker gradient composite buffer layer and a multi-zone modulation terminal.

[0048] Structure and process: Drift region: 35 μm thick, doping concentration 3e15 cm⁻¹ -3 .

[0049] Composite buffer layer: Employs a five-layer graded-doped structure with a total thickness of 6 μm. From bottom to top, the doping concentration increases from 5e18 cm⁻¹. -3 (Connecting substrate) Gradually decreases to 5e16 cm -3 (Connecting the drift region), this gradient design provides an extremely smooth electric field transition.

[0050] The active region second conductivity type array: the junction depth is increased to Xj = 1.2μm to provide a stronger Schottky barrier shielding effect and suppress leakage current under high voltage.

[0051] Terminal structure: A dual-region shallow junction JTE + FLR is adopted. The concentration of the first JTE region (inner side) is slightly higher, and the concentration of the second JTE region (outer side) is slightly lower. The concentration is precisely modulated by two photolithography and implantation processes, so that the electric field distribution in the terminal region is optimally flattened.

[0052] Key manufacturing process points: The gradient composite buffer layer needs to be realized through chemical vapor deposition (CVD) technology with continuously varying doping gas flow.

[0053] In this embodiment, the buffer layer plays a crucial role under high voltages of 3300V. The five-layer gradient buffer layer forms a quasi-"electric field buffer zone." When the device is turned off, the space charge region first expands rapidly in the low-doped drift region, and when it reaches the high-doped buffer layer, the expansion rate is effectively slowed down. This "fast at first, slow later" expansion process greatly softens the reverse recovery waveform and prevents dynamic avalanche.

[0054] The dual-zone modulation terminal ensures an ideal parallel plane breakdown voltage utilization rate of over 90% by meticulously refining the electric field in the terminal area.

[0055] Example 3: This example optimizes the turnkey performance of devices for ultra-high frequency (>1MHz) applications such as switching power supplies (SMPS) and wireless charging. The innovation lies in further reducing all parasitic capacitances while maintaining soft recovery characteristics.

[0056] Structure and process: Voltage rating: 650V.

[0057] Drift region: 6 μm thick, doping concentration 1.5e16 cm⁻¹ -3 .

[0058] Composite buffer layer: Simplified to two layers, with a total thickness of 1.2 μm. The first (bottom) layer has a doping concentration of 1e18 cm⁻¹. -3 The doping concentration of the second (top) layer is 5e17 cm⁻¹. -3 While ensuring soft recovery, the thickness should be reduced as much as possible to minimize series resistance and parasitic capacitance.

[0059] Active region design: Reduce cell size and use a narrower, denser array of the second conductivity type (e.g., stripes) to reduce current crowding and conduction losses.

[0060] Terminal: Employs a single shallow junction JTE region to save space.

[0061] In this embodiment, at ultra-high frequencies, the switching losses of the device are mainly dominated by the charging and discharging losses of parasitic capacitance. Thinning the epitaxial layer and optimizing the structural dimensions directly reduces the junction capacitance Cj. The retained composite buffer layer ensures that even under extremely high di / dt conditions, severe ringing does not occur.

[0062] Experimental Example 1: Verification of the ultra-high-speed soft recovery characteristics of Example 1 (1200V level) (1) Purpose of the experiment: The study verified the superiority of SiC JBS diodes with composite buffer layers and integrated composite terminals in reverse recovery characteristics compared with traditional planar SiC JBS diodes and commercial silicon-based FRDs, focusing on evaluating their reverse recovery charge (Qrr), softness factor (S-factor), and voltage overshoot.

[0063] (2) Test sample: Sample A (Example 1): A 1200V / 20A SiC JBS diode chip manufactured according to Example 1.

[0064] Sample B (Comparative Example 1): A conventional planar SiC JBS diode (without a composite buffer layer, and a conventional JTE terminal structure), with the same voltage and current ratings.

[0065] Sample C (Comparative Example 2): Commercial high-performance 1200V / 20A silicon-based fast recovery diode (FRD).

[0066] (3) Test conditions and equipment: Test platform: Double Pulse Test (DPT) circuit Test parameters: DC bus voltage (Vdc): 800 V; Load current (Iload): 20 A; Junction temperatures (Tj): 25°C and 125°C; Gate resistor (Rg): 5 Ω (controls the switching speed of the SiC MOSFET); di / dt: 150 A / μs; Equipment: High-voltage differential probe, current probe, high-bandwidth oscilloscope (≥1GHz), high-temperature chamber, dynamic parameter tester.

[0067] (4) Experimental methods and procedures: ① Connect samples A, B, and C to the freewheeling diode positions on the DPT platform, respectively.

[0068] ② At room temperature (25°C), apply a double pulse to cause the diode to undergo a switching process from forward conduction (20A) to reverse turn-off (-800V).

[0069] ③ Use an oscilloscope to capture the waveforms of the diode's reverse recovery current (Irr) and reverse recovery voltage (Vr).

[0070] ④ Extract key parameters from the waveform: Qrr (reverse recovery charge), Irrp (peak reverse recovery current), and Vover (turn-off voltage overshoot).

[0071] ⑤ Calculate the softness factor S = tb / ta, where ta is the time it takes for Irr to rise from 0 to Irrp, and tb is the time it takes for Irr to fall from Irrp back to 0. The closer the S value is to 1, the softer the recovery characteristics.

[0072] ⑥ Repeat steps 2-5 and test at 125°C.

[0073] ⑦ Measure the on-state voltage drop (VF@20A) of each sample using a dynamic parameter tester.

[0074] Table 1 Dynamic performance test data at room temperature (25°C)

[0075] Table 2 Dynamic characteristic test data at high temperature (125°C)

[0076] As shown in Tables 1 and 2, the Qrr of the device of the present invention (sample A) is reduced by approximately 40% compared to the conventional SiC JBS (sample B), and by an order of magnitude compared to Si FRD (sample C). This means that in high-frequency switching applications, the switching loss of sample A is significantly reduced, and the system efficiency can be improved by 1-2%.

[0077] Sample A exhibits a significantly higher softness factor (S) than the control sample, and remains stable across different temperatures. Its reverse recovery current waveform is smooth and symmetrical, with minimal voltage overshoot (<50V). This demonstrates that the present invention effectively suppresses EMI and voltage stress, thereby improving system reliability.

[0078] While achieving extreme dynamic performance, the on-state voltage drop (VF) of sample A is comparable to that of sample B and is much lower than that of Si FRD, successfully breaking the traditional trade-off between VF and Qrr.

[0079] Test Example 2: Verifying the terminal protection effect and reliability of Example 2 (3300V level) (1) Experimental objective: To verify the effect of integrated composite terminal structure on improving the breakdown voltage (BV) of high voltage devices and its stability under long-term high voltage stress.

[0080] (2) Test sample: Sample D (Example 2): 3300V / 50A SiC JBS diode chip (unpackaged) manufactured according to Example 2.

[0081] Sample E (Comparative Example 3): A 3300V SiC JBS diode chip with a single conventional JTE terminal and no composite buffer layer.

[0082] (3) Test conditions and equipment: Equipment: High voltage semiconductor parameter analyzer, high and low temperature probe station, HTRB testing system.

[0083] Projects: Static breakdown voltage test, high temperature reverse bias (HTRB) test.

[0084] (4) Experimental methods and procedures: ① Breakdown voltage test: Place samples D and E on a 25°C probe stage, apply reverse bias, and measure the leakage current until avalanche breakdown occurs (breakdown is defined as Ileakage > 100μA), and record the BV value.

[0085] ②HTRB test: Multiple samples D and E were subjected to a reverse bias voltage of 2640V (0.8*3300V) continuously for 1000 hours at 150°C.

[0086] ③ Take out a portion of the sample every 168 hours, cool it to room temperature, and retest its breakdown voltage and leakage current (@3000V) to observe parameter drift.

[0087] Table 3 Breakdown voltage test results

[0088] Table 4. Parameter changes after HTRB test (1000 hours)

[0089] As shown in Tables 3 and 4, the adopted FLR+S-JTE composite termination structure can more effectively modulate the termination electric field, making the breakdown voltage closer to the theoretical value, and the distribution is concentrated, resulting in a high production yield.

[0090] After 1000 hours of HTRB testing, the electrical parameters of the device of this invention showed almost no degradation, while the comparative sample without composite terminations exhibited significant parameter drift and even failure. This demonstrates the long-term stability of the shallow junction termination structure of this invention, which has stronger resistance to surface charge interference and aging, meeting the stringent reliability requirements of industrial and automotive applications.

[0091] Experimental Example 3: Verifying the capacitance characteristics and system efficiency of Example 3 (High-Frequency Application) (1) Experimental objective: To verify that the device optimized for high frequency has extremely low parasitic capacitance and figure of merit, and can actually improve the conversion efficiency of high frequency power supply system.

[0092] (2) Test sample: Sample F (Example 3): A 650V / 10A SiC JBS diode (packaged as DFN8x8) manufactured according to Example 3.

[0093] Sample G (Comparative Example 4): Commercial 650V / 10A SiC Schottky diode (non-JBS structure, no special optimization).

[0094] (3) Test conditions and equipment: Equipment: Impedance analyzer, LLC resonant converter demo board (operating frequency 500kHz-1.2MHz), power analyzer, thermal imager.

[0095] Test items: junction capacitance (Cj) vs reverse voltage (Vr) curves, system efficiency curves, and temperature rise.

[0096] (4) Experimental methods and procedures: ① Capacitance test: Use an impedance analyzer to measure the junction capacitance of samples F and G under different reverse bias voltages, plot the Cj-Vr curve, and calculate the total capacitance charge Qc.

[0097] ② System efficiency test: Samples F and G were used as freewheeling diodes (connected in parallel with SRMOSFET) in the secondary-side synchronous rectification circuit and installed in an LLC resonant converter. Input 400V DC, output 48V / 10A.

[0098] ③ Adjust the switching frequency from 500kHz to 1.2MHz and use a power analyzer to accurately measure the peak efficiency of the system at different frequencies.

[0099] ④ Run at full load for 30 minutes at 1MHz frequency, and use a thermal imager to capture the temperature rise on the surface of the diode package.

[0100] Table 5 Comparison of Key Parameters (@Vr=400V)

[0101] As shown in Table 5, by optimizing the epitaxy and cell design, the parasitic capacitances (Cj and Qc) were successfully reduced, and the figure of merit (FOM) was improved by approximately 30% compared to the comparison sample. This directly translates to lower switching losses.

[0102] In practical high-frequency LLC circuits, lower diode losses directly lead to a significant improvement in overall system efficiency, especially in the ultra-high frequency range above 1MHz, where the advantages are extremely obvious.

[0103] Lower losses mean less heat generation; the temperature rise of sample F was reduced by 14°C, which improved the power density and long-term reliability of the system.

[0104] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device based on SiC material, characterized in that, include: N+ type SiC substrate; An N-type composite buffer layer is disposed on the N+ type SiC substrate. The composite buffer layer is composed of at least two N-type SiC epitaxial layers with different doping concentrations, and the doping concentration decreases layer by layer from bottom to top. An N-type drift region is disposed on the composite buffer layer; An active region is disposed on the upper surface of the N-type drift region, the active region comprising alternating first conductivity type regions and second conductivity type ion implantation regions; the active region also comprises alternating Schottky contact regions and P-type ion implantation regions. And an integrated composite terminal structure surrounding the active region, the integrated composite terminal structure including a shallow junction terminal extension region and a field limiting loop; The first conductivity type region forms a Schottky contact with the anode metal, and the second conductivity type ion implantation region forms an ohmic contact with the anode metal, together constituting the anode of the semiconductor device; a cathode metal is disposed on the back side of the N+ type SiC substrate, constituting the cathode; the semiconductor device is configured as a dual-terminal power device with ultra-high speed recovery characteristics.

2. The semiconductor device based on SiC material according to claim 1, characterized in that: The junction depth of the shallow junction terminal extension region is less than the junction depth of the P-type ion implantation region in the active region, and the junction depth ratio is 1:1.5 to 1:

3.

3. The semiconductor device based on SiC material according to claim 1, characterized in that: The composite buffer layer has a two- or three-layer structure.

4. The semiconductor device based on SiC material according to claim 2, characterized in that: The junction depth of the second conductivity type ion implantation region is 0.3μm-0.8μm, and the junction depth of the shallow junction terminal extension region is 0.1μm-0.4μm.

5. The semiconductor device based on SiC material according to claim 1, characterized in that: The integrated composite terminal structure is a multi-region structure, consisting of at least two shallow junction terminal extension regions with different doping concentrations.

6. The semiconductor device based on SiC material according to any one of claims 1-5, characterized in that: The second conductivity type ion implantation regions within the active region are arranged in a hexagonal or striped periodic pattern.

7. The semiconductor device based on SiC material according to any one of claims 1-5, characterized in that: The rated breakdown voltage of the semiconductor device is 650V to 6500V.

8. A manufacturing process for a SiC-based semiconductor device according to any one of claims 1-7, characterized in that, Includes the following steps: S1, Provides an N+ type SiC substrate; S2. A composite buffer layer and an N-type drift region are epitaxially grown sequentially on the N+ type SiC substrate; S3. A masking layer is formed on the surface of the N-type drift region, and the terminal region pattern is defined by the first photolithography process; S4. Perform the first ion implantation to form a shallow junction terminal extension region and a field-limiting ring structure in the terminal region; S5. Define the active region pattern through the second photolithography process, and perform a second ion implantation to form the second conductivity type ion implantation region of the active region; S6. Perform a high-temperature annealing process to activate the implanted ions in the shallow junction terminal extension region, the field confinement ring, and the second conductivity type ion implantation region.

9. The manufacturing process for a SiC-based semiconductor device according to claim 8, characterized in that: The implantation energy of the first ion implantation in S4 is lower than the implantation energy of the second ion implantation in S5.

10. The application of a SiC-based semiconductor device as described in any one of claims 1-7 in photovoltaic inverters, industrial motor drives, rail transit traction converters, or high-frequency switching power supply systems.

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