Grid-controlled thyristor and content addressable memory array

Abstract

The invention provides a gate controlled thyristor and a content addressable memory array. The grid control thyristor comprises a first transistor, a second transistor and a third transistor which are respectively provided with a control end, a first end and a second end. Control terminals of the first and third transistors are connected to a search line. The control end of the second transistor is connected to a fixed bias, and the second end is connected to the first end of the first transistor. The first end of the third transistor is connected to the matching line, and the second end is connected to the first end of the second transistor. A search bit is determined based on a search line voltage applied to the search line, and the search bit is compared with the data to determine whether the search bit is matched with the data. The architecture is suitable for a 3D NAND memory, and has the characteristics of high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a content-addressable memory, and more particularly to a gate-controlled thyristor and a content-addressable memory array. Background Technology

[0002] Content-addressable memory (CAM) is a type of memory. CAM memory is designed so that users input data, and the CAM memory searches its entire memory to see if the data exists. If the data is found, the CAM memory returns a list containing one or more memory addresses where the data was found.

[0003] To implement a single-branch CAM memory using a single transistor, this transistor must have ambipolar characteristics. For example, ... Figure 1 As shown, some CAM memory 10 currently employs a tunnel field-effect transistor (TFET) 12 with symmetrical source / drain junctions to enable this bipolar characteristic. The gate of the TFET 12 is connected to the search line SL, while one source / drain is connected to the match line ML, and the other source / drain is grounded. Furthermore, the match line ML can be supplied with a power supply voltage VDD via a drive circuit 14. For this tunnel field-effect transistor 12, the transistor will have a current I when a very high or very low voltage is applied to the gate. ML The transistors flow through and exhibit characteristics of different polarities (e.g., P-type and N-type). However, this approach degrades the performance of intrinsic tunneling field-effect transistors (TEFETs), and asymmetric junction profiles are generally preferred for achieving steep subthreshold slopes and high on-current. Furthermore, bipolar transistors typically also suffer from poor on / off current, which negatively impacts the sensing boundaries of CAM memories. Summary of the Invention

[0004] Based on the above, according to an embodiment of the present invention, a gate-controlled thyristor (GCR) is provided. The GCR is used to construct a content-addressable memory cell. The GCR includes: a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal being connected to a search line, and the second terminal being connected to ground potential; a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal being connected to a fixed bias voltage, and the second terminal being connected to the first terminal of the first transistor, the second transistor being used to store data; and a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal being connected to the search line, the first terminal being connected to a matching line, and the second terminal being connected to the first terminal of the second transistor. A search bit is determined based on the search line voltage applied to the search line, and the search bit is compared with the data to determine whether the search bit matches the data.

[0005] According to another embodiment of the present invention, a content-addressable memory array with a NOR architecture is provided. The content-addressable memory array includes: a plurality of matching lines arranged substantially parallel in the row direction; a plurality of search lines arranged substantially parallel in the column direction; and a plurality of content-addressable memory cells, each composed of a gate-controlled thyristor, wherein each of the plurality of content-addressable memory cells is disposed at the intersection of the plurality of matching lines and the plurality of search lines. Each gate-controlled thyristor includes: a first transistor having a control terminal, a first terminal, and a second terminal, the second terminal being connected to ground potential; a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal being connected to a fixed bias voltage, the second terminal being connected to the first terminal of the first transistor, the second transistor being used to store data; and a third transistor having a control terminal, a first terminal, and a second terminal, the second terminal being connected to the first terminal of the second transistor. The first terminal of the third transistor of each gate-controlled thyristor in the same column in the column direction is connected to a corresponding matching line among the plurality of matching lines. The control terminals of the first transistor and the third transistor of each of the gate-controlled thyristors in the same row along the row direction are connected to corresponding search lines among the plurality of search lines. For the selected gate-controlled thyristor, a search bit is determined based on the search line voltage applied to the corresponding search line, and the search bit is compared with the data to determine whether the search bit matches the data.

[0006] According to another embodiment of the present invention, a content-addressable memory array (CNMI) of NAND type architecture is provided. The CNMI array includes: a plurality of matching lines; a plurality of search lines; and a plurality of CNMI cells, each composed of a gate-controlled thyristor (GCR). The plurality of CNMI cells extend and are arranged in a row-column direction to form a memory array. Each GCR includes: a first transistor having a control terminal, a first terminal, and a second terminal; a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal being connected to a fixed bias voltage, the second terminal being connected to the first terminal of the first transistor, the second transistor being used to store data; and a third transistor having a control terminal, a first terminal, and a second terminal, the second terminal being connected to the first terminal of the second transistor. A plurality of GCRs in the same row in the column direction are connected in series. The first terminal of the third transistor of the first GCR of the plurality of GCRs in the same row is connected to a corresponding matching line among the plurality of matching lines. The second terminal of the first transistor of the last GCR of the plurality of GCRs in the same row is connected to ground. In the row direction, the control terminal of the first transistor and the control terminal of the third transistor of each of the plurality of gate-controlled thyristors in the same column are connected to a corresponding search line among the plurality of search lines. For the selected gate-controlled thyristor, a search bit is determined based on the search line voltage applied to the corresponding search line, and the search bit is compared with the data to determine whether the search bit matches the data.

[0007] According to an embodiment of the present invention, in the above-mentioned gate-controlled thyristor or content-addressable memory array, when the search line voltage is greater than a predetermined voltage, the second transistor of the gate-controlled thyristor is in a first-type operating state, and when the search line voltage is less than the predetermined voltage, the second transistor of the gate-controlled thyristor is in a second-type operating state.

[0008] According to an embodiment of the present invention, in the above-mentioned gate-controlled thyristor or content-addressable memory array, the first type of operation state is an NFET state, and the second type of operation state is a PFET state.

[0009] According to an embodiment of the present invention, in the above-mentioned gate-controlled thyristor or content-addressable memory array, the fixed bias voltage is set between a threshold voltage value corresponding to the first data state under the second type of operation state and a threshold voltage value corresponding to the second data state under the first type of operation state.

[0010] According to an embodiment of the present invention, in the above-described gate-controlled thyristor or content-addressable memory array, when the search line voltage is greater than the predetermined voltage, the search bit is the first bit. When the search line voltage is less than the predetermined voltage, the search bit is the second bit.

[0011] According to an embodiment of the present invention, in the above-described gate-controlled thyristor or content-addressable memory array, when the search bit matches the data, the second transistor generates a turn-off current; when the search bit does not match the data, the second transistor generates a turn-on current. The ratio of the turn-on current to the turn-off current is at least 10⁶.

[0012] According to an embodiment of the present invention, in the above-mentioned gate-controlled thyristor or content-addressable memory array, the predetermined voltage is 0V.

[0013] According to an embodiment of the present invention, in the above-mentioned gate-controlled thyristor or content-addressable memory array, the first type of operation state is a P-type operation state, and the second type of operation state is an N-type operation state.

[0014] According to an embodiment of the present invention, in the above-described gate-controlled thyristor or content-addressable memory array, a charge-trapping layer is provided between the control terminal serving as the gate of the second transistor and the channel. According to an embodiment of the present invention, in the above-described gate-controlled thyristor or content-addressable memory array, the charge-trapping layer comprises an oxide / nitride / oxide layer.

[0015] Based on the above, the gate-controlled thyristor of the present invention can be used to construct a TCAM memory cell and to construct a NAND or NOR type CAM memory array using this memory cell. Furthermore, the gate-controlled thyristor of the present invention operates with a high on-current / off-current ratio, thus allowing for a higher sensing boundary for reading and higher accuracy in searching for matching or mismatched data. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a traditional single-branch CAM memory constructed using transistors with bipolar characteristics.

[0017] Figure 2 This is a circuit structure of a gate-controlled thyristor illustrated according to an embodiment of the present invention.

[0018] Figure 3A and Figure 3B This is an operational concept diagram of a gate-controlled thyristor according to an embodiment of the present invention.

[0019] Figure 4 This is a truth representation of a gate-controlled thyristor illustrated according to an embodiment of the present invention.

[0020] Figures 5A to 5C This is a schematic diagram illustrating the experimental results of a gate-controlled thyristor according to an embodiment of the present invention.

[0021] Figures 6 to 7 This is a schematic diagram of CAM search simulation of a gate-controlled thyristor according to an embodiment of the present invention.

[0022] Figure 8 This is an illustrative diagram illustrating the application of a gate-controlled thyristor to an analog CAM according to an embodiment of the present invention.

[0023] Figures 9A to 9C This is an explanatory diagram of the sensing boundary of the gate-controlled thyristor according to an embodiment of the present invention.

[0024] Figure 10 This is a schematic diagram of a NOR-type CAM memory array constructed using gate-controlled thyristors according to an embodiment of the present invention.

[0025] Figure 11 This is a schematic diagram of a NAND-type CAM memory array constructed using gate-controlled thyristors according to an embodiment of the present invention.

[0026] Figure 12 It is the truth table used by the NAND-type CAM memory array constructed using the gate-controlled thyristors of the present invention.

[0027] Explanation of reference numerals in the attached figures:

[0028] 10, 100: Gate-controlled thyristors

[0029] 12: Tunneling Field-Effect Transistor

[0030] 14. T: Drive circuit

[0031] 102-1, 102-2, 102-3: Gate

[0032] 104: P+ doped region

[0033] 106: N+ doped region

[0034] 108-1, 108-2, 108-3: Channels

[0035] 110: ONO layer

[0036] 200: NOR type content-addressable memory array

[0037] 300: NAND Content Addressable Memory Array

[0038] G1, G2, G3: First, second, and third transistors

[0039] ML: Matching line

[0040] SRL: Search Line

[0041] I ML Matching line current

[0042] Vr: Fixed bias voltage

[0043] Vdrv: Drive voltage

[0044] VDD: Power supply voltage

[0045] d: character spacing

[0046] Lg: Gate length Detailed Implementation

[0047] Figure 2 This is a circuit structure of a gate-controlled thyristor illustrated according to an embodiment of the present invention. For example... Figure 2 As shown, this embodiment uses a gate-controlled thyristor (GCT) 100 to structure a content-addressable memory cell. The gate-controlled thyristor 100 includes a first transistor G1, a second transistor G2, and a third transistor G3, each having a control terminal, a first terminal, and a second terminal. In one embodiment, if the first transistor G1, the second transistor G2, and the third transistor G3 are implemented using MOS or FET transistors, the gate can serve as the control terminal to control the on or off state of each transistor, and the source / drain can serve as the first and second terminals mentioned above. The first transistor G1, the second transistor G2, and the third transistor G3 are connected in series. Thus, the second transistor G2 is used for data storage, and the first transistor G1 and the third transistor G3 serve as pass gates.

[0048] like Figure 2 As shown, the first transistor G1 has a control terminal, a first terminal, and a second terminal. The control terminal is connected to the search line SRL, and the second terminal is connected to the ground potential GND. The second transistor G2 has a control terminal, a first terminal, and a second terminal. Its control terminal is connected to the fixed bias voltage Vr, and its second terminal is connected to the first terminal of the first transistor G1. The third transistor G3 has a control terminal, a first terminal, and a second terminal. Its control terminal is connected to the search line SRL, its first terminal is connected to the matching line ML, and its second terminal is connected to the first terminal of the second transistor G2.

[0049] Here, as Figure 2As shown, the drive circuit T is used to drive the matching line ML. The drive circuit T can include different circuit components; for simplicity, a transistor is used as the switching element. When the second transistor G2 is selected for reading, a drive voltage Vdrv is applied to the drive circuit. After the drive circuit T is turned on, the power supply voltage VDD can be applied to the matching line ML to provide a high voltage to the matching line ML. When the gate-controlled thyristor 100 is operating, the matching line ML can be maintained at the power supply voltage VDD. When the gate-controlled thyristor 100 is operated, if the search result is a mismatch, the matching line ML will discharge to ground GND through the first transistor G1, the second transistor G2, and the third transistor G3, that is, a matching line current I is generated. ML At this time, the voltage of the matching line ML will also change, such as starting to drop from the power supply voltage VDD.

[0050] According to an embodiment of the present invention, the second transistor G2 may have a charge trapping layer between its gate and channel, such as a composite layer structure of oxide / nitride / oxide (ONO) layers, for storing data. The material and physical parameters (such as thickness) of the ONO layer can be any material of existing transistor technology, and the present invention is not particularly limited thereto. The value of the data can be determined by whether electrons are injected into the ONO layer of the second transistor G2. As an example, the state in which no electrons are injected into the ONO layer is called data "0", while the state in which a large number of electrons are injected into the ONO layer is called data "1". The threshold voltage value of the second transistor G2 can be adjusted by whether electrons are injected. In addition, as another example, the data state can also be determined by the relative amount of injected electrons, such as data "0" and data "1". For example, data "1" can refer to a relatively large number of electrons injected into the ONO layer, while data "0" can refer to a relatively small number of electrons injected into the ONO layer. However, the difference between the two electron injection amounts is large enough to clearly distinguish data "0" and data "1". In addition to determining the state of data by whether or not electrons are injected, the state of data can also be determined by whether or not holes are injected.

[0051] When operating the gate-controlled thyristor 100, a fixed bias voltage Vr is applied to the control terminal (gate) of the second transistor G2 to read the data "0" or "data 1" stored in the second transistor G2. Simultaneously, a search line voltage V is applied to the search line SRL. SRL Search for line voltage V SRL A voltage less than a predetermined voltage (e.g., 0V) indicates a search bit "0", and the search line voltage is V. SRL A voltage greater than a predetermined voltage (e.g., 0V) represents a search bit "1". The search bit indicates that the data bits stored in the second transistor G2 (content-addressable memory cell) of the gate-controlled thyristor 100 are to be searched.

[0052] At this point, by comparing the search bit with the read data, if they match, the second transistor G2 will not conduct, and the power supply voltage VDD applied to the matching line ML will not discharge to the ground potential GND through transistors G1, G2, and G3. At this time, the matching line current I... ML This is equivalent to the off current equal to Ioff, meaning no current flows. Conversely, if the two are mismatched, the second transistor G2 will conduct, and the power supply voltage VDD applied to the matching line ML will discharge to the ground potential GND through transistors G1, G2, and G3. At this time, the matching line current I... ML This is equivalent to conducting current Ion, meaning that current flows through it. Therefore, by sensing the magnitude of the current, the address of the data to be searched can be determined.

[0053] Furthermore, according to an embodiment of the present invention, the search line voltage V SRL When the voltage is greater than a predetermined voltage (e.g., 0V), the second transistor G2 of the gate-controlled thyristor 100 operates in a type-1 state, behaving equivalent to an NFET transistor (i.e., NFET state). Conversely, if the search line voltage V is below a predetermined voltage, the second transistor G2 operates in a type-1 state. SRL When the voltage is less than a predetermined voltage (e.g., 0V), the second transistor G2 of the gate-controlled thyristor 100 is in the second type operating state, and its behavior is equivalent to that of a PFET transistor (i.e., PFET state).

[0054] Furthermore, in the above structure, the terminal connected to the matching line ML (the first terminal of the third transistor G3) is the P+ junction region, which can be further connected to the bit line. Conversely, the terminal connected to the ground potential GND is the N+ junction region, which can be further connected to the source line. In other words, the gate-controlled thyristor 100 itself physically behaves as a device with a PN junction.

[0055] like Figure 3A As shown, when the second transistor G2 is programmed to data "0" or data "1", it corresponds to different threshold voltages Vt1, Vt2, etc. The search line voltage V applied to the search line SRL... SRL When the voltage is greater than 0V, for the data "0", when the fixed bias voltage Vr exceeds the threshold voltage Vt1, the matching line current I... ML It increases with the increase of the fixed bias voltage Vr; similarly, for data 1, when the fixed bias voltage Vr exceeds the threshold voltage Vt2, the matching line current I... ML It increases with the increase of the fixed bias voltage Vr. Therefore, the search line voltage V applied to the search line SRL... SRL When the voltage is greater than 0V, the gate-controlled thyristor 100 (or can be regarded as transistor G2) behaves like an NFET transistor.

[0056] In addition, if Figure 3B As shown, when the second transistor G2 is programmed to data "0" or data "1", it corresponds to different threshold voltages Vt1, Vt2, etc. The search line voltage V applied to the search line SRL... SRL When the voltage is less than 0V, for the data "0", when the fixed bias voltage Vr is lower than the threshold voltage Vt1, the matching line current I... ML It increases as the fixed bias voltage Vr decreases; similarly, for data "1", when the fixed bias voltage Vr is lower than the threshold voltage Vt2, the conduction current I... ML It increases as the fixed bias voltage Vr decreases. Therefore, the search line voltage V applied to the search line SRL... SRL When the voltage is less than 0V, the gate-controlled thyristor 100 (or can be regarded as transistor G2) behaves like a PFET transistor.

[0057] Figure 4 This is a truth representation diagram of a gate-controlled thyristor according to an embodiment of the present invention. Figure 4 As shown, the horizontal axis represents the state where the second transistor G2 stores data "0" or data "1". As an example, as described above, a data "0" state indicates that the ONO layer of the second transistor G2 has no stored charge, while a data "1" state indicates that the ONO layer of the second transistor G2 has stored charge. Furthermore, the vertical axis represents the state where the search bit is "0" or "1". Here, a search bit "0" is defined as voltage V. SRL When the voltage is less than 0V, the search bit "1" indicates a voltage of V. SRL Greater than 0V.

[0058] like Figure 4 As shown, when the search bit is "0" and the second transistor G2 is in the data "0" state, or when the search bit is "1" and the second transistor G2 is in the data "1" state, the gate-controlled thyristor 100 will output a "matched" result. Here, the gate-controlled thyristor 100 will not generate a matching line current I. ML (i.e., Ioff). When the search bit is "0" and the second transistor G2 is in the state of data "1", or when the search bit is "1" and the second transistor G2 is in the state of data "0", the gate-controlled thyristor 100 will output a "mismatch" result. Here, the gate-controlled thyristor 100 (or transistor G2) generates a matching line current I. ML (i.e., Ion).

[0059] In other words, when the search bit is "0", it means that the data "0" is being searched. If the second transistor G2 also stores the data "0", it means that the data has been found, and no matching line current I will be generated. MLThis refers to the matching state. When the search bit is "1", it means that data "1" is being searched. If the second transistor G2 stores data "0", it means that the data was not found, and a matching line current I is generated. ML This indicates a mismatch. The search method with the search bit set to "1" can also be seen... Figure 4 The truth table can be used to determine this.

[0060] Therefore, by Figure 4 It can be understood that the gate-controlled thyristor 100 of the present invention can be used to implement a TCAM (Ternary CAM) memory cell architecture with a single transistor (i.e., the second transistor G2).

[0061] Figures 5A to 5C This is a schematic diagram illustrating the experimental results of a gate-controlled thyristor according to an embodiment of the present invention, wherein... Figure 5A A schematic diagram of the gate-controlled thyristor 100 used in the experiment is shown. Figure 5B Plot the current-voltage curves of the gate-controlled thyristor 100 as a PFET, and Figure 5C The current-voltage curves of the gate-controlled thyristor 100 as an NFET are plotted.

[0062] like Figure 5A As shown in Figure 3, the gate-controlled thyristor 100 has gates 102-1, 102-2, and 102-3 for a first transistor G1, a second transistor G2, and a third transistor G3, respectively. Gates 102-1 and 102-3 can be further connected to the search line SRL, while gate 102-2 can be further connected to lines providing a fixed bias voltage Vr (these lines correspond to word lines in a memory array, a single-cell multi-word-line architecture). Below gates 102-1, 102-2, and 102-3 are channels 108-1, 108-2, and 108-3 for the first transistor G1, the second transistor G2, and the third transistor G3, respectively. The first terminal of the third transistor G3, connected to the matching line ML (corresponding to the bit line in a memory array), is a P+ doped region 104, and the second terminal of the first transistor G1, connected to the ground potential GND, is an N+ doped region 106. Thus, the gate-controlled thyristor 100 is equivalent to a PN junction element. In addition, the second transistor G2, which serves as a data storage transistor, also includes an ONO layer 110 between the gate 102-2 and the channel 108-2 to capture charges (electrons or holes), that is, to store data.

[0063] After conducting the experiment, Figure 5B and Figure 5C This displays the measurement results of current-voltage (IV). For example... Figure 5B As shown, here, a search line voltage V is applied to the search line SRL. SRL= -3V, which is less than 0V. As mentioned earlier, the second transistor G2 behaves like a PFET transistor. Figure 5B Curves I, II, and III in the diagram represent different states of cse, where cse represents the amount of charge stored in the ONO layer of the second transistor G2. Curve I represents stored electrons (cse = -2e19 (negative)), curve II represents stored holes (cse = +2e19 (positive)), and curve III represents no stored charge (cse = 0 (uncharged)). Furthermore, as... Figure 5C As shown, here, a search line voltage V is applied to the search line SRL. SRL = +3V, which is greater than 0V. As mentioned earlier, the second transistor G2 behaves like an NFET transistor. Similarly, Figure 5C Curve I represents the presence of stored electrons (cse = -2e19 (negative charge)), curve II represents the presence of stored holes (cse = +2e19 (positive charge)), and curve III represents the presence of no stored charge (cse = 0 (uncharged)).

[0064] from Figure 5B and Figure 5C As can be seen, in both PFET and NFET states, the second transistor G2 exhibits a trend where the more charge it carries, the more its IV curve shifts to the right. The charge injection method can be implemented using typical flash memory operation methods, such as programming using the FN tunneling effect or hot electron channel effect; this invention is not particularly limited in this regard. Therefore, by adjusting the threshold voltage Vt of the second transistor G2, the data stored in the second transistor G2 can be changed.

[0065] In addition, from Figure 5B and 5C It is also clear that by changing the search line voltage V applied to the search line SRL... SRL The polarity (positive or negative) of the voltage can change the operating state of the second transistor G2, switching it between PFET and NFET states. In other words, the polarity of the gate voltages Vg1 and Vg3 of the first transistor G1 and the third transistor G3, i.e., the voltage V... SRL The polarity of the gate voltage determines the shift behavior of the IV curve. That is, as mentioned above, a positive gate voltage (Vg1, Vg3) passes through the gate. SRL The >0V) produces the characteristics of an NFET transistor, with negative gate voltages Vg1 and Vg3 (V) passing through the gate. SRL <0V) produces the characteristics of a PFET transistor.

[0066] In addition, from Figure 5B and 5CIt is also clear that the IV curve of the gate-controlled thyristor 100 in this embodiment of the invention, whether in PFET or NFET mode, exhibits a very steep subthreshold slope, and the ratio of the on-current Ion to the off-current Ioff is very high. Figure 5B and 5C For example, in PFET or NFET mode, the on-state current Ion is approximately 1e-6, while the off-state current Ioff is approximately 1e-12 or less. Therefore, the Ion / Ioff ratio can reach at least 1e6.

[0067] Figures 6 to 7 This is a schematic diagram of CAM search simulation of a gate-controlled thyristor according to an embodiment of the present invention. Figure 6 This is an example of an IV diagram. The horizontal axis represents the voltage Vg2 applied to the gate of the second transistor G2, which is the fixed bias voltage Vr. This experimental simulation diagram essentially represents... Figure 3A , Figure 3B The schematic diagrams are combined into a single IV diagram.

[0068] exist Figure 6 The dashed line represents the search line voltage V. SRL With a voltage of +3V, the second transistor G2 behaves like an NFET. IV curve Ia represents the first data state (e.g., data "0"), and IV curve Ib represents the second data state (e.g., data "1"). Furthermore, the solid line represents the search line voltage V. SRL At -3V, the second transistor G2 behaves like a PFET. IV curve IIa represents the first data state (e.g., data "0"), and IV curve IIb represents the second data state (e.g., data "1"). Figure 4 To illustrate, consider the top left of the truth table, where the data is "1" and the search bit is "0", which is equivalent to... Figure 6 The IV curve IIb. Therefore, when a fixed bias voltage Vr = 3V is applied to the gate of the second transistor G2, from Figure 6 It can be seen that its corresponding matching line current I ML It is approximately 10⁻⁶A, which is greater than 0. Therefore, it can be correctly determined that the search result is a mismatch.

[0069] Therefore, to obtain the correct matching result, the fixed bias voltage Vr must be set correctly. Thus, the fixed bias voltage Vr can be set between the threshold voltage Vt1 corresponding to data "0" in PFET state and the threshold voltage Vt2 corresponding to data "1" in NFET state. That is, Vt1 <Vr<Vt2。

[0070] The fixed bias voltage Vr can be set between the threshold voltage value corresponding to the first data state (data "0") under the second type of operation state (PNET state) (i.e., the voltage value corresponding to Ioff of the above-mentioned IV curve IIa) and the threshold voltage value corresponding to the second data state (data "1") under the first type of operation state (NNET state) (i.e., the voltage value corresponding to Ioff of the above-mentioned IV curve Ib).

[0071] In addition, Figure 6 In this context, the first data state, i.e., data "0", uses cse = 0, while the second data state, i.e., data "1", uses cse = -2e19. However, the first and second data states can essentially be set using different charges (electrons or holes). Furthermore, the aforementioned threshold voltage values ​​Vt1 and Vt2 can also be adjusted by changing the charge, causing them to shift left or right, and consequently, the fixed bias voltage Vr can also be adjusted accordingly.

[0072] like Figure 7 As shown, the top voltage-time graph displays the time variations of the voltages Vg1, Vr, and Vg3 applied to the gates of the first transistor G1, the second transistor G2, and the third transistor G3 of the gate-controlled thyristor 100, as well as the power supply voltage VDD and the drive voltage Vdrv of the drive circuit. After the gate-controlled thyristor 100 is started, the drive voltage Vdrv of the drive circuit T rises from 0V to approximately 3V, causing the power supply voltage VDD to be applied to the matching line ML. Then, a fixed bias voltage Vr is applied to the gate of the second transistor G2, and the data stored in the second transistor G2 is read. Simultaneously, the gate voltages Vg1 and Vg3 (i.e., the search line voltage V) applied to the gates of the first transistor G1 and the third transistor G3 are... SRL The voltage is -3V (less than 0V), meaning the search line SRL is in a search bit "0" state. Then, the gate voltages Vg1 and Vg3 (i.e., the search line voltage V) are applied to the gates of the first transistor G1 and the third transistor G3. SRL The value is +3V (greater than 0V), which means that the search bit "1" is displayed on the search line SRL.

[0073] At this time, as Figure 7 The current-voltage diagram in the middle shows the state where this data is "0" (assuming cse = 0). At this time, with the search bit "0", it is in a matched state. Therefore, the matched line current I is shown. ML It is approximately 0 μA (i.e., Ioff). Furthermore, when the search bit is "1", it is in a mismatch state. Therefore, the matching line current I is observed. ML It is approximately 1.2 μA (i.e., Ion).

[0074] In addition, if Figure 7 The current-voltage diagram below shows the state where this data is "1" (assuming cse = -2e19). At this time, when the search bit is "0", it is a mismatch state. Therefore, the matching line current I is shown. ML It is approximately 1.2 μA (i.e., Ion). Furthermore, when the search bit is "1", it is in a matched state. Therefore, a matched line current I is observed. ML It is approximately 0 μA (i.e., Ioff).

[0075] As can be clearly seen from the above simulation results, the gate-controlled thyristor 100 provided in this embodiment can effectively determine whether the search data matches, and the on-current / off-current (Ion / Ioff) ratio between matching and non-matching is quite large, which can provide a very high sensing boundary.

[0076] Figure 8 This is an illustrative diagram illustrating the application of a gate-controlled thyristor to an analog CAM according to an embodiment of the present invention. Figure 8 The diagram shows the IV plots for three different data states: the left represents cse = 0 (uncharged), the middle represents cse = 2e19 (positively charged), and the right represents cse = 4e19 (more positively charged). Holes are used as an example here. The fixed bias voltage Vr is set to 3V. Figure 8 Each IV diagram presents the search line voltage V. SRL Various conditions ranging from -4V to +4V.

[0077] Table 1 shows the horizontal axis representing I when the bias voltage Vr = 3V. ML Furthermore, the various data conditions, with the vertical axis representing different search line voltages V, indicate the overall situation. SRL As shown in Table 1, the boundary between matching and mismatch can be adjusted. For example, when cse = 0, there are two search line voltages V. SRL (-4V, -3V) can produce matching, and at cse = 2e19, there are three search line voltages V. SRL (-4V, -3V, -2V) can produce matching, and at cse = 4e19, there are five search line voltages V. SRL Matching can be achieved at (-4V, -3V, -2V, -1V, 0V). Therefore, the boundary between matched and unmatched voltages can be achieved by adjusting the CSE. Thus, the range of matched voltages (low matching line current I) is... ML The charge can be adjusted within a continuous range. Therefore, different amounts of charge can be programmed into the second transistor G2 as needed to achieve the results of analog CAM.

[0078] Table 1

[0079]

[0080] Figures 9A to 9C This is an explanatory diagram of the sensing boundary of the gate-controlled thyristor according to an embodiment of the present invention. In operation, it typically involves finding the address of a word. Figure 9A This example illustrates the CAM structure of a single word. This example contains N... Figure 2 The CAM, or word length, formed by the gate-controlled thyristors (GCTs) 100 shown is N. Here, the matching lines ML of the N GCTs 100 are connected together, while the search lines SRL_1, SRL_2, ... SRL_N of each GCT 100 are set separately.

[0081] According to the above explanation, during CAM operation, no current flows through the gate-controlled thyristor 100 during matching, while current flows through the gate-controlled thyristor 100 during mismatch. It is generally desirable for the difference between the current during matching and the current during mismatch to be as large as possible, so as to easily determine whether the second transistor G2 in the gate-controlled thyristor 100 stores data. Therefore, a sensing margin (SM) parameter is defined to represent the quality of the CAM sensing margin. The sensing margin SM is defined as shown in equation (1) below, that is, the ratio of 1-bit mismatch (worst case) to full-bit matching. In equation (1) below, the denominator represents the condition where all bits are matched (matching line current I). ML =Ioff). The numerator represents the point where the current is most similar to the point of mismatch and then matching, i.e., when only 1 bit is mismatched and (N-1) bits are matched. Therefore, the sensing boundary SM is calculated in this way. According to this method, the higher the sensing boundary SM, the better.

[0082]

[0083] Figure 9B This is an example of the IV curve of the gate-controlled thyristor 100 of the present invention, wherein, as previously described, the solid line represents the search bit "0" (i.e., V). SRL <0V), the dashed line represents the search bit "1" (i.e., V). SRL >0V). Figure 9C Then it will display Figure 1 The diagram shows the IV curves for using bipolar TFETs to construct a CAM memory. Additionally, Table 2 below lists... Figure 9B , Figure 9C The sensing boundary SM is calculated using the above method (both are calculated with a word length of N = 1024).

[0084] Table 2

[0085]

[0086] As can be clearly seen from Table 2, the gate-controlled thyristor 100 of this embodiment ( Figure 2 The sensing boundary SM of the CAM memory, constructed from , is 11700, while that of the conventional bipolar TFET ( Figure 1 The sensing boundary SM of the CAM memory constructed by the gate-controlled thyristor 100 of the present invention is 11. Since the gate-controlled thyristor 100 of the present invention can provide a high Ion / Ioff ratio, which is more than 1000 times higher than the conventional Ion / Ioff ratio, the CAM memory constructed by the gate-controlled thyristor 100 of the present invention has a good sensing boundary SM.

[0087] Figure 10 This is a schematic diagram of a NOR-type CAM memory array constructed using gate-controlled thyristors according to an embodiment of the present invention. Figure 10 As shown, the multiple gate-controlled thyristors 100 serving as CAM memory cells are configured in a NOR-type manner in the CAM memory array 200. The CAM memory array 200 includes multiple CAM memory cells, each of which is constructed using... Figure 2 The gate-controlled thyristor 100 shown is used as an example. Its specific structure and operation can be referred to the above description. The CAM memory array 200 also includes multiple matching lines ML_1 to ML_m (m lines) which are arranged in a roughly parallel manner in the first direction (row direction, X direction), and multiple search lines SRL_1 to SRL_N (N lines) which are arranged in a roughly parallel manner in the second direction (column direction, Y direction).

[0088] Furthermore, the aforementioned multiple gate-controlled thyristors 100 are respectively arranged at the intersections of multiple matching lines ML_1 to ML_m and multiple search lines SRL_1 to SRL_N. The first terminal of the third transistor of each gate-controlled thyristor 100 located in the same column is connected to the corresponding matching line. For example, the first terminal of the third transistor of each gate-controlled thyristor 100 in the first column is connected to the corresponding first matching line ML_1, and the first terminal of the third transistor of each gate-controlled thyristor 100 in the m-th column is connected to the corresponding m-th matching line ML_m.

[0089] Furthermore, the gates of the first transistor G1 and the third transistor G3 of each gate-controlled thyristor 100 located in the same row are connected to corresponding search lines. For example, the gates of the first transistor G1 and the third transistor G3 of each gate-controlled thyristor 100 in the first row are connected to the corresponding first search line SRL_1, and the gates of the first transistor G1 and the third transistor G3 of each gate-controlled thyristor 100 in the Nth row are connected to the corresponding Nth search line SRL_N. Additionally, the second terminal of the first transistor G1 of each of the plurality of gate-controlled thyristors 100 is connected to ground. Thus, a NOR-type TCAM memory array 200 can be constructed using the aforementioned plurality of gate-controlled thyristors 100.

[0090] In this architecture, the truth table used by the gate-controlled thyristor 100, which serves as each CAM memory unit, can be referenced above. Figure 4 The relevant explanations are provided. Therefore, data can be searched in the CAM memory array 200, and it can be determined whether the searched data matches the data stored in the CAM memory array 200.

[0091] Figure 11 This is a schematic diagram of a NAND-type CAM memory array constructed using gate-controlled thyristors according to an embodiment of the present invention. Figure 11 As shown, the multiple gate-controlled thyristors 100 serving as CAM memory cells are configured in a NAND-type manner in the CAM memory array 300. The CAM memory array 300 also includes multiple matching lines ML_1 to ML_m (m lines) and multiple search lines SRL_1 to SRL_N (N lines).

[0092] Each content-addressable memory cell, i.e., a gate-controlled thyristor, extends and is arranged in the row direction (X direction) and column direction (Y direction) to form a memory array. Multiple gate-controlled thyristors 100 in the same row (e.g., row 1 to row m) in the column direction Y are connected in series. The first terminal of the third transistor G3 of the first gate-controlled thyristor in the same row is connected to the corresponding matching line among multiple matching lines, and the second terminal of the first transistor G1 of the last gate-controlled thyristor 100 in the same row is connected to ground. For example, the first terminal of the third transistor G3 of the first gate-controlled thyristor 100 (i.e., m=1, N=1) in the first row is connected to the corresponding matching line ML_1 among multiple matching lines, and the second terminal of the first transistor G1 of the last gate-controlled thyristor 100 (i.e., m=1, N=N) in the first row is connected to ground.

[0093] Furthermore, in the same column (e.g., columns 1 to N) along the row direction (X direction), the control terminals of the first transistor G1 and the third transistor G3 of each of the plurality of gate-controlled thyristors 100 are connected to the corresponding search lines among the plurality of search lines. For example, in the first column (i.e., (1,1) to (m,1)), the control terminals of the first transistor G1 and the third transistor G3 of each of the plurality of gate-controlled thyristors 100 are connected to the corresponding search line SRL_1 among the plurality of search lines, and the remaining columns have the same architecture. In this way, a NAND-type TCAM memory array 300 can be constructed using the above-described plurality of gate-controlled thyristors 100 architecture.

[0094] Figure 12 This is the truth table used by the NAND-type CAM memory array constructed using the gate-controlled thyristors of this embodiment of the invention. Because the memory cells in the same row of the NAND-type CAM memory array 300 are connected in series, the truth table used for NAND differs from that used for NOR. First, in NAND, matching generates current, while mismatch does not. Therefore, when the search bit is "0", if the data is "0", it indicates a match has been found. At this time, there will be a matching line current I. ML This is generated. Conversely, if the search bit is "1" and the data is "0", it indicates that no match was found, resulting in a mismatch. In this case, the matching line current I... ML It is 0.

[0095] exist Figure 12 There are three data states: data "0" indicates that many electrons have been injected into the ONO layer of the second transistor G2; data "1" indicates that no electrons have been injected into the ONO layer of the second transistor G2; and data "X" indicates that only a small number of electrons have been injected into the ONO layer of the second transistor G2. In addition, the truth table used for NAND flash memory also includes a so-called "don't care" state, i.e., data "X". In this case, regardless of whether the search bit is "0" or "1", there will be a matching line current I. ML produce.

[0096] In summary, the gate-controlled thyristor of this invention can be used to construct TCAM memory cells and NAND or NOR type CAM memory arrays. Furthermore, the gate-controlled thyristor of this invention operates with a high on-current / off-current ratio, thus allowing for a higher sensing boundary and greater accuracy in searching for matching or mismatched data.

Claims

1. A gate-controlled thyristor for constructing a content-addressable memory unit, the gate-controlled thyristor comprising: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is connected to a search line and the second terminal is connected to a ground potential; The second transistor has a control terminal, a first terminal and a second terminal. The control terminal is connected to a fixed bias voltage, and the second terminal is connected to the first terminal of the first transistor. The second transistor is used to store data. as well as The third transistor has a control terminal, a first terminal, and a second terminal. The control terminal is connected to the search line, the first terminal is connected to the matching line, and the second terminal is connected to the first terminal of the second transistor. The search bit is determined based on the search line voltage applied to the search line, and the search bit is compared with the data to determine whether the search bit matches the data.

2. The gate-controlled thyristor according to claim 1, wherein when the search line voltage is greater than a predetermined voltage, the second transistor of the gate-controlled thyristor is in a first-type operating state, and when the search line voltage is less than the predetermined voltage, the second transistor of the gate-controlled thyristor is in a second-type operating state.

3. The gate-controlled thyristor according to claim 2, wherein the first type of operating state is an NFET state and the second type of operating state is a PFET state.

4. The gate-controlled thyristor according to claim 2, wherein the fixed bias voltage is set between a threshold voltage value corresponding to a first data state in the second type of operating state and a threshold voltage value corresponding to a second data state in the first type of operating state.

5. The gate-controlled thyristor according to claim 2, wherein... When the search line voltage is greater than the predetermined voltage, the search bit is the first bit, and When the search line voltage is less than the predetermined voltage, the search bit is the second bit.

6. The gate-controlled thyristor according to claim 2, wherein... When the search bit matches the data, the second transistor generates a shutdown current. When the search bit does not match the data, the second transistor generates a conduction current, and The ratio of the on-current to the off-current is at least 106.

7. The gate-controlled thyristor according to claim 2, wherein the predetermined voltage is 0V.

8. The gate-controlled thyristor according to claim 2, wherein the first type of operation state is an N-type operation state and the second type of operation state is a P-type operation state.

9. The gate-controlled thyristor of claim 1, wherein a charge trapping layer is provided between the control terminal, which serves as the gate of the second transistor, and the channel.

10. The gate-controlled thyristor of claim 9, wherein the charge trapping layer comprises an oxide / nitride / oxide layer.

11. A content-addressable memory array, which is a NOR architecture, the content-addressable memory array comprising: Multiple matching lines are set roughly parallel in the row direction; Multiple search lines are arranged roughly parallel to each other in the column direction; as well as Multiple content-addressable memory cells, each composed of a gate-controlled thyristor, are located at the intersection of the multiple matching lines and the multiple search lines. Each of the aforementioned gate-controlled thyristors includes: The first transistor has a control terminal, a first terminal, and a second terminal, the second terminal being connected to a ground potential; A second transistor has a control terminal, a first terminal, and a second terminal. The control terminal is connected to a fixed bias voltage, and the second terminal is connected to the first terminal of the first transistor. The second transistor is used to store data. The third transistor has a control terminal, a first terminal, and a second terminal, wherein the second terminal is connected to the first terminal of the second transistor. The first terminal of the third transistor of each of the gate-controlled thyristors in the same column of the column direction is connected to a corresponding matching line among the plurality of matching lines. The control terminals of the first transistor and the third transistor of each of the gate-controlled thyristors in the same row in the row direction are connected to the corresponding search lines of the plurality of search lines. For the selected gate-controlled thyristor, the search bit is determined based on the search line voltage applied to the corresponding search line, and the search bit is compared with the data to determine whether the search bit matches the data.

12. The content-addressable memory array according to claim 11, wherein when the search line voltage is greater than a predetermined voltage, the second transistor of the gate-controlled thyristor is in a first-type operating state, and when the search line voltage is less than the predetermined voltage, the second transistor of the gate-controlled thyristor is in a second-type operating state.

13. The content-addressable memory array of claim 12, wherein the first type of operating state is an NFET state and the second type of operating state is a PFET state.

14. The content-addressable memory array of claim 12, wherein the fixed bias is set between a threshold voltage value corresponding to a first data state in the second type of operating state and a threshold voltage value corresponding to a second data state in the first type of operating state.

15. The content-addressable memory array according to claim 12, wherein When the search line voltage is greater than the predetermined voltage, the search bit is the first bit, and When the search line voltage is less than the predetermined voltage, the search bit is the second bit.

16. The content-addressable memory array according to claim 12, wherein When the search bit matches the data, the second transistor generates a shutdown current. When the search bit does not match the data, the second transistor generates a conduction current, and The ratio of the on-current to the off-current is at least 106.

17. The content-addressable memory array of claim 12, wherein the predetermined voltage is 0V.

18. The content-addressable memory array according to claim 12, wherein the first type of operation state is a P-type operation state and the second type of operation state is an N-type operation state.

19. A content-addressable memory array, which is a NAND-type architecture, the content-addressable memory array comprising: Multiple matching lines; Multiple search lines; as well as Multiple content-addressable memory cells, each composed of a gate-controlled thyristor, are arranged in a row-column direction to form a memory array. The gate-controlled thyristor includes: The first transistor has a control terminal, a first terminal, and a second terminal; A second transistor has a control terminal, a first terminal, and a second terminal. The control terminal is connected to a fixed bias voltage, and the second terminal is connected to the first terminal of the first transistor. The second transistor is used to store data. The third transistor has a control terminal, a first terminal, and a second terminal, wherein the second terminal is connected to the first terminal of the second transistor. In this configuration, multiple gate-controlled thyristors in the same row along the column direction are connected in series. The first terminal of the third transistor of the first gate-controlled thyristor in the same row is connected to a corresponding matching line among the multiple matching lines. The second terminal of the first transistor of the last gate-controlled thyristor in the same row is connected to ground. The control terminal of the first transistor and the control terminal of the third transistor of each of the plurality of gate-controlled thyristors in the same column in the row direction are connected to a corresponding search line among the plurality of search lines. For the selected gate-controlled thyristor, the search bit is determined based on the search line voltage applied to the corresponding search line, and the search bit is compared with the data to determine whether the search bit matches the data.

20. The content-addressable memory array according to claim 19, wherein when the search line voltage is greater than a predetermined voltage, the second transistor of the gate-controlled thyristor is in a first-type operating state, and when the search line voltage is less than the predetermined voltage, the second transistor of the gate-controlled thyristor is in a second-type operating state.

21. The content-addressable memory array of claim 20, wherein the first type of operating state is an NFET state and the second type of operating state is a PFET state.

22. The content-addressable memory array of claim 20, wherein the fixed bias is set between a threshold voltage value corresponding to a first data state in the second type of operating state and a threshold voltage value corresponding to a second data state in the first type of operating state.

23. The content-addressable memory array according to claim 20, wherein When the search line voltage is greater than the predetermined voltage, the search bit is the first bit, and When the search line voltage is less than the predetermined voltage, the search bit is the second bit.

24. The content-addressable memory array of claim 20, wherein... When the search bit matches the data, the second transistor generates a shutdown current. When the search bit does not match the data, the second transistor generates a conduction current, and The ratio of the on-current to the off-current is at least 106.

25. The content-addressable memory array of claim 20, wherein the predetermined voltage is 0V.

26. The content-addressable memory array according to claim 20, wherein the first type of operation state is a P-type operation state and the second type of operation state is an N-type operation state.

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