A 950V high-voltage superjunction MOS device with fast recovery characteristics and its fabrication method

Abstract

This invention discloses a 950V high-voltage superjunction MOS device with fast recovery characteristics and its fabrication method. The device has primary and secondary MOS regions with different gate widths. The entire device is epitaxially grown on an N-type substrate, and multiple functional layers are extended under optimal conditions. This invention alleviates the charge imbalance caused by unequal trench widths due to etching angles by using an N-type substrate with two epitaxy layers. In the cell region, the gate metal and source metal are connected respectively to form an internally integrated low-threshold auxiliary MOS structure, reducing the problems of excessive input capacitance and reverse recovery current of the superjunction MOS device. Without affecting the breakdown voltage and dynamic on-resistance, the dynamic characteristics of the device are effectively optimized. The threshold voltage is adjusted by adjusting the P-type injection dose of the low-threshold MOS, avoiding interference caused by excessively low threshold voltage in application, and also preventing punch-through breakdown in the low-threshold P-type region during reverse breakdown.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and more specifically, to a 950V high-voltage superjunction MOS device with fast recovery characteristics and its fabrication method. Background Technology

[0002] Super Junction technology achieves a breakthrough balance between on-resistance (RDS(on)) and breakdown voltage (BV) in high-voltage power MOSFETs through an alternating P / N pillar charge compensation mechanism, becoming the mainstream solution for applications above 600V.

[0003] For easy reference to the accompanying drawings in the instruction manual Figure 2 To explain, Figure 2 This is a cross-sectional view of a conventional deep-trench-filled high-voltage superjunction MOS device, including an N+ substrate 201, a primary N-type epitaxial layer 202, a JFET injection region 203, a deep-trench-filled P-pillar region 204, a P-body injection region 205, a gate oxide layer 206, a polysilicon deposition 207, an N+ source injection region 208, a dielectric layer 209, a front metal electrode 210, and a back metal electrode 211. The polysilicon deposition 207 is a continuous, integrated structure. Its built-in body diode must handle reverse recovery under freewheeling or commutation conditions (such as the inverter bridge arm dead time). However, due to the low doping characteristics of the drift region, the reverse recovery charge (Qrr) and recovery time (trr) of the body diode in the conventional superjunction structure are significantly higher than those of conventional planar MOSFETs. Specifically, the large number of minority carriers stored in the superjunction drift region (such as holes in the N-type drift region) are difficult to extract quickly when reverse biased, causing high switching losses, electromagnetic interference (EMI) and local heat accumulation in the device, which seriously restricts its application potential in new energy vehicle electric drive, high frequency power supply and other scenarios.

[0004] To improve the characteristics of body diodes, the industry has attempted to use parallel external fast recovery diodes (FRDs), but this introduces additional packaging costs and parasitic inductance, leading to dynamic voltage overshoot and reduced efficiency. Another mainstream approach is to reduce minority carrier lifetime through electron irradiation or heavy metal doping (such as platinum). While this can shorten the time reversal (trr), it degrades the on-resistance (RDS(on) increases by 10%~20%) and causes threshold voltage (Vth) drift, impairing device reliability. The trench gate integrated Schottky structure proposed in recent years can reduce carrier injection, but it significantly increases process complexity and reverse leakage current (IR), making it difficult to meet the long-term stability requirements under high temperature and high humidity environments. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a 950V high-voltage superjunction MOS device with fast recovery characteristics and its fabrication method, thereby solving one or more of the above-mentioned problems.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A 950V high-voltage superjunction MOS device with fast recovery characteristics includes an N+ substrate. The N+ substrate has a continuous primary N-type epitaxial layer and a secondary N-type epitaxial layer, with the front side facing upwards. A recessed JFET injection region is provided on the secondary N-type epitaxial layer. Deep trench-filled P-pillar regions are provided on both sides of the primary and secondary N-type epitaxial layers. PbodyS and PbodyG body region injections are separately provided on the surfaces of the deep trench-filled P-pillar regions, respectively. The PbodyG body region injection is the P-type body region injection of the main MOS, and the PbodyS body region injection... The input is a P-type body region implantation for a low threshold auxiliary MOS. A gate oxide layer is provided on the PbodyS body region implantation, PbodyG body region implantation and secondary N-type epitaxial surface. Polysilicon is deposited on the gate oxide layer. The polysilicon deposition has a discontinuous structure. A recessed N+ source implantation region is also provided on the gate oxide layer. The N+ source implantation regions on both sides are correspondingly contacted by the PbodyS body region implantation and PbodyG body region implantation. A dielectric layer is also provided on the gate oxide layer. The dielectric layer covers the polysilicon deposition and contacts the N+ source implantation region and the JFET implantation region.

[0008] The N+ substrate has a back metal electrode on the back side and a front metal electrode on the front side of the gate oxide layer. The front metal electrode covers the dielectric layer and contacts the N+ source injection region.

[0009] Furthermore, the PbodyS body region implantation and PbodyG body region implantation have the same structural ratio but different gate widths.

[0010] Furthermore, the gate width implanted in the Pbody S body region is 1.5 μm, and the gate width implanted in the Pbody G body region is 2.7 μm.

[0011] A method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics, the steps of which are as follows:

[0012] S1. Prepare an N+ substrate, and sequentially grow a first N-type epitaxial growth and a second N-type epitaxial growth on the N+ substrate;

[0013] S2. A thin pre-oxidation layer is grown on the secondary N-type epitaxy, and N-type JFET implantation is performed to form the JFET implantation region. The thin pre-oxidation layer is then removed.

[0014] S3. Perform deep trench etching and P-type epitaxial filling on the primary N-type epitaxial layer and the secondary N-type epitaxial layer to form P-pillars. Grow a sacrificial oxide layer on the surface and remove it completely to keep the surface flat.

[0015] S4. A thin pre-oxidized layer is grown on a flat surface, and a high-dose, low-energy P-type main MOS body region implantation and a low-dose, low-energy P-type low-threshold auxiliary MOS body region implantation are performed. High-temperature push junction is then formed to form PbodyG body region implantation and PbodyS body region implantation.

[0016] S5. A field oxide layer is thermally deposited on the surface, and the active region is etched. A gate oxide layer is grown in the active region, and gate polysilicon is deposited to form polysilicon deposition. The gate is etched and separated to form the gate implanted in the PbodyG body region and the gate implanted in the PbodyS body region.

[0017] S6. Etch the oxide layer and implant to form the N+ source implantation region, activate the source and ESD protection zone, deposit and reflow the ILD, open the hole to complete the metal deposition and etching, deposit and etch the surface dielectric and organic matter to form the front metal electrode, and metallize the N+ substrate on the back to form the back metal electrode.

[0018] Furthermore, the resistivity of the primary N-type epitaxy and the secondary N-type epitaxy in step S1 are different, the thickness of the thin pre-oxidation layer in step S2 is 200 μm, and the implantation condition of the JFET implantation region is 2e12 cm. -2 / 60keV.

[0019] Furthermore, in step S3, the deep trench etching is performed using wet etching, with a trench depth of 65 μm, a trench width of 5 μm, an etching angle of 88.8°, and a P-type epitaxial fill concentration of 4.2e15cm. -2 .

[0020] Furthermore, the injection condition for the PbodyG body region injection in step S4 is 6e13cm. -2 The injection conditions for Pbody S-section were 60 keV and 4e13 cm. -2 / 80keV.

[0021] Furthermore, in step S4, the thickness of the thin pre-oxidized layer is 200 μm, the annealing conditions are 1100 °C, and the annealing time is 180 min.

[0022] Furthermore, in step S5, the ambient temperature for surface thermal deposition is 980℃, and the thickness of the field oxide layer is 8000 μm; the growth temperature of the gate oxide layer is 1050℃, the growth thickness is 1000 μm, and the growth time is 90 min; the self-doping concentration of the polysilicon deposition is 4.3e20 cm⁻¹. -3 The thickness is 4000 μm; the polysilicon gate region in the middle of each cell of the gate region is etched to etch out a PbodyG body region implantation with a gate width of 2.7 μm and a PbodyS body region implantation with a gate width of 1.5 μm. The gate and source of the PbodyS body region implantation are connected and at the same potential.

[0023] Furthermore, in step S6, the remaining thickness of the oxide layer after etching is 200 μm; the implantation activation conditions for the source region and the ESD protection zone are 5e15 cm⁻¹ of arsenic ions. -2 The annealing temperature was 950℃, and the annealing time was 30 min; the interlayer dielectric thickness of the ILD was 11200 μm; the densification reflow temperature was 900℃, and the densification reflow time was 30 min; the pre-etching aperture size was 3 μm, and the hole filling conditions were 1.25 e15 cm⁻¹ of boron difluoride. -2 / 40keV, boron 3.5e15cm -2 The metal is heated to 80 keV and subjected to rapid annealing for 15 seconds; a 4 μm aluminum-copper alloy front metal electrode and a back metal electrode are deposited.

[0024] In summary, the present invention has the following beneficial effects:

[0025] By using an N-type substrate with two epitaxy layers, the charge imbalance caused by the unequal trench widths due to the etching angle can be alleviated. The double epitaxial structure can achieve better charge balance and ensure the stability of the breakdown voltage.

[0026] A low-threshold auxiliary MOS is integrated in the cell region. The threshold voltage of the auxiliary MOS is around 1.3V, which is much lower than the threshold voltage of the main MOS device. The threshold voltage of the auxiliary MOS device is adjusted by the injection dose. The polysilicon of the auxiliary MOS cell is etched and separated, with one side connected to the gate metal and the other side connected to the source metal, forming an internally integrated low-threshold auxiliary MOS structure. This measure reduces the problem of excessive input capacitance and reverse recovery current of the superjunction MOS device, and effectively optimizes the dynamic characteristics of the device without affecting the breakdown voltage and dynamic on-resistance.

[0027] The threshold voltage of the low-threshold auxiliary MOS can be adjusted by regulating the P-type injection dose in the low-threshold auxiliary MOS region. This avoids interference to the device during application due to excessively low threshold voltage and also prevents punch-through breakdown in the low-threshold P-type region when the device is under reverse breakdown voltage. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view of the superjunction MOS device structure provided by the present invention;

[0029] Figure 2 A cross-sectional view of an existing superjunction MOS device structure;

[0030] Figure 3 A comparison diagram of the IV curves of the structure provided in this application and existing superjunction MOS devices;

[0031] Figure 4A comparison of threshold voltage curves of the main MOS and auxiliary MOS in the superjunction MOS device provided by the present invention;

[0032] Figure 5 A comparison diagram of the Ciss-V curves of the superjunction MOS devices provided in this application and those of existing structures, provided by this invention.

[0033] Figure 6 A comparison of the reverse recovery characteristic curves of the structure provided by this application and existing superjunction MOS devices;

[0034] Figure 7 This is a schematic diagram of the structure after step S1 of the superjunction MOS device fabrication method provided by the present invention is completed;

[0035] Figure 8 This is a schematic diagram of the structure after step S2 of the superjunction MOS device fabrication method provided by the present invention is completed;

[0036] Figure 9 This is a schematic diagram of the structure after step S3 of the superjunction MOS device fabrication method provided by the present invention is completed;

[0037] Figure 10 This is a schematic diagram of the structure after step S4 of the superjunction MOS device fabrication method provided by the present invention is completed;

[0038] Figure 11 This is a schematic diagram of the structure after step S5 of the superjunction MOS device fabrication method provided by the present invention is completed;

[0039] Figure 12 This is a schematic diagram of the structure after step S6 of the superjunction MOS device fabrication method provided by the present invention.

[0040] In the figure: 101, N+ substrate; 102, primary N-type epitaxy; 103, secondary N-type epitaxy; 104, JFET implantation region; 105, deep trench filled P-pillar region; 106, Pbody S-body implantation; 107, Pbody G-body implantation; 108, gate oxide layer; 109, polysilicon deposition; 110, N+ source implantation region; 111, dielectric layer; 112, front metal electrode; 113, back metal electrode.

[0041] 201, N+ substrate; 202, N-type epitaxy; 203, JFET implantation region; 204, deep trench filled P-pillar region; 205, Pbody implantation region; 206, gate oxide layer; 207, polysilicon deposition; 208, N+ source implantation region; 209, dielectric layer; 210, front metal electrode; 211, back metal electrode. Detailed Implementation

[0042] Example:

[0043] The following is in conjunction with the appendix Figure 1-12 The present invention will be described in further detail below.

[0044] A method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics, the steps of which are as follows:

[0045] S1. Prepare an N-type doped substrate to form an N+ substrate 101. Clean the substrate and grow a first N-type epitaxial layer and a second N-type epitaxial layer, forming a primary N-type epitaxial layer 102 and a secondary N-type epitaxial layer 103. The primary N-type epitaxial layer 102 and the secondary N-type epitaxial layer 103 are designed as two epitaxial layers with different resistivities, with the resistivity of the primary N-type epitaxial layer 102 being higher than that of the secondary N-type epitaxial layer 103. Due to the etching angle involved in the subsequent deep trench etching based on the two epitaxial layers, the trench width becomes narrower in deeper regions, and the width difference between the upper and lower trenches can reach 1.3 μm. The total charge of the P-pillars gradually decreases from top to bottom. By using a double-layer N-type epitaxial layer, the resistivity of the primary N-type epitaxial layer 102 at the bottom is greater than that of the secondary N-type epitaxial layer 103 at the top, resulting in... Figure 7 The device with the structure shown.

[0046] Specifically, an arsenic-doped N-type substrate with a resistivity of 0.002~0.003 Ω·cm is preferentially selected, and a first N-type epitaxial layer 102 is grown at a temperature of 1000℃. The doping element of the first N-type epitaxial layer 102 is phosphorus, the thickness is 42 μm, and the resistivity is 3.4 Ω·cm. Then, a second N-type epitaxial layer 103 is grown at a temperature of 1000℃. The doping element of the second N-type epitaxial layer 103 is phosphorus, the thickness is 33 μm, and the resistivity is 2.0 Ω·cm.

[0047] S2. Based on the secondary N-type epitaxy 103, a thin pre-oxide layer with a thickness of 200 μm is grown. The N-type JFET implantation region 104 is defined by photolithography. High-energy N-type impurity implantation is used to form the JFET implantation region 104 of the N-type planar gate MOS. The implantation angle is 7°, the implantation energy is 60 keV, and the implantation dose is 2e12cm. -2 After injection, the surface oxide layer is removed to obtain, as shown. Figure 8 The device with the structure shown.

[0048] S3. Continue wet etching of the chip to create deep trenches. The etching angle is 88.8°, the etching depth is 65μm, and the etching width is 5μm. After etching, perform P-pillar epitaxial filling to form a deep trench-filled P-pillar region 105. The epitaxial filler is boron, with a fill thickness of 65μm and a fill concentration of 4.2e15cm. -2 The depth, width, and P-pillar concentration of the superjunction MOSFET directly affect its breakdown voltage performance.

[0049] A sacrificial oxide layer was then grown on the surface at a temperature of 900℃, with a thickness of 1265 μm. The oxide layer was then completely removed using a CMP process to maintain a smooth surface, resulting in a product as shown. Figure 9 The device with the structure shown.

[0050] S4. Continue growing a thin pre-oxidized layer with a thickness of about 200 μm on the smooth surface at a growth temperature of 950 °C. Perform one high-dose, low-energy P-type main MOS body region implantation and one low-dose, low-energy P-type low-threshold auxiliary MOS body region implantation. Boron is preferred as the implanted impurity in the P-body region implantation 107. The implantation angle is 7°, the implantation energy is 60 keV, and the implantation dose is 6e12 / cm². 2 The impurity implanted in the Pbody S region was boron, with an implantation angle of 7°, an implantation energy of 80 keV, and an implantation dose of 4e12 / cm. 2 High-temperature push-bonding was used to form Pbody G region implantation 107 and Pbody S region implantation 106. The push-bonding temperature was 1100℃ and the push-bonding time was 180 min, resulting in the following: Figure 10 The device with the structure shown.

[0051] S5. After the active region is implanted and pushed together, a field oxide layer is thermally deposited on the chip surface at a temperature of 980°C and a thickness of 8000 μm. The active region is then etched.

[0052] After etching the active region, a gate oxide layer is grown. Preferably, the growth temperature of the gate oxide layer 108 is 1050℃, the growth thickness is 1000μm, and the growth time is 90min.

[0053] After the gate oxide layer is grown, polysilicon gate deposition is performed on the surface. The polysilicon gate region in the middle of each cell of the gate region is etched. The self-doping concentration of the polysilicon deposition layer is 4.3e20cm. -3 The oxide layer is 4000 μm thick. A Pbody G body region implantation 107 with a gate width of 2.7 μm and a Pbody S body region implantation 106 with a gate width of 1.5 μm are etched. The gate and source of the Pbody S body region implantation 106 are connected at the same potential, forming the gate of the Pbody G body region implantation 107 and the gate of the Pbody S body region implantation 106. The oxide layer is etched down to the remaining thickness of 200 μm to obtain the desired result. Figure 11 The device with the structure shown.

[0054] S6. Photolithographically define and implant the etched oxide layer to form an N+ source implantation region 110. The implantation target is arsenic ions, the implantation energy is 50keV, and the implantation dose is 5e15cm. -2 , ;

[0055] High-temperature bonding was carried out, and the annealing activation temperature was 950℃, and the annealing activation time was 30min.

[0056] Plasma-enhanced chemical vapor deposition was used to deposit and reflow ILD. The ILD interlayer dielectric thickness was 11200 μm, the dense reflow temperature was 900 °C, and the dense reflow time was 30 min.

[0057] Photolithography was used to define and etch the openings using a wet-plus-dry process, completing the metal deposition etching. After depositing a passivation layer, the lead area was photolithographically etched again. The opening size before metal deposition etching was 3 μm, and the hole filling conditions were boron difluoride at 1.25e15cm⁻¹. -2 / 40keV, boron 3.5e15cm -2 / 80keV, and perform rapid annealing for 15s;

[0058] A front metal electrode 112 is formed by depositing and etching surface dielectrics and organic materials, and a back metal electrode 113 is formed by metallizing the N+ substrate 101. A 4μm aluminum-copper alloy is deposited for the front metal electrode 112 and the back metal electrode is thinned to obtain the desired result. Figure 12 The device with the structure shown.

[0059] A 950V high-voltage superjunction MOS device with fast recovery characteristics obtained based on the above fabrication method, such as... Figure 1As shown, the device includes an N+ substrate 101. The N+ substrate 101 has a continuous primary N-type epitaxial layer 102 and a secondary N-type epitaxial layer 103 arranged sequentially with the front side facing upwards. A recessed JFET implantation region 104 is provided on the secondary N-type epitaxial layer 103. Deep trench-filled P-pillar regions 105 are respectively provided on both sides of the primary N-type epitaxial layer 102 and the secondary N-type epitaxial layer 103. PbodyS body region implantation 106 and PbodyG body region implantation 107 are respectively provided on the surface of the deep trench-filled P-pillar regions 105. PbodyG body region implantation 107 is the P-type body region implantation for the main MOS, and PbodyS body region implantation 106 is the P-type body region implantation for the low-threshold auxiliary MOS. The PbodyS body region implantation 106, PbodyG body region implantation 107, and the secondary N-type epitaxial layer 103 are connected together. The surface of the 03 has a gate oxide layer 108, on which a polysilicon deposition 109 is deposited. The polysilicon deposition 109 has an intermittent structure. The gate oxide layer 108 also has a recessed N+ source implantation region 110. The N+ source implantation regions 110 on both sides are correspondingly contacted by the PbodyS body region implantation 106 and the PbodyG body region implantation 107. The gate oxide layer 108 also has a dielectric layer 111, which covers the polysilicon deposition 109 and contacts the N+ source implantation region 110 and the JFET implantation region 104. The back side of the N+ substrate 101 has a back metal electrode 113, and the front side of the gate oxide layer 108 has a front metal electrode 112, which covers the dielectric layer 111 and contacts the N+ source implantation region 110. The PbodyS-region implanted 106 and PbodyG-region implanted 107 have the same structural proportions but different gate widths. The gate width of the PbodyS-region implanted 106 is 1.5 μm, and the gate width of the PbodyG-region implanted 107 is 2.7 μm. Specifically, an N-type epitaxial growth 102 and a secondary N-type epitaxial growth 103 are grown on an N-type substrate. After the second epitaxial growth, an N-type JFET implantation region 104 is formed by implantation. After deep trench etching and P-type epitaxial filling, a deep trench-filled P-pillar region 105 is formed. After sacrificial oxygen treatment, an activation PbodyS body region implantation 106 and a PbodyG body region implantation 107 are implanted onto the flat device surface. A gate oxide layer 108 is then grown. Polysilicon deposition 109 is deposited on the gate oxide layer 108. After oxide layer etching, an N+ source implantation region 110 is formed by implantation. An ILD is deposited and densely reflowed to form a dielectric layer 111. After via etching and via implantation, a front metal electrode 112 is formed. The back side is thinned and metallized to form a back metal electrode 113.

[0060] The total positive and negative charges of the two N-type epitaxial layers and the corresponding lower half of the P-pillar are approximately equal. The two epitaxial layers alleviate the charge imbalance problem caused by the etching angle of the P-pillar trench. The breakdown voltage of the superjunction MOS can be adjusted by changing the resistivity of the two epitaxial layers and the epitaxial concentration of the P-pillar.

[0061] The implantation dose and energy of 107 implanted in the PbodyG body region can adjust the threshold voltage of the main MOS, while the implantation dose and energy of 106 implanted in the PbodyS body region can adjust the threshold voltage of the low-threshold auxiliary MOS. The threshold voltage of the auxiliary MOS is lower than that of the main MOS. Since MOS is a unipolar device, it can greatly optimize the reverse recovery characteristics of the device. To prevent the auxiliary MOS from turning on erroneously when subjected to circuit interference, the implantation dose in the auxiliary MOS body region cannot be too low.

[0062] The polysilicon etching of the gate is for integrating an auxiliary low threshold voltage MOS structure. In this structure, a single polysilicon cell connects the source and gate on one side. While maintaining the same breakdown voltage, the resistance of the integrated auxiliary low threshold voltage MOS device increases slightly. This increase is equal to the resistance of the JFET injection region 104 accumulation layer, but it significantly optimizes the capacitance and diode characteristics of the 950V superjunction MOS device. The source electrode consists of a metal layer deposited on the device surface and a portion of the polysilicon source electrode. The drain electrode is formed beneath the N+ substrate 101, and the gate electrode is formed on another portion of the polysilicon gate electrode.

[0063] like Figure 3 As shown, the IV comparison curves of this application and the prior art are two-dimensional simulated line currents. The breakdown voltage of the device in this application is much higher than that of conventional superjunction MOSFETs. The two structures differ greatly in voltage magnitude. The breakdown voltage of conventional superjunction MOSFETs can only reach 980V, which cannot reach the required 1100V voltage level. This is mainly due to the single epitaxial superjunction MOSFET structure. Due to the deep trench etching angle problem, the charge is unbalanced, and the device cannot achieve charge balance as in the case of 90° etching.

[0064] like Figure 4 The figure shows a comparison of the threshold voltages of the 950V superjunction MOS in this application. The structure in this application integrates an auxiliary MOS with a low threshold voltage within the basic MOS. From... Figure 4 As can be seen, the threshold voltage of the auxiliary MOS is 1.3V, and the threshold voltage of the main MOS is 5.0V. Because the implantation dose and energy in the auxiliary MOS region are lower than those in the main MOS, their threshold voltages differ significantly. Adjusting the implantation in the main MOS region can adjust its threshold voltage; adjusting the implantation in the auxiliary MOS region can adjust the lower threshold voltage value. However, the implantation at the lower threshold voltage should not be too low to avoid device breakdown during reverse breakdown or external interference triggering the auxiliary MOS.

[0065] like Figure 5 The figure shows a comparison of Ciss-V characteristics between this application and existing structures. Due to the limitations of deep trench etching superjunction technology, the cells of existing structures are generally smaller, resulting in larger dynamic parameters such as capacitance and charge within the same area. Figure 5As can be seen from the above, the input voltage of the 950V superjunction MOS with fast recovery characteristics in this application is reduced to half of the original. This is mainly because the MOS structure in this application has a double epitaxial dummy structure superjunction MOS. The polysilicon gate is etched and connected to the source and gate respectively to form a dummy structure. The low threshold MOS is integrated into it by low energy and low dose implantation of some cells, which effectively optimizes the dynamic parameters of the device such as input capacitance and reverse transfer capacitance.

[0066] Figure 6 To compare the reverse recovery characteristics of the two structures, since the 950V superjunction MOS of this application has fast recovery characteristics and integrates a low threshold voltage, the internal current on the low threshold voltage side is mainly electron current due to the low injection dose and energy of the surface P-region, which is much smaller than the bipolar current in diode mode. Figure 6 As can be seen from the data, the reverse peak current and reverse recovery time of the structure in this application are optimized compared with those of traditional MOS. The reverse peak current is reduced by about 13% compared with traditional superjunction MOS, and the reverse recovery time and reverse recovery charge are also reduced accordingly.

[0067] Without sacrificing the core advantages of superjunction devices (low RDS(on) and high withstand voltage) at a voltage level of 950V, this method achieves synergistic optimization of the fast recovery characteristics of body diodes and system-level reliability. Through precise control of the internal carrier transport path and lifetime distribution, it overcomes the traditional three-way contradiction of "fast recovery performance - conduction loss - process cost," meeting the stringent requirements of high-density power electronic systems for high-frequency, high-efficiency, and high-robust power devices. Utilizing deep trench filling technology, through optimized structural design and manufacturing processes, it effectively reduces the minority carriers stored in the drift region of the superjunction MOS without affecting static parameters such as withstand voltage and threshold voltage, thereby reducing reverse recovery charge and reverse recovery time, lowering switching losses, and improving overall performance. Each cell contains two gates: a main MOS gate and an auxiliary MOS gate. Due to their different threshold voltages, the main MOS turns on during normal chip startup, while the auxiliary MOS gate turns on during reverse recovery. Since MOS devices are unipolar devices, this significantly reduces the reverse recovery time of the superjunction MOS, achieving low dynamic characteristics.

[0068] Compared to traditional deep-trench-filled superjunction MOS structures, this method improves upon the shortcomings of unstable breakdown voltage and inability to further increase breakdown voltage in high-voltage applications. It integrates a low-threshold voltage auxiliary MOS by etching and separating the polysilicon gate and implanting P-type body regions with different doses and energies on both sides of the cell. Since the MOS device is a unipolar device and the auxiliary MOS side has a low concentration, this measure optimizes the reverse recovery characteristics of the 950V superjunction device diode. By simply adjusting the concentration of the first and second N-type pillar epitaxial layers to maintain charge balance with the P-pillars, deep-trench-filled high-voltage superjunction MOS devices with controllable breakdown voltages, exceeding 950V up to 1150V, can be manufactured. Simultaneously, by etching and separating the polysilicon gate in the active region and adjusting the process parameters for low-threshold auxiliary MOS implantation, a near-doubly reduction in input capacitance and Miller capacitance, along with superior reverse recovery characteristics, can be achieved without affecting the breakdown voltage and on-resistance.

[0069] It should be noted that this specific embodiment is merely an explanation of the present invention and is not intended to limit the present invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A 950V high-voltage superjunction MOS device with fast recovery characteristics, characterized in that: The system includes an N+ substrate. On the N+ substrate, facing upwards, are sequentially formed primary and secondary N-type epitaxial layers. A recessed JFET implantation region is located on the secondary N-type epitaxial layer. Deep trench-filled P-pillar regions are located on both sides of the primary and secondary N-type epitaxial layers. The surfaces of these deep trench-filled P-pillar regions are respectively equipped with low-dose, low-energy PbodyS body region implantation and high-dose, low-energy PbodyG body region implantation. The PbodyG body region implantation serves as the P-type body region implantation for the main MOS, while the PbodyS body region implantation is a low-threshold implantation. The auxiliary MOS has a P-type body region implantation, a gate oxide layer on the PbodyS body region implantation, a PbodyG body region implantation and a secondary N-type epitaxial surface, a polysilicon deposition on the gate oxide layer with a discontinuous structure, a recessed N+ source implantation region on the gate oxide layer, and the two N+ source implantation regions on both sides correspondingly contacting the PbodyS body region implantation and the PbodyG body region implantation. A dielectric layer is also provided on the gate oxide layer, which covers the polysilicon deposition and contacts the N+ source implantation region and the JFET implantation region. A back metal electrode is provided on the back side of the N+ substrate, and a front metal electrode is provided on the front side of the gate oxide layer. The front metal electrode covers the dielectric layer and contacts the N+ source injection region. The gate and source injected into the PbodyS body region are connected and at the same potential.

2. The 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 1, characterized in that: The PbodyS-body region implantation and PbodyG-body region implantation have the same structural ratio but different gate widths.

3. The 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 2, characterized in that: The gate width implanted in the PbodyS body region is 1.5 μm, and the gate width implanted in the PbodyG body region is 2.7 μm.

4. A method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics, characterized in that: The steps are as follows: S1. Prepare an N+ substrate, and sequentially grow a first N-type epitaxial growth and a second N-type epitaxial growth on the N+ substrate; S2. A thin pre-oxidation layer is grown on the secondary N-type epitaxy, and N-type JFET implantation is performed to form the JFET implantation region. The thin pre-oxidation layer is then removed. S3. Perform deep trench etching and P-type epitaxial filling on the primary N-type epitaxial layer and the secondary N-type epitaxial layer to form P-pillars. Grow a sacrificial oxide layer on the surface and remove it completely to maintain a smooth surface. S4. A thin pre-oxidized layer is grown on a flat surface, and a high-dose, low-energy P-type main MOS body region implantation and a low-dose, low-energy P-type low-threshold auxiliary MOS body region implantation are performed. High-temperature push junction is then formed to form PbodyG body region implantation and PbodyS body region implantation. S5. A field oxide layer is thermally deposited on the surface, and the active region is etched. A gate oxide layer is grown in the active region, and gate polysilicon is deposited to form polysilicon deposition. The gate is etched and separated to form the gate implanted in the PbodyG body region and the gate implanted in the PbodyS body region. The gate and source injected into the PbodyS body region are connected and at the same potential; S6. Etch the gate oxide layer and implant to form the N+ source implantation region, activate the source, deposit and reflow the ILD, open the hole to complete the metal deposition and etching, form the front metal electrode, and metallize the N+ substrate on the back to form the back metal electrode.

5. The method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 4, characterized in that: In step S1, the resistivity of the primary N-type epitaxy and the secondary N-type epitaxy are different. In step S2, the thickness of the thin pre-oxidation layer is 200 Å, and the implantation condition of the JFET implantation region is 2e12cm. -2 / 60keV.

6. The method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 4, characterized in that: In step S3, the deep trench etching is performed using wet etching. The etched area has a trench depth of 65 μm, a trench width of 5 μm, an etching angle of 88.8°, and a P-type epitaxial fill concentration of 4.2e15cm. -2 .

7. The method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 4, characterized in that: In step S4, the injection condition for the PbodyG body region is 6e13cm. -2 The injection conditions for Pbody S-section were 60 keV and 4e13 cm. -2 / 80keV.

8. The method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 7, characterized in that: In step S4, the thickness of the thin pre-oxidized layer is 200 angstroms, the bonding conditions are 1100℃, and the bonding time is 180 min.

9. The method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 4, characterized in that: In step S5, the ambient temperature for surface thermal deposition is 980℃, and the thickness of the field oxide layer is 8000 Å; the growth temperature of the gate oxide layer is 1050℃, the growth thickness is 1000 Å, and the growth time is 90 min; the self-doping concentration of the polysilicon deposition is 4.3e20cm. -3 The thickness is 4000 angstroms; the polysilicon gate region in the middle of each cell of the gate region is etched to etch out a Pbody G body region implantation with a gate width of 2.7 μm and a Pbody S body region implantation with a gate width of 1.5 μm.

10. The method for fabricating a 950V high-voltage superjunction MOS device with fast recovery characteristics according to claim 4, characterized in that: In step S6, the remaining thickness of the gate oxide layer after etching is 200 Å; the source implantation activation condition is 5e15cm of arsenic ions. -2 / 50keV, followed by high-temperature push-bonding annealing at 950℃ for 30 min; ILD interlayer dielectric thickness of 11200 Å, dense reflow temperature of 900℃, and dense reflow time of 30 min; pre-etching aperture size of 3 μm, and hole filling conditions of boron difluoride 1.25e15cm. -2 / 40keV or boron 3.5e15cm -2 The metal is heated to 80 keV and subjected to rapid annealing for 15 seconds; a 4 μm aluminum-copper alloy front metal electrode and a back metal electrode are deposited.

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