Embedded silicon germanium epitaxial layer structure and manufacturing method thereof
By forming a SiGe seed layer, amorphous layer, and host layer with specific germanium concentrations on the inner wall of the groove in a semiconductor substrate, the dislocation problem caused by high germanium concentration is solved, and the carrier mobility and driving capability of the PMOS device are improved.
Patent Information
- Application Number
- CN202510991765.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-17
- Publication Date
- 2025-10-28
AI Technical Summary
In the prior art, embedded silicon-germanium epitaxial layers are prone to dislocation defects at high germanium concentrations, which obstructs carrier migration paths and affects the driving capability of the device.
A SiGe seed layer, an amorphous layer, and a host layer are formed on the inner wall of a groove in a semiconductor substrate using selective epitaxial growth. The germanium concentration is controlled to be in the range of 15% to 55%, and an amorphous or polycrystalline structure without preferred orientation is formed on the surface of the SiGe amorphous layer to suppress the formation of {111} plane dislocations.
It effectively reduces dislocation defects caused by high germanium concentration, and improves the carrier mobility and driving capability of PMOS devices.
Smart Images
Figure CN120857576A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology and relates to an embedded silicon-germanium epitaxial layer structure and its fabrication method. Background Technology
[0002] Embedded silicon Germanium (eSiGe) technology is a technique that embeds SiGe material into the source and drain regions of a PMOS transistor. By embedding SiGe material in the source and drain regions of the PMOS transistor, compressive stress can be applied to the channel region, thereby improving the carrier mobility in the channel region and enhancing device performance. Currently, forming an embedded silicon Germanium epitaxial layer structure includes the following steps:
[0003] (1) As Figure 1 As shown, the semiconductor substrate 1 located on both sides of the gate structure 2 is etched to form a groove 4;
[0004] (2) Figure 2 As shown, a low-germanium SiGe seed layer 5 is formed on the inner wall of the groove 4;
[0005] (3) Figure 3 As shown, a high-germanium SiGe host layer 7 is formed on the surface of the SiGe seed layer 5;
[0006] (4) Figure 4 As shown, a capping layer 8 is formed on the SiGe main body layer 7.
[0007] To achieve higher carrier mobility, a higher germanium content is required. However, there is a 4.17% lattice constant difference between silicon and germanium. During growth, strain accumulates due to the high germanium content. When the critical thickness is reached (dislocations occur when the strained layer exceeds a certain thickness during growth; this thickness is called the critical thickness), mismatch dislocations will be generated to release this strain. Molecular dynamics simulations show that the release of mismatch stress in the SiGe / Si structure is mainly achieved by generating 60-degree sliding dislocations on the {111} plane. The high-germanium-content SiGe host layer 7 is most likely to form dislocation lines 9 on the {111} plane. Figure 3 (As shown). Dislocations can disrupt the integrity of a crystal. Lattice distortions around dislocations can create local stress fields, leading to changes in the band structure. This energy gradient can scatter charge carriers, hindering their migration paths and thus reducing the device's driving capability.
[0008] Therefore, how to provide an embedded silicon-germanium epitaxial layer structure and fabrication method to reduce dislocation defects caused by high germanium concentration and improve carrier mobility has become a technical problem that urgently needs to be solved by those skilled in the art.
[0009] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0010] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an embedded silicon-germanium epitaxial layer structure and fabrication method to solve the problem that dislocations occur in the silicon-germanium epitaxial layer in the prior art, which obstructs the carrier migration path.
[0011] To achieve the above and other related objectives, the present invention provides a method for fabricating an embedded silicon-germanium epitaxial layer structure, comprising the following steps:
[0012] A semiconductor substrate is provided, wherein a groove is formed at a predetermined position on the semiconductor substrate;
[0013] A SiGe seed layer is formed on the inner wall of the groove, wherein the germanium concentration in the SiGe seed layer is 15% to 25%.
[0014] An amorphous SiGe layer is formed on the surface of the SiGe seed layer. The amorphous SiGe layer is a P-type doped SiGe layer, and the germanium concentration in the amorphous SiGe layer is 55% to 75%.
[0015] A SiGe host layer without crystal planes is formed on the surface of the SiGe amorphous layer. The SiGe host layer is a P-type doped SiGe layer. The germanium concentration in the SiGe host layer is 35% to 55%. The SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer together fill the groove.
[0016] A capping layer is formed on the SiGe main body layer.
[0017] Optionally, the SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer are formed using selective epitaxial growth.
[0018] Optionally, the thickness of the SiGe amorphous layer ranges from 3 nm to 8 nm.
[0019] Optionally, the process temperature for forming the SiGe seed layer is 600℃~800℃, and the pressure is 20 torr~80 torr;
[0020] The process temperature for forming the SiGe amorphous layer is 550℃~700℃, and the pressure is 100 torr~150 torr.
[0021] The process temperature for forming the SiGe host layer is 600℃~700℃, and the pressure is 20 torr~80 torr.
[0022] Optionally, the P-type doped ions include B ions.
[0023] Optionally, a gate structure is formed on the semiconductor substrate, and the groove is located in the semiconductor substrate on both sides of the gate structure.
[0024] The present invention also provides an embedded silicon-germanium epitaxial layer structure, comprising:
[0025] A semiconductor substrate, wherein a groove is provided at a predetermined position on the semiconductor substrate;
[0026] A SiGe seed layer is located on the inner wall of the groove, and the germanium concentration in the SiGe seed layer is 15% to 25%.
[0027] An amorphous SiGe layer is located on the surface of the SiGe seed layer. The amorphous SiGe layer is a P-type doped SiGe layer, and the germanium concentration in the amorphous SiGe layer is 55% to 75%.
[0028] A SiGe host layer is located on the surface of the SiGe amorphous layer. The SiGe host layer is a P-type doped SiGe layer. The germanium concentration in the SiGe host layer is 35% to 55%. The SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer together fill the groove.
[0029] A capping layer is located on the SiGe body layer.
[0030] Optionally, the thickness of the SiGe amorphous layer ranges from 3 nm to 8 nm.
[0031] Optionally, the P-type doped ions include B ions.
[0032] Optionally, the semiconductor substrate has a gate structure, and the groove is located in the semiconductor substrate on both sides of the gate structure.
[0033] As described above, in the embedded silicon-germanium epitaxial layer structure and fabrication method of the present invention, an amorphous SiGe layer is formed on the surface of the SiGe seed layer. Since the amorphous SiGe layer does not have an ordered structure, when the SiGe main body layer is grown on the SiGe amorphous layer as a substrate, it cannot provide clear lattice guidance for the SiGe main body layer, resulting in random distribution of nucleation sites and ultimately forming an amorphous or polycrystalline structure without preferred orientation. This suppresses the formation of {111} planes in the SiGe main body layer, reduces dislocation defects caused by high germanium concentration while maintaining high stress in the silicon-germanium epitaxial layer, and effectively improves the carrier mobility and driving capability of the PMOS device. Attached Figure Description
[0034] Figures 1 to 4 The diagram shows cross-sectional views of various stages in a method for fabricating an embedded silicon-germanium epitaxial layer structure.
[0035] Figure 5 The diagram shows a flowchart of the fabrication method of the embedded silicon-germanium epitaxial layer structure in an embodiment of the present invention.
[0036] Figures 6 to 10 The diagram shows cross-sectional views of each stage in the fabrication method of the embedded silicon-germanium epitaxial layer structure in an embodiment of the present invention.
[0037] Component designation explanation
[0038] 1 Semiconductor substrate
[0039] 2 Gate Structure
[0040] 3 side walls
[0041] 4 grooves
[0042] 5 SiGe seed layer
[0043] 6 SiGe amorphous layer
[0044] 7 SiGe main layer
[0045] 8. Cap layer
[0046] 9 misaligned lines
[0047] Steps S1 to S5 Detailed Implementation
[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0049] Please see 5 to Figure 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0050] This embodiment provides a method for fabricating an embedded silicon-germanium epitaxial layer structure. Please refer to [link to relevant documentation]. Figure 5The method for fabricating the embedded silicon-germanium epitaxial layer structure includes the following steps:
[0051] S1: A semiconductor substrate is provided, wherein a groove is formed at a predetermined position on the semiconductor substrate;
[0052] S2: A SiGe seed layer is formed on the inner wall of the groove, wherein the germanium concentration in the SiGe seed layer is 15% to 25%;
[0053] S3: An amorphous SiGe layer is formed on the surface of the SiGe seed layer. The amorphous SiGe layer is a P-type doped SiGe layer, and the germanium concentration in the amorphous SiGe layer is 55% to 75%.
[0054] S4: A SiGe host layer without crystal planes is formed on the surface of the SiGe amorphous layer. The SiGe host layer is a P-type doped SiGe layer. The germanium concentration in the SiGe host layer is 35% to 55%. The SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer together fill the groove.
[0055] S5: A capping layer is formed on the SiGe main body layer.
[0056] The fabrication method of the embedded silicon-germanium epitaxial layer structure in this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0057] First, please refer to Figure 6 Step S1: Provide a semiconductor substrate 1, wherein a groove 4 is formed at a predetermined position on the semiconductor substrate 1.
[0058] As an example, the semiconductor substrate 1 can be any suitable substrate. In this embodiment, the semiconductor substrate 1 is a silicon substrate with a
[100] crystal orientation; the lattice constant of silicon (Si) is The lattice constant of germanium (Ge) is The mismatch rate between silicon and germanium is 4.17%. The lattice constant of the subsequently formed silicon-germanium layer is greater than that of silicon, so as to generate compressive stress on the channel region of the device.
[0059] As an example, a gate structure 2 is formed on the semiconductor substrate 1, and the semiconductor substrate 1 below the gate structure 2 serves as the channel region of the device. A sidewall 3 is formed on the side of the gate structure 2. In another example, the sidewall 3 may not be provided on the side of the gate structure 2, depending on the requirements.
[0060] As an example, the groove 4 is located in the semiconductor substrate 1 on both sides of the gate structure 2, that is, the groove 4 is located in the source region and drain region of the device, and the subsequently formed silicon-germanium layer is located in the source region and drain region of the device.
[0061] As an example, the groove 4 is a Sigma-type groove, that is, the groove 4 has a small opening and bottom size and a large middle size, which makes the subsequently formed silicon-germanium layer closer to the channel region, and can more effectively transfer the compressive stress to the channel region and reduce stress loss.
[0062] Next, please refer to Figure 7 Step S2: A SiGe seed layer 5 is formed on the inner wall of the groove 4, wherein the germanium concentration in the SiGe seed layer 5 is 15% to 25%.
[0063] As an example, the SiGe seed layer 5 serves as a buffer layer, and the low germanium concentration is used to prevent lattice mismatch between the SiGe seed layer 5 and the semiconductor substrate 1. Since no lattice mismatch occurs between the SiGe seed layer 5 and the semiconductor substrate 1, the long-range ordered semiconductor substrate 1 provides clear lattice guidance for the SiGe seed layer 5, resulting in a SiGe seed layer 5 with crystal planes.
[0064] As an example, in the SiGe seed layer 5, the germanium concentration is the atomic percentage of germanium atoms relative to the total number of germanium and silicon atoms.
[0065] As an example, during the formation of the SiGe seed layer 5, the silicon source includes, but is not limited to, silane (SiH4), dichlorosilane (DCS), etc., and the germanium source includes germanane (GeH4), etc. The process temperature is 600℃~800℃ and the pressure is 20 torr~80 torr.
[0066] As an example, the SiGe seed layer 5 is formed using selective epitaxial growth. Before forming the SiGe seed layer 5, the non-Si regions can be surface passivated, such as by H2 annealing or fluorine-based plasma treatment, to eliminate surface active sites. This makes it more difficult for epitaxial precursor molecules to adsorb onto the oxide / nitride sidewall surfaces, inhibiting the deposition of epitaxial material on the sidewalls, so that the SiGe seed layer 5 is formed only on the inner wall of the groove 4. Furthermore, during the growth process, an in-situ etching gas (such as HCl) can be introduced simultaneously to dynamically remove possible nucleation sites in the non-Si regions, thus avoiding nucleation in non-silicon regions.
[0067] Next, please refer to Figure 8 Step S3: Form a SiGe amorphous layer 6 on the surface of the SiGe seed layer 5. The SiGe amorphous layer 6 is a P-type doped SiGe layer, and the germanium concentration in the SiGe amorphous layer 6 is 55% to 75%.
[0068] As an example, the germanium concentration in the SiGe amorphous layer 6 is 55% to 75%, while the germanium concentration in the SiGe seed layer 5 is 15% to 25%. The lattice difference between the two is huge, which will increase lattice mismatch and stress during the formation of the SiGe amorphous layer 6, leading to structural instability and non-uniform nucleation, thereby forming the amorphous SiGe amorphous layer 6.
[0069] As an example, the dopant ion of the P-type dopant is boron (B), that is, the SiGe amorphous layer 6 is a B-doped SiGe layer.
[0070] As an example, during the formation of the SiGe amorphous layer 6, the silicon source includes, but is not limited to, silane (SiH4), dichlorosilane (DCS), etc., and the germanium source includes, but is not limited to, germanane (GeH4), etc. Simultaneously, a doping gas, borane (B2H6), is introduced to directly incorporate B atoms into the SiGe, achieving high-concentration in-situ doping. In this embodiment, the B doping concentration is not less than 3 × 10⁻⁶. 21 atoms / cm 3 .
[0071] As an example, the process temperature for forming the SiGe amorphous layer 6 is 550℃~700℃, and the pressure is 100torr~150torr. That is, compared with the SiGe seed layer 5, the SiGe amorphous layer 6 has a relatively low process temperature, a relatively high pressure, and a relatively high doping concentration, which is conducive to the formation of the amorphous SiGe amorphous layer 6.
[0072] As an example, in the SiGe amorphous layer 6, the germanium concentration is the atomic percentage of germanium atoms relative to the total number of germanium atoms, silicon atoms, and boron atoms.
[0073] As an example, the SiGe amorphous layer 6 is formed using selective epitaxial growth, meaning that the SiGe amorphous layer 6 is formed only on the surface of the SiGe seed layer 5, and is not deposited on the sidewalls 3. Furthermore, during the growth process, an in-situ etching gas (such as HCl) can be introduced simultaneously to dynamically remove potential nucleation sites in non-Si regions, thus avoiding nucleation in non-silicon regions.
[0074] As an example, the thickness of the SiGe amorphous layer 6 is 3nm to 8nm, for example, it can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, etc., and can be selected according to the requirements.
[0075] Next, please refer to Figure 9Step S4: A SiGe host layer 7 without crystal planes is formed on the surface of the SiGe amorphous layer 6. The SiGe host layer 7 is a P-type doped SiGe layer. The germanium concentration in the SiGe host layer 7 is 35% to 55%. The SiGe seed layer 5, the SiGe amorphous layer 6 and the SiGe host layer 7 together fill the groove 4.
[0076] As an example, based on the process window for growth defects and cost considerations, the germanium concentration in the SiGe host layer 7 is set to 35% to 55%, which can apply high stress to the channel without causing process defects due to excessive germanium concentration.
[0077] As an example, since the SiGe amorphous layer 6 is amorphous and lacks a long-range ordered structure, it cannot provide clear lattice guidance for the SiGe main layer 7, resulting in random distribution of nucleation sites and ultimately forming an amorphous or polycrystalline structure without preferred orientation. This suppresses the formation of {111} planes in the SiGe main layer 7, reduces dislocation defects caused by high germanium concentration, and effectively improves the carrier mobility and driving capability of the PMOS device.
[0078] As an example, the SiGe host layer 7 is a boron-doped SiGe layer. During the formation of the SiGe host layer 7, the silicon source includes, but is not limited to, silane (SiH4), dichlorosilane (DCS), etc., and the germanium source includes, but is not limited to, germanane (GeH4), etc. Simultaneously, a doping gas, borane (B2H6), is introduced to directly incorporate boron atoms into the SiGe, achieving high-concentration in-situ doping. In this embodiment, the boron doping concentration is not less than 3 × 10⁻⁶. 21 atoms / cm 3 .
[0079] As an example, the process temperature for forming the SiGe host layer 7 is 600℃~700℃, and the pressure is 20 torr~80 torr.
[0080] As an example, in the SiGe host layer 7, the germanium concentration is the atomic percentage of germanium atoms relative to the total number of germanium, silicon, and boron atoms.
[0081] As an example, the SiGe host layer 7 is formed using selective epitaxial growth, meaning that the SiGe host layer 7 is formed only on the surface of the SiGe amorphous layer 6, and is not deposited on the sidewalls 3. Furthermore, during the growth process, an in-situ etching gas (such as HCl) can be introduced simultaneously to dynamically remove possible nucleation sites in non-Si regions, thus avoiding nucleation in non-silicon regions.
[0082] As an example, the SiGe amorphous layer 6 and the SiGe host layer 7 are located in the source and drain regions of the device. By doping the SiGe amorphous layer 6 and the SiGe host layer 7 with a high concentration of B, the source and drain resistance is reduced.
[0083] Next, please refer to Figure 10 Step S5: Form a capping layer 8 on the SiGe main body layer 7.
[0084] As an example, the capping layer 8 is made of silicon, and the capping layer 8 also covers the SiGe amorphous layer 6 and the SiGe seed layer 5.
[0085] As an example, a capping layer 8 is formed on the SiGe host layer 7. On the one hand, it can protect the SiGe host layer 7 and prevent stress release, thereby keeping the SiGe host layer 7 under compressive stress and improving device performance. On the other hand, in the subsequent silicide process, the capping layer 8 can react with metals such as nickel (Ni) to generate low-resistance nickel silicide (NiSi), which helps to reduce the contact resistance of the source and drain regions.
[0086] In this embodiment, by forming the SiGe amorphous layer 6 on the surface of the SiGe seed layer 5, since the SiGe amorphous layer 6 does not have an ordered structure, when the SiGe main body layer 7 is grown on the SiGe amorphous layer 6 as a substrate, it cannot provide clear lattice guidance for the SiGe main body layer 7, resulting in random distribution of nucleation sites and ultimately forming an amorphous or polycrystalline structure without preferred orientation. This suppresses the formation of {111} planes in the SiGe main body layer 7, reduces dislocation defects caused by high germanium concentration while maintaining high stress in the silicon-germanium epitaxial layer, and effectively improves the carrier mobility and driving capability of the PMOS device.
[0087] Thus, an embedded silicon-germanium epitaxial layer structure has been fabricated. Please refer to [link / reference]. Figure 10The embedded silicon-germanium epitaxial layer structure includes a semiconductor substrate 1, a SiGe seed layer 5, a SiGe amorphous layer 6, a SiGe body layer 7, and a capping layer 8. A groove is provided at a predetermined position on the semiconductor substrate 1. The SiGe seed layer 5 is located on the inner wall of the groove, and the germanium concentration in the SiGe seed layer 5 is 15%–25%. The SiGe amorphous layer 6 is located on the surface of the SiGe seed layer, and the SiGe amorphous layer is a P-type doped SiGe layer with a germanium concentration of 55%–75%. The SiGe body layer 7 is located on the surface of the SiGe amorphous layer 6, and the SiGe body layer 7 is a P-type doped SiGe layer with a germanium concentration of 35%–55%. The SiGe seed layer 5, the SiGe amorphous layer 6, and the SiGe body layer 7 together fill the groove. The capping layer 8 is located on the SiGe body layer 7.
[0088] As an example, the semiconductor substrate 1 can be any suitable substrate. In this embodiment, the semiconductor substrate 1 is a silicon substrate.
[0089] As an example, a gate structure 2 is provided on the semiconductor substrate 1, and the semiconductor substrate 1 below the gate structure 2 serves as the channel region of the device. The sidewalls 3 are provided on the side of the gate structure 2. In another example, the sidewalls 3 may not be provided on the side of the gate structure 2, depending on the requirements.
[0090] As an example, the groove is located in the semiconductor substrate 1 on both sides of the gate structure 2, that is, the groove 4 is located in the source region and drain region of the device.
[0091] As an example, the groove 4 is a Sigma-type groove, that is, the groove 4 has a shape with a small opening and bottom size and a large middle size.
[0092] As an example, the germanium concentration in the SiGe seed layer 5 is 15% to 25%. The SiGe seed layer 5 serves as a buffer layer, and the low germanium concentration is used to prevent lattice mismatch between the SiGe seed layer 5 and the semiconductor substrate 1.
[0093] As an example, in the SiGe seed layer 5, the germanium concentration is the atomic percentage of germanium atoms relative to the total number of germanium and silicon atoms.
[0094] As an example, the germanium concentration in the SiGe amorphous layer 6 is 55% to 75%, while the germanium concentration in the SiGe seed layer 5 is 15% to 25%. The huge difference in lattice between the two will increase lattice mismatch and stress, leading to structural instability and inducing non-uniform nucleation, thereby forming the amorphous SiGe amorphous layer 6.
[0095] As an example, the dopant ion of the P-type dopant is boron (B), that is, the SiGe amorphous layer 6 is a B-doped SiGe layer.
[0096] As an example, in the SiGe amorphous layer 6, the germanium concentration is the atomic percentage of germanium atoms relative to the total number of germanium atoms, silicon atoms, and boron atoms.
[0097] As an example, the thickness of the SiGe amorphous layer 6 is 3nm to 8nm, for example, it can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, etc., and can be selected according to the requirements.
[0098] As an example, the germanium concentration in the SiGe host layer 7 is 35% to 55%, and the SiGe host layer 7 has an amorphous or polycrystalline structure, which reduces dislocation defects caused by high germanium concentration and effectively improves the carrier mobility and driving capability of PMOS devices.
[0099] As an example, the SiGe host layer 7 is a B-doped SiGe layer, and in the SiGe host layer 7, the germanium concentration is the atomic percentage of germanium atoms relative to the total number of germanium atoms, silicon atoms, and boron atoms.
[0100] As an example, the capping layer 8 is made of silicon, and the capping layer 8 also covers the SiGe amorphous layer 6 and the SiGe seed layer 5.
[0101] In summary, the embedded silicon-germanium epitaxial layer structure and fabrication method of the present invention, by forming an amorphous SiGe layer on the surface of a SiGe seed layer, and because the amorphous SiGe layer lacks an ordered structure, when growing the SiGe main body layer using the amorphous SiGe layer as a substrate, it cannot provide clear lattice guidance for the SiGe main body layer, resulting in random distribution of nucleation sites and ultimately forming an amorphous or polycrystalline structure without preferred orientation. This suppresses the formation of {111} planes in the SiGe main body layer, and while maintaining high stress in the silicon-germanium epitaxial layer, it reduces dislocation defects caused by high germanium concentration, effectively improving the carrier mobility and driving capability of the PMOS device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0102] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating an embedded silicon-germanium epitaxial layer structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein a groove is formed at a predetermined position on the semiconductor substrate; A SiGe seed layer is formed on the inner wall of the groove, wherein the germanium concentration in the SiGe seed layer is 15% to 25%. An amorphous SiGe layer is formed on the surface of the SiGe seed layer. The amorphous SiGe layer is a P-type doped SiGe layer, and the germanium concentration in the amorphous SiGe layer is 55% to 75%. A SiGe host layer without crystal planes is formed on the surface of the SiGe amorphous layer. The SiGe host layer is a P-type doped SiGe layer. The germanium concentration in the SiGe host layer is 35% to 55%. The SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer together fill the groove. A capping layer is formed on the SiGe main body layer.
2. The method for fabricating an embedded silicon-germanium epitaxial layer structure according to claim 1, characterized in that: The SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer are formed by selective epitaxial growth.
3. The method for fabricating an embedded silicon-germanium epitaxial layer structure according to claim 1, characterized in that: The thickness of the SiGe amorphous layer ranges from 3 nm to 8 nm.
4. The method for fabricating an embedded silicon-germanium epitaxial layer structure according to claim 1, characterized in that: The process temperature for forming the SiGe seed layer is 600℃~800℃, and the pressure is 20 torr~80 torr; The process temperature for forming the SiGe amorphous layer is 550℃~700℃, and the pressure is 100 torr~150 torr. The process temperature for forming the SiGe host layer is 600℃~700℃, and the pressure is 20 torr~80 torr.
5. The method for fabricating an embedded silicon-germanium epitaxial layer structure according to claim 1, characterized in that, The P-type doped ions include B ions.
6. The method for fabricating an embedded silicon-germanium epitaxial layer structure according to claim 1, characterized in that: A gate structure is formed on the semiconductor substrate, and the groove is located in the semiconductor substrate on both sides of the gate structure.
7. An embedded silicon-germanium epitaxial layer structure, characterized in that, include: A semiconductor substrate, wherein a groove is provided at a predetermined position on the semiconductor substrate; A SiGe seed layer is located on the inner wall of the groove, and the germanium concentration in the SiGe seed layer is 15% to 25%. An amorphous SiGe layer is located on the surface of the SiGe seed layer. The amorphous SiGe layer is a P-type doped SiGe layer, and the germanium concentration in the amorphous SiGe layer is 55% to 75%. A SiGe host layer is located on the surface of the SiGe amorphous layer. The SiGe host layer is a P-type doped SiGe layer. The germanium concentration in the SiGe host layer is 35% to 55%. The SiGe seed layer, the SiGe amorphous layer, and the SiGe host layer together fill the groove. A capping layer is located on the SiGe body layer.
8. The embedded silicon-germanium epitaxial layer structure according to claim 7, characterized in that: The thickness of the SiGe amorphous layer ranges from 3 nm to 8 nm.
9. The embedded silicon-germanium epitaxial layer structure according to claim 7, characterized in that: The P-type doped ions include B ions.
10. The embedded silicon-germanium epitaxial layer structure according to claim 7, characterized in that: The semiconductor substrate has a gate structure, and the groove is located in the semiconductor substrate on both sides of the gate structure.