Semiconductor element and method for manufacturing the same

Abstract

The disclosure provides a semiconductor device and a method for manufacturing the same. A method includes forming a fin on a substrate; forming a gate on the fin, wherein the sidewall spacer is laterally adjacent to the gate; removing an upper portion of the sidewall spacer; forming a cavity by removing a selected section of the gate and removing a selected fin below the selected section; and forming an insulating feature in the cavity.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing it. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using lithography to pattern the material layers to form circuit elements and components on them.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, and capacitors) by constantly shrinking the smallest feature size, enabling more components to be integrated into specific areas. However, with the shrinking of the smallest feature size, more problems have also arisen that need to be solved. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor device comprising: forming a fin on a substrate; forming a gate on the fin, wherein sidewall spacers are laterally adjacent to the gate; removing the upper portion of the sidewall spacers; forming a cavity by removing a selected segment of the gate and removing a selected fin located below the selected segment; and forming an insulating feature in the cavity.

[0005] This disclosure provides a method for manufacturing a semiconductor device comprising: forming a fin over a substrate; forming a gate over the fin; forming a source / drain feature in the fin adjacent to the gate; forming an interlayer dielectric (ILD) structure over the source / drain feature, wherein the ILD structure comprises silicon oxide; removing a region comprising a portion of the fin and a portion of the gate to form an opening; forming an insulating feature in the opening; and performing a process of etching a selected ILD structure to the underlying source / drain feature, wherein during the process, the semiconductor device is free of silicon oxide at the insulating feature and on the exposed surface adjacent to the insulating feature.

[0006] This disclosure provides a semiconductor device comprising a fin, source / drain features, and an insulating feature. The fin is located above a substrate. The source / drain features are located in grooves formed in the fin. The insulating feature is located between the source / drain features and extends through the fin and into the substrate, wherein the insulating feature has a top surface, and wherein on the top surface, the insulating feature is in contact with a non-oxide dielectric layer. Attached Figure Description

[0007] When with attachment Figure 1 For the best understanding of all aspects of this disclosure, please refer to the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion.

[0008] Figure 1 A flowchart illustrating a method according to certain implementations;

[0009] Figure 2 To illustrate a semiconductor element according to certain embodiments;

[0010] Figure 3 To illustrate, according to certain embodiments, in Figure 1 A perspective diagram of the components in the continuous stages of the manufacturing process;

[0011] Figure 4 To illustrate, according to certain embodiments, in Figure 1 A perspective diagram of the components in the continuous stages of the manufacturing process;

[0012] Figure 5 To illustrate, according to certain embodiments, in Figure 1 A perspective diagram of the components in the continuous stages of the manufacturing process;

[0013] Figure 6 To illustrate, according to certain embodiments, in Figure 1 A perspective diagram of the components in the continuous stages of the manufacturing process;

[0014] Figure 7 To illustrate, according to certain embodiments, in Figure 1 A perspective diagram of the components in the continuous stages of the manufacturing process;

[0015] Figure 8 To illustrate, according to certain embodiments, in Figure 1 A perspective diagram of the components in the continuous stages of the manufacturing process;

[0016] Figure 9 To draw elements in Figure 8 A cross-sectional schematic diagram of the X-section of the manufacturing process;

[0017] Figure 10 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the apparatus during the continuous stages of the manufacturing process of the method;

[0018] Figure 11 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the apparatus during the continuous stages of the manufacturing process of the method;

[0019] Figure 12 To illustrate, according to certain embodiments, in Figure 1A schematic cross-sectional view of the X-section of the apparatus during the continuous stages of the manufacturing process of the method;

[0020] Figure 13 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the apparatus during the continuous stages of the manufacturing process of the method;

[0021] Figure 14 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the apparatus during the continuous stages of the manufacturing process of the method;

[0022] Figure 15 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the apparatus during the continuous stages of the manufacturing process of the method;

[0023] Figure 16 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the Y-section of the component during the continuous stages of the manufacturing process.

[0024] Figure 17 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the Y-section of the component during the continuous stages of the manufacturing process.

[0025] Figure 18 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0026] Figure 19 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0027] Figure 20 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0028] Figure 21 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0029] Figure 22 To illustrate, according to certain embodiments, in Figure 1A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0030] Figure 23 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0031] Figure 24 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0032] Figure 25 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0033] Figure 26 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0034] Figure 27 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0035] Figure 28 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0036] Figure 29 To illustrate, according to certain embodiments, in Figure 1 A cross-sectional schematic diagram of each pair of Y-section and X-section cross-sections of the component during the continuous stages of the manufacturing process.

[0037] Figure 30 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the component during the continuous stages of the manufacturing process.

[0038] Figure 31 To illustrate, according to certain embodiments, in Figure 1 A schematic cross-sectional view of the X-section of the component during the continuous stages of the manufacturing process.

[0039] Figure 32 A flowchart illustrating a method according to certain implementation methods is provided;

[0040] Figure 33 To illustrate the elements according to certain embodiments Figure 32 A schematic cross-sectional view of the X-section during the continuous stages of the manufacturing process of the method;

[0041] Figure 34 To illustrate the elements according to certain embodiments Figure 32 A schematic cross-sectional view of the X-section during the continuous stages of the manufacturing process of the method;

[0042] Figure 35 To illustrate the elements according to certain embodiments Figure 32 A schematic cross-sectional view of the X-section during the continuous stages of the manufacturing process of the method;

[0043] Figure 36 To illustrate the elements according to certain embodiments Figure 32 A schematic cross-sectional view of the X-section during the continuous stages of the manufacturing process of the method;

[0044] Figure 37 To illustrate the elements according to certain embodiments Figure 32 A schematic cross-sectional view of the X-section during the continuous stages of the manufacturing process of the method;

[0045] Figure 38 To illustrate the elements according to certain embodiments Figure 32 A schematic cross-sectional view of the X-section during the continuous stages of the manufacturing process of the method;

[0046] Figure 39 A flowchart illustrating a method according to certain implementation methods is provided;

[0047] Figure 40 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0048] Figure 41 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0049] Figure 42 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0050] Figure 43 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0051] Figure 44To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0052] Figure 45 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0053] Figure 46 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0054] Figure 47 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0055] Figure 48 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0056] Figure 49 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0057] Figure 50 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0058] Figure 51 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0059] Figure 52 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0060] Figure 53 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0061] Figure 54 To illustrate the perspective view, X-section cross-sectional view and Y-section cross-sectional view of the component according to certain embodiments during the continuous manufacturing stage;

[0062] Figure 55 A flowchart illustrating a method according to certain implementation methods is provided;

[0063] Figure 56 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0064] Figure 57 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0065] Figure 58 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0066] Figure 59 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0067] Figure 60 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0068] Figure 61 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0069] Figure 62 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0070] Figure 63 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0071] Figure 64 To illustrate the perspective view, the cross-sectional view of the X-section, and the cross-sectional view of the Y-section;

[0072] Figure 65 To illustrate cross-sectional views of the X and Y sections of an element during a continuous manufacturing stage, according to certain embodiments;

[0073] Figure 66 To illustrate cross-sectional views of the X and Y sections of an element during a continuous manufacturing stage, according to certain embodiments;

[0074] Figure 67 To illustrate cross-sectional views of the X and Y sections of an element during a continuous manufacturing stage, according to certain embodiments;

[0075] Figure 68 To illustrate, according to certain embodiments, cross-sectional views of the X and Y sections of an element during a continuous manufacturing phase are provided.

[0076] [Symbol Explanation]

[0077] 100: Semiconductor components

[0078] 103: Multi-layer structure

[0079] 105: Fins

[0080] 106: Bottom

[0081] 108: Gate section

[0082] 109: Dielectric Materials

[0083] 110: Dielectric structure

[0084] 111: First dielectric wall

[0085] 112: Second dielectric wall

[0086] 119: Insulation Characteristics

[0087] 201:Substrate

[0088] 205, 207: Epitaxial layers

[0089] 209: STI Characteristics

[0090] 217, 225, 226, 227: Masking layer

[0091] 218: First masking layer

[0092] 219: Second masking layer

[0093] 222: Gate structure

[0094] 230: Spacer

[0095] 230g: Gate sidewall spacer

[0096] 230f: Fin sidewall spacer

[0097] 303: Sacrificial gate electrode

[0098] 309: Sacrificial gate dielectric

[0099] 400: Source / Drain Characteristics

[0100] 440: Padding layer

[0101] 450: Dielectric

[0102] 460: Hard Mask

[0103] 499: Gate cavity

[0104] 500: Gate

[0105] 540: Gate dielectric layer

[0106] 550: Gate electrode material

[0107] 599,2101: Upper surface

[0108] 701: Nanosheets

[0109] 709: Internal isolation component

[0110] 800: Interconnect

[0111] 801: Gate capping layer

[0112] 891,2301:lower part

[0113] 892,2302: upper part

[0114] 893: Shoulder

[0115] 901, 1001, 1003, 1103: Opening

[0116] 903: Masking layer

[0117] 1000, 2300, 3000, 4000: Method

[0118] 1080: Gate section

[0119] 1081: First gate segment

[0120] 1082: Second gate section

[0121] 1131: Edge

[0122] 1104: Fin cavity

[0123] 1601: First insulating dielectric material

[0124] 2001: Second Insulating Dielectric Material

[0125] S1010, S1020, S1030, S1040, S1050, S1060, S1070, S1080, S1090, S1100, S1110, S1120, S1130, S1140, S1150, S1160, S1170, S1180, S1190, S1200: Operation Detailed Implementation

[0126] The following disclosure provides many different implementations, or embodiments, to achieve the various features of this disclosure. Specific embodiments of components and arrangements are described below to simplify this disclosure. Of course, these are merely embodiments and are not intended to be limiting. For example, the formation of a first feature on or above a second feature in the following description may include implementations where the first and second features are in direct contact, or implementations where additional features are formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for brevity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0127] Furthermore, for ease of description, this disclosure may use spatial relative terms such as “above,” “upper layer,” “over,” “top,” “top,” “below,” “lower layer,” “below,” “lower part,” “bottom,” “side,” etc., to describe the relationship of an element or feature to other elements or features shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be in other pipe orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used in this disclosure may be interpreted accordingly.

[0128] In some embodiments disclosed herein, a “material structure” is a structure comprising at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material; and a structure formed from the “material” comprises at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material. The structure formed from the “material” comprises at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material. For example, in some embodiments, each of the tungsten structure and the structure formed of tungsten is a structure with a tungsten content of at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.%.

[0129] For the sake of brevity, this disclosure may not describe in detail typical technologies associated with semiconductor device manufacturing. Furthermore, the various tasks and processes described in this disclosure can be incorporated into a more comprehensive program or process with additional functionality not described in detail in this disclosure. In particular, various processes in semiconductor device manufacturing are well known; therefore, for the sake of brevity, this disclosure will only briefly mention many typical processes, or omit them entirely without providing well-known process details. After a full reading of this disclosure, those skilled in the art will readily understand that the structures disclosed herein can be used with various technologies and can be incorporated into a wide variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures contain varying numbers of components, and a single component shown in the accompanying drawings may represent multiple components.

[0130] This disclosure describes embodiments of semiconductor devices and methods for manufacturing such devices. The methods described in this disclosure can be readily integrated into current process flows. Furthermore, the methods described in this disclosure relate to the formation of an insulating structure that divides a fin in two, such as a continuous polysilicon on-diffusion edge (CPODE) structure or a continuous metal on-diffusion edge (CMODE) architecture. In some embodiments, a portion of the selected fin structure is removed and replaced with an insulating material.

[0131] In embodiments disclosed herein, a CMODE process is provided, in which insulating features are formed after the metal gate is formed, or a CPODE process is provided, in which insulating features are formed before the metal gate is formed. In some embodiments, dielectric structures such as diced polysilicon gate dielectric structures, diced metal gate dielectric structures, or dummy fins are formed on the sidewalls of the cavity etched during the CMODE or CPODE process. Therefore, insulating features are formed in contact with the dielectric structures. In other embodiments, insulating features directly contact the remaining gate segment.

[0132] In some embodiments, the sidewall spacers are located on the sidewall of the gate segment to be removed during the CPODE or CMODE process. In this embodiment, the etching process used in the CPODE or CMODE process is tuned and controlled to remove at least the upper portion or all of the sidewall spacers that are in contact with the gate segment to be removed. Therefore, the subsequent removal process of the adjacent ILD structure does not etch into the insulation features or insulation feature interfaces, nor does it degrade the quality of the insulation features or insulation feature interfaces.

[0133] In other words, some embodiments here ensure that materials similar to or identical to the ILD structure, which would be etched during the removal of the ILD structure, do not appear on the upper surface of adjacent insulating features. When the ILD structure is silicon oxide, the embodiments remove the silicon oxide from the adjacent upper surface region where the insulating feature is formed. Furthermore, some embodiments may also specify forming the insulating feature itself without using a material similar to or identical to the material of the ILD structure (e.g., silicon oxide). In some embodiments, the insulating feature may include a liner formed of a material similar to or identical to the material of the ILD structure (e.g., silicon oxide). In this embodiment, the thickness of the liner is minimized, for example, not exceeding 4 nm, to prevent or reduce etch degradation of the insulating feature at the interface.

[0134] The embodiments disclosed herein offer advantages over the prior art, although it should be understood that other embodiments may offer different advantages, not all of which are necessarily discussed herein, and no particular advantage is required for any of the embodiments.

[0135] Regarding the following discussion, Figure 1 A flowchart is provided for a method 1000 for manufacturing a semiconductor element 100 during a semiconductor manufacturing process.

[0136] The following is for reference Figures 2 to 29 Description method 1000, Figures 2 to 29 The semiconductor device 100 is illustrated at various stages of manufacturing according to method 1000. It is understood that method 1000 includes steps with characteristics of complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore will only be briefly described here. Furthermore, other steps may be performed before, after, and / or during method 1000.

[0137] Figure 2 This is a top-down view illustrating the intermediate structure of a semiconductor element 100, such as a gate-all-around (GAA) semiconductor element, according to some embodiments. Figure 2 In the semiconductor element 100, there is a multilayer structure 103, which includes a plurality of nanosheets (shown in the figure below) formed on a semiconductor substrate 201, a semiconductor structure (e.g., fin 105) formed in the multilayer structure 103, and a plurality of gates 500 on the fin 105. Figure 2 Further explanation is provided regarding the plurality of dielectric structures 110 separating the two gates 500, and the insulating feature 119 that divides one of the fins 105 in two and intersects the gate 500 with the dielectric structure 110.

[0138] It should be noted that the semiconductor element 100 may include any appropriate number of fins 105 to form the desired semiconductor element 100. In addition, any appropriate number of gates 500, insulating features 119 and dielectric structures 110 may be formed to form the desired semiconductor element 100.

[0139] Now for reference Figure 1 and Figure 3A method 1000 for manufacturing a semiconductor device 100 includes, in operation S1010, providing a substrate 201. In some embodiments, the substrate 201 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 201 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 201 may include various doping configurations according to design requirements known in the art. For example, different doping configurations (e.g., p-wells, n-wells) may be formed in regions on the substrate 201 designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation dopants and / or diffusion processes, such as a p-layer boron (B) and an n-layer phosphorus (P). In some embodiments, the substrate 201 includes at least a single-crystal semiconductor layer on its surface portion. The substrate 201 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 201 may comprise compound semiconductors and / or alloy semiconductors. In the embodiment shown in the figures, substrate 201 is made of crystalline Si.

[0140] like Figure 3 As shown, in operation S1020, method 1000 ( Figure 2 One or more epitaxial layers are formed on substrate 201. In some embodiments, an epitaxial stack (multilayer structure 103) is formed on substrate 201. The epitaxial stack (multilayer structure 103) includes an epitaxial layer 205 of a first composition interspersed by an epitaxial layer 207 of a second composition. The first and second compositions can be different. Embodiments are possible, including those that provide a first composition and a second composition with different oxidation rates and / or etch selectivity. In one embodiment, epitaxial layer 205 is silicon-germanium (SiGe), and epitaxial layer 207 is silicon. In embodiments where epitaxial layer 205 comprises SiGe and epitaxial layer 207 comprises silicon, the oxidation rate of silicon is less than that of SiGe. It is worth noting that... Figure 3 The three epitaxial layers 205 and 207 are illustrated for illustrative purposes only and are not intended to limit the scope beyond the specific descriptions in the claims. It will be understood that any number of epitaxial layers can be formed in the epitaxial stack (multilayer structure 103); the number of epitaxial layers depends on the number of channel regions required for the GAA semiconductor device 100. In some embodiments, the number of epitaxial layers 207 is between two and ten, for example, six or seven.

[0141] In some embodiments, epitaxial layer 205 has a thickness from about 5 nm to about 15 nm. The thickness of epitaxial layer 205 can be substantially uniform. In some embodiments, epitaxial layer 207 has a thickness from about 5 nm to about 15 nm. In some embodiments, the thickness of the stacked epitaxial layers 207 is substantially uniform. As described in more detail below, epitaxial layer 207 can serve as a channel region for subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations. Epitaxial layer 205 can be used to define the gaps between adjacent channel regions of subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations.

[0142] For example, the epitaxial growth of the epitaxial stack (multilayer structure 103) can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer, for example, epitaxial layer 207, comprises the same material as the substrate 201. In some embodiments, epitaxial layers 205 and 207 comprise materials different from the substrate 201. As described above, in at least some embodiments, epitaxial layer 205 comprises an epitaxially grown Si1-xGex layer (where x is about 10% to about 55%), and epitaxial layer 207 comprises an epitaxially grown silicon (Si) layer. In some embodiments, epitaxial layer 205 comprises epitaxially grown silicon oxide. Alternatively, in some embodiments, either epitaxial layer 205 or 207 may comprise other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. As discussed, the materials of epitaxial layers 205 and 207 may be selected based on providing different oxidation and etch selectivity characteristics. In various embodiments, epitaxial layers 205 and 207 are substantially dopant-free (i.e., having approximately 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 The external dopant concentration), wherein, for example, no intentional doping is performed during epitaxial growth. In some embodiments, the bottom and top layers of the epitaxial stack (multilayer structure 103) are SiGe layers (not shown). In other embodiments, the bottom layer of the epitaxial stack (multilayer structure 103) is a Si layer, and the top layer of the epitaxial stack (multilayer structure 103) is a SiGe layer (not shown).

[0143] In some embodiments, the method includes forming a masking layer 217 on the epitaxial stack (multilayer structure 103), such as Figure 3As shown. Masking layer 217 includes a first masking layer 218 and a second masking layer 219. An exemplary first masking layer 218 is a pad oxide layer made of silicon oxide, which may be formed by thermal oxidation. An exemplary second masking layer 219 is made of silicon nitride (SiN), which may be formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0144] like Figure 4 As shown, in operation S1030, method 1000 ( Figure 2 The epitaxial stack (multilayer structure 103) is patterned to form semiconductor fins 105. For example, mask layer 217 can be patterned into a mask pattern using a patterning operation involving lithography and etching. Operation S1030 then involves patterning the epitaxial stack (multilayer structure 103) through openings defined in the patterned mask layer 217 in an etching process, such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The stacked epitaxial layers 205 and 207 are thus patterned into fins 105. Furthermore, the substrate 201 beneath the epitaxial layers 205 and 207 can be patterned so that the middle portion (bottom 106) of the substrate 201 forms the lower portion of the fins 105. Although Figure 4 The formation of two fins 105 is shown, but any appropriate number of fins can be formed. Grooves are etched between adjacent fins 105.

[0145] In various embodiments, each fin 105 includes an upper portion of staggered epitaxial layers 205 and 207, and a bottom 106 formed by etching a substrate 201. Each fin 105 projects upward from the substrate 201 in the Z direction and extends longitudinally in the Y direction. The sidewalls of each fin 105 may be straight or inclined (not shown). Figure 4 In the middle, the additional fins will be spaced apart along the X direction. Fins 105 may have the same width or different widths.

[0146] like Figure 5 As shown, in operation S1040, method 1000 ( Figure 2Shallow trench isolation (STI) features (represented as STI feature 209) are formed in trenches with dielectric material layers adjacent to each fin 105. STI feature 209 is formed by first filling the trenches around each fin 105 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 105. The dielectric material layer may contain one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicone glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin-dip techniques. Then, as... Figure 5 As shown, a dielectric material layer is planarized using, for example, chemical mechanical planarization (CMP) until the top surface of the mask layer 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (represented as STI feature 209). In the embodiment shown in the figures, STI feature 209 is formed on substrate 201. Any suitable etching technique can be used to recess the isolation STI feature 209, including dry etching, wet etching, RIE, and / or other etching methods. In one exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of STI feature 209 without etching fin 105. Mask layer 217 (e.g. Figure 4 (As shown) It can also be removed before, during, and / or after the recess of STI feature 209. In some embodiments, masking layer 217 is removed before the recess of STI feature 209. In some embodiments, masking layer 217 is used for etchant removal of the recessed STI feature 209.

[0147] like Figure 6 As shown, in operation S1050, method 1000 ( Figure 2 ) to form a sacrificial (dummy) gate structure 222. Figure 6 Half of the sacrificial gate structure 222 is shown. Although Figure 6 This represents the formation of one sacrificial gate structure 222, but any suitable number of sacrificial gate structures can be formed. Each sacrificial gate structure 222 protrudes upward from the substrate 201 along the Z direction and extends longitudinally along the X direction. Figure 6 In this configuration, the additional sacrificial gate structure 222 will be spaced along the Y direction.

[0148] A sacrificial gate structure 222 is formed on a portion of the fin 105 that will become the channel region. The sacrificial gate structure 222 may extend onto multiple adjacent fins 105. The sacrificial gate structure 222 is located directly over and defines the channel region of the GAA element to be formed. Each sacrificial gate structure 222 includes a sacrificial gate dielectric 309 and a sacrificial gate electrode 303 on the sacrificial gate dielectric 309.

[0149] The sacrificial gate structure 222 is formed by first depositing a sacrificial gate dielectric layer on the fin 105 using a blanket deposition method. Then, a sacrificial gate electrode layer is deposited layer by layer on the sacrificial gate dielectric layer and on the fin 105. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 100 nm to about 200 nm. The sacrificial gate electrode layer comprises silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nm to about 5 nm. In some embodiments, the sacrificial gate dielectric layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A masking layer 225 is formed on the sacrificial gate electrode layer. The masking layer 225 may include a masking layer 226 (e.g., silicon oxide) and a masking layer 227 (e.g., silicon nitride). Subsequently, as... Figure 6 As shown, a patterning operation is performed on the masking layer 225, and the sacrificial gate electrode layer and the sacrificial gate dielectric layer are patterned into a sacrificial gate structure 222, which includes a sacrificial gate dielectric 309 and a sacrificial gate electrode 303.

[0150] After the sacrificial gate structure 222 is formed, each fin 105 is partially exposed or revealed on the opposite side of the sacrificial gate structure 222, thereby defining a source / drain (S / D) region. In this disclosure, "source / drain region" or "source / drain feature" may refer to the source or drain, individually or collectively, depending on the context.

[0151] Now for reference Figure 7 In operation S1060, method 1000 ( Figure 2 Sidewall spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and the fin 105 by depositing spacer material, followed by etching. The sidewall spacers 230 may comprise padding materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide, SiOCN film, and / or combinations thereof. In some embodiments, each spacer 230 may comprise multiple layers, such as a spacer layer and a primary spacer layer on a substrate. In some embodiments, the sidewall spacers 230 are silicon oxide.

[0152] For example, the sidewall spacer 230 may be formed by depositing spacer material comprising a liner material layer and a dielectric material layer over the sacrificial gate structure 222 using, for example, sub-vapor CVD (SACVD), flowable CVD, ALD, PVD or other suitable processes.

[0153] like Figure 8As shown, after the deposition of the liner material layer and the dielectric material layer, in operation S1070, a back etch (e.g., anisotropic etch) is performed to expose and remove the portion of fin 105 that is adjacent to the sacrificial gate structure 222 and not covered by the sacrificial gate structure 222 (e.g., source / drain region). Figure 9 yes Figure 8 A cross-sectional view of the X-section of the manufacturing stage, along the single fin 105 and across the central sacrificial gate structure 222 located between two adjacent sacrificial gate structures 222.

[0154] Cross-reference Figure 8 and Figure 9 The liner material layer and dielectric material layer are retained on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230g, and on the sidewalls of the fins as fin sidewall spacers 230f. In some embodiments, the etch-back process may include wet etching, dry etching, multi-step etching, and / or combinations thereof. The spacers 230 may have a thickness of about 5 nm to about 20 nm.

[0155] like Figure 10 As further shown, method 1000 ( Figure 2 The process includes forming an inner spacer 709 in operation S1080. For example, operation S1080 may include laterally etching the epitaxial layer 205 of the second composition. In an exemplary embodiment, the SiGe etch return is removed to laterally recess the layer (epitaxy layer 205). As a result, a recess is formed between the laterally adjacent layer (epitaxy layer 205) and the longitudinally adjacent layer (epitaxy layer 207). Next, a material for forming the inner spacer 709 is deposited. For example, the inner spacer 709 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon nitride, silicon carbide oxide, silicon carbide oxide, silicon carbide nitride oxide, and / or other suitable dielectric materials. The inner spacer 709 may be formed by ALD or any other suitable method. As shown, after depositing the material for forming the inner spacer 709, the material may be trimmed from the sidewalls of the epitaxial layer 207.

[0156] While operating S1090, the method can continue to form source / drain characteristics 400, such as Figure 11 As shown. In an exemplary embodiment, the source / drain feature 400 is formed by epitaxial growth. In an exemplary embodiment, the source / drain feature 400 is a strained source / drain feature 400.

[0157] In an exemplary embodiment, the source / drain feature 400 may include both n-type and p-type epitaxial material source / drain features. The epitaxial material may comprise one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs, or one or more layers of Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, the source / drain may also contain boron (B). The source / drain epitaxial layers may be formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE).

[0158] exist Figure 12 In method 1000, at operation S1100, source / drain feature 400 is capped with a dielectric material. Specifically, a dielectric pad layer 440 may be formed over the source / drain feature 400 and along the sidewalls of spacer 230. Furthermore, a dielectric 450 may be formed on the pad layer 440 over the source / drain feature 400. In an exemplary embodiment, dielectric 450 is a first interlayer dielectric (ILD). Dielectric 450 may be silicon oxide or other suitable dielectric material. In some embodiments, ILD dielectric 450 is the same material as the sidewall spacer 230. In some embodiments, dielectric pad layer 440 is a dielectric, such as silicon nitride or other suitable material.

[0159] like Figure 13 As further shown, method 1000 includes, in operation S1110, turning on and removing the sacrificial gate structure 222, including removing the sacrificial gate dielectric 309 and the sacrificial gate electrode 303. Specifically, a chemical mechanical planarization (CMP) process may be performed to remove the masking layer 225 and expose the sacrificial gate structure 222. Further, the sacrificial gate structure 222 is removed to form a gate cavity 499. As shown, the gate cavity 499 is bounded by the sidewall spacers 230.

[0160] exist Figure 14 In method 1000, the intermediate epitaxial layer 205 is removed in operation S1120. As a result, gaps are formed between the epitaxial layers 207 of the first composition. In this way, the epitaxial layers 207 of the first composition are formed as vertically spaced semiconductor nanosheets 701.

[0161] exist Figure 15 In the process, method 1000 includes, at operation S1130, completing the metal gate replacement process to form metal gate 500.

[0162] In an exemplary embodiment, the metal gate replacement process includes forming a gate dielectric layer 540 in the gate cavity 499 and in the gaps under the nanosheet 701, and forming a gate electrode material 550 on the gate dielectric layer 540 to fill the gate cavity 499 and the gaps.

[0163] An exemplary gate dielectric layer 540 is conformally deposited. The gate dielectric layer 540 may be formed on the semiconductor nanosheet 701, and the gate electrode material 550 may be formed on the gate dielectric layer 540. Thus, each semiconductor nanosheet 701 is covered by the gate dielectric layer 540 and surrounded by the gate electrode material 550.

[0164] According to some embodiments, the gate dielectric layer 540 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 540 is a high-k dielectric material, in which case the gate dielectric layer 540 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 540 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0165] Gate electrode material 550 is deposited on top of gate dielectric layer 540 and fills the remaining portion of the gate cavity. Gate electrode material 550 can be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiples thereof. For example, although the figure shows a single gate material, any number of work function tuning layers can be deposited.

[0166] like Figure 15 As shown, the replacement metal gate process further includes removing excess portions of the gate dielectric layer 540 and gate electrode material 550 located on the top surface of the ILD. For example, a planarization process, such as a CMP process, can be performed to remove the excess portions of the gate dielectric layer 540 and gate electrode material 550. Thus, the semiconductor device 100 has an upper surface 599. The remaining material portions of the gate dielectric layer 540 and gate electrode material 550 thus form the replacement metal gate 500 of the fabricated semiconductor device 100. The gate dielectric layer 540 and gate electrode material 550 may be collectively referred to as a "gate," a "gate stack," or a "gate structure." Each gate 500 may extend along the sidewall of the channel region of the fin structure.

[0167] Figure 16 This is a cross-sectional view of the Y-section taken along gate 500. (See image below.) Figure 16 As shown, an optional gate capping layer 801 may be formed on the gate 500.

[0168] Optional gate capping 801 can be formed by initially depositing a dielectric material on the gate. In some embodiments, gate capping 801 is formed using dielectric materials such as silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or similar materials. According to some embodiments, gate capping 801 is formed using a metal oxide material, such as zirconium (Zr), hafnium (Hf), aluminum (Al), or the like. Furthermore, gate capping 801 can be formed using suitable deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), combinations of these processes, or similar processes. However, any suitable material and deposition process can also be used. After deposition, gate capping 801 can be planarized using a planarization process (e.g., CMP process).

[0169] Figure 17 This is a cross-sectional view along the Y-section of gate 500. Cross-reference Figure 1 and Figure 17 In some embodiments, method 1000 may continue to form an opening 901 in the gate 500 during operation S1140. After the gate capping layer 801 is planarized, a masking layer 903 may be deposited on the plane of the gate capping layer 801. After deposition, the masking layer 903 is patterned to expose the underlying material, including the gate capping layer 801 at the desired locations of the dielectric structure 110 to be formed.

[0170] After patterning, mask layer 903 is used as an etching mask to etch the underlying material to form opening 901 (e.g., trench, recess, channel, or similar structure). In the etching process, the gate capping layer 801 and the material of the gate 500 are etched using an anisotropic etching process. In some embodiments, the etching process continues through the gate dielectric layer 540 and into the STI region (STI feature 209). Opening 901 may be formed between adjacent fins 105 and may be formed to cut through one or more gates 500. According to some embodiments, such as Figure 2 As shown, two openings 901 are formed to cut between two adjacent gates 500 and are located on opposite sides of one or more fins 105, for example, selected fins. After the openings 901 are formed, the masking layer 903 is removed.

[0171] Cross-reference Figure 1 and Figure 18 and Figure 19 According to some embodiments, method 1000 may continue to form a dielectric wall (dielectric structure 110) from dielectric material 109 in operation S1150. Figure 18 It is a Y-section cross-sectional view taken along the gate 500 and across the four fins 105, and Figure 19It is an X-ray cross-sectional view taken along fin 105 and across the four gates 500. Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 28 is with Figure 18 Similar Y-section cross-sectional views; while Figure 21 , Figure 23 , Figure 25 , Figure 27 and Figure 29 is with Figure 19 An X-section view that is similar to the aforementioned Y-section view and is at the same manufacturing stage.

[0172] After opening 901 is formed, masking layer 903 can be removed. Then, dielectric walls (dielectric structure 110) are formed by initially depositing dielectric material 109 to fill and overfill opening 901. According to some embodiments, dielectric material 109 is formed using any dielectric material and deposition process suitable for forming gate capping layer 801. In some embodiments, dielectric material 109 is the same as the dielectric material used to form gate capping layer 801, although the dielectric material may be different. Figure 18 In some embodiments, the optional gate capping layer 801 is absent or may be considered part of the dielectric material 109. For example, in embodiments where the gate capping layer 801 is formed using silicon nitride (SiN), the dielectric material 109 may also be silicon nitride (SiN) formed in a deposition process such as atomic layer deposition (ALD). However, any suitable dielectric material and deposition process may be used. According to some embodiments, the dielectric wall (dielectric structure 110) is formed with a width of about 5 nm to about 50 nm (e.g., about 10 nm) between adjacent gate segments 108. However, any suitable width may also be used.

[0173] As shown, the dielectric wall (dielectric structure 110) extends into the STI region (STI feature 209) and divides the relatively long gate into a plurality of relatively short gate segments 108. The dielectric wall (dielectric structure 110) can be used to isolate the gate segments 108 from each other. In addition, excess dielectric material 109 of the dielectric wall (dielectric structure 110) outside the opening 901 can be retained and used as a mask layer in subsequent etching processes.

[0174] exist Figure 18 In this configuration, a first dielectric wall 111 separates the first gate segment 1081 from the selected gate segment 1080. Furthermore, a second dielectric wall 112 separates the second gate segment 1082 from the selected gate segment 1080.

[0175] Figure 19The gate 500 is formed between the sidewall spacers 230. As described above, the sidewall spacers 230 are initially formed around the sacrificial gate. The sidewall spacers 230 may comprise spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide, SiOCN film, and / or combinations thereof. For example, the sidewall spacers 230 may be formed by depositing spacer material comprising an inner spacer material layer and a dielectric material layer on the sacrificial gate structure 222 using, for example, subatomic CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. In some embodiments, the sidewall spacers 230 are low-k silicon oxide.

[0176] like Figure 19 As shown, source / drain features 400 have been formed in the region recessed from fin 105. Typically, fin 105 is recessed in a region not covered by the sacrificial gate. Epitaxial material is then grown at the recess to form source / drain features 400. After forming source / drain features 400, they are capped with a dielectric material. For example, a dielectric liner layer 440 may be formed on spacer 230. Furthermore, a dielectric 450 may be formed on the liner layer 440 and source / drain features 400. In an exemplary embodiment, dielectric 450 is a first interlayer dielectric (ILD). Dielectric 450 may be silicon oxide or other suitable dielectric material. In some embodiments, dielectric liner layer 440 is a dielectric, such as silicon nitride or other suitable material. After forming dielectric 450, the sacrificial gate is removed as shown and replaced with gate 500.

[0177] Cross-reference Figure 1 as well as Figure 20 and Figure 21 Method 1000 may continue in operation S1160, wherein, according to some embodiments, an opening 1001 is formed in the dielectric material 109 above each selected gate segment 1080 of the gate 500 to be removed in the initial step of forming the insulating feature.

[0178] In some embodiments, forming the opening 1001 in the dielectric material 109 may include depositing various masking layers, such as a carbon substrate layer, an oxide-based intermediate layer, and an extreme ultraviolet (EUV) photoresist top layer. This process may include performing an EUV photoresist exposure technique to pattern the photoresist, followed by etching the intermediate and bottom layers. The dielectric material 109 is then etched to form the opening 1001. The dielectric material 109 may be etched using a dry etching process, such as a process suitable for etching silicon nitride materials.

[0179] Photoresist and other patterning materials used in EUV lithography (intermediate layer, spin-coated glass or base layer, spin-coated carbon) can be removed after the hard mask is opened, for example, by using in-situ or off-situ ashing processes.

[0180] Cross-reference Figure 1 and Figure 22 and Figure 23 Method 1000 can continue to remove gate segment 1080 in operation S1170.

[0181] In some embodiments, removing the gate segment 1080 forms an opening 1003 and includes selectively removing the gate segment 1080, which includes the gate 500 and the gate dielectric layer 540. The gate segment 1080 can be removed by dry etching or wet etching. In some embodiments, the process can remove all gate segments 1080 between dielectric walls (dielectric structure 110) and above the STI region (STI feature 209), such as Figure 22 As shown. Further, this process can remove all gate segments 1080 between the sidewall spacer 230 and the boss or bottom 106 of the fin 105, including between nanosheets 701, such as... Figure 23 As shown.

[0182] Cross-reference Figure 1 as well as Figure 24 and Figure 25 Method 1000 can continue in operation S1180 by removing the nanosheet 701, etching the sidewall spacer 230, and recessing the selected fin 105 to form a cavity or opening 1103. For example... Figure 25 As shown, when the opening 1103 is formed, the sidewall spacer 230 can be completely removed.

[0183] After peeling back the portions of nanosheet 701 and fin 105 protruding above the STI region (STI feature 209), further etching processes can be used to remove material from nanosheet 701 and sidewall spacers 230, and to recess fin 105. In some embodiments, uncovered fins 105 and uncovered sidewall spacers 230 are removed, and a portion of the underlying substrate 201 is etched. Thus, the upper surface of substrate 201 is recessed. As shown, opening 1103 includes a protrusion or fin cavity 1104 extending through the STI region (STI feature 209) and into substrate 201.

[0184] In some embodiments, the sidewall spacers 230 are removed using an oxide removal process and / or a low-k oxide selective slab cutting process. As a result, the edge 1131 of the opening 1103 is formed by the dielectric liner layer 440, nanosheets 701, inner spacers 709, and substrate 201. In other words, all sidewall spacers 230 between the edge 1131 and the dielectric liner layer 440.

[0185] In some embodiments, the etching process is plasma etching, which may be followed by a wet cleaning process. Plasma etching can be tailored and controlled to remove material from the sidewall spacers 230. For example, plasma etching may use halogen-based etchants, such as CF4, CHF3, CH2F2, CHF3, or BCl3. In some embodiments, HF and amino etchants with or without plasma-enhancing properties may be used, for example, to remove oxide-based spacers 230.

[0186] Cross-reference Figure 1 and Figure 26 and Figure 27 Method 1000 can continue to form insulating feature 119 in opening 1103 in operation S1190.

[0187] As shown in the figure, the insulating feature 119 can be formed by depositing a first insulating dielectric material 1601 in the opening 1103. The first insulating dielectric material 1601 can be formed as a padding layer that completely covers the surface of the opening 1103 and the upper surface of the dielectric material 109. Figure 27 As shown, the first insulating dielectric material 1601 is in contact with the padding layer 440.

[0188] In some embodiments, the first insulating dielectric material 1601 may comprise silicon oxide, silicon oxynitride, a dielectric material with a dielectric constant (k) lower than that of silicon oxide (therefore referred to as a low-k dielectric material layer), and / or other suitable dielectric material layers. In some embodiments, the first insulating dielectric material 1601 is low-k silicon oxide.

[0189] Furthermore, the insulating feature 119 can be formed by depositing a second insulating dielectric material 2001 on the first insulating dielectric material 1601. The second insulating dielectric material 2001 can completely fill the opening 1103.

[0190] In some embodiments, the second insulating dielectric material 2001 may comprise silicon nitride, silicon oxynitride, and / or other suitable dielectric material layers. In some embodiments, the second insulating dielectric material 2001 is silicon nitride.

[0191] In some embodiments, the second insulating dielectric material 2001 can be deposited using a refill process. In one embodiment, the second insulating dielectric material 2001 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), spin deposition, or other suitable techniques. As shown, the second insulating dielectric material 2001 can first be formed as a blanket layer covering the surface of the dielectric material 109.

[0192] Cross-reference Figure 1 as well as Figure 28 and Figure 29Operation S1190 may further include planarizing the structure of the semiconductor element 100 to form an insulating feature 119 in the opening 1103.

[0193] As shown in the figure, the planarization process can remove all the covering portions of the dielectric material 109, the first insulating dielectric material 1601 and the second insulating dielectric material 2001, and form a structure of a semiconductor element 100 having an upper surface 2101.

[0194] Since the sidewall spacer 230 adjacent to the insulating feature 119 is removed, the upper surface 2101 at the insulating feature 119 is formed sequentially by a second insulating dielectric material 2001, a first insulating dielectric material 1601, a dielectric liner layer 440, and an ILD dielectric structure (dielectric 450). For example, between the two ILD dielectric structures (dielectric 450) surrounding the insulating feature 119, the upper surface 2101 is formed by the ILD dielectric structure (dielectric 450), the dielectric liner layer 440, the first insulating dielectric material 1601, the second insulating dielectric material 2001, the first insulating dielectric material 1601, the dielectric liner layer 440, and the ILD dielectric structure (dielectric 450).

[0195] Operation S1190 can be considered as completing the insulation feature fabrication process by forming an insulation feature 119 comprising a first insulating dielectric material 1601 and a second insulating dielectric material 2001.

[0196] like Figure 1 As shown, method 1000 may include further processing. For example, various lithography, patterning, and passivation processes can be performed to form dielectric and metallization layers and to form the desired interconnect structure, such as in a typical back-end-of-line (BEOL) process. For example, the ILD structure on the source / drain feature 400 can be removed and replaced with a conductive material to form a source / drain interconnect.

[0197] Although Figures 24 to 29 An embodiment is shown in which all sidewall spacers 230 are removed when opening 1103 is formed during operations S1160 to S1180, but other embodiments are contemplated. For example, only a portion of each sidewall spacer 230 may be removed.

[0198] For example, refer to Figure 1 and Figure 30 The S1180 can be operated by performing an etching process. Figures 22 to 23 The structure is modified to remove nanosheets 701, partially etch sidewall spacers 230, and recess selected fins 105 to form cavities or openings 1103. For example... Figure 30 As shown, only the sidewall spacer 230 is partially removed when forming the opening 1103.

[0199] Specifically, the etching process is adjusted and controlled to completely remove the upper part 2302 of the sidewall spacer 230 (in Figure 23 (as indicated by the Chinese symbol), while the lower portion 2301 of the sidewall spacer 230 remains. For example, the etching process can use halogen-based chemicals (e.g., CF4, CHF3, CH2F2, CHF3, or BCl3) for a directional plasma etching step. In some embodiments, low-pressure (e.g., below 100 mT) and high-bias-power (e.g., above 300 W) etching conditions can be used to enhance the directionality of the plasma to precisely control the recess of the sidewall spacer 230, thereby removing the upper portion 2302.

[0200] For example, after peeling back the nanosheet 701 and the portion of the fin 105 protruding above the STI region (STI feature 209), further etching processes can be used to remove material from the nanosheet 701, remove the upper portion 2302 of the sidewall spacer 230, and the recessed fin 105. In some embodiments, the uncovered fin 105 is removed, the uncovered sidewall spacer 230 is partially etched, and a portion of the underlying substrate 201 is etched. Thus, the upper surface of the substrate 201 is recessed.

[0201] In some embodiments, the sidewall spacer 230 is partially removed using an oxide removal process and / or a low-k oxide selective slab cutting process. As a result, the edge 1131 of the opening 1103 is formed by the dielectric liner layer 440, the lower portion 2301 of the sidewall spacer 230, the nanosheet 701, the inner spacer 709, and the substrate 201.

[0202] In some embodiments, the etching process is plasma etching, which may be followed by a wet cleaning process. The plasma etching is adjusted and controlled to remove only the upper portion 2302 of the sidewall spacer 230.

[0203] See Figure 1 and Figure 31 Operation S1190 can be processed by forming an insulating feature 119 in the opening 1103. Figure 30 The structure is as described above. For example, the first insulating dielectric material 1601 and the second insulating dielectric material 2001 can be deposited and planarized as described above. As a result, the semiconductor element 100 is formed having an upper surface 2101.

[0204] Since the upper portion 2302 of the spacer 230 adjacent to the insulating feature 119 is removed, the upper surface 2101 at the insulating feature 119 is formed sequentially by a second insulating dielectric material 2001, a first insulating dielectric material 1601, a dielectric liner layer 440, and an ILD dielectric structure (dielectric 450). For example, between the two ILD dielectric structures (dielectric 450) surrounding the insulating feature 119, the upper surface 2101 is formed by the ILD dielectric structure (dielectric 450), the dielectric liner layer 440, the first insulating dielectric material 1601, the second insulating dielectric material 2001, the first insulating dielectric material 1601, the dielectric liner layer 440, and the ILD dielectric structure (dielectric 450).

[0205] exist Figures 30 to 31 In this embodiment, the insulating feature 119 is formed with a furnace-shaped cross-section. Specifically, the insulating feature 119 includes a lower portion 891 and an upper portion 892. The lower portion 891 and the upper portion 892 are connected at a laterally outwardly extending shoulder 893. The cross-sectional width of the upper portion 892 is wider than that of the lower portion 891.

[0206] Operation S1190 can be considered as completing the CMODE process by forming an insulating feature 119 in the form of a CMODE structure, which includes a first insulating dielectric material 1601 and a second insulating dielectric material 2001.

[0207] It should be noted that, although in Figures 20 to 29 and Figures 30 to 31 In one embodiment, the etching process removes the gate 500 before etching the sidewall spacers 230; however, other embodiments are considered. For example, the etching process that removes the gate 500 may also etch or partially etch the sidewall spacers 230. In such an embodiment, the etching process that removes the nanosheet 701 and etches the substrate 201 may also partially etch the sidewall spacers 230, or the etching process that removes the nanosheet 701 and etches the substrate 201 may not include etching the sidewall spacers 230.

[0208] Although about Figures 1 to 31 The operation of method 1000 is described in a continuous metal diffusion edge (CMODE) process, wherein the insulating feature 119 is formed after the metal gate is formed, but the insulating feature 119 can be formed in a continuous polysilicon diffusion edge (CPODE) process, i.e., before the metal gate is formed.

[0209] Specifically, in the CMODE process shown in the attached diagram, the removed gate segment is a metal gate segment, and the gate dielectric is a high-k gate dielectric. For the CMODE process, removing the gate during operation S1190 includes removing the inter-chip portion of the gate located beneath the nanosheet. In the CPODE process, the gate processed by operations S1160 to S1190 is a dummy gate. In the CPODE process, the inter-chip portion of the gate has not yet been formed. Therefore, operation S1190 includes removing the sacrificial interlayer epitaxial layer 205.

[0210] In method 1000, whether using the CMODE or CPODE process, the sidewall spacers 230 are removed or etched during the gate removal process and / or during the subsequent process of removing the nanosheets and recessed substrate. In other embodiments, the sidewall spacers 230 may be etched at different stages of manufacturing.

[0211] For example, Figure 32 and Figures 33 to 37 Another method is shown for etching the sidewall spacer 230 before forming the opening 1103.

[0212] See Figure 32 and Figure 33 Method 2300 is included in operation S2305, which provides, for example... Figure 33 The structure of the semiconductor device 100 shown is illustrated. The epitaxial stack (multilayer structure 103) of epitaxial layers 205 and 207 is patterned into fins 105. A sacrificial gate structure 222 is formed on the fins 105, and sidewall spacers 230 are formed on the sacrificial gate. The uncovered portion of the fins 105 is recessed, and source / drain features 400 are grown in the recesses. A pad layer 440 and a dielectric 450 are formed on the source / drain features 400. Operation S2305 may include operations S1010 to S1100 as described above. (Refer to...) Figure 32 and Figure 34 Method 2300 further includes, in operation S2315, removing the sacrificial gate structure 222. The result of removing the sacrificial gate structure 222 is the formation of a gate cavity 499 located between the sidewall spacers 230.

[0213] Reference Figure 32 and Figure 35 Method 2300 further includes, in operation S4005, trimming the sidewall spacer 230. Specifically, removing the upper portion 2302 of the sidewall spacer 230, leaving only the lower portion 2301 of the sidewall spacer 230.

[0214] See Figure 32 and Figure 36 In operation S2335, a metal gate replacement process is performed to remove the sacrificial gate structure 222 and replace the sacrificial gate structure 222 with a metal gate 500.

[0215] Method 2300 further includes, in operation S2345, forming an opening of a mask on a selected metal gate segment 1080. Figure 36 (Not shown in the diagram). Specifically, a mask (dielectric material 109) may be formed over the metal gate 500 and patterned to cover the first gate segment 1081, similar to operation S1160 described above.

[0216] Method 2300 can continue removing the non-covered gate segment 1080 in operation S2355, similar to operation S1170. In method 2300, since the sidewall spacers 230 have been trimmed, the etching process for removing the metal gate segment 1080 does not require etching the sidewall spacers 230.

[0217] Reference Figure 32 and Figure 37 Method 2300 can continue to remove the nanosheet 701 and the recessed selected fin 105 to form a cavity or opening 1103 in operation S2365, similar to operation S1180 described above. However, in method 2300, since the sidewall spacer 230 has already been trimmed, the etching process for removing the nanosheet 701 and the recessed selected fin 105 does not need to etch the sidewall spacer 230.

[0218] Method 2300 can continue to operate S1190 and S1200 as described above to form insulating feature 119 in opening 1103 and perform further processing.

[0219] Therefore, method 2300 can form as follows Figure 31 The semiconductor element 100 shown has insulating feature 119, wherein the lower portion 2301 of the sidewall spacer is retained but is far from the upper surface 2101 of the semiconductor element 100 and is separated from the upper surface 2101 of the semiconductor element 100 by elements not formed of silicon oxide.

[0220] Figure 38 This describes the formation of the interconnect 800 of the source / drain feature 400. During this process, dielectric 450 (not shown) is etched, and conductive material is deposited to form the interconnect 800.

[0221] like Figure 38 As shown, the insulating feature is formed in a furnace-shaped cross-section, meaning the lower portion of the sidewall spacer 230 is located next to the insulating feature 119, and the upper portion of the sidewall spacer 230 has been removed. Furthermore, the metal gate 500 is formed in a cross-sectional furnace shape. For example, the upper portion of the gate dielectric layer 540 is partially etched, such that the upper portion of the metal gate 500 has a larger lateral width in the cross-sectional view of the accompanying drawings than the lower portion of the metal gate 500.

[0222] Now refer to Figure 39 and Figures 40 to 54 Another implementation is described. Specifically, a method 3000 for forming an insulating feature 119 with a FinFET semiconductor element 100 is described.

[0223] Cross-reference Figure 39 and Figures 40 to 42 Method 3000 includes providing a semiconductor element 100 having a FinFET structure in operation S3005. Figure 40 Provides perspective views of the manufacturing stage. Figure 41 Provide X-section cross-sectional views of the manufacturing stage, and Figure 42 A Y-section cross-sectional view of the manufacturing stage is provided. As shown, in the semiconductor device 100, a fin 105 is formed from and covers a substrate 201; and an STI feature 209 is formed around the fin 105. Furthermore, a parallel gate structure 222 is formed on the fin 105, and a source / drain feature adjacent to the sacrificial gate structure 222 is formed in the fin 105. As shown, a sacrificial gate dielectric 309 may be formed on the STI feature 209 before the sacrificial gate electrode 303 is formed. As shown, a dielectric structure (dielectric 450) is formed on the source / drain feature 400. As further shown, a mask (dielectric material 109), such as compressed silicon nitride, is formed on the structure of the semiconductor device 100.

[0224] Cross-reference Figure 39 and Figures 43 to 45 Method 3000 includes patterning a mask (dielectric material 109) on the gate structure 222 during operation S3015. Specifically, an opening 1001 is formed in the mask (dielectric material 109) on a selected gate segment 1080.

[0225] Cross-reference Figure 39 and Figures 46 to 48 Method 3000 includes operation S3015 removing a selected gate segment 1080. As a result, an opening 1003 is formed. As shown, operation S3015 removes the sacrificial gate electrode 303 and the sacrificial gate dielectric 309. Therefore, the selected fin 105 and the surrounding STI feature 209 are exposed. The opening 1003 exposes the oxide sidewall spacer 230.

[0226] Cross-reference Figure 39 and Figures 49 to 51 Method 3000 includes operation S3025 removing selected fin 105, removing sidewall spacer 230 and recessing bottom substrate 201 to form opening 1103.

[0227] Therefore, the upper surface of substrate 201 is recessed. As shown, opening 1103 includes a protrusion or fin cavity 1104 extending through the STI region (STI feature 209) and into substrate 201.

[0228] In some embodiments, an oxide removal process and / or a low-k oxide selective sheet cutting process are used to remove the sidewall spacer 230.

[0229] In some embodiments, the etching process is plasma etching, which may be followed by a wet cleaning process. The plasma etching is tuned and controlled to remove material from the sidewall spacers 230.

[0230] Cross-reference Figure 39 and Figures 49 to 51 Method 3000 includes operation S3035 removing selected fin 105, removing sidewall spacer 230 and recessing bottom substrate 201 to form opening 1103.

[0231] Cross-reference Figure 39 and Figures 52 to 54 Method 3000 includes operation S3045 forming an insulating feature 119 in the opening 1103. For example, a first insulating dielectric material 1601 may be formed as a padding layer that completely covers the surface of the opening 1103 and covers the top surface of the dielectric material 109. In some embodiments, the first insulating dielectric material 1601 may comprise silicon oxide, oxynitride, a dielectric material with a dielectric constant (k) lower than that of silicon oxide (therefore referred to as a low-k dielectric material layer), and / or other suitable dielectric material layers. In some embodiments, the first insulating dielectric material 1601 is low-k silicon oxide.

[0232] A second insulating dielectric material 2001 may be deposited on top of the first insulating dielectric material 1601. The second insulating dielectric material 2001 may completely fill the opening 1103. In some embodiments, the second insulating dielectric material 2001 may comprise a silicon nitride, oxynitride, and / or other suitable dielectric material layer. In some embodiments, the second insulating dielectric material 2001 is silicon nitride.

[0233] In some embodiments, the second insulating dielectric material 2001 can be deposited using a refill process. In one embodiment, the second insulating dielectric material 2001 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), spin deposition, or other suitable techniques. As shown, the second insulating dielectric material 2001 can first be formed as a blanket layer covering the surface of the dielectric material 109.

[0234] As shown in the figure, operation S3045 further includes planarizing the structure of the semiconductor element 100 to form an insulating feature 119 in the opening 1103. Specifically, all covering portions of the dielectric material 109 and the first insulating dielectric material 1601 and the second insulating dielectric material 2001 can be removed to form a structure of the semiconductor element 100 having an upper surface 2101.

[0235] Similar to the previously described embodiments, the oxide sidewall spacer 230 is not located adjacent to the insulating feature 119 on the upper surface 2101 because the sidewall spacer 230 is removed when the opening of the insulating feature 119 is formed.

[0236] Method 3000 may continue further processing in operation S3055. Since the sacrificial gate structure 222 is etched to form insulating feature 119, method 3000 may proceed with a metal gate replacement process to replace the remaining sacrificial gate with a metal gate. For example, the sacrificial gate is removed to form gate cavity 499, and a metal gate 500 is formed in gate cavity 499 as described above with respect to operations S1110 to S1130.

[0237] Now refer to Figure 55 and Figures 56 to 68 Another implementation is described. Specifically, a method 4000 for forming an insulating feature 119 with a FinFET semiconductor element 100 is described.

[0238] Cross-reference Figure 55 and Figures 56 to 58 Method 3000 includes providing a semiconductor element 100 having a FinFET structure in operation S4005. Figure 56 Provides perspective views of the manufacturing stage. Figure 57 Provide X-section cross-sectional views of the manufacturing stage, and Figure 58 Provide a Y-section view of the manufacturing stage.

[0239] As shown, in semiconductor device 100, fin 105 is formed on a substrate; and STI feature 209 is formed around fin 105. Furthermore, a dummy fin (dielectric structure 110) is formed on STI feature 209. Source / drain features 400 are formed in fin 105 surrounding a parallel sacrificial gate, and a hard mask 460 is formed on source / drain features 400. After removing the sacrificial gate, a parallel gate 500 is formed on fin 105 and the dummy fin (dielectric structure 110). Gate 500 may include layers such as a work function metal and an amorphous silicon layer. As shown, before the formation of gate 500, a gate dielectric layer 540 may be formed on fin 105, dummy fin (dielectric structure 110), and STI feature 209. As further shown, a mask (dielectric material 109), such as a silicon nitride hard mask, is formed on the structure of semiconductor device 100. Figure 58 In the process, the gate 500 is etched so that a portion of the hard mask (dielectric material 109) extends downward to contact the dummy fin (dielectric structure 110) formed in the semiconductor element 100 to define the removal area.

[0240] Cross-reference Figure 55 and Figures 59 to 61 Method 3000 includes etching through the amorphous silicon layer to form an opening 1001 on the fin 105 selected for removal in operation S4015. In some embodiments, dry etching is performed to remove the amorphous silicon layer. Figure 59 Provide perspective views of the manufacturing stage. Figure 60 Provide X-section cross-sectional views of the manufacturing stage, and Figure 61 Provide a Y-section view of the manufacturing stage.

[0241] Cross-reference Figure 55 and Figures 62 to 64 Method 3000 includes etching through the work function metal of gate 500 to remove gate 500, and forming an opening 1003 on the fin 105 selected for removal in operation S4025. In some embodiments, wet etching or dry etching is performed to remove the work function metal of gate 500. Figure 62 Provide perspective views of the manufacturing stage. Figure 63 Provide X-section cross-sectional views of the manufacturing stage, and Figure 64 Provide a Y-section view of the manufacturing stage.

[0242] Cross-reference Figure 55 , Figure 65 (X-section view) and Figure 66 In the manufacturing stage (Y-section cross-sectional view), method 3000 may continue etching the sidewall spacer 230 and the recessed selected fin 105 at operation S4035 to form a cavity or opening 1103. For example... Figure 65 As shown, the sidewall spacer 230 can be completely removed when the opening 1103 is formed. As shown, the opening 1103 includes a protrusion or fin cavity 1104 that extends through the STI region (STI feature 209) and into the substrate 201.

[0243] In some embodiments, the sidewall spacer 230 is removed by using an oxide removal process and / or a low-k oxide selective slab cutting process.

[0244] Cross-reference Figure 55 , Figure 67 X-section cross-section, and Figure 68 In one manufacturing stage of the Y-section view, method 3000 may continue to form insulating feature 119 in opening 1103 in operation S4045.

[0245] As shown in the figure, the insulating feature 119 can be formed by depositing a first insulating dielectric material 1601 in the opening 1103. The first insulating dielectric material 1601 can be formed as a pad layer that completely covers the surface of the opening 1103 and the upper surface of the dielectric material 109.

[0246] In some embodiments, the first insulating dielectric material 1601 may comprise silicon oxide, silicon oxynitride, a dielectric material with a dielectric constant (k) lower than that of silicon oxide (hence referred to as a low-k dielectric material layer), and / or other suitable dielectric material layers. In some embodiments, the first insulating dielectric material 1601 is low-k silicon oxide.

[0247] Furthermore, the insulating feature 119 can be formed by depositing a second insulating dielectric material 2001 on the first insulating dielectric material 1601. The second insulating dielectric material 2001 can completely fill the opening 1103.

[0248] In some embodiments, the second insulating dielectric material 2001 may comprise a silicon nitride, oxide oxynitride, and / or other suitable dielectric material layer. In some embodiments, the second insulating dielectric material 2001 is silicon nitride.

[0249] In some embodiments, the second insulating dielectric material 2001 can be deposited using a refill process. In one embodiment, the second insulating dielectric material 2001 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), spin deposition, or other suitable techniques. As shown, the second insulating dielectric material 2001 can first be formed as a blanket layer covering the surface of the dielectric material 109.

[0250] Operation S4045 further includes planarizing the structure of semiconductor element 100 to form insulating feature 119 in opening 1103.

[0251] As shown in the figure, the planarization process can remove all the covering portions of the dielectric material 109, the first insulating dielectric material 1601 and the second insulating dielectric material 2001, and form a structure of a semiconductor element 100 having an upper surface 2101.

[0252] Operation S4045 can be considered as completing the insulation feature fabrication process by forming an insulation feature 119 comprising a first insulating dielectric material 1601 and a second insulating dielectric material 2001.

[0253] like Figure 55 As shown, method 4000 may include further processing of operation S4055. For example, various lithography, patterning, and passivation processes may be performed to form dielectric and metallization layers and to form the desired interconnect structure, such as in a typical back-end-of-line (BEOL) process.

[0254] In one embodiment, a method is provided comprising forming a fin on a substrate; forming a gate on the fin, wherein a sidewall spacer is laterally adjacent to the gate; removing an upper portion of the sidewall spacer; forming a cavity by removing a selected segment of the gate and removing a selected fin located below the selected segment; and forming an insulating feature in the cavity.

[0255] In some embodiments of the method, the interlayer dielectric (ILD) structure is adjacent to an insulating feature, and the method further includes etching the ILD structure and forming a conductive interconnect with a source / drain feature adjacent to the insulating feature.

[0256] In some embodiments, the method further includes forming a source / drain feature adjacent to the gate; forming an interlayer dielectric (ILD) structure on the source / drain feature, wherein the ILD structure and the sidewall spacers are formed of the same material; and etching the ILD structure to form a conductive interconnect with the source / drain feature of an adjacent insulating feature, wherein if sidewall spacers are present when the ILD structure is etched, the insulating feature covers the sidewall spacers to avoid etching the sidewall spacers.

[0257] In some embodiments of this method, removing the upper part of the sidewall spacer includes removing the entire sidewall spacer.

[0258] In some embodiments of this method, the removal of the upper portion of the sidewall spacer is performed after the removal of a selected segment of the gate.

[0259] In some embodiments of the method, the sidewall spacers comprise low-k silicon oxide.

[0260] In some embodiments of this method, the gate is a metal gate.

[0261] In some embodiments of the method, the gate is a sacrificial gate, and the method further includes removing the remainder of the sacrificial gate to form a gate cavity; and forming a metal gate in the gate cavity.

[0262] In another embodiment, a method of manufacturing a semiconductor device is provided, comprising forming a fin on a substrate; forming a gate on the fin; forming a source / drain feature adjacent to the gate in the fin; forming an interlayer dielectric (ILD) structure on the source / drain feature, wherein the ILD structure comprises silicon oxide; removing a region comprising a portion of the fin and a portion of the gate to form an opening; forming an insulating feature in the opening; and performing a process to etch the selected ILD structure down to the source / drain feature of the underlying layer, wherein, during the process, the semiconductor device exposed surfaces at and adjacent to the insulating feature are free of silicon oxide.

[0263] In some embodiments, the method further includes forming a sidewall spacer, wherein the sidewall spacer is directly adjacent to the gate; and removing at least the upper portion of the sidewall spacer portion in the region while removing the region containing the fin portion and the gate portion to form an opening.

[0264] In some implementations, the method includes removing all sidewall spacers within the area.

[0265] In some embodiments of this method, the process of etching the selected ILD structure does not etch the interface of the insulating features.

[0266] In some embodiments of this method, the gate is a metal gate.

[0267] In some embodiments of this method, the gate is a sacrificial gate, and the method further includes removing the remainder of the sacrificial gate to form a gate cavity after forming an insulating feature in the opening; and forming a metal gate in the gate cavity before performing a process to etch the selected ILD structure.

[0268] In another embodiment, a semiconductor element is provided, comprising a fin located above a substrate; source / drain features located in grooves formed in the fin; and an insulating feature located between the source / drain features and extending through the fin and into the substrate, wherein the insulating feature has an uppermost surface and at the uppermost surface, the insulating feature is in contact with a non-oxide dielectric layer.

[0269] In some implementations of a semiconductor device, the gate is located above the fin, with insulating features extending through the gate.

[0270] In some embodiments of a semiconductor device, the oxide layer contacts the lower portion of an insulating feature, wherein the upper portion of the insulating feature is located above the oxide layer.

[0271] In some embodiments of a semiconductor device, no portion of the insulating feature is in contact with the oxide layer.

[0272] In some embodiments of a semiconductor device, conductive interconnects are located above selected source / drain features, and a non-oxide dielectric layer contacts both the conductive interconnects and the insulating features.

[0273] In various embodiments, the insulating feature includes a padding layer formed of a first insulating dielectric material. In some embodiments, the first insulating dielectric material is not silicon oxide, and the insulating feature does not contain silicon oxide. However, in some embodiments, the first insulating dielectric material may be silicon oxide. In such embodiments, the padding layer formed of the first insulating dielectric material may have a small thickness, for example, a thickness not exceeding 4 nm.

[0274] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use the content of this disclosure as the basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described in this disclosure. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications therein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: Multiple fins are formed above a substrate; A gate is formed above the plurality of fins, wherein a sidewall spacer is laterally adjacent to the gate; Remove the upper part of the sidewall spacer; A cavity is formed by removing a selected section of the gate and a selected fin located below the selected section; as well as An insulating feature is formed in the cavity.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, An interlayer dielectric structure is adjacent to the insulating feature, and the method further includes etching the interlayer dielectric structure and forming a conductive interconnect to a source / drain feature adjacent to the insulating feature.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Further includes: Forming a source / drain feature adjacent to the gate; An interlayer dielectric structure is formed above the source / drain feature, wherein the interlayer dielectric structure and the sidewall spacer are formed of the same material; The interlayer dielectric structure is etched, and a conductive interconnect is formed to the source / drain feature adjacent to the insulating feature. If the sidewall spacer is present when etching the interlayer dielectric structure, the insulating feature covers the sidewall spacer to prevent etching of the sidewall spacer.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The gate is a sacrificial gate, and the method further includes: Remove a remaining portion of the sacrificial gate to form a gate cavity; and A metal gate is formed in the gate cavity.

5. A method for manufacturing a semiconductor device, characterized in that, The method includes: A fin is formed above a substrate; A gate is formed above the fin; Multiple source / drain features are formed in the fin adjacent to the gate; Multiple interlayer dielectric structures are formed over the plurality of source / drain features, wherein the plurality of interlayer dielectric structures comprise silicon oxide; Remove a region containing a portion of the fin and a portion of the gate to form an opening; An insulating feature is formed in the opening; as well as A process is performed to etch a selected interlayer dielectric structure onto a bottom source / drain feature, wherein, during the process, the semiconductor device is free of silicon oxide at the insulating feature and on an exposed surface adjacent to the insulating feature.

6. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, Further includes: Forming a sidewall spacer, wherein the sidewall spacer is directly adjacent to the gate; and While removing the region containing the portion of the fin and the portion of the gate to form the opening, at least one upper portion of a portion of the sidewall spacer in that region is also removed.

7. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The gate is a sacrificial gate, and the method further includes: After forming the insulating feature in the opening, a remaining portion of the sacrificial gate is removed to form a gate cavity; and Before performing the process to etch the selected interlayer dielectric structure, a metal gate is formed in the gate cavity.

8. A semiconductor element, characterized in that, Include: One fin, located above a substrate; Multiple source / drain features are located in multiple grooves formed in the fin; and An insulating feature is located between the plurality of source / drain features and extends through the fin and into the substrate, wherein the insulating feature has an uppermost surface and wherein on the uppermost surface, the insulating feature is in contact with a non-oxide dielectric layer.

9. The semiconductor device as claimed in claim 8, characterized in that, An oxide layer is in contact with a lower portion of the insulating feature, and an upper portion of the insulating feature is located above the oxide layer.

10. The semiconductor device as claimed in claim 8, characterized in that, A conductive interconnect is located above a selected source / drain feature, wherein the non-oxide dielectric layer is in contact with the conductive interconnect and the insulating feature.

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