Bcd device and method of fabrication

Abstract

The application provides a BCD device and a preparation method, relates to the technical field of semiconductors, solves the problem that the BCD device in the prior art does not meet the industry test requirements, and the BCD device provided in the scheme is provided with a first silicon oxide layer rich in silicon, a silicon oxynitride layer and an oxide layer on a metal layer; the silicon oxynitride layer has a higher dielectric strength than the oxide layer, and can withstand a higher electric field strength without being broken down; the ACBV that can be withstood by the silicon oxynitride layer can meet the industry test requirements, and ensures that the device can operate stably for a long time under high voltage and high frequency signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a BCD device and a preparation method. BACKGROUND

[0002] BCD process is a process technology capable of fabricating bipolar, CMOS (Complementary Metal Oxide Semiconductor) and DMOS (Double-diffused Metal Oxide Semiconductor) on the same chip. With the development of integrated circuits, BCD process has become the mainstream process technology of integrated circuits due to its high integration, high reliability, voltage resistance and power saving advantages, and has broad market application prospects in the fields of power management, industrial control, consumer electronics and automotive electronics.

[0003] ACBV (Alternating Current Breakdown Voltage) is a way of testing the reliability of a device, which is used to test the voltage resistance of the dielectric layer in the device under high-frequency alternating voltage. However, the ACBV that the high-voltage-resistant isolation device (i.e., BCD device) integrated by the BCD process in the related art can withstand in the test fails to meet the industry test requirements, resulting in that the device cannot be stably operated for a long time under high voltage and high-frequency signals. SUMMARY

[0004] The present application provides a BCD device and a preparation method, which solves the problem that the BCD device in the related art fails to meet the industry test requirements. The ACBV that the BCD device provided in the present application can withstand can meet the industry test requirements, ensuring that the device can be stably operated for a long time under high voltage and high-frequency signals.

[0005] In a first aspect, the present application provides a BCD device, which includes a substrate layer, a second metal layer, an anti-reflection layer, a first silicon-rich silicon oxide layer, a silicon oxynitride layer, an oxide layer, a second silicon-rich silicon oxide layer and a passivation layer.

[0006] The substrate layer includes a dielectric layer, a first metal layer and a plurality of metal vias, the first metal layer is located below the dielectric layer and connected to the metal vias, the metal vias are provided in the dielectric layer, and the metal vias are filled with conductive metal;

[0007] The second metal layer is arranged on the substrate layer, the second metal layer is connected to the plurality of metal vias to communicate the first metal layer through the conductive metal in the metal vias, and the second metal layer is provided with a first groove in a target region, the target region being located between any two metal vias;

[0008] The anti-reflection layer is disposed on the second metal layer;

[0009] The first silicon-rich silicon oxide layer is disposed on the anti-reflection layer and covers the surface of the first trench;

[0010] The silicon oxynitride layer is disposed on the first silicon-rich silicon oxide layer and covers the first silicon-rich silicon oxide layer and forms the second trench at the target region;

[0011] The oxide layer is disposed on the silicon oxynitride layer and fills the second trench;

[0012] The second silicon-rich silicon oxide layer is disposed on the oxide layer;

[0013] The passivation layer is disposed on the second silicon-rich silicon oxide layer.

[0014] In a second aspect, the application further provides a BCD device preparation method, which comprises:

[0015] Providing a substrate layer, the substrate layer comprising a dielectric layer, a first metal layer and a plurality of metal vias, the first metal layer being located below the dielectric layer and connected to the metal vias, and the metal vias being disposed in the dielectric layer;

[0016] Sequentially depositing a second metal layer and an anti-reflection layer on the substrate layer to connect the second metal layer to the first metal layer through the metal vias;

[0017] Etching the second metal layer and the anti-reflection layer and forming a first trench in a target region, the target region being located between any two metal vias;

[0018] Uniformly depositing a first silicon-rich silicon oxide layer on the anti-reflection layer and the first trench, the first silicon-rich silicon oxide layer being used to protect the second metal layer and the anti-reflection layer;

[0019] Uniformly depositing a silicon oxynitride layer on the first silicon-rich silicon oxide layer and forming a second trench on the silicon oxynitride layer at a position corresponding to the target region;

[0020] Depositing an oxide layer on the silicon oxynitride layer and filling the second trench through the oxide layer;

[0021] Performing a planarization treatment on the oxide layer and sequentially depositing a second silicon-rich silicon oxide layer and a passivation layer on the oxide layer.

[0022] The BCD device of the present application deposits a first silicon-rich silicon oxide layer, a silicon oxynitride layer and an oxide layer on the metal layer. The silicon oxynitride layer has a higher dielectric strength than the oxide layer and can withstand a higher electric field strength without being broken down. Moreover, in the silicon oxynitride layer, the silicon oxynitride structure formed by nitrogen element doping can enhance the compactness of the material, reduce micropores and defects, thereby reducing the leakage current and increasing the breakdown voltage that the device can withstand. In addition, the energy band structure of the silicon oxynitride layer is wider, further suppressing the tunneling effect of the carriers and enhancing the insulation performance. Moreover, the nitrogen element in the silicon oxynitride can form a stronger chemical bond (such as Si-N bond), improve the charge injection resistance of the material, reduce the retention of charges, thereby maintaining a stable electric field distribution and a higher breakdown voltage. Therefore, the silicon oxynitride layer provided on the BCD device can increase the voltage withstand performance of the device, thereby improving the ACBV of the device and providing a favorable guarantee for the long-term normal operation and service life of the device. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A structure schematic diagram of the BCD device provided by an embodiment of the present application is shown.

[0024] Figure 2 A schematic diagram of the ACBV test results provided by an embodiment of the present application is shown.

[0025] Figure 3 A step schematic diagram of the BCD device preparation method provided by an embodiment of the present application is shown.

[0026] Figure 4 A step schematic diagram of etching to form the first groove provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be further described in detail below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, but not to limit the embodiments of the present application. In addition, it should be noted that, in order to facilitate the description, only the parts related to the embodiments of the present application are shown in the drawings, and those skilled in the art should understand that, as long as the technical features are not contradictory, any combination of technical features can constitute an optional embodiment.

[0028] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances to facilitate the implementation of the embodiments of the present application in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the objects before and after are in an "or" relationship. In the description of the present application, "a plurality of" means two or more, and "several" means one or more.

[0029] BCD process is a process technology for manufacturing Bipolar, CMOS and DMOS devices on the same chip. Since the BCD process technology integrates the advantages of the above three devices, it makes the BCD process a mainstream process technology of integrated circuits. With the development of integrated circuits, BCD process has broad market application prospects in the fields of power management, industrial control, consumer electronics and automotive electronics due to its advantages of high integration, high reliability, voltage resistance and power saving.

[0030] ACBV (Alternating Current Breakdown Voltage) is a way of testing the reliability of a device, which is used to test the voltage resistance of the dielectric layer in the device under high-frequency alternating voltage. For high-voltage isolation devices integrated by BCD process, high ACBV is a key factor to ensure the long-term stability of the device under high-voltage and high-frequency signals. In the related art, the high-voltage isolation devices integrated by BCD process (i.e. BCD devices) usually use a relatively thick metal interlayer dielectric layer as the dielectric layer of the isolation capacitor, but the ACBV it can withstand is still lower than the voltage requirement of 6kV set in the industry test requirement, which leads to the device cannot run stably under high-voltage and high-frequency signals for a long time.

[0031] To this end, the present application provides a BCD device, Figure 1The structure schematic diagram of the BCD device provided by the embodiment of the present application comprises a substrate layer 101, a second metal layer 102, an anti-reflection layer 103, a first silicon-rich silicon oxide layer 104, a silicon oxynitride layer 105, an oxide layer 106, a second silicon-rich silicon oxide layer 107 and a passivation layer 108. The substrate layer 101 comprises a dielectric layer 1011, a first metal layer and a plurality of metal vias 1012, the first metal layer is below the dielectric layer 1011 and connected to the metal vias 1012, the metal vias 1012 are arranged in the dielectric layer 1011, and the metal vias 1012 are filled with conductive metal. The second metal layer 102, the anti-reflection layer 103, the first silicon-rich silicon oxide layer 104, the silicon oxynitride layer 105, the oxide layer 106, the second silicon-rich silicon oxide layer 107 and the passivation layer 108 can be used as a top dielectric layer structure of the BCD device, and the substrate layer 101 can be used as a substrate of the top structure of the BCD device, so as to deposit the above-mentioned top dielectric layer structure thereon.

[0032] The second metal layer 102 is arranged on the substrate layer 101, and the second metal layer 102 is connected to the plurality of metal vias 1012 to communicate the first metal layer through the conductive metal in the metal vias 1012, and the second metal layer 102 is provided with a first trench in a target region, and the target region is between any two metal vias 1012. Optionally, the width of the first trench is greater than or equal to 1.5 um and less than or equal to 3.5 um, so as to ensure that the second metal layer 102 forms a trench for isolation, and the first silicon-rich silicon oxide layer 104, the silicon oxynitride layer 105 and the oxide layer 106 can be deposited, thereby ensuring the insulation performance of the isolation part.

[0033] The anti-reflection layer 103 is arranged on the second metal layer 102. The first silicon-rich silicon oxide layer 104 is arranged on the anti-reflection layer 103, and the first silicon-rich silicon oxide layer 104 covers the surface of the first trench. Optionally, the first silicon-rich silicon oxide layer 104 is used to protect the second metal layer and the anti-reflection layer 103. That is, on the second metal layer 102, the first trench can separate the metals on both sides of the trench, and the first silicon-rich silicon oxide layer 104 covers the second metal layer 102, and the first silicon-rich silicon oxide layer 104 also covers the surface of the first trench, such as the side surface and the bottom surface of the first trench, so that the width and the depth of the first trench are reduced.

[0034] The silicon oxynitride layer 105 is arranged on the first silicon-rich silicon oxide layer 104, and covers the first silicon-rich silicon oxide layer 104 and forms a second trench in the target region. The silicon oxynitride layer 105 also covers the first silicon-rich silicon oxide layer 104 in the first trench, thereby further reducing the width and depth of the first trench to obtain the second trench. The oxide layer 106 is arranged on the silicon oxynitride layer 105 and fills the second trench, that is, the oxide layer 106 not only fills the second trench, but also is located on the silicon oxynitride layer 105, and the thickness of the oxide layer 106 is greater than that of the silicon oxynitride layer 105. Moreover, the second silicon-rich silicon oxide layer 107 is arranged on the oxide layer 106, and the passivation layer 108 is arranged on the second silicon-rich silicon oxide layer 107. Optionally, the passivation layer 108 is a silicon nitride layer, which has the characteristics of high strength, high temperature resistance and anti-oxidation corrosion, and helps to protect the internal structure of the device.

[0035] The silicon oxynitride layer has higher dielectric strength and can withstand higher electric field intensity without being broken down compared with the oxide layer. Moreover, in the silicon oxynitride layer, the silicon oxynitride structure formed by nitrogen element doping can enhance the compactness of the material, reduce micropores and defects, thereby reducing the leakage current and improving the breakdown voltage that the device can withstand. In addition, the energy band structure of the silicon oxynitride layer is wider, which further suppresses the tunneling effect of the carriers and enhances the insulation performance. Moreover, the nitrogen element in the silicon oxynitride can form a stronger chemical bond (such as Si-N bond), improve the charge injection resistance of the material, reduce the retention of charges, thereby maintaining a stable electric field distribution and a higher breakdown voltage. Therefore, by arranging the silicon oxynitride layer on the silicon-rich silicon oxide layer, the breakdown voltage performance of the device can be improved, so that the ACBV of the device is improved, which provides an advantageous guarantee for the long-term normal operation and life improvement of the device.

[0036] The BCD device of the present application and the device prepared by the related art are subjected to the same ACBV test. After the ACBV test, the measured ACBV result is as shown in Figure 2 Figure 2 The ACBV test result diagram provided by an embodiment of the present application is shown in the figure. The left side of the figure is the result of the BCD device prepared by the related art after the ACBV test, and the value is 5.96kV. The right side of the figure is the result of the BCD device of the present application after the ACBV test, and the value is 6.85kV. By comparison, the ACBV value of the BCD device of the present application reaches 6.85kV, which not only meets the industry test requirement of ACBV>6.00kV, but also increases by 14.9% compared with the related art, that is, the ACBV of the BCD device provided by the present application is obviously improved, which provides an advantageous guarantee for the long-term normal operation and life improvement of the device.

[0037] ​In some embodiments, the thickness of the silicon oxynitride layer is greater than or equal to 900A and less than or equal to 1500A. By setting the thickness of the silicon oxynitride layer, the charge injection resistance of the silicon oxynitride layer is improved, the retention of the charge is more effectively reduced, and the voltage resistance performance of the device is increased. Alternatively, in an embodiment, the thickness of the silicon oxynitride layer is 1200A. The silicon oxynitride layer with the thickness can enable the BCD device to meet the voltage resistance performance requirements, and the ACBV value after testing can meet the industry testing requirements. It should be noted that the thickness of the silicon oxynitride layer can also be 1000A or 1300A, which can be configured according to the actual process accuracy.

[0038] The application also provides a BCD device preparation method for preparing the above-mentioned BCD device, Figure 3 The BCD device preparation method provided by an embodiment of the application is shown in the following steps. In the process of preparing the BCD device, the bipolar, CMOS and DMOS can be prepared according to the BCD process, the dielectric layer can be formed by deposition, and the regions on the prepared bipolar, CMOS or DMOS can be connected outwardly through the metal via. For example, the metal silicide layer of the gate region of the CMOS can be connected through the corresponding metal via, so that the gate region of the CMOS can be connected to other metal layers. Then, the top dielectric layer structure is formed on the substrate for processing, so as to improve the ACBV of the device. The specific steps are as follows:

[0039] In step S110, a substrate layer is provided, which includes a dielectric layer, a first metal layer and a plurality of metal vias. The first metal layer is located below the dielectric layer and is connected to the metal vias. The metal vias are arranged in the dielectric layer.

[0040] The substrate layer includes a dielectric layer, a first metal layer and a plurality of metal vias. For example, the dielectric layer is formed by deposition on the prepared bipolar, CMOS and DMOS. The first metal layer includes the metal silicide layer mentioned above, which can connect the gate region of the CMOS to other metal layers through the metal via. It can be understood that the first metal layer also includes the metal layer to be connected on the bipolar, CMOS and DMOS. In the process of preparing the top dielectric layer of the BCD device, the above-mentioned layer structure is used as the substrate layer. Alternatively, the substrate layer can also include a plurality of metal layers and oxide layers formed by layering.

[0041] In addition, the etching of the metal via can be based on a photolithography process. The via is etched in the corresponding region, and the conductive metal is filled in the formed metal via, such as tungsten or copper, by chemical vapor deposition or electroplating.

[0042] Step S120, sequentially depositing a second metal layer and an anti-reflection layer on the substrate layer to connect the second metal layer and the first metal layer through the metal via.

[0043] The deposited second metal layer and the anti-reflection layer can be sequentially deposited on the substrate layer by chemical vapor deposition or physical vapor deposition, wherein the second metal layer is on the substrate layer, and the anti-reflection layer is on the second metal layer. The first metal layer and the second metal layer are connected through the metal via by depositing the second metal layer. Alternatively, the deposited anti-reflection layer is generated by depositing silicon oxynitride, i.e., the anti-reflection layer is another silicon oxynitride layer and is arranged on the second metal layer.

[0044] Step S130, etching the second metal layer and the anti-reflection layer, and forming a first trench in the target region.

[0045] The target region is between any two metal vias. The first trench is formed in the target region by etching the second metal layer and the anti-reflection layer. Figure 4 The step of etching to form the first trench provided by an embodiment of the present application is shown in the schematic diagram. In an embodiment, the specific steps of etching to form the first trench are as follows:

[0046] Step S210, performing photoetching development on the anti-reflection layer to determine a first etching region on the anti-reflection layer and a second etching region on the second metal layer in the target region.

[0047] Step S220, sequentially etching the first etching region of the anti-reflection layer and the second etching region of the second metal layer to form a first trench in the target region.

[0048] It is conceivable that the first etching region and the second etching region are the same size. After photoetching development, the position of the first etching region on the anti-reflection layer can be determined. Based on this, the second etching region on the second metal layer can also be determined. For example, after completing etching of the first etching region on the anti-reflection layer, the second etching region on the second metal layer is exposed, and then etching the second etching region, i.e., sequentially etching the first etching region of the anti-reflection layer and the second etching region of the second metal layer to form a first trench in the target region.

[0049] Optionally, the etching of the anti-reflective layer can be implemented based on a dry etching method, such as a reactive ion etching process, in which plasma is generated by gas discharge and reacts with the surface of the anti-reflective layer, thereby continuously etching the anti-reflective layer. Optionally, the etching of the second metal layer can be implemented based on a dry etching method, such as a plasma etching process, in which metal surface is bombarded by Cl2 / BCl3 and other plasma, thereby etching the metal layer. After the etching of the anti-reflective layer and the second metal layer is completed, the first trench is formed in the target region. By physical bombardment or chemical reaction between plasma or gaseous reactants and materials in the dry etching, the first trench can have a good verticality.

[0050] In step S140, the first silicon-rich silicon oxide layer is formed by uniformly depositing on the anti-reflective layer and the first trench.

[0051] The first silicon-rich silicon oxide layer is used to protect the second metal layer and the anti-reflective layer. The first silicon-rich silicon oxide layer is deposited on the anti-reflective layer and the first trench, and the first silicon-rich silicon oxide layer can cover the surface of the first trench, but the first silicon-rich silicon oxide layer does not fill the first trench. Optionally, the first silicon-rich silicon oxide layer is deposited based on a CVD (Chemical Vapor Deposition) process, such as by controlling the gas pressure and temperature to enable the deposition to cover the surface of the first trench when the deposition is performed in the first trench. For example, the deposition pressure can be controlled to be greater than or equal to 1 Torr and less than or equal to 4 Torr, and the temperature can be controlled to be greater than or equal to 350°C and less than or equal to 400°C, thereby depositing the first silicon-rich silicon oxide layer on the anti-reflective layer and the first trench. In some embodiments, after the deposition of the first silicon-rich silicon oxide layer is completed, an annealing process is further performed, such as by introducing N2 and H2 to perform the annealing process at a temperature greater than or equal to 350°C and less than or equal to 420°C, thereby improving the surface quality of the first silicon-rich silicon oxide layer.

[0052] In step S150, the silicon oxynitride layer is formed by uniformly depositing on the first silicon-rich silicon oxide layer, and the second trench is formed in the target region on the silicon oxynitride layer.

[0053] The second trench is formed by depositing a silicon oxynitride layer on the target region, i.e., the silicon oxynitride layer also does not fill the first trench. Optionally, the silicon oxynitride layer is deposited based on a CVD process, such as by controlling the gas pressure and temperature to deposit the silicon oxynitride layer on the first silicon-rich silicon oxide layer. For example, the gas pressure is controlled to be greater than or equal to 2 Torr and less than or equal to 5 Torr, and the temperature is controlled to be greater than or equal to 350 °C and less than or equal to 400 °C, while the corresponding gas is introduced, to deposit the silicon oxynitride layer. In some embodiments, after the deposition of the silicon oxynitride layer is completed, an annealing process is further performed, such as by introducing N2 and H2 at a temperature greater than or equal to 350 °C and less than or equal to 420 °C, to improve the density of the silicon oxynitride layer, reduce micropores and defects, and thus reduce the leakage current, thereby helping to improve the breakdown voltage that the device can withstand.

[0054] In step S160, an oxide layer is deposited on the silicon oxynitride layer, and the second trench is filled with the oxide layer.

[0055] In this regard, the oxide layer fills the second trench, and the oxide layer is located on the silicon oxynitride layer. In the process of preparing the oxide layer, chemical vapor deposition can be used to deposit the oxide on the silicon oxynitride layer, thereby covering the silicon oxynitride layer and the second trench in a large area.

[0056] In step S170, a planarization process is performed on the oxide layer, and a second silicon-rich silicon oxide layer and a passivation layer are sequentially deposited on the oxide layer.

[0057] After the oxide layer is formed, the surface of the oxide layer is further planarized to make the surface of the oxide layer flat, and then a second silicon-rich silicon oxide layer and a passivation layer are sequentially deposited on the oxide layer, and the device is protected by the second silicon-rich silicon oxide layer and the passivation layer.

[0058] In some embodiments, a CMP (Chemical Mechanical Polishing) process is used to remove uneven parts on the surface of the oxide layer to planarize the surface of the oxide layer. High-precision planarization of the oxide layer is achieved by combining chemical etching and mechanical grinding technologies, for example, by adding chemical reagents and abrasive particles to the polishing liquid, and by applying mechanical pressure and friction to remove uneven parts on the surface of the oxide layer.

[0059] From the above scheme, the second metal layer is sequentially deposited with the anti-reflective layer, the first silicon-rich silicon oxide layer and the silicon oxynitride layer, so as to better protect the second metal layer, and the interface state density of the silicon oxynitride layer formed in the growth process is low, reducing the charge traps and defects at the interface. By reducing the interface state density, the silicon oxynitride layer can effectively suppress the occurrence of local breakdown, thereby helping to increase the device withstand voltage performance, so as to improve the ACBV of the device, providing a favorable guarantee for the long-term normal operation and life of the device.

[0060] It should also be noted that the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or apparatus that includes a list of elements not only includes those elements, but also includes other elements not explicitly listed, or inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0061] It should be noted that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A BCD device, characterized in that, include: The substrate layer includes a dielectric layer, a first metal layer and a plurality of metal vias, wherein the first metal layer is located below the dielectric layer and connected to the metal vias, the metal vias pass through the dielectric layer and are filled with conductive metal; A second metal layer is disposed on the substrate layer. The second metal layer is connected to a plurality of metal vias to communicate with the first metal layer through conductive metal in the metal vias. The second metal layer has a first trench in a target area, the target area being located between any two metal vias. An anti-reflective layer is disposed on the second metal layer; A first silicon-rich silicon oxide layer is disposed on the antireflective layer and covers the surface of the first trench. A silicon oxynitride layer is disposed on the first silicon-rich silicon oxide layer and covers the first silicon-rich silicon oxide layer, and a second trench is formed in the target region; An oxide layer is disposed on the silicon oxynitride layer and fills the second trench; A second silicon-rich silicon oxide layer is disposed on the oxide layer; A passivation layer is disposed on the second silicon-rich silicon oxide layer.

2. The BCD device according to claim 1, characterized in that, The thickness of the silicon oxynitride layer is greater than or equal to 900 Å and less than or equal to 1500 Å.

3. The BCD device according to claim 1 or 2, characterized in that, The width of the first trench is greater than or equal to 1.5 μm and less than or equal to 3.5 μm.

4. The BCD device according to claim 1, characterized in that, The anti-reflective layer is a layered structure formed by silicon oxynitride deposition.

5. The BCD device according to claim 1, characterized in that, The passivation layer is a silicon nitride layer.

6. A method for fabricating a BCD device, characterized in that, The method for preparing the BCD device according to any one of claims 1-5 includes: A substrate layer is provided, the substrate layer including a dielectric layer, a first metal layer and a plurality of metal vias, the first metal layer being located below the dielectric layer and connected to the metal vias, the metal vias being disposed through the dielectric layer; A second metal layer and an anti-reflection layer are sequentially deposited on the substrate to connect the second metal layer to the first metal layer through the metal via. The second metal layer and the anti-reflective layer are etched, and a first trench is formed in the target area, which is located between any two metal vias; A first silicon-rich silicon oxide layer is uniformly deposited on the anti-reflection layer and the first trench, and the first silicon-rich silicon oxide layer is used to protect the second metal layer and the anti-reflection layer. A silicon oxynitride layer is uniformly deposited on the first silicon-rich silicon oxide layer, and a second trench is formed on the silicon oxynitride layer at a position corresponding to the target region. An oxide layer is deposited on the silicon oxynitride layer, and the second trench is filled through the oxide layer; The oxide layer is planarized, and a second silicon-rich silicon oxide layer and a passivation layer are sequentially deposited on the oxide layer.

7. The method for fabricating a BCD device according to claim 6, characterized in that, The etching of the second metal layer and the anti-reflective layer, and the formation of a first trench in the target area, includes: Photolithography is performed on the anti-reflection layer to determine a first etchable area on the anti-reflection layer and a second etchable area on the second metal layer in the target area. The first etchable area of ​​the anti-reflective layer and the second etchable area of ​​the second metal layer are sequentially etched to form the first trench in the target area.

8. The method for fabricating a BCD device according to claim 6, characterized in that, Both the first silicon-rich silicon oxide layer and the silicon oxynitride layer are formed by deposition using a CVD process.

9. The method for fabricating a BCD device according to claim 6 or 8, characterized in that, The method further includes: An annealing process is performed after the first silicon-rich silicon oxide layer is formed. Furthermore, an annealing process is performed after the silicon oxynitride layer is formed.

10. The method for fabricating a BCD device according to claim 6, characterized in that, The planarization process for the oxide layer includes: The surface of the oxide layer is planarized by removing uneven portions on the surface using a CMP process.

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