Semiconductor device including SiC semiconductor body

Abstract

A semiconductor device including a SiC semiconductor body is presented. The SiC semiconductor body includes a mesa between the trench gate structures. The mesa includes a one-sided channel region. The one-sided channel region abuts a first mesa sidewall of the opposing first and second mesa sidewalls. The mesa further includes a first region of the first conductivity type adjoining the first mesa sidewall and a top surface of the mesa. The mesa further includes a second region of a second conductivity type adjoining a second mesa sidewall and a top surface of the mesa. The first region and the second region are separated by a pn junction at the top surface of the mesa. The widths of the first zones at the top surface of the table top alternate between a first width range and a second width range along the longitudinal direction of the table top, the first width range being greater than 10% of the width of the table top at the top surface and less than 50% of the width of the table top at the top surface, and the second width range is greater than or equal to 50% of the width of the mesa at the top surface and less than 90% of the width of the mesa at the top surface.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device comprising a SiC semiconductor body. Background Art

[0002] The development of next-generation SiC semiconductor devices (such as insulated-gate field-effect transistors (IGFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or insulated-gate bipolar transistors (IGBTs)) aims to improve electrical device characteristics and reduce costs by shrinking device geometry. While cost reduction is possible through shrinking device geometry, various trade-offs and challenges must be met when increasing device functionality per unit area. For example, when trenches are arranged relative to or relative to doped regions, the resistance R of the on-state for a given area must be reduced due to process-related variations. on xA can be challenging. Such process-related variations can be caused by process techniques including different lithography levels. For example, when trying to reduce the resistance R of the on-state in a specific area... on When the width of the countertop is reduced, forming contacts (such as contact plugs, contact lines, or through holes) on the countertop area can become challenging.

[0003] When reducing the geometry of a device, there is a need to improve the electrical contacts on the mesa area. Summary of the Invention

[0004] One example of this disclosure relates to a semiconductor device including a SiC semiconductor body. The SiC semiconductor body includes a mesa between trench gate structures. The mesa includes a single-sided channel region. The single-sided channel region abuts a first mesa sidewall among opposing first and second mesa sidewalls. The mesa further includes a first region of a first conductivity type abutting the first mesa sidewall and a top surface of the mesa. The mesa further includes a second region of a second conductivity type abutting a second mesa sidewall and a top surface of the mesa. The first and second regions are separated by a pn junction at the top surface of the mesa. The width of the first region at the top surface of the mesa alternates between a first width range and a second width range along the longitudinal direction of the mesa. The first width range is greater than 10% and less than 50% of the width of the mesa at the top surface. The second width range is greater than or equal to 50% and less than 90% of the width of the mesa at the top surface.

[0005] Another example of this disclosure relates to a semiconductor device including a SiC semiconductor body. The SiC semiconductor body includes a mesa between trench gate structures. The mesa includes a one-sided channel region. The one-sided channel region abuts a first mesa sidewall of opposing first and second mesa sidewalls. The mesa further includes a first lateral region of a first conductivity type adjacent to a top surface of the mesa. The first lateral region extends from the first mesa sidewall to a second mesa sidewall. The mesa further includes a second lateral region of a second conductivity type adjacent to the top surface of the mesa. The second lateral region extends from the first mesa sidewall to the second mesa sidewall. The first lateral region and the second lateral region are arranged alternately along the longitudinal direction of the mesa.

[0006] Another example of this disclosure relates to a method of manufacturing a semiconductor device. The method includes forming trench gate structures in a SiC semiconductor body. Mesa are disposed between the trench gate structures. The method further includes forming a one-sided channel region in the mesa. The one-sided channel region is adjacent to a first mesa sidewall of opposing first and second mesa sidewalls. The method further includes forming a first region of a first conductivity type in the mesa. The first region is adjacent to the first mesa sidewall and the top surface of the mesa. The method further includes forming a second region of a second conductivity type in the mesa. The second region is adjacent to a second mesa sidewall and the top surface of the mesa. The first and second regions are separated by a pn junction at the top surface of the mesa. The width of the first region at the top surface of the mesa alternates between a first width range and a second width range along the longitudinal direction of the mesa. The first width range is greater than 10% and less than 50% of the width of the mesa at the top surface. The second width range is greater than or equal to 50% and less than 90% of the width of the mesa at the top surface.

[0007] Another example of this disclosure relates to a method of manufacturing a semiconductor device. The method includes forming trench gate structures in a SiC semiconductor body. Mesa are disposed between the trench gate structures. The method further includes forming a one-sided channel region in the mesa. The one-sided channel region abuts a first mesa sidewall of opposing first and second mesa sidewalls. The method further includes forming a first lateral region of a first conductivity type on the top surface of the adjacent mesa. The first lateral region extends from the first mesa sidewall to the second mesa sidewall. The method further includes forming a second lateral region of a second conductivity type on the top surface of the adjacent mesa. The second lateral region extends from the first mesa sidewall to the second mesa sidewall. The first lateral region and the second lateral region are arranged alternately along the longitudinal direction of the mesa.

[0008] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of semiconductor devices and methods of manufacturing semiconductor devices and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0010] Figure 1 and Figure 2 This is an exemplary process diagram for manufacturing semiconductor devices.

[0011] Figures 3A to 3D A top view of a semiconductor device including a mesa laterally limited by a trench gate structure is illustrated schematically and exemplary.

[0012] Figure 4A and Figure 4B It is used to illustrate along the line in Figures 3A to 3D The top view shows a cross-sectional view of an exemplary layout of the semiconductor device, taken by lines AA' and BB'.

[0013] Figure 5 A top view of a semiconductor device including a mesa laterally limited by a trench gate structure is illustrated schematically and exemplary.

[0014] Figure 6A and Figure 6B It is used to illustrate along the line in Figure 5 The top view shows a cross-sectional view of an exemplary layout of the semiconductor device, taken by lines AA' and BB'.

[0015] Figure 7 A top view of a semiconductor device including a mesa laterally limited by a trench gate structure is illustrated schematically and exemplary.

[0016] Figure 8A and Figure 8B It is used to illustrate along the line in Figure 7 The top view shows a cross-sectional view of an exemplary layout of the semiconductor device, taken by lines AA' and BB'. Detailed Implementation

[0017] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate, by way of illustration, specific examples in which a semiconductor substrate can be processed. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, a feature illustrated or described for one example may be used on or in combination with other examples to produce yet another example. It is intended that this disclosure include such modifications and variations. The use of concrete language to describe these examples should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements are designated by the same reference numerals in different drawings.

[0018] The terms “having,” “containing,” “including,” “comprising,” and the like are open-ended and indicate the presence of the stated structure, element, or feature, but do not exclude the presence of additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0019] The term "electrical connection" can describe a permanent low-resistance connection between electrically connected elements, such as a direct contact between related elements or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrical coupling" can include one or more intermediary elements adapted for signal and / or power transmission that can be connected between electrically coupled elements (e.g., elements controllable to temporarily provide a low-resistance connection in a first state and temporarily provide high-resistance electrical decoupling in a second state).

[0020] If "or" is used to combine two elements A and B, this should be understood as disclosing all possible combinations: A only, B only, and A and B (unless otherwise explicitly or implicitly defined). Alternative wording for the same combination is "at least one of A and B" or "A and / or B". This is similarly modified for combinations with more than two elements.

[0021] The range given for physical dimensions includes boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value, such as "at most" and "at least".

[0022] The main components of a layer or structure derived from a chemical compound or alloy are elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0023] The term “on” should not be interpreted as simply “directly on”. Rather, if an element is positioned “on” another element (e.g., one layer is “on” another layer or “on” a substrate), then additional components (e.g., additional layers) may be positioned between the two elements (e.g., if a layer is “on” a substrate, then additional layers may be positioned between the layer and the substrate).

[0024] The specification and accompanying drawings merely illustrate the principles of this disclosure. Furthermore, all examples described herein are primarily and explicitly intended for illustrative purposes only, to aid the reader in understanding the principles of this disclosure and the concepts contributed by one or more inventors to the field. All statements herein recounting the principles, aspects, and examples of this disclosure, as well as specific examples thereof, are intended to cover their equivalents.

[0025] An example of a semiconductor device configuration includes a SiC semiconductor body. The SiC semiconductor body includes a mesas between trench gate structures.

[0026] The countertop includes a single-sided channel area. The single-sided channel area is adjacent to the first countertop sidewall of the first and second opposing countertop sidewalls.

[0027] The mesa further includes a first region of a first conductivity type adjacent to the first mesa sidewall and the top surface of the mesa. The mesa further includes a second region of a second conductivity type adjacent to the second mesa sidewall and the top surface of the mesa. The first and second regions are separated by a pn junction at the top surface of the mesa.

[0028] The width of the first zone at the top surface of the countertop can alternate between a first width range and a second width range along the longitudinal direction of the countertop. The first width range is greater than 10% of the countertop width at the top surface and can be less than 50% of the countertop width at the top surface. The second width range can be greater than or equal to 50% of the countertop width at the top surface and can be less than 90% of the countertop width at the top surface. Therefore, the minimum width of the first zone can be within the first width range, and the maximum width of the first zone can be within the second width range. Similarly, the minimum width of the second zone is therefore within the first width range, and the maximum width of the second zone is therefore within the second width range. At a predefined position along the longitudinal direction, the sum of the widths of the first and second zones can correspond to the width of the countertop. For example, the difference between the minimum width and the maximum width of the first zone can be within the range of 20% to 80%, or 30% to 70%, or 40% to 60% of the countertop width.

[0029] For example, the semiconductor device may be part of an integrated circuit, or it may be a discrete semiconductor device or semiconductor module. For example, the semiconductor device may be or may include an insulated-gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). The semiconductor device may be a vertical semiconductor device having a load current flowing between a first surface and a second surface opposite the first surface in a vertical direction. Vertical power semiconductor devices may be configured to conduct currents greater than 1A, or greater than 10A, or greater than 30A, or greater than 50A, or greater than 75A, or even greater than 100A, and may be further configured to block voltages between load electrodes, such as the voltage between the collector and emitter of an IGBT or the voltage between the drain and source of a MOSFET, in the range of hundreds to thousands of volts, for example, 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, and 10kV. For example, the blocking voltage can correspond to the voltage level specified in the datasheet of a power semiconductor device.

[0030] Semiconductor devices can be based on SiC semiconductor bodies derived from crystalline SiC materials. As an example, the crystalline SiC material can have a hexagonal lattice. For example, the semiconductor material can be 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. According to one example, the semiconductor material is 4H polytype silicon carbide (4H-SiC). The SiC semiconductor body can include or consist of a semiconductor substrate having, not having, or having one or more semiconductor layers (e.g., epitaxial growth layers). For example, one of the semiconductor layers can be a doped semiconductor layer of a current-diffusing layer.

[0031] The top surface of the mesa may define a front or top surface of the SiC semiconductor body, and the SiC semiconductor body may further have a second surface, for example, which may be a back or rear surface of the SiC semiconductor body. For example, the SiC semiconductor body may be attached to a lead frame via the second surface. For example, bonding pads may be arranged above the first surface of the SiC semiconductor body, and bonding wires may be bonded to the bonding pads.

[0032] To achieve the desired current-carrying capacity, SiC semiconductor devices can be designed from multiple SiC semiconductor device cells connected in parallel. These parallel-connected SiC semiconductor device cells can be, for example, formed in a strip or strip-segmented shape. Of course, SiC semiconductor device cells can also have any other shape, such as circular, elliptical, or polygonal (e.g., hexagonal or octagonal). The semiconductor device cells can be arranged within a transistor cell region of the SiC semiconductor body. The transistor cell region can be an area where the emitter region of the IGBT (or the source region of the MOSFET) and the collector region of the IGBT (or the drain region of the MOSFET) are arranged opposite each other in a vertical direction. In the transistor cell region, load current can enter or leave the SiC semiconductor body of the semiconductor device, for example via contact plugs or contact lines on the top surface of the mesa. The semiconductor device can further include an edge-terminating region, which may include a termination structure. In the blocking mode or reverse-biased mode of the semiconductor device, the blocking voltage between the transistor cell region and the field-free region decreases laterally across the termination structure. The termination structure can have a higher or slightly lower voltage blocking capability than the transistor cell region. For example, the termination structure may include a junction termination extension (JTE) with or without lateral doping variation (VLD), one or more laterally separated guard rings, or any combination thereof.

[0033] For example, the mesa can be laterally confined by the trench gate structure, such as along a second lateral direction. The longitudinal direction of the mesa can be a first lateral direction extending perpendicular to the second lateral direction. The longitudinal direction and the second lateral direction of the mesa can be perpendicular to a vertical direction. For example, each trench gate structure can include a gate dielectric and a gate electrode.

[0034] Electrical contacts on the top surface of the mesa (e.g., linear contacts extending longitudinally) can directly contact the first and second regions on the top surface of the mesa. By varying the width of the first region on the top surface, and conversely, varying the width of the second region on the top surface along the longitudinal direction of the mesa and within the width range described herein, the negative effects of reduced contact resistance or minimal contact width caused by a reduction in device geometry (e.g., mesa width) can be offset. This allows for improved R when reducing device geometry. on xA. Furthermore, the improved contact resistance of the n-region and p-region at the top surface of the mesa allows for stabilization of the n-region and p-region at the source or emitter potential. This can allow for improved switching behavior of the device.

[0035] For example, the first region can be the source region. The second region can be the contact region. The first depth from the bottom side of the contact region to the top surface of the mesa can be greater than the second depth from the bottom side of the source region to the top surface of the mesa.

[0036] For example, the second region may be part of a continuous region of a second conductivity type. The continuous region may be adjacent to the second mesa sidewall and the bottom side of the trench gate structure. For example, the vertical doping concentration distribution of the continuous region may include multiple doping concentration distributions of doped regions that partially overlap along the vertical direction. The bottom portion of the continuous region may be configured to shield the gate dielectric of the trench gate structure from the effects of a high electric field. For example, the bottom portion of the continuous region may be laterally adjacent to a current-diffusion region of a first conductivity type. The current-diffusion region may have a higher doping concentration than the drift region. For example, the drift region may be adjacent to the bottom side of the current-diffusion region.

[0037] For example, the continuous region can completely cover or line the second sidewall from the bottom side of the trench gate structure to the top surface of the mesa.

[0038] For example, the semiconductor device may further include a body region of a second conductivity type. The body region may be laterally disposed between the continuous region and the first mesa sidewall. The body region may abut the first sidewall of the mesa. A portion of the body region adjacent to the first sidewall may define a one-sided channel region. For example, a contact region or a second region may terminate vertically within the body region, for example, at least relative to a cross-sectional view taken along the longitudinal direction of the mesa, wherein the contact region or the second region has a greater width than the first region or the source region.

[0039] For example, the semiconductor device may further include a buried third region of a first conductivity type. For example, the buried third region may be adjacent to the bottom side of the first region and may allow for a reduction in the path resistance of the channel current from the single-sided channel region to the contact on the top surface of the mesa in those segments along the mesa region, wherein on the top surface portion, the contact region or the second region is wider than the source region or the first region.

[0040] For example, the maximum doping concentration in the first region can be at least an order of magnitude greater than the maximum doping concentration in the buried third region.

[0041] For example, in a top view of the top surface of the tabletop, the shape of the first region along the longitudinal direction can be at least one of a sine wave, a square wave, a triangular wave, or a sawtooth wave. Other shapes having minimum and maximum widths that alternate between the first and second width ranges can also allow for the technical benefits described herein.

[0042] For example, the first region can be n ++ The doped source region. The second region has more than 10% greater surface coverage over the top surface of the mesa than the first region. This can be advantageous when the electrical contact properties of the n-doped and p-doped regions differ from each other.

[0043] For example, the first region can be n ++The doped source region. The surface coverage of the second region on the top surface of the mesa can be equal to the surface coverage of the first region on the top surface of the mesa. For example, this can allow maximizing the electrical contact surface share of both the n-doped and p-doped regions.

[0044] The details regarding the structural, functional, or technical benefits of the features described above relative to semiconductor devices (such as FETs or IGBTs) also apply to examples of semiconductor devices further described below.

[0045] Another configuration example relates to a semiconductor device including a SiC semiconductor body. The SiC semiconductor body includes a mesa between trench gate structures. The mesa includes a single-sided channel region. The single-sided channel region abuts a first mesa sidewall adjacent to opposing first and second mesa sidewalls. The SiC semiconductor body further includes a first lateral region of a first conductivity type adjacent to the top surface of the mesa. The first lateral region can extend from the first mesa sidewall to a second mesa sidewall. The SiC semiconductor body further includes a second lateral region of a second conductivity type adjacent to the top surface of the mesa. The second lateral region can extend from the first mesa sidewall to the second mesa sidewall. The first and second lateral regions can be arranged alternately along the longitudinal direction of the mesa.

[0046] Electrical contacts on the top surface of the platform (e.g., linear contacts extending longitudinally) can directly contact the first and second lateral regions on the top surface. By alternately arranging the first and second lateral regions, electrical contacts at predefined locations along the longitudinal direction are provided either on the first or second lateral region. This can offset the negative effects of reduced contact resistance or minimal contact width caused by the reduction in device geometry and by the predefined locations of the source and body regions along the longitudinal direction. This allows for improved R when reducing device geometry. on xA.

[0047] For example, the semiconductor device may further include buried interconnect regions of a first conductivity type. The buried interconnect regions may extend along a longitudinal direction and may electrically connect the first lateral regions to each other. For example, the buried interconnect regions may be adjacent to the bottom side of a second lateral region.

[0048] For example, the maximum doping concentration of the first lateral region can be at least an order of magnitude greater than the maximum doping concentration of the buried interconnect region.

[0049] For example, the second lateral region may be part of a continuous region of a second conductivity type. The continuous region may adjoin the second mesa sidewall and bottom side of the trench gate structure. For example, the vertical doping concentration distribution of the continuous region may include multiple doping concentration distributions of doped regions that partially overlap along the vertical direction. The bottom portion of the continuous region may be configured to shield the gate dielectric of the trench gate structure from the effects of a high electric field. For example, the bottom portion of the continuous region may laterally adjoin a current-diffusion region of a first conductivity type. For example, the current-diffusion region may have a larger doping concentration than the drift region adjacent to the bottom side of the current-diffusion region.

[0050] For example, the semiconductor device may further include linear contacts on the top surface of the mesa. For some examples described herein, the linear contacts may extend along a longitudinal direction and directly contact alternating first and second lateral regions at different locations along the longitudinal direction. Similarly, for some other examples described herein, the linear contacts may extend along a longitudinal direction and directly contact each of the first and second regions at predefined locations along the longitudinal direction, wherein, for example, the contact surface portions of p-doped and n-doped regions alternate along the longitudinal direction.

[0051] Details regarding the structural, functional, or technical benefits of the features described above relative to semiconductor devices (such as FETs or IGBTs) also apply to the exemplary methods further described below. Processing the SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0052] Some of the examples above and below are described in conjunction with a silicon carbide substrate. Alternatively, wide-bandgap semiconductor substrates (e.g., wide-bandgap wafers) can be processed, for example, comprising wide-bandgap semiconductor materials different from silicon carbide. The bandgap of a wide-bandgap semiconductor wafer can be greater than that of silicon (1.12 eV). For example, a wide-bandgap semiconductor wafer can be a silicon carbide (SiC) wafer or a gallium arsenide (GaAs) wafer. In some other examples, a silicon semiconductor substrate can be processed.

[0053] In some of the illustrated examples, an n-channel FET or IGBT is shown. However, the examples described herein can also be applied to p-channel devices, such as p-channel MOSFETs or p-channel IGBTs.

[0054] The specification and accompanying drawings merely illustrate the principles of this disclosure. Furthermore, all examples described herein are primarily and explicitly intended for illustrative purposes only, to aid the reader in understanding the principles of this disclosure and the concepts contributed by one or more inventors to the field. All statements herein recounting the principles, aspects, and examples of this disclosure, as well as specific examples thereof, are intended to cover their equivalents.

[0055] It should be understood that the disclosure of multiple actions, processes, operations, steps, or functions in the specification or claims is not to be construed as being in a specific order, unless expressly or implicitly stated otherwise, for example, for technical reasons, such as by expressions like "hereafter". Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a particular order, unless such actions or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may individually include or may be divided into multiple sub-actions, sub-functions, sub-processes, sub-operations, or sub-steps. Unless expressly excluded, such sub-actions may be included and are part of the disclosure of that single action.

[0056] By reference Figure 1 The flowchart illustrates an example of a method for manufacturing semiconductor devices.

[0057] Process feature S100 includes forming trench gate structures in a SiC semiconductor body. Mesa are arranged between the trench gate structures.

[0058] Process feature S110 includes forming a one-sided channel region in the table. The one-sided channel region is adjacent to the first table sidewall of the opposing first and second table sidewalls.

[0059] Process feature S120 includes forming a first region of a first conductivity type in the mesa. The first region is adjacent to a first mesa sidewall and the top surface of the mesa. Process feature S120 further includes forming a second region of a second conductivity type in the mesa. The second region is adjacent to a second mesa sidewall and the top surface of the mesa. The first region and the second region are separated by a pn junction at the top surface of the mesa. The width of the first region at the top surface of the mesa can alternate between a first width range and a second width range along the longitudinal direction of the mesa. The first width range can be greater than 10% of the width of the mesa at the top surface and can be less than 50% of the width of the mesa at the top surface. The second width range can be greater than or equal to 50% of the width of the mesa at the top surface and less than 90% of the width of the mesa at the top surface.

[0060] By reference Figure 2 The flowchart illustrates another example of a method for manufacturing semiconductor devices.

[0061] Process feature S200 includes forming trench gate structures in a SiC semiconductor body. Mesa are arranged between the trench gate structures.

[0062] Process feature S210 includes forming a one-sided channel region in the table. The one-sided channel region is adjacent to the first table sidewall of the first and second opposing table sidewalls.

[0063] Process feature S220 includes a first lateral region of a first conductivity type forming the top surface of the adjacent mesa. The first lateral region can extend from a first mesa sidewall to a second mesa sidewall. Process feature S220 further includes a second lateral region of a second conductivity type forming the top surface of the adjacent mesa. The second lateral region can extend from the first mesa sidewall to the second mesa sidewall. The first lateral region and the second lateral region can be arranged alternately along the longitudinal direction of the mesa.

[0064] Process features may include sub-processes. For example, forming a trench gate structure may particularly include sub-processes of forming a gate trench, or forming a trench gate dielectric, or forming a gate trench electrode. For example, some or all of the sub-processes of a process feature described herein may be performed before or after a sub-process of another process feature described herein. For example, forming a portion of a continuum region described herein may be performed after forming a gate trench and before forming a trench gate electrode.

[0065] For example, forming a trench gate structure may include forming a gate trench in a SiC semiconductor substrate through a mask etching process (i.e., a dry etching process using an etching mask such as a hard mask). Forming the trench gate structure may further include forming a trench gate dielectric in the trench. For example, one or more cleaning processes for surface conditioning may be performed directly prior to the formation of the trench gate dielectric. The trench gate dielectric may be formed by an oxidation process or may include an oxidation process, such as a thermal oxidation process and / or an oxide deposition process. Other dielectric materials may be used in addition to oxides or as an alternative to oxides. For example, high-k materials may be used. For example, the trench gate dielectric layer may include a high-k dielectric layer comprising Al2O3, ZrO2, HfO2, AlN, or aluminosilicate AlSiO2. xThe trench gate dielectric may include at least one of silicon (La or Si) doped with HfO2, TiO2, Y2O3, or Si3N4. For example, the trench gate dielectric may include at least a first dielectric sublayer and a second dielectric sublayer. The dielectric constant of the first dielectric sublayer adjacent to the channel region may be less than the dielectric constant of the high-k dielectric sublayer, for example, equal to or greater than the dielectric constant of SiO2. For example, the first dielectric layer may include at least one of, for example, SiO2, AlN, or Si3N4. Forming the trench gate structure may also include forming a trench gate electrode. The trench gate electrode may include one or more conductive materials, such as: metals, metal alloys, such as Cu, Au, AlCu, Ag, or alloys thereof; metal compounds, such as TiN; highly doped semiconductor materials, such as highly doped polysilicon. For example, one or more conductive materials may form a layer stack. For example, the trench gate electrode may be electrically connected to the gate pad via a gate interconnect structure (such as a gate channel). Gate pads / interconnect structures and, for example, first load electrode pads (e.g., source pads of a MOSFET or emitter pads of an IGBT) can be part of a wiring region above the SiC semiconductor body. Forming the wiring region can include forming one or more (e.g., two, three, four, or even more) wiring levels. Each wiring level can be formed by a single or stacked conductive layer (e.g., one or more metal layers). For example, the wiring levels can be photolithographically patterned. Interlayer dielectric structures can be arranged between the stacked wiring levels. One or more contact plugs and / or one or more contact lines can be formed in the openings of the interlayer dielectric structures to electrically connect portions of different wiring levels (e.g., metal lines or contact areas) to each other.

[0066] A single-sided channel region in the mesa can be formed as part of a body region adjacent to the first mesa sidewall. For example, the body region can be formed by ion implantation (e.g., by ion implantation that is not masked at least relative to the transistor cell region) prior to forming the gate trench structure.

[0067] For example, each of the first and second regions can be formed, for example, by ion implantation. The first and second regions can be aligned with each other by an ion implantation mask pattern (e.g., a hard mask) defined by photolithography. For example, dopants of the first and / or second regions can be introduced into the SiC semiconductor body by ion implantation using an ion implantation mask. Similar to the first and second regions, a first lateral region and a second lateral region can be formed, for example, by ion implantation. The first and second lateral regions can be aligned with each other by an ion implantation mask pattern (e.g., a hard mask) defined by photolithography. For example, dopants of the first and / or second lateral regions can be introduced into the SiC semiconductor body by ion implantation using an ion implantation mask.

[0068] For example, the method may further include forming buried interconnect regions of a first conductivity type. The buried interconnect regions may extend along a longitudinal direction and electrically connect the first lateral regions to each other. For example, the buried interconnect regions may be adjacent to the bottom side of the second lateral regions. For example, the buried interconnect regions may allow for a reduction in the path resistance of the channel current from the single-sided channel region to the contact on the top surface of the mesa. For example, the buried interconnect regions may allow electronic current to flow directly and with low resistance from the first lateral region below the second lateral region into the channel region, thereby extending the electrically active channel width along the entire longitudinal direction (particularly below the second lateral region). This can be particularly helpful in reducing the path resistance in those regions where the contact areas have a larger width. In those regions where the source contacts are wider, the buried region will actually increase the path resistance. In summary, the overall path resistance can be reduced.

[0069] For example, forming a buried interconnect region may include introducing a dopant of a first conductivity type into the SiC semiconductor body by ion implantation through the sidewalls of the gate trench or through the top surface of the SiC semiconductor body before forming the gate trench.

[0070] Figures 3A to 3D The schematic top view illustrates an example configuration of a semiconductor device 100 including a mesa 104 within a SiC semiconductor body 102. The mesa 104 is laterally confined by trench gate structures 106. Each of the trench gate structures 106 includes a trench gate dielectric 1061 and a trench gate electrode 1062.

[0071] exist Figures 3A to 3D Each platform 104 in the diagram includes n adjacent to the first platform sidewall 1101. + The first doped region 112 is, for example, a source region. The mesa 104 further includes p-type structures adjacent to the second mesa sidewall 1102. + The doped second region 114, for example, is a contact region. The pn junction 116 laterally separates the first region 112 from the second region 114.

[0072] Figures 3A to 3D The configuration example differs in the layout of the first zone 112 and the second zone 114 on the top surface of the countertop 104. Figures 3A to 3D In the view of the top surface of the tabletop 104, the shape of the first area 112 along the longitudinal direction x1 is Figure 3A Square wave in, or Figure 3B The sine wave in the middle, or Figure 3C Triangular waves in, or Figure 3D The sawtooth wave in the middle.

[0073] exist Figures 3A to 3DThe common feature of the layout is that the width w1 of the first region 112 at the top surface of the tabletop 104 alternates between a first width range and a second width range along the longitudinal direction x1 of the tabletop 104. The first width range is greater than 10% of the width w of the tabletop 104 at the top surface and less than 50% of the width w of the tabletop 104 at the top surface. The second width range is greater than or equal to 50% of the width w of the tabletop 104 at the top surface and less than 90% of the width w of the tabletop 104 at the top surface. Similarly, the width w2 of the second region 114 at the top surface of the tabletop 104 alternates between a first width range and a second width range along the longitudinal direction x1 of the tabletop 104. The first width range is greater than 10% of the width w of the tabletop 104 at the top surface and less than 50% of the width w of the tabletop 104 at the top surface. The second width range is greater than or equal to 50% of the width w of the tabletop 104 at the top surface and less than 90% of the width w of the tabletop 104 at the top surface.

[0074] Figure 4A Schematic and exemplary illustrations show along Figures 3A to 3D A partial cross-sectional view of the semiconductor device 100 observed from any of the lines AA'. Figure 4B Schematic and exemplary illustrations show along Figures 3A to 3D A partial cross-sectional view of semiconductor device 100 observed from line BB' of any one of the n. + The first doped region 112 is the source region, and p + The second doped region 114 is the contact region.

[0075] refer to Figure 4A and / or Figure 4B Semiconductor device 100 may be a vertical power semiconductor device, which further includes at least a portion of an edge-terminating region surrounding the active region (in Figure 4A , Figure 4B (Not shown in the figure). The semiconductor device 100 includes a mesa 104 having a top surface 1103. The mesa 104 is constrained by a trench gate structure 106 along a second lateral direction x2. The second lateral direction x2 is perpendicular to the longitudinal direction x1.

[0076] like Figure 4B As shown in the figure, the first depth d1 from the bottom side of the contact region 114 to the top surface 1103 of the mesa 104 is greater than the second depth d2 from the bottom side of the source region 112 to the top surface 1103 of the mesa 104.

[0077] The second region 114 is part of the p-doped continuous region 117. The continuous region 117 is adjacent to the second mesa sidewall 1102 and the bottom side 118 of the trench gate structure 106.

[0078] The continuous region 117 completely covers the second sidewall 1102 from the bottom side 118 of the trench gate structure 106 to the top surface 1103 of the mesa 104. The vertical doping concentration distribution of the continuous region 117 may include multiple doping concentration distributions of p-doped sub-regions (e.g., the bottom portion 1171 adjacent to the bottom side 118 of the trench gate structure 106, the middle portion 1172 adjacent to the second mesa sidewall 1102, and the contact region 114) that partially overlap along the vertical direction y. The p-doped main region 120 is arranged along the second lateral direction x2 between the continuous region 117 and the first mesa sidewall 1101. A one-sided channel region 108 is defined by a portion of the main region 120 adjacent to the first mesa sidewall. For example, the one-sided channel region 108 may be defined by this portion of the main region 120, in which, for example, when a turn-on voltage is applied to the trench gate electrode 1102, inversion can be induced by the field effect.

[0079] Semiconductor device 100 further includes an n-doped current diffusion region 122 between the body region 120 and the n-doped drift region 124. The n-doped current diffusion region is adjacent to the single-sided channel region 108 and can have a larger doping concentration than the n-doped drift region 124. For semiconductor devices based on SiC semiconductor substrates, the average impurity concentration in the drift region 124 can be 5 × 10⁻⁶. 14 cm -3 and 1×10 17 cm -3 Between, for example, from 1×10 15 cm -3 Up to 2×10 16 cm -3 Within the range. The vertical extent of the drift region 124 may depend on the voltage blocking requirements of the semiconductor device 100, such as a specified voltage level. When the semiconductor device 100 is operated in voltage blocking mode, the space charge region may extend partially or completely vertically through the drift region 124, depending on the blocking voltage applied to the SiC semiconductor device. When the semiconductor device is operated at or near the specified maximum blocking voltage, the space charge region may reach or extend into a buffer zone configured to prevent the space charge region from further reaching the contact of the second load electrode at the second surface of the SiC semiconductor body 102.

[0080] A first load electrode L1 (e.g., a source or emitter electrode) is disposed above the mesa 104 and is electrically connected to a first or source region 112 and a second or contact region 114 via the top surface 1103 of the mesa 104. Given the arrangement of the first region 112 and the second region 114 at the top surface 1103 of the mesa (see, for example...), Figures 3A to 3DThe contact surface on the top surface 1103 of the platform 104 is covered by the second or contact region 114 (also by the first or source region 112) along the longitudinal direction x1.

[0081] Figure 5 The schematic top view illustrates another configuration example of a semiconductor device 100 including a mesa 104 within a SiC semiconductor body 102. The mesa 104 is laterally confined by trench gate structures 106. Each trench gate structure 106 includes a trench gate dielectric 1061 and a trench gate electrode 1062.

[0082] exist Figure 5 Each platform 104 in the diagram includes n + A first lateral region 132, such as a source region, is doped. The first lateral region 132 extends from a first mesa sidewall 1101 to a second mesa sidewall 1102. The mesa 104 further includes p... + A second lateral region 134, such as a contact region, is doped. The second lateral region 134 extends from the first mesa sidewall 1101 to the second mesa sidewall 1102. The first lateral region 132 and the second lateral region 134 are arranged alternately along the longitudinal direction x1 and are separated by a pn junction 138.

[0083] Figure 6A Schematic and exemplary illustrations show along Figure 5 A partial cross-sectional view of the semiconductor device 100 observed along line AA'. Figure 6B Schematic and exemplary illustrations show along Figure 5 The line BB' shows a partial cross-section of the semiconductor device 100. + The first lateral region 112 of the doped region is the source region, and p + The second lateral region of the doped region is the contact region.

[0084] refer to Figure 6A and / or Figure 6B The semiconductor device 100 includes a mesa 104 having a top surface 1103. The mesa 104 is constrained by a trench gate structure 106 along a second lateral direction x2 opposite to the longitudinal direction or the first direction x1.

[0085] The second lateral region 134 is part of the p-doped continuous region 137. The continuous region 137 is adjacent to the second mesa sidewall 1102 and the bottom side 118 of the trench gate structure 106. The continuous region 137 completely covers the second sidewall from the bottom side 118 of the trench gate structure 106 to the top surface 1103 of the mesa 104 along the longitudinal direction x1 at the location where the second lateral or contact region 134 is arranged. The vertical doping concentration distribution of the continuous region 137 may include multiple doping concentration distributions of p-doped sub-regions (e.g., the bottom portion 1371 adjacent to the bottom side 118 of the trench gate structure 106, the middle portion 1372 adjacent to the second mesa sidewall 1102, and the second lateral or contact region 134) that partially overlap along the vertical direction y. The p-doped main region 120 is arranged along the second lateral direction x2 between the continuous region 137 and the first mesa sidewall 1101. The single-sided channel area 108 is defined by a portion of the main body area 120 adjacent to the first platform sidewall 1101.

[0086] The semiconductor device 100 further includes an n-doped buried interconnect region 136. The buried interconnect region 136 extends along a longitudinal direction x1 and electrically connects the first lateral regions 132 to each other. For example, the buried interconnect region 136 may be adjacent to the bottom side of a second lateral or contact region 134, and may also be adjacent to the bottom side of the first lateral or source region 132, for providing electrical interconnection. For example, the maximum doping concentration of the first lateral region 132 is at least an order of magnitude greater than the maximum doping concentration of the buried interconnect region 136. For example, the buried interconnect region 136 may also be used in… Figures 3A to 4B The configuration example shown in the figure.

[0087] Semiconductor device 100 further includes an n-doped current diffusion region 122 between a body region 120 and an n-doped drift region 124. The n-doped current diffusion region 122 is adjacent to a one-sided channel region 108.

[0088] A first load electrode L1 (e.g., a source or emitter electrode) is disposed above the mesa 104 and electrically connected via the top surface 1103 of the mesa 104 to a first lateral or source region 132 and a second lateral or contact region 134, for example as a linear contact extending along the longitudinal direction x1. Given the arrangement of the first lateral region 132 and the second lateral region 134 at the top surface 1103 of the mesa (see, for example...), Figures 3A to 3D The linear contact surfaces on the top surface 1103 of the table 104 alternate between the first transverse region 132 and the second transverse region 134 along the longitudinal direction x1.

[0089] Figure 7 Schematic top view and Figure 8A and Figure 8B The relevant cross-sectional views schematically and exemplaryly illustrate the use of... Figure 5 , Figure 6A , Figure 6B The illustration shows another configuration example of the semiconductor device 100. Unlike in... Figure 5 , Figure 6A , Figure 6B The example shown in the figure is in Figure 7 , Figure 8A , Figure 8B The example illustrated has a middle portion 1372 of a continuous region 137 that extends upward to the top surface 1103 of the mesa 104. For example, the middle portion 1372 of the continuous region 137 may have a higher doping concentration at the top surface 1103 than each of the first lateral region 132 and the second lateral region 134.

[0090] Aspects and features mentioned and described together with one or more of the previously described examples and figures may also be combined with one or more other examples in order to replace similar features in other examples or to additionally introduce the feature into other examples.

[0091] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations can be used instead of the illustrated and described embodiments without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device (100), comprising: A SiC semiconductor body (102) includes a mesas (104) between trench gate structures (106), wherein the mesas (104) include: A single-sided channel area (108) is adjacent to the first platform sidewall (1101) of the opposing first and second platform sidewalls (1101, 1102); A first region (112) of a first conductive type adjacent to the top surface (1103) of the first mezzanine sidewall (1101) and the mezzanine (104); A second region (114) of a second conductivity type adjacent to the second mesa sidewall (1102) and the top surface (1103) of the mesa (104), wherein the first region (112) and the second region (114) are separated by a pn junction (116) at the top surface (1103) of the mesa (104); and wherein The width (w1) of the first region (112) at the top surface (1103) of the tabletop (104) alternates between a first width range and a second width range along the longitudinal direction (x1) of the tabletop (104). The first width range is greater than 10% of the width (w) of the tabletop (104) at the top surface (1103) and less than 50% of the width (w) of the tabletop (104) at the top surface (1103), and the second width range is greater than or equal to 50% of the width (w) of the tabletop (104) at the top surface (1103) and less than 90% of the width (w) of the tabletop (104) at the top surface (1103).

2. The semiconductor device (100) according to the preceding claim, wherein the first region (112) is a source region and the second region (114) is a contact region, and wherein a first depth (d1) from the bottom side of the contact region (114) to the top surface (1103) of the mesa (104) is greater than a second depth (d2) from the bottom side of the source region (112) to the top surface (1103) of the mesa (104).

3. The semiconductor device (100) according to any one of the preceding claims, wherein the second region (114) is part of a continuous region (117) of a second conductivity type, and wherein the continuous region (117) is adjacent to the second mesa sidewall (1102) and bottom side (118) of the trench gate structure (106).

4. The semiconductor device (100) according to the preceding claims, wherein the continuous region (117) completely covers the second sidewall (1102) from the bottom side (118) of the trench gate structure (106) to the top surface (1103) of the mesa (104).

5. The semiconductor device (100) according to any one of the preceding two claims further includes a body region (120) of a second conductivity type, wherein the body region (120) is laterally arranged between the continuous region (117) and the first mesa sidewall (1101).

6. The semiconductor device (100) according to any one of the preceding claims further includes a buried third region of a first conductivity type, wherein the buried third region is adjacent to the bottom side of the first region (112).

7. The semiconductor device (100) according to the preceding claim, wherein the maximum doping concentration of the first region is at least one order of magnitude greater than the maximum doping concentration of the buried third region.

8. The semiconductor device (100) according to any one of the preceding claims, wherein, In a top view on the top surface (1103) of the platform (104), the shape of the first region (112) along the longitudinal direction (x1) is at least one of a sine wave, a square wave, a triangular wave, or a sawtooth wave.

9. The semiconductor device (100) according to any one of the preceding claims, wherein the first region (112) is n ++ The doped source region, and the surface coverage of the second region (114) on the top surface (1103) of the mesa (104) is more than 10% greater than the surface coverage of the first region (112) on the top surface (1103) of the mesa (104).

10. The semiconductor device (100) according to any one of claims 1 to 8, wherein the first region (112) is n ++ The doped source region, and the surface coverage of the second region (114) on the top surface (1103) of the mesa (104) is equal to the surface coverage of the first region (112) on the top surface (1103) of the mesa (104).

11. A semiconductor device (100), comprising: A SiC semiconductor body (102) includes a mesas (104) between trench gate structures (106), wherein the mesas (104) include: A single-sided channel area (108) is adjacent to the first platform sidewall (1101) of the opposing first and second platform sidewalls (1101, 1102); A first transverse region (132) of a first conductivity type, which is adjacent to the top surface (1103) of the mesa (104) and extends from the first mesa sidewall (1101) to the second mesa sidewall (1102); and A second transverse region (134) of the second conductivity type is adjacent to the top surface (1103) of the platform (104) and extends from the first platform sidewall (1101) to the second platform sidewall (1102), wherein the first transverse region (132) and the second transverse region (134) are arranged alternately along the longitudinal direction (x1) of the platform (104).

12. The semiconductor device (100) according to the preceding claim further comprises: A buried interconnect region (136) of a first conductivity type, wherein the buried interconnect region (136) extends along the longitudinal direction (x1) and electrically connects the first transverse regions (132) to each other.

13. The semiconductor device (100) according to the preceding claim, wherein the maximum doping concentration of the first lateral region (132) is at least one order of magnitude greater than the maximum doping concentration of the buried interconnect region (136).

14. The semiconductor device (100) according to any one of the preceding three claims, wherein the second lateral region (134) is part of a continuous region (137) of a second conductivity type, and wherein the continuous region (137) is adjacent to the second mesa sidewall (1102) and bottom side (118) of the trench gate structure (106).

15. The semiconductor device (100) according to any one of the preceding claims further includes a linear contact on the top surface (1103) of the mesa (104), the linear contact extending along a longitudinal direction (x1).

16. A method for manufacturing a semiconductor device (100), the method comprising: A trench gate structure (106) is formed in a SiC semiconductor body (102), wherein mesas (104) are arranged between the trench gate structures (106); A one-sided channel area (108) is formed in the platform (104), the one-sided channel area (108) being adjacent to the first platform sidewall (1101) of the opposing first and second platform sidewalls (1101, 1102); A first region (112) of a first conductivity type is formed in the platform (104), the first region (112) being adjacent to the first platform sidewall (1101) and the top surface (1103) of the platform (104); A second region (114) of a second conductivity type is formed in the mesa (104), the second region (114) being adjacent to the second mesa sidewall (1102) and the top surface (1103) of the mesa (104), wherein the first region (112) and the second region (114) are separated by a pn junction (116) at the top surface (1103) of the mesa (104); and wherein The width (w1) of the first region (112) at the top surface (1103) of the tabletop (104) alternates between a first width range and a second width range along the longitudinal direction (x1) of the tabletop (104). The first width range is greater than 10% of the width (w) of the tabletop (104) at the top surface (1103) and less than 50% of the width (w) of the tabletop (104) at the top surface (1103), and the second width range is greater than or equal to 50% of the width (w) of the tabletop (104) at the top surface (1103) and less than 90% of the width (w) of the tabletop (104) at the top surface (1103).

17. A method for manufacturing a semiconductor device (100), the method comprising: A trench gate structure (106) is formed in a SiC semiconductor body (102), wherein mesas (104) are arranged between the trench gate structures (106); A one-sided channel area (108) is formed in the platform (104), the one-sided channel area (108) being adjacent to the first platform sidewall (1101) of the opposing first and second platform sidewalls (1101, 1102); A first transverse region (132) of a first conductivity type is formed, which is adjacent to the top surface (1103) of the mesa (104) and extends from the first mesa sidewall (1101) to the second mesa sidewall (1102); and A second transverse region (134) of a second conductivity type is formed, which is adjacent to the top surface (1103) of the platform (104) and extends from the first platform sidewall (1101) to the second platform sidewall (1102), wherein the first transverse region (132) and the second transverse region (134) are arranged alternately along the longitudinal direction (x1) of the platform (104).

18. The method according to the preceding claim, further comprising: A buried interconnect region (136) of the first conductivity type is formed, wherein the buried interconnect region (136) extends along the longitudinal direction (x1) and electrically connects the first transverse regions (132) to each other.

19. The method according to the preceding claim, wherein forming the buried interconnect region (136) includes introducing a dopant of a first conductivity type into the SiC semiconductor body (102) by ion implantation through the sidewalls of the gate trench or through the top surface of the SiC semiconductor body (102) prior to forming the gate trench.

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