Solar cell, photovoltaic module and photovoltaic system

Abstract

The invention relates to a solar cell, a photovoltaic module and a photovoltaic system. The solar cell comprises an intrinsic semiconductor substrate which comprises an intrinsic region, a first surface and a second surface, the first surface and the second surface are arranged on two opposite sides of the intrinsic semiconductor substrate, and the intrinsic region is arranged between the first surface and the second surface; the first doping structure has a first doping type, and the first doping structure is arranged on one side, close to the first surface, of the intrinsic region; the second doping structure has a second doping type, and the second doping structure is arranged on one side, close to the second surface, of the intrinsic region; wherein the first doping type is opposite to the second doping type, and the first doping structure, the intrinsic region and the second doping structure form a p-i-n structure. On one hand, the complexity and the manufacturing cost of the solar cell preparation process can be reduced, and on the other hand, the conversion efficiency of the solar cell can be improved.

Description

[0001] This application is a divisional application of application number CN2024100846697 (Invention title: Solar cell and its preparation method, photovoltaic module, photovoltaic system, application date: January 19, 2024). Technical Field

[0002] This application relates to the field of solar cell technology, and in particular to a solar cell, photovoltaic module and photovoltaic system. Background Technology

[0003] A solar cell is a device that directly converts light energy into electrical energy through the photoelectric effect. Generally speaking, solar cells are manufactured on semiconductor wafers or substrates by forming a pn junction near the surface of a substrate using semiconductor processing technology.

[0004] Solar cells typically use p-type or n-type silicon substrates. Regardless of the substrate type, relevant elements must be incorporated during the growth of the silicon single crystal. Due to the complexity of the silicon single crystal growth process, the dopant elements can be distributed differently radially or longitudinally within the crystal. This results in varying resistivity in silicon wafers cut from a single silicon rod. Furthermore, even within a single wafer, the resistivity can differ from the center to the edge. This not only complicates the solar cell fabrication process but also affects the conversion efficiency of the solar cell. Summary of the Invention

[0005] Therefore, it is necessary to provide a solar cell, photovoltaic module, and photovoltaic system to address the above-mentioned problems.

[0006] In a first aspect, embodiments of this application provide a solar cell, comprising:

[0007] An intrinsic semiconductor substrate includes an intrinsic region, a first surface, and a second surface, wherein the first surface and the second surface are disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region is disposed between the first surface and the second surface.

[0008] A first doped structure, having a first doping type, wherein the first doped structure is disposed on the side of the intrinsic region closest to the first surface; and

[0009] The second doped structure has a second doping type, and the second doped structure is disposed on the side of the intrinsic region closer to the second surface;

[0010] Wherein, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic region and the second doping structure constitute a pin structure.

[0011] In one embodiment, the resistivity of the intrinsic region is greater than 100 Ω·cm;

[0012] And / or, the doping concentration of the p-type dopant in the intrinsic region is less than or equal to 1.3 × 10⁻⁶. 14 ㎝ -3 Furthermore, the doping concentration of the n-type dopant in the intrinsic region is less than or equal to 4.4 × 10⁻⁶. 13 ㎝ -3 .

[0013] In one embodiment, the thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

[0014] In one embodiment, the doping concentration of the first doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 ;

[0015] And / or, the doping concentration of the second doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 .

[0016] In one embodiment, the first doped structure has a first dimension between the side of the first doped structure close to the first surface and the side of the first doped structure away from the first surface, the first dimension being between 5nm and 5000nm.

[0017] And / or, the second doped structure has a second dimension between the side of the second doped structure closer to the first surface and the side of the second doped structure farther from the first surface, the second dimension being between 5nm and 5000nm.

[0018] In one embodiment, the solar cell further includes a third doped structure having a second doping type and disposed on the side of the first doped structure away from the intrinsic region;

[0019] The third doped structure and the first doped structure form a pn junction.

[0020] In one embodiment, the solar cell further includes a fourth doped structure having a first doping type and disposed on the side of the second doped structure away from the intrinsic region;

[0021] The fourth doped structure and the second doped structure form a pn junction.

[0022] In one embodiment, the first doped structure is embedded within the intrinsic semiconductor substrate and located between the intrinsic region and the first surface.

[0023] In one embodiment, the second doped structure is embedded within the intrinsic semiconductor substrate and located between the intrinsic region and the second surface.

[0024] In one embodiment, the second doped structure is disposed on the side of the second surface away from the first surface.

[0025] In one embodiment, the solar cell further includes a first tunneling layer disposed on the second surface, and a second doped structure disposed on the side of the first tunneling layer away from the first surface.

[0026] In one embodiment, the solar cell further includes:

[0027] The first passivation anti-reflection layer is disposed on the side of the first doped structure away from the intrinsic region;

[0028] The first electrode is disposed on the side of the first doped structure away from the second doped structure, and penetrates the first passivation antireflection layer and is electrically connected to the first doped structure.

[0029] A second passivation and antireflection layer is disposed on the side of the second doped structure away from the intrinsic region; and

[0030] The second electrode is disposed on the side of the second doped structure away from the first doped structure, and penetrates the second passivation antireflection layer and is electrically connected to the second doped structure.

[0031] In one embodiment, the first doped structure is disposed on the side of the first surface away from the second surface.

[0032] In one embodiment, the second doped structure is disposed on the side of the second surface away from the first surface.

[0033] In one embodiment, the solar cell further includes: a first intrinsic semiconductor layer disposed on the first surface, and the first doped structure disposed on the side of the first intrinsic semiconductor layer away from the second surface; and

[0034] The second intrinsic semiconductor layer is disposed on the second surface, and the second doped structure is disposed on the side of the second intrinsic semiconductor layer away from the first surface.

[0035] In one embodiment, the solar cell further includes:

[0036] A first transparent conductive layer is disposed on the side of the first doped structure away from the first intrinsic semiconductor layer;

[0037] The first electrode is disposed on the side of the first transparent conductive layer away from the first intrinsic semiconductor layer and is electrically connected to the first transparent conductive layer.

[0038] A second transparent conductive layer is disposed on the side of the second doped structure away from the second intrinsic semiconductor layer; and

[0039] The second electrode is disposed on the side of the second transparent conductive layer away from the second intrinsic semiconductor layer and is electrically connected to the second transparent conductive layer.

[0040] In one embodiment, the solar cell further includes:

[0041] A second tunneling layer is disposed on the first surface, and the first doped structure is disposed on the side of the second tunneling layer away from the second surface; and

[0042] The third tunneling layer is disposed on the second surface, and the second doped structure is disposed on the side of the third tunneling layer away from the first surface.

[0043] Secondly, embodiments of this application provide another type of solar cell, including:

[0044] An intrinsic semiconductor substrate has a first surface and a second surface disposed opposite to each other; a first conductive region and a second conductive region are provided on the intrinsic semiconductor substrate along a first direction, the first direction being perpendicular to the thickness direction of the intrinsic semiconductor substrate;

[0045] A first passivation layer is disposed on the first surface and located in the first conductive region;

[0046] A second passivation layer is disposed on the first surface and located in the second conductive region;

[0047] A first doped structure, having a first doping type, is disposed on the side of the first passivation layer away from the intrinsic semiconductor substrate; and

[0048] The second doped structure has a second doping type and is disposed on the side of the second passivation layer away from the intrinsic semiconductor substrate;

[0049] Wherein, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic semiconductor substrate and the second doping structure constitute a pin structure.

[0050] In one embodiment, the resistivity of the intrinsic semiconductor substrate is greater than 100 Ω·cm;

[0051] And / or, the doping concentration of the p-type dopant in the intrinsic semiconductor substrate is less than or equal to 1.3 × 10⁻⁶. 14 ㎝-3 Furthermore, the doping concentration of the n-type dopant in the intrinsic semiconductor substrate is less than or equal to 4.4 × 10⁻⁶. 13 ㎝ -3 .

[0052] In one embodiment, the thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

[0053] In one embodiment, the doping concentration of the first doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 ;

[0054] And / or, the doping concentration of the second doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 .

[0055] In one embodiment, the first doped structure has a third dimension between the side of the first doped structure close to the first surface and the side of the first doped structure away from the first surface, the third dimension being between 5 nm and 5000 nm.

[0056] And / or, the second doped structure has a fourth dimension between the side of the second doped structure closer to the first surface and the side of the second doped structure farther from the first surface, the fourth dimension being between 5 nm and 5000 nm.

[0057] In one embodiment, the solar cell further includes a third doped structure having a second doping type and disposed on the side of the first doped structure away from the intrinsic semiconductor substrate;

[0058] The third doped structure and the first doped structure form a pn junction.

[0059] In one embodiment, the solar cell further includes a fourth doped structure having a first doping type and disposed on the side of the second doped structure away from the intrinsic semiconductor substrate;

[0060] The fourth doped structure and the second doped structure form a pn junction.

[0061] In one embodiment, the first passivation layer and the second passivation layer are configured as tunneling dielectric layers;

[0062] And / or, the materials of the first doped structure and the second doped structure include polycrystalline silicon.

[0063] In one embodiment, the materials of the first passivation layer and the second passivation layer include intrinsic semiconductor materials;

[0064] And / or, the materials of the first doped structure and the second doped structure include microcrystalline silicon or amorphous silicon.

[0065] In one embodiment, the solar cell further includes:

[0066] The first anti-reflection layer is disposed on the side of the first doped structure away from the intrinsic semiconductor substrate and on the side of the second doped structure away from the intrinsic semiconductor substrate;

[0067] The first electrode is disposed on the side of the first doped structure away from the intrinsic semiconductor substrate, and penetrates the first antireflection layer and is electrically connected to the first doped structure.

[0068] The second electrode is disposed on the side of the second doped structure away from the intrinsic semiconductor substrate, and penetrates the first antireflection layer and is electrically connected to the second doped structure.

[0069] A third passivation layer is disposed on the second surface; and

[0070] The second antireflection layer is disposed on the side of the third passivation layer away from the intrinsic semiconductor substrate.

[0071] Thirdly, embodiments of this application provide a photovoltaic module, including the solar cell described in either the first or second aspect.

[0072] Fourthly, embodiments of this application provide a photovoltaic system, including the photovoltaic module described in the third aspect.

[0073] The solar cells, photovoltaic modules, and photovoltaic systems provided in this application embodiment form a pin structure by setting an intrinsic region, a first doped structure, and a second doped structure on an intrinsic semiconductor substrate. Compared to traditional techniques using p-type or n-type semiconductor substrates to fabricate solar cells, the solar cell substrate provided in this application embodiment, because it uses an intrinsic semiconductor substrate containing an intrinsic region, does not require the addition of p-type or n-type dopants during the fabrication of the intrinsic semiconductor substrate blank (e.g., a silicon rod). This reduces the complexity of the solar cell fabrication process and is more conducive to silicon crystal growth, reducing dislocation density, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rod is cut into wafers, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafers. This improves the electrical uniformity of the silicon wafers, thereby increasing the conversion efficiency of the solar cell; it also improves the utilization rate of the silicon rod, thereby reducing the manufacturing cost of the solar cell. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a solar cell provided in an embodiment of this application.

[0076] Figure 2 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0077] Figure 3 This is a partial cross-sectional structural diagram of another solar cell provided in an embodiment of this application.

[0078] Figure 4 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0079] Figure 5 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0080] Figure 6 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0081] Figure 7 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0082] Figure 8 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0083] Figure 9 This is a schematic flowchart of a method for fabricating a solar cell according to an embodiment of this application.

[0084] Figure 10 This is a schematic flowchart of a method for fabricating a solar cell according to an embodiment of this application.

[0085] Figure label:

[0086] 1. Solar cell; 111. Semiconductor substrate; 111a. Intrinsic region; 111b. First surface; 111c. Second surface; 111d. First conductive region; 111e. Second conductive region; 112. First doped structure; 113. Second doped structure; 114. First tunneling layer; 115. First passivation antireflection layer; 116. Second passivation antireflection layer; 117. First electrode; 118. Second electrode; 119. First intrinsic semiconductor layer; 120. Second intrinsic semiconductor layer; 121. First transparent conductive layer; 122. Second transparent conductive layer; 123. Second tunneling layer; 124. Third tunneling layer; 125. First passivation layer; 126. Second passivation layer; 127. First antireflection layer; 128. Second antireflection layer; 129. Third passivation layer; 130. Third doped structure; 131. Fourth doped structure. Detailed Implementation

[0087] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0089] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0090] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0091] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0092] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0093] Firstly, referring to Figure 1As shown, this application provides a solar cell 1, which can be a PERT (Passivated Emitter Rear Totally-diffused) cell, a TOPCon (Tunnel Oxide Passivated Contact) cell, an SHJ (Silicon HeteroJunction) cell, a tandem cell, etc.

[0094] Specifically, the solar cell 1 includes an intrinsic semiconductor substrate 111, a first doped structure 112, and a second doped structure 113. The intrinsic semiconductor substrate 111 includes an intrinsic region 111a, a first surface 111b, and a second surface 111c. The first surface 111b and the second surface 111c are located on opposite sides of the intrinsic semiconductor substrate 111, and the intrinsic region 111a is located between the first surface 111b and the second surface 111c. Here, the first surface 111b can be one of the light-facing surface and the back-light surface of the solar cell 1, and the second surface 111c can be the other of the light-facing surface and the back-light surface of the solar cell 1.

[0095] Furthermore, the first doped structure 112 has a first doping type and is disposed on the side of the intrinsic region 111a near the first surface 111b. The second doped structure 113 has a second doping type and is disposed on the side of the intrinsic region 111a near the second surface 111c. The first and second doping types are opposite, and the first doped structure 112, the intrinsic region 111a, and the second doped structure 113 constitute a pin structure. It can be understood that in one example, the first doping type is p-type and the second doping type is n-type. In a contrasting example, the first doping type is n-type and the second doping type is p-type.

[0096] It should be noted that the first doped structure 112 and the second doped structure 113 can be doped regions disposed on the intrinsic semiconductor substrate 111, or they can be film structures containing dopants. When at least one of the first doped structure 112 and the second doped structure 113 is a doped region disposed on the intrinsic semiconductor substrate 111, the intrinsic region 111a is a portion of the intrinsic semiconductor substrate 111. When both the first doped structure 112 and the second doped structure 113 are film structures containing dopants, the intrinsic region 111a is the entire region of the intrinsic semiconductor substrate 111.

[0097] The solar cell 1 provided in this application embodiment has an intrinsic region 111a formed on an intrinsic semiconductor substrate 111, and a first doped structure 112 and a second doped structure 113 formed on opposite sides of the intrinsic semiconductor substrate 111a, such that the first doped structure 112, the intrinsic region 111a and the second doped structure 113 constitute a pin structure. Thus, compared to conventional techniques for fabricating solar cells 1 using p-type or n-type semiconductor substrates 111, the solar cell 1 provided in this application embodiment, because it uses an intrinsic semiconductor substrate 111 containing the intrinsic region 111a, does not require the addition of p-type or n-type dopants during the fabrication of the intrinsic semiconductor substrate 111 blank (e.g., a silicon rod). This reduces the complexity of the solar cell 1 fabrication process and is more conducive to silicon crystal growth, reducing dislocation density, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rod is cut into wafers, there is no difference in resistivity in the radial and longitudinal directions of the intrinsic silicon wafers. On the one hand, this is beneficial to improving the electrical consistency of the silicon wafers, thereby improving the conversion efficiency of solar cell 1; on the other hand, it is beneficial to improve the utilization rate of silicon rods, thereby reducing the manufacturing cost of solar cell 1.

[0098] It should also be noted that the solar cell 1 provided in this embodiment has a pi junction and an in junction on both sides of the intrinsic semiconductor substrate 111. This structure can improve the carrier separation effect, thereby improving the photoelectric conversion efficiency of the solar cell 1. Specifically, compared with the substrate of a conventional solar cell 1, the intrinsic semiconductor substrate 111 in this embodiment contains an intrinsic region 111a, so the doping concentration of the intrinsic semiconductor substrate 111 is much lower than that of a conventional substrate. Since the lower the doping concentration of the substrate, the deeper the built-in electric field of the solar cell 1 penetrates into the substrate, the built-in electric field of the solar cell 1 in this embodiment penetrates into the substrate to a greater depth, and the influence range of the built-in electric field is larger, thereby improving the carrier separation effect.

[0099] In one embodiment, the resistivity of the intrinsic region 111a is greater than 100 Ω·cm. This effectively results in a very low dopant content in the intrinsic region 111a. This facilitates increasing the depth to which the built-in electric field penetrates the intrinsic semiconductor substrate 111, thereby contributing to improved carrier separation.

[0100] In one embodiment, the doping concentration of the p-type dopant in intrinsic region 111a is less than or equal to 1.3 × 10⁻⁶. 14 ㎝ -3 Furthermore, the doping concentration of the n-type dopant in intrinsic region 111a is less than or equal to 4.4 × 10⁻⁶. 13 ㎝ -3This effectively results in a very low dopant content in the intrinsic region 111a. This, in turn, increases the depth to which the built-in electric field penetrates the intrinsic semiconductor substrate 111, thereby improving carrier separation.

[0101] In one embodiment, the thickness of the intrinsic semiconductor substrate 111 is between 50 μm and 300 μm. Exemplarily, the thickness of the intrinsic semiconductor substrate 111 can be 50 μm, 60 μm, 65 μm, 80 μm, 100 μm, 130 μm, 160 μm, 190 μm, 230 μm, 270 μm, 290 μm, 300 μm, or between any two of the above values. By keeping the thickness of the intrinsic semiconductor substrate 111 within the above range, it is beneficial to reduce the thickness of the solar cell 1 and to form a stable pin structure.

[0102] In one embodiment, the doping concentration of the first doped structure 112 is between 3 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20 ㎝ -3 For example, the doping concentration of the first doped structure 112 can be 3 × 10⁻⁶. 18 ㎝ -3 5×10 18 ㎝ -3 1×10 19 ㎝ -3 5×10 20 ㎝ -3 Or it may be between any two of the above values. By keeping the doping concentration of the first doped structure 112 within the above range, it is beneficial to reduce manufacturing costs on the one hand, and on the other hand, the first doped structure 112 can have better conductivity on the other hand.

[0103] In one embodiment, the doping concentration of the second doped structure 113 is between 3 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20 ㎝ -3 For example, the doping concentration of the second doped structure 113 can be 3 × 10⁻⁶. 18 ㎝ -3 5×10 18 ㎝ -3 1×10 19 ㎝ -3 5×10 20 ㎝ -3 Or it may be between any two of the above values. By keeping the doping concentration of the second doped structure 113 within the above range, it is beneficial to reduce manufacturing costs and also to give the second doped structure 113 better conductivity.

[0104] In one embodiment, reference Figure 1 As shown, the first doped structure 112 has a first dimension H1 between the side near the first surface 111b and the side away from the first surface 111b, where the first dimension H1 is between 5nm and 5000nm. For example, the first dimension H1 can be 5nm, 10nm, 100nm, 1500nm, 2500nm, 3000nm, 4000nm, 5000nm, or any two of the above values. By placing the first dimension H1 within the above range, it is beneficial to reduce manufacturing costs and to form a stable pin structure.

[0105] In one embodiment, reference Figure 1 As shown, the second doped structure 113 has a second size H2 between the side of the second doped structure 113 closest to the first surface 111b and the side of the second doped structure 113 furthest from the first surface 111b. The second size H2 is between 5 nm and 5000 nm. For example, the second size H2 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, 5000 nm, or any two of the above values. By placing the second size H2 within the above range, it is beneficial to reduce manufacturing costs and to form a stable pin structure.

[0106] In one embodiment, reference Figure 2 As shown, the solar cell 1 also includes a third doped structure 130, which has a second doping type and is located on the side of the first doped structure 112 away from the intrinsic region 111a. The third doped structure 130 and the first doped structure 112 form a pn junction. By providing the third doped structure 130, it is beneficial to increase the doping concentration at the contact interface between the first electrode 117 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the contact interface between the first electrode 117 and the intrinsic semiconductor substrate 111, and thus improving the efficiency of the solar cell 1.

[0107] In one embodiment, the solar cell 1 further includes a fourth doped structure 131, which has a first doping type and is disposed on the side of the second doped structure 113 away from the intrinsic region 111a. The fourth doped structure 131 and the second doped structure 113 form a pn junction. By providing the fourth doped structure 131, it is beneficial to increase the doping concentration at the contact interface between the second electrode 118 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the contact interface between the second electrode 118 and the intrinsic semiconductor substrate 111, and thus improving the efficiency of the solar cell 1.

[0108] In one embodiment, reference Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the first doped structure 112 is embedded in the intrinsic semiconductor substrate 111 and is located between the intrinsic region 111a and the first surface 111b. Specifically, the intrinsic semiconductor substrate 111 has a first doped region, which is doped with a dopant of a first doping type, and the first doped region is the first doped structure 112.

[0109] In one embodiment, the first doped region may be formed by diffusion from the first surface 111b toward the second surface 111c. The doping depth of the first doped region may be between 0.1 μm and 3 μm. The doping concentration of the first doped region may be between 3 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20 ㎝ -3 .

[0110] In one embodiment, the doping concentration of the first doped region gradually decreases from the first surface 111b to the second surface 111c.

[0111] In one embodiment, reference Figure 1 and Figure 2 As shown, the second doped structure 113 is embedded in the intrinsic semiconductor substrate 111 and is located between the intrinsic region 111a and the second surface 111c. Specifically, the intrinsic semiconductor substrate 111 has a second doped region, which is doped with a dopant of a second doping type, and the second doped region is the second doped structure 113.

[0112] In one embodiment, the second doped region may be formed by diffusion from the second surface 111c toward the first surface 111b. The doping depth of the second doped region may be between 0.1 μm and 3 μm. The doping concentration of the second doped region may be between 3 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20 ㎝ -3 .

[0113] In one embodiment, the doping concentration of the second doped region gradually decreases from the second surface 111c to the first surface 111b.

[0114] In one embodiment, reference Figure 2As shown, the third doped structure 130 and the fourth doped structure 131 are also embedded within the intrinsic semiconductor substrate 111. Specifically, the intrinsic semiconductor substrate 111 has a third doped region and a fourth doped region. The third doped region is of the second doping type, and the fourth doped region is of the first doping type. The third doped region is located on the side of the first doped region near the first surface 111b, and the fourth doped region is located on the side of the second doped region near the second surface 111c. The third doped region forms the third doped structure 130, and the fourth doped region forms the fourth doped structure 131.

[0115] This helps to increase the doping concentration on the surface of the intrinsic semiconductor substrate 111, thereby reducing the contact resistance between the electrode and the intrinsic semiconductor substrate 111, and thus improving the efficiency of the solar cell 1.

[0116] In one embodiment, reference Figure 3 and Figure 4 As shown, the second doped structure 113 is disposed on the side of the second surface 111c away from the first surface 111b. Exemplarily, the second doped structure 113 can be a polycrystalline silicon thin film containing a dopant. Further, the thickness of the polycrystalline silicon thin film can be between 10 nm and 300 nm, and the doping concentration of the polycrystalline silicon thin film can be between 1 × 10⁻⁶. 19 ㎝ -3 Up to 5×10 20 ㎝ -3 .

[0117] In one embodiment, the solar cell 1 further includes a first tunneling layer 114 disposed on the second surface 111c, and a second doped structure 113 disposed on the side of the first tunneling layer 114 away from the first surface 111b. This allows a passivated contact structure to be formed on the second surface 111c, improving the open-circuit voltage of the solar cell 1 and thus increasing its conversion efficiency.

[0118] In one embodiment, the thickness of the first tunneling layer 114 is between 0.5 nm and 5 nm.

[0119] In one embodiment, reference Figures 1-4As shown, the solar cell 1 further includes a first passivation antireflection layer 115, a first electrode 117, a second passivation antireflection layer 116, and a second electrode 118. The first passivation antireflection layer 115 is disposed on the side of the first doped structure 112 away from the intrinsic region 111a. The first electrode 117 is disposed on the side of the first doped structure 112 away from the second doped structure 113, and penetrates the first passivation antireflection layer 115 and is electrically connected to the first doped structure 112. The second passivation antireflection layer 116 is disposed on the side of the second doped structure 113 away from the intrinsic region 111a. The second electrode 118 is disposed on the side of the second doped structure 113 away from the first doped structure 112, and penetrates the second passivation antireflection layer 116 and is electrically connected to the second doped structure 113. Specifically, Figure 1 and Figure 2 The solar cell 1 shown is a PERT cell. Figure 3 and Figure 4 The solar cell 1 shown is a TOPCon cell.

[0120] In one embodiment, reference Figure 4 As shown, a third doped structure 130 can be embedded in the intrinsic semiconductor substrate 111, which helps to increase the doping concentration on the surface of the intrinsic semiconductor substrate 111, thereby reducing the contact resistance between the first electrode 117 and the intrinsic semiconductor substrate 111, and thus improving the efficiency of the solar cell 1.

[0121] In one embodiment, the material of the first passivation antireflection layer includes one or more of the following: AlOx, SiNx, SiOx, SiNxOy, TiOx, MgF2, etc.

[0122] In one example, the first passivation antireflection layer is an AlOx layer with a thickness between 1 nm and 20 nm.

[0123] In one example, the first passivation antireflection layer is a SiNx layer with a thickness between 10 nm and 100 nm.

[0124] In one example, the first passivation antireflection layer is a SiOx layer with a thickness between 10 nm and 150 nm.

[0125] In one example, the first passivation antireflection layer is a SiNxOy layer with a thickness between 10 nm and 150 nm.

[0126] In one example, the first passivation antireflection layer is a TiOx layer with a thickness between 10 nm and 150 nm.

[0127] In one example, the first passivation antireflection layer is a MgF2 layer with a thickness between 10 nm and 150 nm.

[0128] In one embodiment, the material of the second passivation antireflection layer includes one or more of AlOx, SiNx, SiOx, SiNxOy, TiOx, and MgF2. The material of the second passivation antireflection layer can be the same as that of the first passivation antireflection layer, and the thickness of the second passivation antireflection layer can be the same as that of the first passivation antireflection layer. Further details will not be elaborated upon in this embodiment.

[0129] In one embodiment, the materials of the first electrode 117 and the second electrode 118 may include one or more metals such as Ag, Al, Cu, Ni, or a mixture of these metals and glass frit.

[0130] In one embodiment, reference Figure 5 and Figure 6 As shown, the first doped structure 112 is disposed on the side of the first surface 111b away from the second surface 111c. Exemplarily, the first doped structure 112 can be a microcrystalline or amorphous thin film containing a dopant. Further, the thickness of the first doped structure 112 can be between 5 nm and 25 nm.

[0131] In one embodiment, the second doped structure 113 is disposed on the side of the second surface 111c away from the first surface 111b. Exemplarily, the second doped structure 113 can be a microcrystalline or amorphous thin film containing a dopant. Further, the thickness of the second doped structure 113 can be between 5 nm and 25 nm.

[0132] In one embodiment, the solar cell 1 further includes a first intrinsic semiconductor layer 119 and a second intrinsic semiconductor layer 120. The first intrinsic semiconductor layer 119 is disposed on a first surface 111b, and a first doped structure 112 is disposed on the side of the first intrinsic semiconductor layer 119 away from the second surface 111c. The second intrinsic semiconductor layer 120 is disposed on the second surface 111c, and a second doped structure 113 is disposed on the side of the second intrinsic semiconductor layer 120 away from the first surface 111b. Exemplarily, both the first intrinsic semiconductor layer 119 and the second intrinsic semiconductor layer 120 are intrinsic amorphous silicon thin films.

[0133] In one embodiment, the thickness of the first intrinsic semiconductor layer 119 and the second intrinsic semiconductor layer 120 is between 2nm and 20nm.

[0134] In one embodiment, reference Figure 5As shown, the solar cell 1 further includes a first transparent conductive layer 121, a first electrode 117, a second transparent conductive layer 122, and a second electrode 118. The first transparent conductive layer 121 is disposed on the side of the first doped structure 112 away from the first intrinsic semiconductor layer 119. The first electrode 117 is disposed on the side of the first transparent conductive layer 121 away from the first intrinsic semiconductor layer 119 and is electrically connected to the first transparent conductive layer 121. The second transparent conductive layer 122 is disposed on the side of the second doped structure 113 away from the second intrinsic semiconductor layer 120. The second electrode 118 is disposed on the side of the second transparent conductive layer 122 away from the second intrinsic semiconductor layer 120 and is electrically connected to the second transparent conductive layer 122. Exemplarily, the material of the first transparent conductive layer 121 may include one or more of indium tin oxide, tin oxide, and zinc oxide. The material of the second transparent conductive layer 122 may include one or more of indium tin oxide, tin oxide, and zinc oxide.

[0135] It should be noted here that, Figure 5 The solar cell 1 shown is an SHJ cell. Figure 6 The solar cell 1 shown is a tandem cell, and only the bottom cell of this tandem cell is shown in the figure. The bottom cell is an SHJ cell. Exemplarily, this tandem cell can be a perovskite-silicon heterojunction tandem cell.

[0136] In one embodiment, reference Figure 7 As shown, the solar cell 1 further includes a second tunneling layer 123 and a third tunneling layer 124. The second tunneling layer 123 is disposed on the first surface 111b, and the first doped structure 112 is disposed on the side of the second tunneling layer 123 away from the second surface 111c. The third tunneling layer 124 is disposed on the second surface 111c, and the second doped structure 113 is disposed on the side of the third tunneling layer 124 away from the first surface 111b.

[0137] It should be noted here that, Figure 7 The solar cell 1 shown is a tandem cell, and only the bottom cell of this tandem cell is shown in the figure. This bottom cell is a TOPCon cell. For example, this tandem cell can be a perovskite-TOPCon tandem cell.

[0138] In one example, the first doped structure 112 is a polycrystalline silicon thin film containing an n-type dopant, and further, the doping concentration of the first doped structure 112 is between 1 × 10⁻⁶. 19 ㎝ -3 Up to 5×10 20 ㎝ -3 The thickness of the first doped structure 112 is between 10 nm and 300 nm.

[0139] In one example, the second doped structure 113 is a polycrystalline silicon thin film containing a p-type dopant, and further, the doping concentration of the second doped structure 113 is between 5 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20 ㎝ -3 The thickness of the second doped structure 113 is between 10 nm and 300 nm.

[0140] It should be noted that, in Figure 5 , Figure 6 and Figure 7 The solar cell 1 shown may also include a third doped structure 130 and / or a fourth doped structure 131. In one example, the third doped structure 130 may be disposed in the same film layer as the first doped structure 112, and the fourth doped structure 131 may be disposed in the same film layer as the second doped structure 113. In another example, the first doped structure 112, the second doped structure 113, the third doped structure 130, and the fourth doped structure 131 may also be separate film layer structures.

[0141] Secondly, referring to Figure 8 As shown, this application embodiment provides another solar cell 1, which is a BC (Back Contact) cell. Specifically, the solar cell 1 includes an intrinsic semiconductor substrate 111, a first passivation layer 125, a second passivation layer 126, a first doped structure 112, and a second doped structure 113. The intrinsic semiconductor substrate 111 has a first surface 111b and a second surface 111c disposed opposite to each other; the intrinsic semiconductor substrate 111 has a first conductive region 111d and a second conductive region 111e arranged along a first direction X, the first direction X being perpendicular to the thickness direction of the intrinsic semiconductor substrate 111. The first passivation layer 125 is disposed on the first surface 111b and located in the first conductive region 111d. The second passivation layer 126 is disposed on the first surface 111b and located in the second conductive region 111e. The first doped structure 112 has a first doping type and is disposed on the side of the first passivation layer 125 away from the intrinsic semiconductor substrate 111. The second doped structure 113 has a second doping type and is disposed on the side of the second passivation layer 126 away from the intrinsic semiconductor substrate 111.

[0142] In this case, the first doping type and the second doping type are opposite, and the first doping structure 112, the intrinsic semiconductor substrate 111 and the second doping structure 113 constitute a pin structure.

[0143] The solar cell 1 provided in this application embodiment has an intrinsic region 111a, a first doped structure 112, and a second doped structure 113 formed on an intrinsic semiconductor substrate 111, such that the first doped structure 112, the intrinsic region 111a, and the second doped structure 113 constitute a pin structure. Thus, compared to conventional techniques for fabricating solar cells 1 using p-type or n-type semiconductor substrates 111, the solar cell 1 provided in this application embodiment, because it uses an intrinsic semiconductor substrate 111 containing the intrinsic region 111a, does not require the addition of p-type or n-type dopants during the fabrication of the blank (e.g., a silicon rod) of the intrinsic semiconductor substrate 111. This reduces the complexity of the solar cell 1 fabrication process and is more conducive to silicon crystal growth, reducing dislocation density, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rod is cut into wafers, there is no difference in resistivity in the radial and longitudinal directions of the intrinsic silicon wafers. On the one hand, this is beneficial to improving the electrical consistency of the silicon wafers, thereby improving the conversion efficiency of solar cell 1; on the other hand, it is beneficial to improve the utilization rate of silicon rods, thereby reducing the manufacturing cost of solar cell 1.

[0144] It should also be noted that the solar cell 1 provided in this embodiment has a pi junction and an in junction on the intrinsic semiconductor substrate 111. This structure can improve the carrier separation effect, thereby improving the photoelectric conversion efficiency of the solar cell 1. Specifically, compared with the substrate of a conventional solar cell 1, the intrinsic semiconductor substrate 111 in this embodiment contains an intrinsic region 111a, so the doping concentration of the intrinsic semiconductor substrate 111 is much lower than that of a conventional substrate. Since the lower the doping concentration of the substrate, the deeper the built-in electric field of the solar cell 1 penetrates into the substrate, the built-in electric field of the solar cell 1 in this embodiment penetrates into the substrate to a greater depth, and the influence range of the built-in electric field is larger, thereby improving the carrier separation effect.

[0145] It is understood that a plurality of first conductive regions 111d and a plurality of second conductive regions 111e may be provided on the intrinsic semiconductor substrate 111, and the plurality of first conductive regions 111d and the plurality of second conductive regions 111e are arranged alternately along a first direction X. Each first conductive region 111d is provided with a first passivation layer 125 and a first doped structure 112, and each second conductive region 111e is provided with a second passivation layer 126 and a second doped structure 113. An isolation trench is provided between adjacent first doped structures 112 and second doped structures 113.

[0146] In one embodiment, the resistivity of the intrinsic semiconductor substrate 111 is greater than 100 Ω·cm. This effectively results in a very low dopant content in the intrinsic region 111a. This allows for a greater depth of the built-in electric field penetrating the intrinsic semiconductor substrate 111, thereby contributing to improved carrier separation.

[0147] In one embodiment, the doping concentration of the p-type dopant in the intrinsic semiconductor substrate 111 is less than or equal to 1.3 × 10⁻⁶. 14 ㎝ -3 Furthermore, the doping concentration of the n-type dopant in the intrinsic semiconductor substrate 111 is less than or equal to 4.4 × 10⁻⁶. 13 ㎝ -3 This effectively results in a very low dopant content in the intrinsic region 111a. This, in turn, increases the depth to which the built-in electric field penetrates the intrinsic semiconductor substrate 111, thereby improving carrier separation.

[0148] In one embodiment, the thickness of the intrinsic semiconductor substrate 111 is between 50 μm and 300 μm. Exemplarily, the thickness of the intrinsic semiconductor substrate 111 can be 50 μm, 60 μm, 65 μm, 80 μm, 100 μm, 130 μm, 160 μm, 190 μm, 230 μm, 270 μm, 290 μm, 300 μm, or between any two of the above values. By keeping the thickness of the intrinsic semiconductor substrate 111 within the above range, it is beneficial to reduce the thickness of the solar cell 1 and to form a stable pin structure.

[0149] In one embodiment, the doping concentration of the first doped structure 112 is between 3 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20 ㎝ -3 For example, the doping concentration of the first doped structure 112 can be 3 × 10⁻⁶. 18 ㎝ -3 5×10 18 ㎝ -3 1×10 19 ㎝ -3 5×10 20 ㎝ -3 Or it may be between any two of the above values. By keeping the doping concentration of the first doped structure 112 within the above range, it is beneficial to reduce manufacturing costs on the one hand, and on the other hand, the first doped structure 112 can have better conductivity on the other hand.

[0150] In one embodiment, the doping concentration of the second doped structure 113 is between 3 × 10⁻⁶. 18 ㎝ -3 Up to 5×10 20㎝ -3 For example, the doping concentration of the second doped structure 113 can be 3 × 10⁻⁶. 18 ㎝ -3 5×10 18 ㎝ -3 1×10 19 ㎝ -3 5×10 20 ㎝ -3 Or it may be between any two of the above values. By keeping the doping concentration of the second doped structure 113 within the above range, it is beneficial to reduce manufacturing costs and also to give the second doped structure 113 better conductivity.

[0151] In one embodiment, a third dimension H3 is provided between the side of the first doped structure 112 closest to the first surface 111b and the side of the first doped structure 112 furthest from the first surface 111b. The third dimension H3 is between 5 nm and 5000 nm. Exemplarily, the third dimension H3 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, 5000 nm, or any two of the above values. By placing the third dimension H3 within the above range, it is beneficial to reduce manufacturing costs and to form a stable pin structure.

[0152] In one embodiment, a fourth dimension H4 is provided between the side of the second doped structure 113 closest to the first surface 111b and the side of the second doped structure 113 furthest from the first surface 111b. The fourth dimension H4 is between 5 nm and 5000 nm. Exemplarily, the fourth dimension H4 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, 5000 nm, or any two of the above values. By placing the fourth dimension H4 within the above range, it is beneficial to reduce manufacturing costs and to form a stable pin structure.

[0153] In one embodiment, the solar cell 1 further includes a third doped structure 130, which has a second doping type and is disposed on the side of the first doped structure 112 away from the intrinsic semiconductor substrate 111; the third doped structure 130 and the first doped structure 112 form a pn junction. In one example, the third doped structure 130 and the first doped structure 112 can be disposed in the same film structure. This is beneficial for increasing the doping concentration at the contact interface between the first electrode 117 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the contact interface between the first electrode 117 and the intrinsic semiconductor substrate 111, and thus improving the efficiency of the solar cell 1. It is understood that the first doped structure 112 and the third doped structure 130 can also be separate film structures.

[0154] In one embodiment, the solar cell 1 further includes a fourth doped structure 131, which has a first doping type and is disposed on the side of the second doped structure 113 away from the intrinsic semiconductor substrate 111; the fourth doped structure 131 and the second doped structure 113 form a pn junction. In one example, the fourth doped structure 131 and the second doped structure 113 can be disposed in the same film structure, which is beneficial to increasing the doping concentration at the contact interface between the second electrode 118 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the contact interface between the second electrode 118 and the intrinsic semiconductor substrate 111, and thus improving the efficiency of the solar cell 1. It is understood that the second doped structure 113 and the fourth doped structure 131 can also be separate film structures.

[0155] In one embodiment, the first passivation layer 125 and the second passivation layer 126 are configured as tunneling dielectric layers. Exemplarily, the first passivation layer 125 and the second passivation layer 126 may be made of SiOx. The thickness of the first passivation layer 125 and the second passivation layer 126 may be between 0.5 nm and 5 nm.

[0156] Furthermore, the material of the first doped structure 112 and the material of the second doped structure 113 include polycrystalline silicon. The thickness of the first doped structure 112 and the second doped structure 113 can be between 10 nm and 300 nm.

[0157] In one embodiment, the materials of the first passivation layer 125 and the second passivation layer 126 include intrinsic semiconductor materials. Exemplarily, the materials of the first passivation layer 125 and the second passivation layer 126 can be intrinsic microcrystalline silicon or intrinsic amorphous silicon. The thicknesses of the first passivation layer 125 and the second passivation layer 126 can be between 2 nm and 20 nm. Further, the materials of the first doped structure 112 and the second doped structure 113 include microcrystalline silicon or amorphous silicon. The thicknesses of the first doped structure 112 and the second doped structure 113 can be between 5 nm and 25 nm.

[0158] In one embodiment, the solar cell 1 further includes a first antireflection layer 127, a first electrode 117, a second electrode 118, a third passivation layer 129, and a second antireflection layer 128. The first antireflection layer 127 is disposed on the side of the first doped structure 112 away from the intrinsic semiconductor substrate 111, and on the side of the second doped structure 113 away from the intrinsic semiconductor substrate 111. The first electrode 117 is disposed on the side of the first doped structure 112 away from the intrinsic semiconductor substrate 111, penetrates the first antireflection layer 127, and is electrically connected to the first doped structure 112. The second electrode 118 is disposed on the side of the second doped structure 113 away from the intrinsic semiconductor substrate 111, penetrates the first antireflection layer 127, and is electrically connected to the second doped structure 113. The third passivation layer 129 is disposed on the second surface 111c. The second antireflection layer 128 is disposed on the side of the third passivation layer 129 away from the intrinsic semiconductor substrate 111.

[0159] In one embodiment, the material of the third passivation layer 129 may include SiNx, AlOx, amorphous silicon, etc. When the material of the third passivation layer 129 is SiNx, the thickness of the third passivation layer 129 may be between 50nm and 120nm. When the material of the third passivation layer 129 is AlOx, the thickness of the third passivation layer 129 may be between 1nm and 20nm. When the material of the third passivation layer 129 is amorphous silicon, the thicknesses of the first passivation layer 125 and the second passivation layer 126 may be between 2nm and 20nm.

[0160] In one embodiment, the materials of the first antireflection layer 127 and the second antireflection layer 128 may include one or more of SiNx, SiOx, SiNxOy AlOx, ITO, SnO2, MgF2, TiOx and ZnO.

[0161] It should be noted that the inventors conducted experiments on the electrical performance of a conventional BC battery using a silicon substrate and the BC battery in the embodiments of this application, and the data are shown in the table below:

[0162]

[0163] As can be seen from the table above, compared with traditional BC batteries, the embodiments of this application improve the fill factor and open-circuit voltage, reduce the short-circuit current, and in particular, improve the efficiency by 0.04%. It can be seen that the embodiments of this application have a significant efficiency gain.

[0164] It should be noted that the above experimental results are limited by the current experimental level, and the inventors believe that there is still room for further improvement in solar cells using intrinsic semiconductor substrates.

[0165] Thirdly, referring to Figure 9As shown, this application provides a method for fabricating a solar cell. This method is used to fabricate the solar cell described in the first aspect. Specifically, the method includes the following steps:

[0166] S100: Provide an intrinsic semiconductor substrate, the intrinsic semiconductor substrate including an intrinsic region, a first surface and a second surface, the first surface and the second surface being disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region being disposed between the first surface and the second surface.

[0167] S200: A first doped structure and a second doped structure are formed on an intrinsic semiconductor substrate. The first doped structure has a first doping type and is located on the side of the intrinsic region closer to the first surface; the second doped structure has a second doping type and is located on the side of the intrinsic region closer to the second surface; the first doping type and the second doping type are opposite, and the first doped structure, the intrinsic region and the second doped structure constitute a pin structure.

[0168] In one embodiment, with Figure 1 Taking the solar cell shown as an example, S200 specifically includes the following steps:

[0169] S210: The intrinsic semiconductor substrate is placed in a high-temperature diffusion furnace, and a p-type dopant (such as boron) is diffused into the intrinsic semiconductor substrate. Then, the oxide layer (borosilicate glass) and the diffusion layer on the second surface of the intrinsic semiconductor substrate are removed to form a first doped structure. For example, the diffusion depth can be 0.8 μm, and the doping concentration can be 5 × 10⁻⁶. 18 ㎝ -3 Understandably, before S210, a pyramidal textured surface needs to be fabricated on the first and second surfaces of the intrinsic semiconductor substrate.

[0170] S220: Clean the intrinsic semiconductor substrate.

[0171] S230: The intrinsic semiconductor substrate is placed in a high-temperature diffusion furnace, and an n-type dopant (such as phosphorus) is diffused into the intrinsic semiconductor substrate. Then, the oxide layers (such as borosilicate glass or phosphosilicate glass) on the first and second surfaces are removed to form a second doped structure, and the intrinsic semiconductor substrate is cleaned. For example, the diffusion depth can be 0.8 μm, and the doping concentration can be 1 × 10⁻⁶. 20 ㎝ -3 .

[0172] S240: A first passivation anti-reflection layer is formed on the first doped structure, and a second passivation anti-reflection layer is formed on the second doped structure.

[0173] S250: Form a first electrode and a second electrode, wherein the first electrode penetrates the first passivation antireflection layer and is electrically connected to the first doped structure, and the second electrode penetrates the second passivation antireflection layer and is electrically connected to the second doped structure. For example, a silver-aluminum paste can be printed onto the first passivation antireflection layer using a screen printing process, and a silver paste can be printed onto the second passivation antireflection layer, followed by sintering to obtain the first electrode and the second electrode.

[0174] It should be noted that if preparation is required... Figure 2 The solar cell shown in step S210 requires diffusion to form a third doped structure on the intrinsic region near the first surface. In step S230, a fourth doped structure also requires diffusion to form on the intrinsic region near the second surface.

[0175] In one embodiment, with Figure 3 Taking the solar cell shown as an example, S200 specifically includes the following steps:

[0176] S210: The intrinsic semiconductor substrate is placed in a high-temperature diffusion furnace, and a p-type dopant (such as boron) is diffused into the intrinsic semiconductor substrate. Then, the oxide layer (borosilicate glass) and the diffusion layer on the second surface of the intrinsic semiconductor substrate are removed to form a first doped structure. For example, the diffusion depth can be 0.8 μm, and the doping concentration can be 5 × 10⁻⁶. 18 ㎝ -3 Understandably, before S210, a pyramidal textured surface needs to be fabricated on the first and second surfaces of the intrinsic semiconductor substrate.

[0177] S220: Clean the intrinsic semiconductor substrate.

[0178] S230: A first tunneling layer is formed on the second surface of the intrinsic semiconductor substrate.

[0179] S240: A second doped structure is formed on the first tunneling layer. For example, a polycrystalline silicon thin film doped with an n-type dopant is first deposited on the first tunneling layer, and then the polycrystalline silicon thin film is annealed to activate the dopant, thereby forming the second doped structure.

[0180] S250: A first passivation anti-reflection layer is formed on the first doped structure, and a second passivation anti-reflection layer is formed on the second doped structure.

[0181] S260: Form a first electrode and a second electrode, wherein the first electrode penetrates the first passivation antireflection layer and is electrically connected to the first doped structure, and the second electrode penetrates the second passivation antireflection layer and is electrically connected to the second doped structure. For example, a silver-aluminum paste can be printed onto the first passivation antireflection layer using a screen printing process, and a silver paste can be printed onto the second passivation antireflection layer, followed by sintering to obtain the first electrode and the second electrode.

[0182] In one embodiment, with Figure 5 Taking the solar cell shown as an example, S200 specifically includes the following steps:

[0183] S210: A first intrinsic semiconductor layer is formed on the first surface of the intrinsic semiconductor substrate.

[0184] S220: A second intrinsic semiconductor layer is formed on the second surface of the intrinsic semiconductor substrate.

[0185] S230: A first doped structure is formed on the first intrinsic semiconductor layer.

[0186] S240: A second doped structure is formed on the second intrinsic semiconductor layer.

[0187] S250: A first transparent conductive layer is formed on the first doped structure.

[0188] S260: A second transparent conductive layer is formed on the second doped structure.

[0189] S270: A first electrode is formed on a first transparent conductive layer, and a second electrode is formed on a second transparent conductive layer. For example, electrode paste can be printed using a screen printing process, and then cured to obtain the first and second electrodes.

[0190] It should be noted that if you need to make Figure 8 The solar cell shown requires forming a second tunneling layer on the first surface and a third tunneling layer on the second surface before fabricating the first and second doped structures. Then, the first doped structure is formed on the second tunneling layer, and the second doped structure is formed on the third tunneling layer.

[0191] Fourthly, refer to Figure 10 As shown in the embodiments of this application, another method for fabricating a solar cell is provided. This method is used to fabricate the solar cell described in the second aspect, and specifically includes the following steps:

[0192] S10: Provide an intrinsic semiconductor substrate having a first surface and a second surface disposed opposite to each other. The intrinsic semiconductor substrate has a first conductive region and a second conductive region arranged along a first direction perpendicular to the thickness direction of the intrinsic semiconductor substrate.

[0193] S20: A first passivation layer is formed on the first surface, and a first doped structure is formed on the side of the first passivation layer away from the intrinsic semiconductor substrate. The first passivation layer is located in a first conductive region, and the first doped structure has a first doping type.

[0194] S30: A second passivation layer is formed on the first surface, and a second doped structure is formed on the side of the second passivation layer away from the intrinsic semiconductor substrate. The second passivation layer is located in the second conductive region, and the second doped structure has a second doping type, which is the opposite of the first doping type and the second doping type. The first doped structure, the intrinsic semiconductor substrate, and the second doped structure constitute a pin structure.

[0195] In one embodiment, the preparation method further includes the following steps:

[0196] S40: A first anti-reflection layer is formed on the first surface, the first anti-reflection layer covers the first doped structure and the second doped structure, and a third passivation layer and a second anti-reflection layer are formed on the second surface, the third passivation layer being located between the intrinsic semiconductor substrate and the second anti-reflection layer.

[0197] S50: Form a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doped structure and the second electrode is electrically connected to the second doped structure.

[0198] Fifthly, embodiments of this application provide a photovoltaic module, including solar cells from either the first or second aspect.

[0199] For example, the photovoltaic module includes multiple solar cells that can be wired together in series via solder strips, thereby collecting the electrical energy generated by each individual solar cell for subsequent power transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingled configuration.

[0200] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate (not shown). The encapsulation layer covers the surface of the cell string, and the cover plate covers the surface of the encapsulation layer away from the cell string. Solar cells are electrically connected in a single piece or in multiple segments to form multiple cell strings, which are electrically connected in series and / or parallel. Specifically, in some embodiments, multiple cell strings can be electrically connected through conductive links. The encapsulation layer covers the surface of the solar cells. For example, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or other light-transmitting cover plate.

[0201] The photovoltaic module provided in this application embodiment has an intrinsic region on an intrinsic semiconductor substrate, and a first doped structure and a second doped structure are respectively formed on opposite sides of the intrinsic region, so that the first doped structure, the intrinsic region, and the second doped structure constitute a pin structure. Thus, compared with the traditional technology of fabricating solar cells using p-type or n-type semiconductor substrates, the solar cell substrate provided in this application embodiment, because it uses an intrinsic semiconductor substrate containing an intrinsic region, does not require the addition of p-type or n-type dopants during the fabrication of the intrinsic semiconductor substrate blank (e.g., silicon rod). This reduces the complexity of the solar cell fabrication process and is more conducive to silicon crystal growth, reducing dislocation density, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rod is cut into wafers, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafers. This improves the electrical uniformity of the silicon wafers, thereby increasing the conversion efficiency of the solar cell; it also improves the utilization rate of the silicon rod, thereby reducing the manufacturing cost of the solar cell.

[0202] Sixthly, embodiments of this application provide a photovoltaic system including the photovoltaic module described in the fifth aspect.

[0203] Specifically, photovoltaic (PV) systems can be applied in PV power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios for PV systems are not limited to these; that is, PV systems can be applied in all areas that require solar energy for power generation. Taking a PV power grid as an example, a PV system can include PV arrays, combiner boxes, and inverters. A PV array can be an array of multiple PV modules; for example, multiple PV modules can form multiple PV arrays. The PV arrays are connected to combiner boxes, which collect the current generated by the PV arrays. The collected current then flows through an inverter, converting it into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0204] The photovoltaic system provided in this application embodiment forms a pin structure by setting an intrinsic region on an intrinsic semiconductor substrate and setting a first doped structure and a second doped structure on opposite sides of the intrinsic region. Compared to traditional technologies that use p-type or n-type semiconductor substrates to fabricate solar cells, the solar cell substrate provided in this application embodiment, because it uses an intrinsic semiconductor substrate containing an intrinsic region, does not require the addition of p-type or n-type dopants during the fabrication of the intrinsic semiconductor substrate blank (e.g., a silicon rod). This reduces the complexity of the solar cell fabrication process and is more conducive to silicon crystal growth, reducing dislocation density, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rod is cut into wafers, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafers. This improves the electrical uniformity of the silicon wafers, thereby increasing the conversion efficiency of the solar cell; it also improves the utilization rate of the silicon rod, thereby reducing the manufacturing cost of the solar cell.

[0205] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0206] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: An intrinsic semiconductor substrate includes an intrinsic region, a first surface, and a second surface, wherein the first surface and the second surface are disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region is disposed between the first surface and the second surface. A first doped structure having a first doping type, wherein the first doped structure is disposed on the side of the first surface away from the second surface; as well as The second doped structure has a second doping type, and the second doped structure is disposed on the side of the second surface away from the first surface; Wherein, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic region and the second doping structure constitute a pin structure.

2. The solar cell according to claim 1, characterized in that, The resistivity of the intrinsic region is greater than 100 Ω·cm; And / or, the doping concentration of the p-type dopant in the intrinsic region is less than or equal to 1.3 × 10⁻⁶. 14 ㎝ -3 Furthermore, the doping concentration of the n-type dopant in the intrinsic region is less than or equal to 4.4 × 10⁻⁶. 13 ㎝ -3 .

3. The solar cell according to claim 1, characterized in that, The thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

4. The solar cell according to claim 1, characterized in that, The doping concentration of the first doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 ; And / or, the doping concentration of the second doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 .

5. The solar cell according to claim 1, characterized in that, The first doped structure has a first dimension between the side of the first doped structure close to the first surface and the side of the first doped structure away from the first surface, and the first dimension is between 5nm and 5000nm. And / or, the second doped structure has a second dimension between the side of the second doped structure closer to the first surface and the side of the second doped structure farther from the first surface, the second dimension being between 5nm and 5000nm.

6. The solar cell according to claim 1, characterized in that, The solar cell further includes a third doped structure, which has a second doping type and is located on the side of the first doped structure away from the intrinsic region. The third doped structure and the first doped structure form a pn junction.

7. The solar cell according to claim 6, characterized in that, The solar cell further includes a fourth doped structure, which has a first doping type and is located on the side of the second doped structure away from the intrinsic region. The fourth doped structure and the second doped structure form a pn junction.

8. The solar cell according to claim 1, characterized in that, The solar cell further includes a first tunneling layer, which is disposed on the second surface, and the second doped structure is disposed on the side of the first tunneling layer away from the first surface.

9. The solar cell according to claim 8, characterized in that, The solar cell also includes: The first passivation anti-reflection layer is disposed on the side of the first doped structure away from the intrinsic region; The first electrode is disposed on the side of the first doped structure away from the second doped structure, and penetrates the first passivation antireflection layer and is electrically connected to the first doped structure. A second passivation and antireflection layer is disposed on the side of the second doped structure away from the intrinsic region; and The second electrode is disposed on the side of the second doped structure away from the first doped structure, and penetrates the second passivation antireflection layer and is electrically connected to the second doped structure.

10. The solar cell according to claim 1, characterized in that, The solar cell further includes: a first intrinsic semiconductor layer, the first intrinsic semiconductor layer being disposed on the first surface, and the first doped structure being disposed on the side of the first intrinsic semiconductor layer away from the second surface; and The second intrinsic semiconductor layer is disposed on the second surface, and the second doped structure is disposed on the side of the second intrinsic semiconductor layer away from the first surface.

11. The solar cell according to claim 10, characterized in that, The solar cell also includes: A first transparent conductive layer is disposed on the side of the first doped structure away from the first intrinsic semiconductor layer; The first electrode is disposed on the side of the first transparent conductive layer away from the first intrinsic semiconductor layer and is electrically connected to the first transparent conductive layer. A second transparent conductive layer is disposed on the side of the second doped structure away from the second intrinsic semiconductor layer; and The second electrode is disposed on the side of the second transparent conductive layer away from the second intrinsic semiconductor layer and is electrically connected to the second transparent conductive layer.

12. The solar cell according to claim 1, characterized in that, The solar cell also includes: A second tunneling layer is disposed on the first surface, and the first doped structure is disposed on the side of the second tunneling layer away from the second surface; and A third tunneling layer is disposed on the second surface, and the second doped structure is disposed on the side of the third tunneling layer away from the first surface.

13. A solar cell, characterized in that, include: An intrinsic semiconductor substrate has a first surface and a second surface disposed opposite to each other; a first conductive region and a second conductive region are provided on the intrinsic semiconductor substrate along a first direction, the first direction being perpendicular to the thickness direction of the intrinsic semiconductor substrate; A first passivation layer is disposed on the first surface and located in the first conductive region; A second passivation layer is disposed on the first surface and located in the second conductive region; A first doped structure having a first doping type is disposed on the side of the first passivation layer away from the intrinsic semiconductor substrate; as well as The second doped structure has a second doping type and is disposed on the side of the second passivation layer away from the intrinsic semiconductor substrate; Wherein, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic semiconductor substrate and the second doping structure constitute a pin structure.

14. The solar cell according to claim 13, characterized in that, The resistivity of the intrinsic semiconductor substrate is greater than 100 Ω·cm; And / or, the doping concentration of the p-type dopant in the intrinsic semiconductor substrate is less than or equal to 1.3 × 10⁻⁶. 14 ㎝ -3 Furthermore, the doping concentration of the n-type dopant in the intrinsic semiconductor substrate is less than or equal to 4.4 × 10⁻⁶. 13 ㎝ -3 .

15. The solar cell according to claim 13, characterized in that, The thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

16. The solar cell according to claim 13, characterized in that, The doping concentration of the first doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 ; And / or, the doping concentration of the second doped structure is between 3 × 10⁻⁶. 18 ㎝ -3 -5×10 20 ㎝ -3 .

17. The solar cell according to claim 13, characterized in that, The first doped structure has a third dimension between the side of the first doped structure close to the first surface and the side of the first doped structure away from the first surface, the third dimension being between 5nm and 5000nm; And / or, the second doped structure has a fourth dimension between the side of the second doped structure closer to the first surface and the side of the second doped structure farther from the first surface, the fourth dimension being between 5 nm and 5000 nm.

18. The solar cell according to claim 13, characterized in that, The solar cell further includes a third doped structure, which has a second doping type and is located on the side of the first doped structure away from the intrinsic semiconductor substrate. The third doped structure and the first doped structure form a pn junction.

19. The solar cell according to claim 13, characterized in that, The solar cell further includes a fourth doped structure, which has a first doping type and is located on the side of the second doped structure away from the intrinsic semiconductor substrate. The fourth doped structure and the second doped structure form a pn junction.

20. The solar cell according to claim 13, characterized in that, The first passivation layer and the second passivation layer are configured as tunneling dielectric layers; And / or, the materials of the first doped structure and the second doped structure include polycrystalline silicon.

21. The solar cell according to claim 13, characterized in that, The materials of the first passivation layer and the second passivation layer include intrinsic semiconductor materials; And / or, the materials of the first doped structure and the second doped structure include microcrystalline silicon or amorphous silicon.

22. The solar cell according to claim 13, characterized in that, The solar cell also includes: The first anti-reflection layer is disposed on the side of the first doped structure away from the intrinsic semiconductor substrate and on the side of the second doped structure away from the intrinsic semiconductor substrate; The first electrode is disposed on the side of the first doped structure away from the intrinsic semiconductor substrate, and penetrates the first antireflection layer and is electrically connected to the first doped structure. The second electrode is disposed on the side of the second doped structure away from the intrinsic semiconductor substrate, and penetrates the first antireflection layer and is electrically connected to the second doped structure. A third passivation layer is disposed on the second surface; and The second antireflection layer is disposed on the side of the third passivation layer away from the intrinsic semiconductor substrate.

23. A photovoltaic module, characterized in that, Including the solar cell as described in any one of claims 1-22.

24. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 23.

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