Back contact cell, photovoltaic module, and method for manufacturing back contact cell

Abstract

The present application relates to the technical field of solar cells. Disclosed are a back contact cell, a photovoltaic module, and a method for manufacturing a back contact cell. The back contact cell comprises: a semiconductor substrate comprising a first face, a second face and a side face, wherein the second face has a first region and a second region; a first doped semiconductor layer is arranged in at least a portion of the first region, and a second doped semiconductor layer is arranged in the second region and extends over a portion of the first doped semiconductor layer; and the side face has a first textured structure region extending in a direction from the first face to the second face, the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate being less than or equal to 80%. Thus, the probability of generating micro-defects between layers due to different lateral etching efficiencies among a first doped semiconductor layer, a second doped semiconductor layer and a semiconductor substrate can be reduced or eliminated, so as to reduce or eliminate the problem of recombination of finally obtained back contact cells, thereby improving the passivation effect of back contact cells, and thus increasing the cell efficiency of the back contact cells.

Description

A method for manufacturing a back contact cell, a photovoltaic module, and a back contact cell.

[0001] This application claims priority to Chinese Patent Application No. 202410815636.5, filed on June 21, 2024, entitled "A Back Contact Battery, a Photovoltaic Module and a Method for Manufacturing a Back Contact Battery", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of solar cell technology, and more particularly to a back contact cell, a photovoltaic module, and a method for manufacturing a back contact cell. Background Technology

[0003] A back-contact solar cell refers to a solar cell where both the emitter and the metal contact are located on the back of the cell, with no metal electrodes obstructing the front. Compared to solar cells with obstructed front surfaces, back-contact solar cells have higher short-circuit current and photoelectric conversion efficiency, and are one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0004] In the fabrication of back-contact batteries, a doped semiconductor material layer is typically formed on the back surface of a semiconductor substrate, followed by the formation of a dielectric mask layer. Then, a portion of the dielectric mask layer on the semiconductor substrate is removed to form a patterned doped semiconductor layer. However, batteries produced using this process have low efficiency and offer no significant technological advantage compared to other methods. Therefore, further improvements in the technology of back-contact batteries and their efficiency are urgently needed and represent a pressing technical challenge for the industry. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a back contact battery, a photovoltaic module and a method for manufacturing a back contact battery, so as to improve the battery efficiency of the back contact battery.

[0006] To achieve the above objectives, in a first aspect, this application provides a back contact battery. The back contact battery includes: a semiconductor substrate, a first doped semiconductor layer, and a second doped semiconductor layer. The semiconductor substrate includes a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface. The second surface has a first region and a second region alternately distributed along a first direction. The first doped semiconductor layer is disposed in at least a portion of the first region, and the second doped semiconductor layer is disposed in the second region and extends to cover a portion of the first doped semiconductor layer. The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. The side surface has a first textured structure region extending along the direction from the first surface to the second surface, and the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%.

[0007] Compared to existing technologies, when the back contact battery is in operation, the aforementioned first and second doped semiconductor layers can effectively shunt charge carriers, which is beneficial for the formation of photocurrent. The side surface has a first textured structure region extending from the first surface to the second surface; that is, the side closest to the first surface of the semiconductor substrate has the first textured structure region. Therefore, while the first surface traps light, the side surface of the semiconductor substrate can also enhance the light-trapping effect of the semiconductor substrate, increasing the light absorption rate, thereby improving the light utilization rate of the first surface of the semiconductor substrate. Furthermore, the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%. That is, the side closest to the second surface of the semiconductor substrate definitely does not have the first textured structure. This reduces or eliminates the probability of micro-defects generated between layers due to the difference in lateral etching efficiency between the first and second doped semiconductor layers and the semiconductor substrate, thereby reducing or eliminating recombination problems in the final back contact battery, improving the passivation effect of the back contact battery, and thus improving the battery efficiency. Furthermore, the selectable range of the above ratio is relatively large, which can meet the requirements of different application scenarios for the back contact battery, improving the battery efficiency of the back contact battery.

[0008] In one implementation, the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is greater than or equal to 5% and less than or equal to 50%.

[0009] When the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is greater than or equal to 5% and less than or equal to 50%, in terms of product structure, the side surface of the semiconductor substrate has a first textured structure region of 5% to 50%. Compared to texturing more than 50% of the side surface of the semiconductor substrate, this can improve the passivation effect of the side surface. Furthermore, the presence of a first textured structure region near the first surface is beneficial for light trapping, improving the photoelectric conversion efficiency of the back contact cell. Combined with the fabrication process, this ratio range allows for faster production rates and higher efficiency when etched using a roller-carrying liquid method. This is because the amount of liquid carried by the roller-carrying liquid is reduced compared to processes with a larger proportion of first textured structure. Due to the reduced liquid volume, the friction between the roller and the semiconductor substrate increases, which is beneficial for the transport efficiency and stability of the semiconductor substrate.

[0010] In one implementation, the surface of the first region is planar. Along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region to form a groove structure. Along the thickness direction of the semiconductor substrate, the maximum distance between the planar surface and the bottom surface of the groove structure is greater than or equal to 2 μm and less than or equal to 15 μm.

[0011] With the above technical solution, the presence of the groove structure can at least partially offset the first doped semiconductor layer on the first region and the portion of the second doped semiconductor layer on the second region along the thickness direction of the semiconductor substrate. This facilitates at least partially offsetting the electrode structures of the first and second doped semiconductor layers, which have opposite conductivity types, along the thickness direction of the semiconductor substrate, reducing the risk of leakage. Furthermore, if the maximum distance between the plane and the bottom surface of the groove structure along the thickness direction of the semiconductor substrate is within the above-mentioned range, it can prevent the portion of damage to the semiconductor substrate caused by the laser in the early process from not being effectively removed due to an excessively small maximum distance, thus ensuring the quality of the structure formed on the semiconductor substrate later, and thereby ensuring the quality of the final back contact battery. In addition, it can also prevent excessive etching of the semiconductor substrate due to an excessively large maximum distance, which would prolong the process time and make it difficult to ensure the mass production of the battery process.

[0012] In one implementation, the width of the portion of the plane not covered by the first doped semiconductor layer is greater than or equal to 50 nm and less than or equal to 1000 nm, and the width direction is consistent with the first direction.

[0013] With the above technical solution, the width of the portion of the plane not covered by the first doped semiconductor layer is within the aforementioned range. This provides a wider and flatter transition interface for the formation of the second doped semiconductor layer, which is beneficial for increasing the thickness of the second doped semiconductor layer formed in the remaining first region. This results in better conformability of the second doped semiconductor layer, enhances the passivation effect of the second doped semiconductor layer in the first region, further reduces the carrier recombination rate in the first region, and improves the photoelectric conversion efficiency of the back contact cell. Furthermore, it helps to remove more of the damage to the semiconductor substrate caused by the thermal impact of the laser spot edge in previous processes, ensuring the quality and efficiency of the back contact cell.

[0014] In one implementation, the side of the groove structure is inclined relative to the plane, and the angle between the side of the groove structure and the plane is greater than or equal to 100° and less than or equal to 150°.

[0015] When the above technical solution is adopted, the included angle between the side surface of the groove structure and the plane is within the aforementioned range. This not only facilitates the control of the etching area by the etching paste during the fabrication of the insulating groove, reducing or avoiding etching paste deviation, but also allows for better coverage of the side surface of the groove structure during the formation of the second doped semiconductor layer. This prevents unfilled gaps in the second doped semiconductor layer at the boundary between the first and second regions, which have a surface height difference. This reduces the number of defects on the second side of the back contact cell and also improves the formation quality of the second doped semiconductor layer at the boundary between the first and second regions, thereby enhancing the passivation effect of the second doped semiconductor layer at this boundary, reducing the carrier recombination rate, and ultimately improving the photoelectric conversion efficiency of the back contact cell.

[0016] In one implementation, a second texture structure is formed on the bottom surface of the groove structure, and the maximum distance between the top of the second texture structure and the bottom surface of the groove structure is less than the minimum length of the side surface of the groove structure.

[0017] By adopting the above technical solution, it is beneficial that during the formation of the second doped semiconductor layer, the portion of the second doped semiconductor layer from the bottom surface of the groove structure to the side surface of the groove structure better covers the side surface of the groove structure. This prevents unfilled gaps in the second doped semiconductor layer on the side surface of the groove structure, thereby further reducing the number of defects on the second side of the back contact cell and further improving the formation quality of the second doped semiconductor layer at the boundary between the first and second regions. This, in turn, improves the passivation effect of the second doped semiconductor layer at the boundary between the first and second regions, reduces the carrier recombination rate at this point, and thus improves the photoelectric conversion efficiency of the back contact cell.

[0018] In one implementation, the second texture structure is a pyramid-shaped velvety structure, which helps to increase the surface area of ​​the bottom surface of the groove structure, improve the light-trapping effect of the groove structure, and allow more light to be refracted through the bottom surface of the groove structure into the semiconductor substrate and utilized by the semiconductor substrate. Furthermore, the portion of the second doped semiconductor layer corresponding to the second region includes a portion located on the bottom surface of the groove structure. The side of the second doped semiconductor layer formed on the bottom surface through deposition or other processes that faces away from the semiconductor substrate also undulates with the undulations of the bottom surface. That is, the side of the second doped semiconductor layer formed on the bottom surface that faces away from the semiconductor substrate also has a roughly the same undulating morphology as the bottom surface of the groove structure. Therefore, when a texture structure is formed on the bottom surface of the groove structure, the side of the second doped semiconductor layer formed on the bottom surface that faces away from the semiconductor substrate also has corresponding uneven characteristics. This helps to increase the surface area of ​​the side of the second doped semiconductor layer formed on the bottom surface that faces away from the semiconductor substrate, thereby increasing the contact area between the second doped semiconductor layer and the corresponding electrode, reducing the contact resistance between the second doped semiconductor layer and the corresponding electrode, and further improving the working performance of the back contact battery.

[0019] In one implementation, a third texture structure is formed on the surface of the first region, and the side of the third texture structure facing away from the semiconductor substrate has the shape of the base of a pyramid.

[0020] In one implementation, the first doped semiconductor layer includes a doped crystalline silicon layer; the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. And / or, the first doped semiconductor layer has an N-type conductivity, and the second doped semiconductor layer has a P-type conductivity.

[0021] The aforementioned first doped semiconductor layer includes a doped crystalline silicon layer. In this case, compared with a doped amorphous silicon layer, the doped crystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.

[0022] In one implementation, the back contact battery further includes: a first passivation layer, at least located between the first doped semiconductor layer and the first region. And / or, the back contact battery further includes a second passivation layer, located between the second doped semiconductor layer and the second region, and extending over a portion of the first region; the portion of the second doped semiconductor layer corresponding to the first region is located on the portion of the second passivation layer corresponding to the first region.

[0023] With the above technical solution, the first passivation layer and the first doped semiconductor layer can form a passivation contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the charge carrier recombination rate in the first region of the second surface of the semiconductor substrate, and further improving the photoelectric conversion efficiency of the back contact cell. In addition, the second passivation layer and the second doped semiconductor layer can form a passivation contact structure, which also has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the charge carrier recombination rate in the second region of the second surface of the semiconductor substrate, and further improving the photoelectric conversion efficiency of the back contact cell.

[0024] In one implementation, the side surface also has a polished structural surface area, which is located between the first textured structural area and the second surface.

[0025] Using the above technical solution, the side portion with the first textured structure region is close to the first surface. The first surface is a light-facing surface, which is beneficial for the back contact battery to trap light from the side, increasing light utilization and thus improving the photoelectric conversion efficiency of the back contact battery. The side portion near the second surface has a polished structure surface region. This part is on the back side of the back contact battery, closer to the PN junction on the back side, resulting in a higher carrier density. The polished structure surface region on the side reduces surface defects, thereby reducing carrier recombination.

[0026] In one implementation, a passivation layer and an anti-reflection layer are stacked on top of the first texture structure region; or,

[0027] The first textured structure region is stacked with an aluminum oxide passivation layer and a silicon nitride antireflection layer, or...

[0028] An intrinsic amorphous silicon passivation layer and a silicon nitride antireflection layer are stacked on the first textured structure region.

[0029] By adopting the above technical solution, a stacked passivation layer and an anti-reflection layer are set on the first texture structure region, which improves the passivation effect while ensuring the light trapping effect and reduces carrier recombination.

[0030] In one implementation, a tunneling silicon oxide layer and an N-type doped polysilicon layer are stacked on the surface region of the polished structure; or,

[0031] The polished surface region is stacked with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer, and the side surface is sequentially wrapped with an intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, and a silicon nitride layer; or,

[0032] The surface area of ​​the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer, and the side surface is sequentially wrapped with an aluminum oxide layer and a silicon nitride layer.

[0033] The above technical solution involves stacking a tunneling silicon oxide layer, an N-type doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, and a silicon nitride layer on the surface region of the polished structure. Simultaneously, the intrinsic amorphous silicon layer, the P-type doped microcrystalline silicon layer, and the silicon nitride layer also wrap around the surface of the first textured structure region on the side. This composite passivation through layering effectively reduces edge recombination of the semiconductor substrate. Furthermore, the subtle defects generated at the boundary between the first textured structure region and the polished structure surface region due to corrosion are mitigated because the etching rate of the semiconductor substrate differs from that of the first doped semiconductor layer on the side. These defects at the boundary lead to carrier recombination. The passivation by wrapping the side compensates for the efficiency loss caused by these defects, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0034] In one implementation, the boundary line between the first textured structure region and the polished structure surface region is a wavy line.

[0035] By adopting the above technical solution, the boundary line between the first textured structure area and the polished structure surface area on the side of the back contact battery is a wavy line, which can avoid excessive stress concentration on the side of the back contact battery and reduce edge chipping.

[0036] In one implementation, a tunneling silicon oxide layer and an N-type doped polysilicon layer are stacked on the surface region of the polished structure, and the thickness of the N-type doped polysilicon layer near the boundary of the surface region of the polished structure is thinner than that of the N-type doped polysilicon layer away from the boundary.

[0037] Using the above technical solution, near the boundary line, since the boundary is formed by wet etching, the boundary defects of wet etching will increase. The N-type doped polycrystalline silicon layer is thinned at this point, which is beneficial for the passivation of the subsequent intrinsic amorphous silicon layer or alumina layer, reducing recombination caused by defects and improving the photoelectric conversion efficiency of the back contact cell.

[0038] In one implementation, the back contact battery further includes a transparent conductive layer. The transparent conductive layer covers the second doped semiconductor layer and the first doped semiconductor layer; the transparent conductive layer has insulating trenches to physically insulate the portion of the transparent conductive layer corresponding to the first region from the portion of the transparent conductive layer corresponding to the second region.

[0039] Using the above technical solution, the transparent conductive layer covering the first and second doped semiconductor layers has high conductivity, which can promptly export the charge carriers collected by the first and second doped semiconductor layers, reducing the carrier recombination rate. Furthermore, the transparent conductive layer not only improves the current collection capability of the back contact battery but also acts as an anti-reflection film to improve the light absorption rate of the back contact battery. In addition, the transparent conductive layer also has passivation properties. Regarding the insulating groove within the transparent conductive layer, this insulating groove is used to physically insulate the portion of the transparent conductive layer corresponding to the first region from the portion corresponding to the second region. Specifically, since the portion of the transparent conductive layer corresponding to the first region is ohmically connected to the first electrode, and the portion corresponding to the second region is ohmically connected to the second electrode, these two portions of the transparent conductive layer cannot be directly electrically connected; that is, they must be physically insulated, i.e., not in contact. Based on this, it can be understood that, to prevent short circuits, the positions of the two ends of the insulating groove are not restricted, as long as they insulate the transparent conductive layer from the first and second electrodes.

[0040] Secondly, this application also provides a photovoltaic module. This photovoltaic module includes the back-contact battery described in the above-mentioned technical solution.

[0041] Compared with the prior art, the beneficial effects of the photovoltaic module provided in this application are the same as those of the back contact battery described in the above technical solution, and will not be repeated here.

[0042] Thirdly, this application also provides a method for manufacturing a back contact battery. The method for manufacturing the back contact battery includes:

[0043] First, a semiconductor substrate is provided. The semiconductor substrate includes a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface; the second surface includes a first region and a second region alternately distributed along a first direction.

[0044] Next, at least a first doped semiconductor layer is formed on the first region;

[0045] Next, the semiconductor substrate is texturized to give the side a first textured structure region extending from the first surface to the second surface; the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%, and the length direction of the first textured structure region is consistent with the direction from the first surface to the second surface.

[0046] Next, a second doped semiconductor layer is formed covering the second region and extending over a portion of the first doped semiconductor layer; the second doped semiconductor layer has the opposite conductivity type to the first doped semiconductor layer.

[0047] Compared to existing technologies, when the back contact battery is in operation, the aforementioned first and second doped semiconductor layers can effectively shunt charge carriers, which is beneficial for the formation of photocurrent. The side surface has a first textured structure region extending from the first surface to the second surface; that is, the side closest to the first surface of the semiconductor substrate has the first textured structure region. Therefore, while the first surface traps light, the side surface of the semiconductor substrate can also enhance the light-trapping effect of the semiconductor substrate, increasing the light absorption rate, thereby improving the light utilization rate of the first surface of the semiconductor substrate. Furthermore, the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%. That is, the side closest to the second surface of the semiconductor substrate definitely does not have the first textured structure. This reduces or eliminates the probability of micro-defects generated between layers due to the difference in lateral etching efficiency between the first and second doped semiconductor layers and the semiconductor substrate, thereby reducing or eliminating recombination problems in the final back contact battery, improving the passivation effect of the back contact battery, and thus improving the battery efficiency. Furthermore, the selectable range of the above ratio is relatively large, which can meet the requirements of different application scenarios for the back contact battery. Furthermore, compared to existing technologies, the aforementioned manufacturing method for back contact batteries reduces the complexity of the manufacturing process. In summary, this application solves the problems of combining complex patterning processes, leakage control, and passivation improvement in back contact batteries, thereby improving the battery efficiency of back contact batteries.

[0048] In one implementation, forming at least a first doped semiconductor layer on the first region includes:

[0049] A first doped semiconductor material layer is formed on the entire second surface;

[0050] A mask material layer is formed entirely on the first doped semiconductor material layer;

[0051] A mask material layer is processed to form a mask layer on a portion of the first doped semiconductor material layer corresponding to the first region.

[0052] Under the protection of the mask layer, the portion of the first doped semiconductor material layer located on the second region is removed, so that at least the first doped semiconductor layer is formed on the first region;

[0053] Remove the mask layer.

[0054] In one implementation, after forming a mask layer on a portion of the first doped semiconductor material layer corresponding to the first region, and then removing the portion of the first doped semiconductor material layer located in the second region under the protection of the mask layer, the method for manufacturing the back contact battery before at least forming the first doped semiconductor layer on the first region further includes:

[0055] Remove the first doped semiconductor material layer and the mask material layer covering the first side to expose the first side of the semiconductor substrate; and remove at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate.

[0056] When the above technical solution is adopted, a textured structure will be formed on the first surface of the exposed semiconductor substrate and at least part of the side surface of the semiconductor substrate during texturing. This can improve the light trapping effect of the semiconductor substrate, increase the light absorption rate, and thus improve the utilization rate of light by the semiconductor substrate.

[0057] In one implementation, the removal method is wet removal; wherein the concentration of HF is greater than or equal to 5% and less than or equal to 10%, the belt speed is greater than or equal to 1m / s and less than or equal to 2m / s, and the circulation rate is greater than or equal to 80% and less than or equal to 95%.

[0058] When the above technical solution is adopted, the concentration of HF is greater than or equal to 5% and less than or equal to 10%, and the belt speed is greater than or equal to 1m / s and less than or equal to 2m / s; the circulation rate is greater than or equal to 80% and less than or equal to 95%; the ratio of the length of the first textured structure region on the side of the back contact battery to the thickness of the semiconductor substrate is less than or equal to 80%.

[0059] In one implementation, after at least a first doped semiconductor layer is formed on the first region, and before texturing the semiconductor substrate, the method for manufacturing the back contact battery further includes: selectively etching a portion of the semiconductor substrate corresponding to the second region, such that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, forming a groove structure; the surface of the first region is a plane; and the maximum distance between the plane and the bottom surface of the groove structure along the thickness direction of the semiconductor substrate is greater than or equal to 2 μm and less than or equal to 15 μm.

[0060] With the above technical solution, the presence of the groove structure can at least partially offset the first doped semiconductor layer on the first region and the portion of the second doped semiconductor layer on the second region along the thickness direction of the semiconductor substrate. This facilitates at least partially offsetting the electrode structures of the first and second doped semiconductor layers, which have opposite conductivity types, along the thickness direction of the semiconductor substrate, reducing the risk of leakage. Furthermore, if the maximum distance between the plane and the bottom surface of the groove structure along the thickness direction of the semiconductor substrate is within the above-mentioned range, it can prevent the portion of damage to the semiconductor substrate caused by the laser in the early process from not being effectively removed due to an excessively small maximum distance, thus ensuring the quality of the structure formed on the semiconductor substrate later, and thereby ensuring the quality of the final back contact battery. In addition, it can also prevent excessive etching of the semiconductor substrate due to an excessively large maximum distance, which would prolong the process time and make it difficult to ensure the mass production of the battery process.

[0061] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 is a cross-sectional view of the back contact battery in an embodiment of this application;

[0064] Figure 2 is a SEM image of the side of the back contact battery in the embodiment of this application;

[0065] Figure 3 is a second SEM image of the side of the back contact battery in the embodiment of this application;

[0066] Figure 4 is a partially enlarged schematic diagram of Figure 1 in an embodiment of this application;

[0067] Figure 5 is a cross-sectional view of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0068] Figure 6 is a cross-sectional view of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0069] Figure 7 is a cross-sectional view (3) of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0070] Figure 8 is a cross-sectional view of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0071] Figure 9 is a cross-sectional view of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0072] Figure 10 is a cross-sectional view of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0073] Figure 11 is a cross-sectional view (7) of the back contact battery provided in the embodiment of this application during the manufacturing process;

[0074] Figure 12 is a SEM image of the side of the back contact battery provided in the embodiment of this application;

[0075] Figure 13 is a SEM image of the first side of the back contact battery provided in an embodiment of this application.

[0076] Figure label:

[0077] 1-Semiconductor substrate, 10-First side, 11-Second side, 12-First region, 13-Second region, 14-First textured structure region, 15-Second textured structure, 16-Side surface; 2-First doped semiconductor layer, 3-Second doped semiconductor layer, 4-Transparent conductive layer, 5-First passivation layer, 6-Second passivation layer, 7-First doped semiconductor material layer, 8-Mask material layer, 80-Mask layer, 90-Second doped semiconductor material layer, 91-Third passivation layer, 92-Antireflection layer, 93-First electrode, 94-Second electrode. Specific Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0079] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0081] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0082] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0083] Referring to the background section, after forming a dielectric mask layer on a doped semiconductor material layer, the doped semiconductor material layer and the dielectric mask layer are deposited around the semiconductor substrate on its side surface and light-receiving surface. Currently, the doped semiconductor material layer and the dielectric mask layer on the side surface and light-receiving surface of the semiconductor substrate are generally removed to allow the obtained structure to undergo subsequent cleaning and texturing processes. In this case, after the aforementioned cleaning and texturing process, a textured structure is formed on both the side surface and the light-receiving surface of the semiconductor substrate.

[0084] However, because the P and N doped layers of the final back-contact battery are close to the back surface of the semiconductor substrate, and because the lateral etching rates of the semiconductor substrate and the doped layers are different, recombination problems can occur in the final back-contact battery. This reduces the battery efficiency of the back-contact battery.

[0085] To address the aforementioned technical problems, in a first aspect, embodiments of this application provide a back contact battery. Referring to FIG1, the back contact battery includes: a semiconductor substrate 1, a first doped semiconductor layer 2, and a second doped semiconductor layer 3.

[0086] The semiconductor substrate 1 includes a first surface 10 and a second surface 11 opposite to each other, and a side surface 16 connecting the first surface 10 and the second surface 11. The second surface 11 has a first region 12 and a second region 13 alternately distributed along a first direction A. Preferably, the first direction A is orthogonal to the direction from the first surface 10 to the second surface 11.

[0087] In practical applications, the embodiments of this application do not specifically limit the material of the semiconductor substrate. For example, the semiconductor substrate can be any semiconductor material such as silicon substrate, germanium silicon substrate, germanium substrate, or gallium arsenide substrate.

[0088] It should be understood that the first surface 10 is the light-facing surface, and the second surface 11 is the back-light-facing surface. The light-facing surface (i.e., the first surface 10) of the semiconductor substrate 1 can be a plane, or, as shown in Figure 1, the light-facing surface of the semiconductor substrate 1 can also be a textured surface. Since a textured surface has a light-trapping effect, when the light-facing surface of the semiconductor substrate 1 is textured, the reflectivity of the light-facing surface can be reduced, which facilitates more light being refracted from the light-facing surface into the semiconductor substrate 1 and absorbed and utilized by the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0089] A first doped semiconductor layer 2 is disposed in at least a portion of the first region 12, and a second doped semiconductor layer 3 is disposed in the second region 13 and extends to cover a portion of the first doped semiconductor layer 2. The second doped semiconductor layer 3 and the first doped semiconductor layer 2 have opposite conductivity types.

[0090] In terms of scope, the boundary between the first region 12 and the second region 13 on the second surface 11 of the semiconductor substrate 1 is a virtual boundary. As shown in FIG1, the first doped semiconductor layer 2 is formed on at least a portion of the first region 12. Therefore, the scope of the first region 12 on one side of the second surface 11 of the semiconductor substrate 1 can be determined according to the actual application scenario regarding the formation scope of the first doped semiconductor layer 2 and the leakage prevention requirements between the first doped semiconductor layer 2 and the second doped semiconductor layer 3. It can be understood that after the scope of the first region 12 is determined, the scope of the second region 13 on one side of the first surface 10 can be determined.

[0091] Referring to Figures 2 and 3, the side surface 16 has a first textured structure region 14 extending along the direction from the first surface 10 to the second surface 11. The ratio of the length L1 of the first textured structure region 14 to the thickness D of the semiconductor substrate 1 is less than or equal to 80%, and the length direction of the first textured structure region 14 is consistent with the direction from the first surface 10 to the second surface 11. For example, the ratio of the length of the first textured structure region 14 to the thickness of the semiconductor substrate 1 is greater than or equal to 5% and less than or equal to 50%. For example, the ratio can be 5%, 10%, 15%, 20%, 30%, 45%, or 50%, etc. Specifically, when the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is 5% to 50%, compared to more than 50% texturing on the side surface of the semiconductor substrate, the passivation effect of the side surface can be improved. Furthermore, the presence of the first textured structure region in the direction close to the first surface is beneficial for light trapping and improves the photoelectric conversion efficiency of the back contact cell. Simultaneously, combined with the fabrication process, this ratio range allows for faster production rates and higher efficiency through roller-assisted etching. This is because the amount of liquid carried by the roller is reduced compared to a process with a larger proportion of the first textured structure. The reduced liquid volume increases the friction between the roller and the semiconductor substrate, which is beneficial for the transmission efficiency and stability of the semiconductor substrate. For example, in Figure 2, the ratio of the length L1 of the first textured structure region 14 to the thickness D of the semiconductor substrate 1 is approximately 20%. In Figure 3, the ratio is approximately 80%. Furthermore, the side surface 16 also has a polished structural surface region located between the first textured structure region and the second surface. Therefore, by adopting the above technical solution, the side portion with the first textured structure region is close to the first surface, which is a light-facing surface. This facilitates light trapping from the side by the back contact battery, increasing light utilization and thus improving the photoelectric conversion efficiency of the back contact battery. The side portion near the second side has a polished structural surface area. This portion is located on the back side of the battery, closer to the PN junction on the back side, resulting in a higher carrier density. The polished structural surface area on the side reduces surface defects, thereby reducing carrier recombination. In an alternative embodiment, the aforementioned polished structural surface area has a tower-based texture.

[0092] Referring to Figures 1 to 3, compared with the prior art, when the back contact battery is in operation, the first doped semiconductor layer 2 and the second doped semiconductor layer 3 can effectively shunt charge carriers, which is beneficial for the formation of photocurrent. The side surface 16 has a first textured structure region 14 extending along the direction from the first surface 10 to the second surface 11. That is, the side surface near the first surface 10 of the semiconductor substrate 1 has the first textured structure region 14. Therefore, while the first surface 10 performs light-trapping, the side surface of the semiconductor substrate 1 can also enhance the light-trapping effect of the semiconductor substrate 1, increase the light absorption rate, and thus improve the light utilization rate of the first surface 10 of the semiconductor substrate 1. Furthermore, the ratio of the length of the first textured structure region 14 to the thickness of the semiconductor substrate 1 is less than or equal to 80%. That is, the side closest to the second surface 11 of the semiconductor substrate 1 must not have the first textured structure region 14. This reduces or eliminates the probability of micro-defects arising between layers due to the different lateral etching efficiencies of the first doped semiconductor layer 2 and the second doped semiconductor layer 3 with the semiconductor substrate 1, thereby reducing or eliminating recombination problems in the final back contact battery, improving the passivation effect of the back contact battery, and thus increasing the battery efficiency. Furthermore, the range of the above ratio is relatively large, which can meet the requirements of different application scenarios for the back contact battery. In addition, the above back contact battery consists of only three parts: the semiconductor substrate 1, the first doped semiconductor layer 2, and the second doped semiconductor layer 3, making the back contact battery structure simple and easy to manufacture, reducing the complexity of the process compared to existing technologies. Furthermore, a passivation layer and an anti-reflection layer are stacked on the first textured structure region of the side surface 16; or, an aluminum oxide passivation layer and a silicon nitride anti-reflection layer are stacked on the first textured structure region; or, an intrinsic amorphous silicon passivation layer and a silicon nitride anti-reflection layer are stacked on the first textured structure region. A stacked passivation layer and antireflection layer are formed on the first textured structure region to improve the passivation effect while ensuring light trapping and reducing carrier recombination. In summary, the embodiments of this application solve the problems of combining complex patterning processes for back contact batteries with leakage current control and improved passivation, thereby improving the battery efficiency of back contact batteries.

[0093] As one possible implementation, referring to Figure 4, the surface of the first region 12 is planar. Along the direction from the second surface 11 to the first surface 10, the surface of the second region 13 is lower than the surface of the first region 12 to form a groove structure. Along the thickness direction of the semiconductor substrate 1, the maximum distance L2 between the planar surface and the bottom surface of the groove structure is greater than or equal to 2 μm and less than or equal to 15 μm. For example, the maximum distance L2 between the planar surface and the bottom surface of the groove structure can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm, etc.

[0094] The aforementioned groove structure can at least partially offset the portions of the first doped semiconductor layer 2 and the second doped semiconductor layer 3 located on the second region 13 along the thickness direction of the semiconductor substrate 1. This facilitates the at least partial offset of the electrode structures of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, which are respectively in ohmic contact with opposite conductivity types, along the thickness direction of the semiconductor substrate 1, reducing the risk of leakage. Furthermore, the maximum distance between the plane and the bottom surface of the groove structure along the thickness direction of the semiconductor substrate 1 is within the aforementioned range. This prevents the portion of the semiconductor substrate 1 damaged by the laser in the early process from not being effectively removed due to an excessively small maximum distance, ensuring the quality of the structure formed on the semiconductor substrate 1 later, thereby ensuring the quality of the final back contact battery. In addition, it can also prevent excessive etching of the semiconductor substrate 1 due to an excessively large maximum distance, which would prolong the process time and make it difficult to ensure the mass production of the battery.

[0095] In one alternative embodiment, referring to Figure 4, the width W1 of the portion of the plane not covered by the first doped semiconductor layer 2 is greater than or equal to 50 nm and less than or equal to 1000 nm, and the width direction is consistent with the first direction. For example, the width W1 of the portion of the plane not covered by the first doped semiconductor layer 2 can be 50 nm, 100 nm, 150 nm, 300 nm, 450 nm, 650 nm, 800 nm, 900 nm, or 1000 nm, etc. Specifically, the plane here refers to the portion of the surface of the first region 12 near the second region that is not covered by the first doped semiconductor layer 2, with a width of W1.

[0096] The width of the portion of the plane not covered by the first doped semiconductor layer 2 is within the aforementioned range, which provides a wider and flatter transition interface for the formation of the second doped semiconductor layer 3. This facilitates increasing the thickness of the second doped semiconductor layer 3 formed in the remaining first region 12, resulting in better conformability of the second doped semiconductor layer 3. It also enhances the passivation effect of the second doped semiconductor layer 3 in the first region 12, further reducing the carrier recombination rate in the first region 12 and improving the photoelectric conversion efficiency of the back contact cell. Furthermore, it helps to remove more of the damage to the semiconductor substrate 1 caused by the thermal impact of the laser spot edge in previous processes, ensuring the quality and efficiency of the back contact cell.

[0097] In one alternative embodiment, referring to Figure 4, the side of the groove structure is inclined relative to the plane, and the included angle A between the side of the groove structure and the plane is greater than or equal to 100° and less than or equal to 150°. For example, the included angle A between the side of the groove structure and the plane can be 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145°, or 150°, etc.

[0098] The angle between the side surface of the groove structure and the plane is within the aforementioned range. This not only facilitates the control of the etching area by the etching paste during the fabrication of the insulating groove, reducing or avoiding etching paste deviation, but also allows the portion of the second doped semiconductor layer 3 extending from the second region 13 above a portion of the first region 12 to better cover the side surface of the groove structure during the formation of the second doped semiconductor layer 3. This prevents unfilled gaps in the second doped semiconductor layer 3 at the boundary between the first region 12 and the second region 13, which have a surface height difference. This reduces the number of defects on the second surface 11 side of the back contact cell and also improves the formation quality of the second doped semiconductor layer 3 at the boundary between the first region 12 and the second region 13. Consequently, it improves the passivation effect of the second doped semiconductor layer 3 at the boundary between the first region 12 and the second region 13, reduces the carrier recombination rate at this location, and thus improves the photoelectric conversion efficiency of the back contact cell.

[0099] In one alternative embodiment, referring to Figure 4, a second texture structure 15 is formed on the bottom surface of the groove structure, and the maximum distance L3 between the top of the second texture structure 15 and the bottom surface of the groove structure is less than the minimum length L4 of the side surface of the groove structure.

[0100] With the above technical solution, during the formation of the second doped semiconductor layer 3, the portion of the second doped semiconductor layer 3 from the bottom surface of the groove structure to the side surface of the groove structure better covers the side surface of the groove structure. This prevents unfilled gaps from existing in the second doped semiconductor layer 3 on the side surface of the groove structure. This further reduces the number of defects on the second surface 11 side of the back contact cell, while also improving the formation quality of the second doped semiconductor layer 3 at the boundary between the first region 12 and the second region 13. Consequently, it improves the passivation effect of the second doped semiconductor layer 3 at the boundary between the first region 12 and the second region 13, reduces the carrier recombination rate at this point, and thus improves the photoelectric conversion efficiency of the back contact cell.

[0101] In one alternative embodiment, referring to Figure 4, the second texture structure 15 is a pyramid-shaped velvet structure; and / or, a third texture structure is formed on the surface of the first region 12, the side of the third texture structure facing away from the semiconductor substrate 1 having the shape of the base of a pyramid.

[0102] The second texture structure 15 is a pyramid-shaped velvet structure, which is beneficial for increasing the surface area of ​​the bottom surface of the groove structure, improving the light-trapping effect of the groove structure, and allowing more light to be refracted through the bottom surface of the groove structure into the semiconductor substrate 1 and utilized by the semiconductor substrate 1. Furthermore, the pyramid-shaped velvet structure is a pentahedral structure. Compared with texture structures with fewer surfaces, such as V-grooves, when the second texture structure 15 is a pyramid-shaped velvet structure, it is beneficial for increasing the specific surface area of ​​the bottom surface of the groove structure. Furthermore, the portion of the second doped semiconductor layer 3 corresponding to the second region 13 has a portion located on the bottom surface of the groove structure. The side of the second doped semiconductor layer 3 formed on the bottom surface of the groove structure by deposition or other processes that faces away from the semiconductor substrate 1 will also undulate with the undulation of the bottom surface of the groove. That is, the side of the second doped semiconductor layer 3 formed on the bottom surface of the groove structure that faces away from the semiconductor substrate 1 also has a roughly the same undulating morphology as the bottom surface of the groove structure. Therefore, when a textured structure is formed on the bottom surface of the groove structure, the side of the second doped semiconductor layer 3 formed on the bottom surface of the groove structure that faces away from the semiconductor substrate 1 also has corresponding uneven features. This is beneficial to increasing the surface area of ​​the side of the second doped semiconductor layer 3 formed on the bottom surface of the groove that faces away from the semiconductor substrate 1, thereby increasing the contact area between the second doped semiconductor layer 3 and the corresponding electrode, reducing the contact resistance between the second doped semiconductor layer 3 and the corresponding electrode, and further improving the working performance of the back contact battery.

[0103] Regarding the first doped semiconductor layer and the second doped semiconductor layer, from a material perspective, the materials of the first doped semiconductor layer and the second doped semiconductor layer may include at least one semiconductor material such as silicon, germanium silicon, or germanium.

[0104] Preferably, the first doped semiconductor layer includes a doped crystalline silicon layer. In this case, compared with a doped amorphous silicon layer, the doped crystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.

[0105] Preferably, the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. It should be noted that "microcrystalline" in the context of the doped microcrystalline silicon layer refers to the grain size of the silicon material. Specifically, microcrystalline silicon material refers to silicon material with a grain size at the nanometer scale.

[0106] In terms of conductivity type, the first doped semiconductor layer has an N-type conductivity, while the second doped semiconductor layer has a P-type conductivity.

[0107] In terms of thickness, the thickness of the first doped semiconductor layer is greater than or equal to 30 nm and less than or equal to 120 nm. For example, the thickness of the first doped semiconductor layer can be 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, or 120 nm, etc. The thickness of the second doped semiconductor layer is greater than or equal to 3 nm and less than or equal to 50 nm. For example, the thickness of the second doped semiconductor layer can be 3 nm, 10 nm, 16 nm, 20 nm, 30 nm, 40 nm, or 50 nm, etc.

[0108] In terms of formation location, the aforementioned first doped semiconductor layer can be directly formed on at least a portion of the first region on the second surface. Alternatively, as shown in Figure 1, the aforementioned back contact battery further includes a first passivation layer 5, which is located at least between the first doped semiconductor layer 2 and the first region 12. In this case, the first passivation layer 5 and the first doped semiconductor layer 2 can form a passivated contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the first region 12 on the second surface 11 of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the back contact battery. Alternatively, the first passivation layer 5 is located between the first doped semiconductor layer 2 and the first region 12 and on the polished surface region on the side. The material of the aforementioned first passivation layer 5 can be determined according to the material of the first doped semiconductor layer 2. For example, when the first doped semiconductor layer includes a doped crystalline silicon layer, the first passivation layer is a tunneling passivation layer. Preferably, the material of the first passivation layer can be silicon oxide, and the thickness of the first passivation layer is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm, etc.

[0109] As described above, compared to pyramidal or other textured structures, when the third textured structure on the surface of the first region 12 resembles the base of a pyramid on the side facing away from the semiconductor substrate 1, it helps to achieve a relatively low surface roughness on the surface of the first region 12, thus improving the formation quality of the first passivation layer 5. Specifically, the first passivation layer 5 on the first region 12 is relatively thin, and a rough pyramidal textured surface would degrade the passivation effect of the first passivation layer 5, leading to a surface recombination effect. However, the polished base textured structure ensures a high passivation effect for the first passivation layer 5. Furthermore, as described above, compared to forming a textured surface, when the surface of the first region 12 is planar, the surface of the first region 12 is smoother, resulting in a smaller specific surface area. Under certain conditions, when the first passivation layer 5 is formed on the first region 12 and is relatively thin, a rough surface would degrade the passivation effect of the first passivation layer 5, leading to a surface recombination effect. Specifically, the deposition thickness of the film is inversely proportional to the specific surface area of ​​the surface on which it is deposited. Therefore, when the surface of the first region 12 is planar, it is more conducive to the formation of a uniform thickness film of the first passivation layer 5 on the first region 12, which is conducive to enhancing the passivation effect of the first passivation layer 5 in the first region 12, further reducing the carrier recombination rate in the first region 12, and improving the photoelectric conversion efficiency of the back contact battery.

[0110] The aforementioned second doped semiconductor layer can be directly formed on the second region of the second surface and extend above the first region. Alternatively, as shown in Figure 1, the back contact cell further includes a second passivation layer 6. The second passivation layer 6 is located between the second doped semiconductor layer 3 and the second region 13 and extends above a portion of the first region 12. The portion of the second doped semiconductor layer 3 corresponding to the first region 12 is located on the portion of the second passivation layer 6 corresponding to the first region 12. In this case, the second passivation layer 6 and the second doped semiconductor layer 3 can form a passivated contact structure, which has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the second region 13 of the second surface 11 of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the back contact cell. Alternatively, the second passivation layer 6 is located between the second doped semiconductor layer 3 and the second region 13 and extends above a portion of the first region 12, as well as on the polished structure surface region of the semiconductor substrate side. Specifically, in Example 1, a tunneling silicon oxide layer and an N-type doped polysilicon layer are stacked on the polished structure surface region. Example 2: The surface region of the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer. Then, the entire side surface (i.e., the N-type doped polycrystalline silicon layer and the first textured structure region) is sequentially wrapped with an intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, and a silicon nitride layer. Example 3: The surface region of the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer. Then, the entire side surface (i.e., the N-type doped polycrystalline silicon layer and the first textured structure region) is sequentially wrapped with an aluminum oxide layer, a silicon nitride layer, an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer.

[0111] The above technical solution involves stacking a tunneling silicon oxide layer, an N-type doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, and a silicon nitride layer on the surface region of the polished structure. Simultaneously, the intrinsic amorphous silicon layer, the P-type doped microcrystalline silicon layer, and the silicon nitride layer also wrap around the surface of the first textured structure region on the side. This composite passivation through layering effectively reduces edge recombination of the semiconductor substrate. Furthermore, the subtle defects generated at the boundary between the first textured structure region and the polished structure surface region due to corrosion are mitigated because the etching rate of the semiconductor substrate differs from that of the first doped semiconductor layer on the side. These defects at the boundary lead to carrier recombination. The passivation by wrapping the side compensates for the efficiency loss caused by these defects, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0112] The material of the second passivation layer can be determined based on the material of the second doped semiconductor layer. For example, if the second doped semiconductor layer includes a doped amorphous silicon layer, the second passivation layer includes an intrinsic amorphous silicon layer. Preferably, the thickness of the second passivation layer is greater than or equal to 1 nm and less than or equal to 50 nm. For example, the thickness of the second passivation layer can be 1 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc.

[0113] As one possible implementation, the boundary between the first textured structure region and the polished structure surface region is a wavy line.

[0114] By adopting the above technical solution, the boundary line between the first textured structure area and the polished structure surface area on the side of the back contact battery is a wavy line, which can avoid excessive stress concentration on the side of the back contact battery and reduce edge chipping.

[0115] As one possible implementation, the surface region of the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polysilicon layer, and the thickness of the N-type doped polysilicon layer near the boundary of the surface region of the polished structure is thinner than that of the N-type doped polysilicon layer far from the boundary.

[0116] Using the above technical solution, near the boundary line, since the boundary is formed by wet etching, the boundary defects of wet etching will increase. The N-type doped polycrystalline silicon layer is thinned at this point, which is beneficial for the passivation of the subsequent intrinsic amorphous silicon layer or alumina layer, reducing recombination caused by defects and improving the photoelectric conversion efficiency of the back contact cell.

[0117] As one possible implementation, referring to Figure 1, the aforementioned back contact battery further includes a transparent conductive layer 4. The transparent conductive layer 4 covers the second doped semiconductor layer 3 and the first doped semiconductor layer 2. The transparent conductive layer 4 has insulating grooves to physically insulate the portion of the transparent conductive layer 4 corresponding to the first region from the portion of the transparent conductive layer 4 corresponding to the second region.

[0118] The aforementioned transparent conductive layer can be composed of one or more stacked layers selected from ITO (indium tin oxide), ITiO (titanium tin oxide), IWO (tungsten tin oxide), and ICO (cerium tin oxide). The thickness of the transparent conductive layer is greater than or equal to 10 nm and less than or equal to 500 nm. For example, the thickness of the transparent conductive layer can be 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 180 nm, 200 nm, 230 nm, 300 nm, 400 nm, or 500 nm. Preferably, the thickness of the transparent conductive layer is greater than or equal to 50 nm and less than or equal to 200 nm. The thickness direction of the aforementioned transparent conductive layer is consistent with the direction from the first surface to the second surface.

[0119] Using the above technical solution, the transparent conductive layer covering the first and second doped semiconductor layers has high conductivity, which can promptly export the charge carriers collected by the first and second doped semiconductor layers, reducing the carrier recombination rate. Furthermore, the transparent conductive layer not only improves the current collection capability of the back contact battery but also acts as an anti-reflection film to improve the light absorption rate of the back contact battery. In addition, the transparent conductive layer also has passivation properties. Regarding the insulating groove within the transparent conductive layer, this insulating groove is used to physically insulate the portion of the transparent conductive layer corresponding to the first region from the portion corresponding to the second region. Specifically, since the portion of the transparent conductive layer corresponding to the first region is ohmically connected to the first electrode, and the portion corresponding to the second region is ohmically connected to the second electrode, these two portions of the transparent conductive layer cannot be directly electrically connected; that is, they must be physically insulated, i.e., not in contact. Based on this, it can be understood that, to prevent short circuits, the positions of the two ends of the insulating groove are not restricted, as long as they insulate the transparent conductive layer from the first and second electrodes.

[0120] Secondly, embodiments of this application also provide a photovoltaic module. This photovoltaic module includes the back-contact battery described in the above-described technical solution.

[0121] The beneficial effects of the photovoltaic modules provided in this application are the same as those of the back contact batteries described in the above technical solutions, and will not be repeated here.

[0122] Thirdly, embodiments of this application also provide a method for manufacturing a back contact battery. The method for manufacturing the back contact battery includes:

[0123] First, a semiconductor substrate 1 is provided. The semiconductor substrate 1 includes a first surface 10 and a second surface 11 opposite to each other, and a side surface 16 connecting the first surface 10 and the second surface 11; the second surface 11 includes a first region 12 and a second region 13 alternately distributed along a first direction A. A description of the semiconductor substrate 1 can be found in the description in the first aspect, and will not be repeated here.

[0124] Before actual use, the semiconductor substrate is polished and cleaned. Specifically, the semiconductor substrate is placed in a tank polishing machine for pre-cleaning to remove cutting damage and organic matter and other contaminants generated during transportation. The polishing and cleaning steps for the semiconductor substrate include: cleaning with SC-1 from the RCA (Resist Cleaning) process. SC-1 consists of NH4OH / KOH-H2O2-H2O in a ratio of (1:1:5), and the cleaning temperature is 65°C. Next, the residual chemicals from the SC-1 cleaning are neutralized by rinsing with deionized water. Then, alkaline polishing is performed. The alkaline polishing formula is: 5.00% wt KOH, with a KOH stock concentration of (45%), at a temperature of 80°C for 300 seconds. This removes the surface damage layer caused by cutting, and the silicon wafer surface is polished. Next, a high-efficiency SC-1 cleaning was performed, with the ratio of NH4OH / KOH-H2O2-H2O being (1:1:5), at a temperature of 65℃ for 300 seconds. Following this, SC-2 was used to remove residual metal ions. SC-2 was a solution of HCl:H2O2:H2O in a ratio of 1:1:5, at a temperature of 65℃ for 200 seconds. Finally, the semiconductor substrate surface was cleaned with 5% wt hydrofluoric acid, dried, and then polished.

[0125] Next, at least a first doped semiconductor layer is formed on the first region.

[0126] The material, thickness, and formation extent of the first doped semiconductor layer in the first region can be referred to the preceding text. In the actual manufacturing process, forming at least the first doped semiconductor layer in the first region may include the following steps:

[0127] Referring to Figure 5, a first doped semiconductor material layer 7 is formed entirely on the second surface 11. Exemplarily, a process such as chemical vapor deposition can be used to form the semiconductor material layer entirely on the second surface. Then, the semiconductor material layer is doped to form the first doped semiconductor material layer entirely on the second surface.

[0128] Next, referring to Figure 6, a mask material layer 8 is formed integrally on the first doped semiconductor material layer 7. The material of this mask material layer can be one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, or intrinsic silicon. The thickness of the mask material layer is greater than or equal to 10 nm and less than or equal to 120 nm. For example, the thickness of the mask material layer can be 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, or 120 nm, etc. The method for forming the above-mentioned mask material layer includes one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD).

[0129] Next, referring to Figures 6 and 7, the mask material layer 8 is processed to form a mask layer 80 on the portion of the first doped semiconductor material layer 7 corresponding to the first region 12. For example, a portion of the mask material layer 8 is vaporized and ablated using laser ablation. The laser can be one of a green nanosecond laser, a green picosecond laser, an ultraviolet nanosecond laser, or an ultraviolet picosecond laser.

[0130] Next, referring to Figures 6 and 7, the first doped semiconductor material layer 7 and the mask material layer 8 covering the first surface 10 are removed to expose the first surface 10 of the semiconductor substrate 1; and at least a portion of the first doped semiconductor material layer 7 and at least a portion of the mask material layer 8 covering the side surface are removed to expose at least a portion of the side surface of the semiconductor substrate 1.

[0131] When the above technical solution is adopted, a textured structure will be formed on the first surface of the exposed semiconductor substrate and at least part of the side surface of the semiconductor substrate during texturing. This can improve the light trapping effect of the semiconductor substrate, increase the light absorption rate, and thus improve the utilization rate of light by the semiconductor substrate.

[0132] For example, the removal method is wet removal. The HF concentration is greater than or equal to 5% and less than or equal to 10%, the belt speed is greater than or equal to 1 m / s and less than or equal to 2 m / s, and the circulation rate is greater than or equal to 80% and less than or equal to 95%. For example, the HF concentration can be 5%, 6%, 7%, 8%, 9%, or 10%, etc. The belt speed can be 1 m / s, 1.3 m / s, 1.5 m / s, 1.8 m / s, 1.9 m / s, or 2 m / s, etc. The circulation rate can be 80%, 82%, 85%, 88%, 90%, 92%, or 95%, etc.

[0133] Using the above technical solution, a wet-process chain machine is used. A 5%-10% mass concentration HF solution is prepared using a roller-driven liquid conveyor. The conveyor speed is 1-2 m / s, and the circulation rate is 80%-95%. This ensures the front side of the semiconductor substrate contacts the roller. The HF solution corrodes the front side and the sides near the front of the semiconductor substrate, removing silicon nitride from the front side and some of the edge silicon nitride. In this step, different process conditions are selected, using an HF concentration greater than or equal to 5% and less than or equal to 10%, a conveyor speed greater than or equal to 1 m / s and less than or equal to 2 m / s, and a circulation rate greater than or equal to 80% and less than or equal to 95%. This allows for a ratio of the length of the first textured structure region on the side of the back contact cell to the thickness of the semiconductor substrate to be less than or equal to 80%.

[0134] Next, referring to Figures 7 and 8, under the protection of the mask layer 80, the portion of the first doped semiconductor material layer 7 located on the second region 13 is removed to form at least the first doped semiconductor layer 2 on the first region 12. Exemplarily, an etching method such as laser etching or wet etching is used to remove the portion of the first doped semiconductor material layer 7 located on the second region 13 under the protection of the mask layer 80. Furthermore, referring to Figures 5 to 8, when the back contact battery also includes a first passivation layer 5, after providing a semiconductor substrate 1 and before forming at least the first doped semiconductor layer 2 on the first region 12, the above-described method for manufacturing the back contact battery includes: forming the first passivation layer 5 on the first region 12. The first passivation layer 5 is located at least between the first doped semiconductor layer 2 and the first region 12. Descriptions of the material and thickness of the first passivation layer 5 can be found in the description in the first aspect and will not be repeated here.

[0135] For example, before forming the first doped semiconductor layer, a deposition and etching process can be used to form the first passivation layer only on the first region. Alternatively, as shown in FIG5, before forming the first doped semiconductor layer 2, a deposition process can be used to form the first passivation layer 5, which is disposed entirely on the second surface 11. Then, as shown in FIG8, after removing the portion of the first doped semiconductor layer 2 above the second region 13 under the protection of the mask layer 80, a corresponding etching process can be used, under the protection of the mask layer 80, to remove the portion of the first passivation layer 5 above the second region 13. It should be noted that the above-mentioned method for forming the first passivation layer includes one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD).

[0136] Next, referring to Figure 9, the portion of the semiconductor substrate 1 corresponding to the second region 13 is selectively etched to create a groove structure where the surface of the second region 13 is lower than the surface of the first region 12 along the direction from the second surface 11 to the first surface 10. The surface of the first region 12 is planar. Exemplarily, in the actual fabrication process, a mask layer 80 is formed on the first doped semiconductor layer 2. Under the protection of the mask layer 80, a wet chemical process is used to etch the portion of the semiconductor substrate 1 corresponding to the second region 13, creating a groove structure where the surface of the second region 13 is lower than the surface of the first region 12 along the direction from the second surface 11 to the first surface 10. Simultaneously, the etching solution etches laterally, forming the sides and planar portions of the groove structure not covered by the first doped semiconductor layer (i.e., platforms). It should be noted that the etching parameters involved in the above wet chemical process are set according to actual needs and are not specifically limited here.

[0137] Along the thickness direction of the semiconductor substrate 1, the maximum distance L2 between the planar surface and the bottom surface of the groove structure is greater than or equal to 2 μm and less than or equal to 15 μm. For example, the maximum distance L2 between the planar surface and the bottom surface of the groove structure can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm, etc.

[0138] The aforementioned groove structure can at least partially offset the portions of the first doped semiconductor layer 2 and the second doped semiconductor layer 3 located on the second region 13 along the thickness direction of the semiconductor substrate 1. This facilitates the at least partial offset of the electrode structures of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, which are respectively in ohmic contact with opposite conductivity types, along the thickness direction of the semiconductor substrate 1, reducing the risk of leakage. Furthermore, if the maximum distance L2 between the plane and the bottom surface of the groove structure along the thickness direction of the semiconductor substrate 1 is within the aforementioned range, it can prevent the portion of damage to the semiconductor substrate 1 caused by the laser in the early process from not being effectively removed due to an excessively small maximum distance, thus ensuring the quality of the structure formed on the semiconductor substrate 1 later, and thereby ensuring the quality of the final back contact battery. In addition, it can also prevent excessive etching of the semiconductor substrate 1 due to an excessively large maximum distance, which would prolong the process time and make it difficult to ensure the mass production of the battery process.

[0139] Based on the preceding description, compared to forming a textured surface, the surface of the first region 12 is flatter and has a smaller specific surface area when it is planar. Under certain conditions, a first passivation layer 5 is formed on the first region 12, and this first passivation layer 5 is relatively thin. A rough surface can lead to a deterioration in the passivation effect of the first passivation layer 5, resulting in a surface recombination effect. Specifically, the deposition thickness of the film is inversely proportional to the specific surface area of ​​the surface on which it is deposited. Therefore, when the surface of the first region 12 is planar, it is more conducive to the formation of a uniform thickness film of the first passivation layer 5 on the first region 12, which enhances the passivation effect of the first passivation layer 5 in the first region 12, further reduces the carrier recombination rate in the first region 12, and improves the photoelectric conversion efficiency of the back contact cell.

[0140] Next, referring to Figures 2 and 3, the semiconductor substrate 1 is texturized to give the side surface a first textured structure region 14 extending along the direction from the first surface 10 to the second surface 11; the ratio of the length of the first textured structure region 14 to the thickness of the semiconductor substrate 1 is less than or equal to 80%, and the length direction of the first textured structure region 14 is consistent with the direction from the first surface 10 to the second surface 11. For example, the ratio of the length of the first textured structure region 14 to the thickness of the semiconductor substrate 1 is greater than or equal to 5% and less than or equal to 50%.

[0141] In the actual manufacturing process, texturing a semiconductor substrate may include the following steps:

[0142] First, clean the semiconductor substrate;

[0143] For example, the semiconductor substrate is cleaned with SC-1, which consists of KOH, H2O2 and H2O in a ratio of 1:2:5. The cleaning temperature is 65°C and the cleaning time is 360s.

[0144] Next, the groove structure is polished;

[0145] For example, the polishing treatment is an alkaline polishing treatment, with a KOHwt concentration greater than or equal to 0.2% and less than or equal to 5%. For instance, the KOHwt concentration can be 0.2%, 1%, 2%, 3%, 4%, or 5%, etc. The temperature is greater than or equal to 40°C and less than or equal to 85°C. For instance, the temperature can be 40°C, 50°C, 60°C, 70°C, 75°C, 80°C, or 85°C, etc. The time is greater than or equal to 200s and less than or equal to 600s. For instance, the time can be 200s, 240s, 280s, 300s, 320s, 340s, 360s, 400s, 500s, or 600s, etc.

[0146] Next, texturing is performed on the side surfaces of the semiconductor substrate, the bottom surface of the groove structure, and the first surface of the semiconductor substrate.

[0147] For example, the texturing process of the semiconductor substrate uses a TS53V01:KOH:DIW system, wherein the TS53V01 wt% concentration is greater than or equal to 0.2% and less than or equal to 1.5%, for example, the TS53V01 wt% concentration can be 0.2%, 0.5%, 0.8%, 1.0%, 1.2%, 1.3%, or 1.5%, etc. The KOH wt% concentration is greater than or equal to 0.2% and less than or equal to 3%, for example, the KOH wt% concentration can be 0.2%, 0.5%, 0.8%, 1.0%, 1.2%, 1.3%, 1.5%, 2%, 2.3%, 2.8%, or 3%, etc. The temperature is greater than or equal to 75°C and less than or equal to 85°C, for example, the temperature can be 75°C, 76°C, 77°C, 78°C, 79°C, 80°C, 81°C, 82°C, 83°C, 84°C, or 85°C, etc. The time is greater than or equal to 300s and less than or equal to 720s. For example, the time can be 300s, 350s, 400s, 450s, 500s, 550s, 600s, 650s, 700s, or 720s, etc.

[0148] Next, high-efficiency SC-1 cleaning is performed. SC-1 is composed of KOH, H2O2 and H2O, with a ratio of 1:2:5. The cleaning temperature is 65℃ and the cleaning time is 300s.

[0149] Next, as shown in Figure 10, remove the mask layer 80. For example, the mask layer 80 can be removed using 5% wt-10% wt hydrofluoric acid for 600 s.

[0150] Next, referring to FIG11, a second doped semiconductor layer 3 is formed covering the second region 13 and extending over a portion of the first doped semiconductor layer 2; the second doped semiconductor layer 3 and the first doped semiconductor layer 2 have opposite conductivity types.

[0151] For example, referring to Figures 11 and 12, a semiconductor material layer can be integrally formed on the second surface 11 using processes such as chemical vapor deposition (e.g., one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD)). Next, the semiconductor material layer is doped to form a second doped semiconductor material layer 90 integrally on the second surface 11. Then, laser vaporization is used to ablate the portion of the second doped semiconductor material layer 90 above at least a portion of the first doped semiconductor layer 2 to form a second doped semiconductor layer 3 covering the second region 13 and extending above a portion of the first doped semiconductor layer 2. It should be noted that if a mask layer 80 covering the first region 12 is retained after forming the groove structure or texturing process but before forming the second doped semiconductor layer 3, the portion of the mask layer 80 covering at least a portion of the first doped semiconductor layer 2 also needs to be removed to allow the first doped semiconductor layer 2 to be electrically connected to the corresponding electrode. Furthermore, the aforementioned laser can be one of a green nanosecond laser, a green picosecond laser, an ultraviolet nanosecond laser, or an ultraviolet picosecond laser.

[0152] Additionally, referring to Figures 9 to 11, when the back contact battery also includes a second passivation layer 6, after selectively etching the portion of the semiconductor substrate 1 corresponding to the second region 13 to form a groove structure such that the surface of the second region 13 is lower than the surface of the first region 12 along the direction from the second surface 11 to the first surface 10, before forming the second doped semiconductor layer 3 covering the second region 13 and extending over a portion of the first doped semiconductor layer 2, the manufacturing method of the aforementioned back contact battery includes: forming a second passivation layer 6 covering the second region 13 and extending over a portion of the first region 12. The second passivation layer 6 is located between the second doped semiconductor layer 3 and the second region 13 and extends over a portion of the first region 12; the portion of the second doped semiconductor layer 3 corresponding to the first region 12 is located on the portion of the second passivation layer 6 corresponding to the first region 12.

[0153] For example, before forming the second doped semiconductor layer, a second passivation layer can be formed by deposition and etching processes, covering only the second region and extending over a portion of the first region. Alternatively, as shown in Figures 15 and 16, after forming the first doped semiconductor layer 2, a second passivation layer 6 is formed entirely on the second surface 11 using a deposition process. Then, as shown in Figure 17, after removing the portion of the second doped semiconductor layer 3 above at least a portion of the first doped semiconductor layer 2 using a laser process, the portion of the second passivation layer 6 above at least a portion of the first doped semiconductor layer 2 is removed using a corresponding laser process.

[0154] Furthermore, referring to Figure 11, when a third passivation layer 91 and an antireflection layer 92 are formed on the first surface 10 of the back contact battery, after selectively etching the portion of the semiconductor substrate 1 corresponding to the second region 13 to form a groove structure such that the surface of the second region 13 is lower than the surface of the first region 12 along the direction from the second surface 11 to the first surface 10, before or after forming the second doped semiconductor layer 3 covering the second region 13 and extending over a portion of the first doped semiconductor layer 2, the manufacturing method of the aforementioned back contact battery includes: forming a third passivation layer 91 on the first surface 10, and then forming an antireflection layer 92 on the third passivation layer 91. Exemplarily, the material of the third passivation layer may include Al2O3, ia-Si:H, or SiO2. x SiN x H, SiO x N y The total thickness of the third passivation layer and the antireflection layer is greater than or equal to 5 nm and less than or equal to 200 nm. For example, the total thickness can be 5 nm, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 180 nm, or 200 nm, etc. The thickness of the third passivation layer is greater than or equal to 2 nm and less than or equal to 100 nm. For example, the thickness of the third passivation layer can be 2 nm, 30 nm, 40 nm, 60 nm, 80 nm, or 100 nm, etc. The thickness of the antireflection layer is greater than or equal to 3 nm and less than or equal to 100 nm. For example, the thickness of the antireflection layer can be 3 nm, 30 nm, 40 nm, 60 nm, 80 nm, or 100 nm, etc.

[0155] Next, referring to FIG11, a transparent conductive layer 4 is formed covering the first doped semiconductor layer 2 and the second doped semiconductor layer 3;

[0156] Next, an insulating groove is formed in the transparent conductive layer 4 to physically insulate the portion of the transparent conductive layer 4 corresponding to the first region from the portion of the transparent conductive layer 4 corresponding to the second region.

[0157] For example, an etchant is used to remove part of the transparent conductive layer to form an insulating trench, preventing leakage caused by the interconnection of the first and second doped semiconductor layers. The insulation resistance of the insulating trench is tested to be >2MΩ, and the etching width is greater than or equal to 40μm and less than or equal to 150μm. For example, the etching width can be 40μm, 60μm, 80μm, 100μm, 120μm, 140μm, or 150μm, etc.

[0158] Next, referring to FIG11, electrode paste is printed on the transparent conductive layer 4 located on the first doped semiconductor layer 2 and the second doped semiconductor layer 3 to form a first electrode 93 electrically connected to the first doped semiconductor layer 2 and a second electrode 94 electrically connected to the second doped semiconductor layer 3.

[0159] Compared with existing technologies, when the back contact battery is in operation, the first doped semiconductor layer 2 and the second doped semiconductor layer 3 can effectively shunt charge carriers, which is beneficial for the formation of photocurrent. Secondly, the transparent conductive layer 4 covering the first doped semiconductor layer 2 and the second doped semiconductor layer 3 has high conductivity, which can promptly export the charge carriers collected by the first doped semiconductor layer 2 and the second doped semiconductor layer 3, reducing the carrier recombination rate. Furthermore, the transparent conductive layer 4 not only improves the current collection capability of the back contact battery, but also acts as an anti-reflection film to improve the light absorption rate of the back contact battery. In addition, the transparent conductive layer 4 also has passivation properties. Furthermore, the transparent conductive layer 4 has insulating grooves. These insulating grooves can then serve as insulation, preventing leakage and thus controlling leakage current. Furthermore, the side surface has a first textured structure region 14 extending along the direction from the first surface 10 to the second surface 11. That is, the side surface near the first surface 10 of the semiconductor substrate 1 has the first textured structure region 14. Therefore, while the first surface 10 performs light trapping, the side surface of the semiconductor substrate 1 can also enhance the light trapping effect of the semiconductor substrate 1, increase the light absorption rate, and thus improve the light utilization rate of the first surface 10 of the semiconductor substrate 1. In addition, the ratio of the length of the first textured structure region 14 to the thickness of the semiconductor substrate 1 is less than or equal to 80%. That is, the side surface near the second surface 11 of the semiconductor substrate 1 definitely does not have the first textured structure region 14. At this time, the probability of micro-defects generated between layers due to the difference in lateral etching efficiency between the first doped semiconductor layer 2 and the second doped semiconductor layer 3 and the semiconductor substrate 1 can be reduced or eliminated, thereby reducing or eliminating the recombination problem of the final back contact battery, improving the passivation effect of the back contact battery, and thus improving the battery efficiency of the back contact battery. Furthermore, the above ratio has a wide selectable range, which can meet the requirements of back contact batteries for different application scenarios. Furthermore, compared to existing technologies, the aforementioned manufacturing method for back contact batteries reduces the complexity of the manufacturing process. In summary, this application solves the problems of combining complex patterning processes, leakage control, and passivation improvement in back contact batteries, thereby improving the battery efficiency of back contact batteries.

[0160] The present application also provides the following specific embodiments for detailed explanation.

[0161] Example 1:

[0162] S1 provides a monocrystalline silicon substrate (i.e., a semiconductor substrate), which has a front side, a back side, and a side side. The dimension of the side side along the direction from the first surface to the second surface is the thickness dimension of the monocrystalline silicon substrate. The monocrystalline silicon substrate is cleaned of damaged layers and polished.

[0163] S2, a tunneling silicon oxide layer, a doped polycrystalline silicon layer, and a silicon nitride mask layer are sequentially formed on the back side of a single-crystal silicon substrate;

[0164] S3, perform laser ablation on a local area of ​​the silicon nitride mask layer to form an opening region, and then etch the opening region to remove the tunneling silicon oxide and doped polysilicon layer corresponding to the opening region.

[0165] S4. The single-crystal silicon substrate treated in S3 is placed in an HF solution to float on water, which etches away all the silicon nitride mask layers on the front and sides of the single-crystal silicon substrate.

[0166] S5, the single crystal silicon substrate after S4 is texturized in an alkaline bath. During the texturization process of the semiconductor substrate, SC-1 texturization is performed on the semiconductor substrate. SC-1 is composed of KOH-H2O2-H2O in a ratio of (1:2:5). The cleaning temperature is 65℃ and the cleaning time is 360s.

[0167] In step S6, an aluminum oxide passivation layer and a silicon nitride antireflection layer are deposited on the front side of a single-crystal silicon substrate, and intrinsic amorphous silicon and doped microcrystalline silicon are deposited on the back side. The non-opening region in step S3 is opened to expose the doped polycrystalline silicon layer.

[0168] S7, deposit a transparent conductive layer on the back side of the single-crystal silicon substrate, and etch the area where the film was not opened in step S6 to break the transparent conductive layer and form an insulating first transparent conductive layer and a second transparent conductive layer.

[0169] S8, electrode grid lines are formed on the first transparent conductive layer and the second transparent conductive layer, respectively.

[0170] Example 2

[0171] Compared to Example 1, Example 2 adds an alkaline polishing process after the semiconductor substrate undergoes SC-1 cleaning in step S5. Specifically, the KOH wt concentration is 5%, the temperature is 80°C, and the time is 200s. At this point, the maximum distance between the plane and the bottom surface of the groove structure along the thickness direction of the semiconductor substrate is 10μm, more effectively removing the damage caused to the semiconductor substrate by the laser in the previous process. This results in significant advantages in open-circuit voltage and fill factor, with an efficiency improvement of 0.091%.

[0172] Example 3:

[0173] The process in this embodiment is the same as that in Embodiment 1, except for S4, as follows:

[0174] S4, the front side of the single crystal silicon substrate is brought into contact with the roller by means of a roller carrying liquid. The solution in the roller carrying liquid contains HF solution, the concentration of HF is greater than or equal to 5% and less than or equal to 10%, the belt speed is greater than or equal to 1m / s and less than or equal to 2m / s, and the circulation volume is greater than or equal to 80% and less than or equal to 95%.

[0175] When removing the first doped semiconductor material layer (i.e., the doped polysilicon layer) and the mask material layer (i.e., the silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used with an HF concentration of 5%, a belt speed of 1.5 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 10%.

[0176] Compared to Example 1, as shown in Figure 12, in Example 3, most of the first doped semiconductor material layer and most of the mask material layer covering the side are retained, and the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 10%. In this case, the open-circuit voltage and Isc are superior, and the efficiency is improved by 0.18%.

[0177] Example 4:

[0178] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0179] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 5%, a belt speed of 1.0 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 5%.

[0180] Compared with Example 1, Example 4 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.203%.

[0181] Example 5:

[0182] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0183] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 5%, a belt speed of 1.5 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 20%.

[0184] Compared with Example 1, Example 5 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.178%.

[0185] Example 6:

[0186] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0187] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 5%, a belt speed of 1.8 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 50%.

[0188] Compared with Example 1, Example 6 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.178%.

[0189] Example 7:

[0190] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0191] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 7%, a belt speed of 1.8 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 60%.

[0192] Compared with Example 1, Example 7 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.15%.

[0193] Example 8:

[0194] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0195] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 8%, a belt speed of 1.9 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 80%.

[0196] Compared with Example 1, Example 8 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.098%.

[0197] Example 9:

[0198] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0199] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 9%, a belt speed of 1.5 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 85%.

[0200] Compared with Example 1, Example 9 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.004%.

[0201] Example 10:

[0202] This embodiment is basically the same as the process steps in embodiment 3, except that step S4 is different, as follows:

[0203] S4, when removing the first doped semiconductor material layer (i.e., doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first side to expose the first side of the semiconductor substrate, a wet chain machine is used, with an HF concentration of 9%, a belt speed of 1.5 m / s, and a cycle rate of 80%. After removing at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side to expose at least a portion of the side of the semiconductor substrate, the ratio of the length of the first textured structure region on the side to the thickness of the semiconductor substrate is 90%.

[0204] Compared with Example 1, Example 10 has advantages in open-circuit voltage and Isc, and the efficiency is improved by 0.003%.

[0205] Example 11:

[0206] When texturing the side surface of the semiconductor substrate, the bottom surface of the groove structure, and the first surface of the semiconductor substrate, the TS53V01:KOH:DIW system is used, wherein the TS53V01 wt% concentration is 1.5%, the KOH wt% concentration is 2%, the temperature is 85℃, and the time is 350s.

[0207] Compared with Example 1, Example 11 removes part of the first doped semiconductor material layer (i.e., partially doped polysilicon layer) and mask material layer (i.e. silicon nitride mask layer) covering the first surface and side surface. The ratio of the length of the first textured structure region on the side surface to the thickness of the semiconductor substrate is 5%. The etching rate of texturing is increased, the 100-face / 111-face selectivity is reduced, the side surface of the groove structure is flatter, and the angle between the side surface of the groove structure and the plane is 133°, which makes the second passivation layer more conformal. This isolates the first doped semiconductor layer and the second doped semiconductor layer, significantly reduces leakage current IVRV2, and improves efficiency by 0.215%.

[0208] Example 12:

[0209] When texturing the side surface of the semiconductor substrate, the bottom surface of the groove structure, and the first surface of the semiconductor substrate, the TS53V01:KOH:DIW system is used, wherein the TS53V01 wt% concentration is 1%, the KOH wt% concentration is 1%, the temperature is 82℃, and the time is 550s.

[0210] Compared to Example 1, Example 12 removes a portion of the first doped semiconductor material layer (i.e., partially doped polysilicon layer) and mask material layer (i.e., silicon nitride mask layer) covering the first surface and side surfaces. The ratio of the length of the first textured structure region on the side surface to the thickness of the semiconductor substrate is 5%. The texturing time is increased, resulting in a width of 212 nm for the portion of the plane not covered by the first doped semiconductor layer. This provides a wider and flatter transition interface for the second passivation layer. Simultaneously, the side surface of the groove structure shifts laterally towards the isolation region, further reducing the damage to the semiconductor substrate in the isolation region caused by the thermal effects of the laser spot edge. As a result, both the open-circuit voltage and fill factor are improved, and the efficiency is increased by 0.226%.

[0211] Table 1. Test parameters of the back contact batteries manufactured in Examples 1-12

[0212] Where Jsc represents the short-circuit current density, Voc represents the open-circuit voltage, FF represents the fill factor, Eff represents the efficiency, Rs represents the series resistance, and IVRV2 represents the leakage current.

[0213] The test data from the above embodiments show that, when the back contact battery is in operation, the first and second doped semiconductor layers can effectively shunt charge carriers, which is beneficial for the formation of photocurrent. The side has a first textured structure region extending from the first surface to the second surface; that is, the side closest to the first surface of the semiconductor substrate has the first textured structure region. Therefore, while the first surface traps light, the side of the semiconductor substrate can also enhance the light-trapping effect of the semiconductor substrate, increasing the light absorption rate, thereby improving the utilization rate of light from the first surface of the semiconductor substrate. Furthermore, the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%. That is, the side closest to the second surface of the semiconductor substrate definitely does not have the first textured structure. This reduces or eliminates the probability of micro-defects generated between layers due to the different lateral etching efficiencies of the first and second doped semiconductor layers and the semiconductor substrate, thereby reducing or eliminating recombination problems in the final back contact battery, improving the passivation effect of the back contact battery, and thus improving the battery efficiency. Furthermore, the selectable range of the above ratio is relatively large, which can meet the requirements of different application scenarios for the back contact battery and improve the battery efficiency of the back contact battery. Meanwhile, when the ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is greater than or equal to 5% and less than or equal to 50%, in terms of product structure, the side surface of the semiconductor substrate has a first textured structure region of 5% to 50%. Compared to texturing more than 50% of the side surface of the semiconductor substrate, this can improve the passivation effect of the side surface. Furthermore, the presence of a first textured structure region near the first surface is beneficial for light trapping, improving the photoelectric conversion efficiency of the back contact cell. Combined with the fabrication process, this ratio range allows for faster production rates and higher efficiency when etched using a roller-carrying liquid method. This is because the amount of liquid carried by the roller is reduced compared to a process with a larger proportion of first textured structure. Due to the reduced liquid volume, the friction between the roller and the semiconductor substrate increases, which is beneficial for the transmission efficiency and stability of the semiconductor substrate.

[0214] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0215] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A back-contact battery, wherein, include: A semiconductor substrate includes a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface; The second surface has a first region and a second region that are alternately distributed along a first direction; A first doped semiconductor layer is disposed in at least a portion of the first region; A second doped semiconductor layer is disposed in the second region and extends to cover a portion of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. The side surface has a first textured structure region extending along the direction from the first surface to the second surface; The ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%.

2. The back contact battery according to claim 1, wherein, The ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is greater than or equal to 5% and less than or equal to 50%.

3. The back contact battery according to claim 1, wherein, The surface of the first region is a plane; along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region to form a groove structure; Along the thickness direction of the semiconductor substrate, the maximum distance between the plane and the bottom surface of the groove structure is greater than or equal to 2 μm and less than or equal to 15 μm.

4. The back contact battery according to claim 3, wherein, The width of the portion of the plane not covered by the first doped semiconductor layer is greater than or equal to 50 nm and less than or equal to 1000 nm; the width direction is consistent with the first direction.

5. The back contact battery according to claim 3, wherein, The side of the groove structure is inclined relative to the plane, and the angle between the side of the groove structure and the plane is greater than or equal to 100° and less than or equal to 150°.

6. The back contact battery according to claim 3, wherein, A second texture structure is formed on the bottom surface of the groove structure, and the maximum distance between the top of the second texture structure and the bottom surface of the groove structure is less than the minimum length of the side surface of the groove structure.

7. The back contact battery according to claim 6, wherein, The second texture structure is a pyramid-shaped velvet structure; and / or, A third texture structure is formed on the surface of the first region, and the side of the third texture structure facing away from the semiconductor substrate has the shape of the base of a pyramid.

8. The back contact battery according to claim 1, wherein, The first doped semiconductor layer includes a doped crystalline silicon layer; the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. And / or, The first doped semiconductor layer has an N-type conductivity, and the second doped semiconductor layer has a P-type conductivity.

9. The back contact battery according to claim 1, wherein, The back contact battery further includes: a first passivation layer, at least located between the first doped semiconductor layer and the first region; and / or, The back contact battery further includes a second passivation layer located between the second doped semiconductor layer and the second region, and extending over a portion of the first region; the portion of the second doped semiconductor layer corresponding to the first region is located on the portion of the second passivation layer corresponding to the first region.

10. The back contact battery according to any one of claims 1 to 9, wherein, The side also has a polished structural surface area, which is located between the first textured structural area and the second surface.

11. The back contact battery according to any one of claims 1 to 9, wherein, A passivation layer and an anti-reflection layer are stacked on the first texture structure region; or, An aluminum oxide passivation layer and a silicon nitride antireflection layer are stacked on the first textured structure region; or, An intrinsic amorphous silicon passivation layer and a silicon nitride antireflection layer are stacked on the first textured structure region.

12. The back contact battery according to claim 10, wherein, The surface region of the polished structure is layered with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer; or... The surface region of the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer, and the side surface is sequentially wrapped with an intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, and a silicon nitride layer; or... The surface region of the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer, and the side surface is sequentially wrapped with an aluminum oxide layer and a silicon nitride layer.

13. The back contact battery according to claim 10, wherein, The boundary line between the first textured structure region and the polished structure surface region is a wavy line.

14. The back contact battery according to claim 13, wherein, The surface region of the polished structure is stacked with a tunneling silicon oxide layer and an N-type doped polysilicon layer. The thickness of the N-type doped polysilicon layer near the boundary line of the surface region of the polished structure is thinner than that of the N-type doped polysilicon layer away from the boundary line.

15. The back contact battery according to claim 1, wherein, It also includes a transparent conductive layer, which covers the second doped semiconductor layer and the first doped semiconductor layer; the transparent conductive layer has an insulating groove to physically insulate the portion of the transparent conductive layer corresponding to the first region from the portion of the transparent conductive layer corresponding to the second region.

16. A photovoltaic module, wherein, Includes the back contact battery as described in any one of claims 1 to 15.

17. A method for manufacturing a back contact battery, wherein, include: A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, and a side surface connecting the first and second surfaces; The second surface includes a first region and a second region that are alternately distributed along a first direction; At least a first doped semiconductor layer is formed on the first region; The semiconductor substrate is texturized to give the side surface a first textured structure region extending along the direction from the first surface to the second surface; The ratio of the length of the first textured structure region to the thickness of the semiconductor substrate is less than or equal to 80%, and the length direction of the first textured structure region is consistent with the direction from the first surface to the second surface. A second doped semiconductor layer is formed covering the second region and extending over a portion of the first doped semiconductor layer; the second doped semiconductor layer has the opposite conductivity type to the first doped semiconductor layer.

18. The method for manufacturing a back contact battery according to claim 17, wherein, Forming at least a first doped semiconductor layer on the first region includes: A first doped semiconductor material layer is formed on the second surface in an integral layer; A mask material layer is formed entirely on the first doped semiconductor material layer; The mask material layer is processed to form a mask layer on the portion of the first doped semiconductor material layer corresponding to the first region; Under the protection of the mask layer, the portion of the first doped semiconductor material layer located in the second region is removed, so as to form at least the first doped semiconductor layer in the first region; Remove the mask layer.

19. The method for manufacturing a back contact battery according to claim 18, wherein, After forming a mask layer on the portion of the first doped semiconductor material layer corresponding to the first region, and under the protection of the mask layer, removing the portion of the first doped semiconductor material layer located in the second region, before forming at least the first doped semiconductor layer on the first region, the manufacturing method of the back contact battery further includes: Remove the first doped semiconductor material layer and the mask material layer covering the first surface to expose the first surface of the semiconductor substrate; and remove at least a portion of the first doped semiconductor material layer and at least a portion of the mask material layer covering the side surface to expose at least a portion of the side surface of the semiconductor substrate.

20. The method for manufacturing a back contact battery according to claim 19, wherein, The removal method is wet removal; wherein, the concentration of HF is greater than or equal to 5% and less than or equal to 10%, the belt speed is greater than or equal to 1m / s and less than or equal to 2m / s, and the circulation rate is greater than or equal to 80% and less than or equal to 95%.

21. The method for manufacturing a back contact battery according to claim 20, wherein, After forming at least a first doped semiconductor layer on the first region, and before texturing the semiconductor substrate, the method for manufacturing the back contact battery further includes: selectively etching a portion of the semiconductor substrate corresponding to the second region, such that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, forming a groove structure; the surface of the first region is a plane; Along the thickness direction of the semiconductor substrate, the maximum distance between the plane and the bottom surface of the groove structure is greater than or equal to 2 μm and less than or equal to 15 μm.

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