Solar cell and method of manufacturing the same, stacked cell, and photovoltaic module

Abstract

The application relates to a solar cell and a manufacturing method thereof, a laminated cell and a photovoltaic module, and relates to the technical field of photovoltaics. The manufacturing method comprises the following steps: providing a substrate; forming a tunneling oxide layer on the surface of the substrate through atomic layer deposition; treating the tunneling oxide layer by using plasma to reduce the interface state density of the tunneling oxide layer to below a preset density; depositing an amorphous silicon layer on the side of the tunneling oxide layer away from the substrate, and simultaneously doping the amorphous silicon layer with a first element in situ; and performing annealing treatment on the amorphous silicon layer by using a laser, so that the amorphous silicon forms polycrystalline silicon and activates the doping atoms to form a semiconductor doping layer. The passivation effect of the tunneling oxide layer and the semiconductor doping layer is improved, the breakage rate of the solar cell is reduced, and the sheet resistance uniformity is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a solar cell and its manufacturing method, a tandem cell and a photovoltaic module. Background Technology

[0002] With the rapid development of the photovoltaic power generation field, how to improve the photoelectric conversion efficiency of solar cells and maintain the market competitiveness of solar cells is an urgent problem to be solved by those skilled in the art.

[0003] However, there are still many problems in the manufacturing of existing solar cells, which affect their development. Summary of the Invention

[0004] Therefore, it is necessary to provide a solar cell and its manufacturing method, a tandem cell, and a photovoltaic module to address the problems in the prior art.

[0005] To achieve the above objectives, firstly, this application provides a method for manufacturing a solar cell.

[0006] Provide a base;

[0007] A tunneling oxide layer is formed on the surface of the substrate by atomic layer deposition, and the tunneling oxide layer is treated with plasma to reduce the interface state density of the tunneling oxide layer to below a preset density.

[0008] An amorphous silicon layer is deposited on the side of the tunneling oxide layer away from the substrate, and a first element is in situ doped into the amorphous silicon layer.

[0009] The amorphous silicon layer is annealed using a laser, which transforms the amorphous silicon into polycrystalline silicon and activates doped atoms to form a semiconductor doped layer.

[0010] Optionally, the preset density is 1×10⁻⁶. 11 cm -2 ·eV -1 .

[0011] Optionally, the interface state density of the tunneling oxide layer is 5 × 10⁻⁶. 10 cm -2 ·eV -1 ~1×10 11 cm -2 ·eV -1 .

[0012] Optionally, the plasma treatment of the tunneling oxide layer includes:

[0013] Hydrogen gas is ionized at a power of 50W to 100W to obtain hydrogen plasma, which is then used to treat the tunneling oxide layer for a duration of 30s to 60s.

[0014] Optionally, the temperature at which the tunneling oxide layer is deposited in atomic layer deposition is below 300°C.

[0015] Optionally, the amorphous silicon layer is annealed by scanning it with an ultraviolet laser at a speed of 10 mm / s to 50 mm / s.

[0016] Optionally, the wavelength of the ultraviolet laser is 300nm~380nm, and the energy density of the ultraviolet laser is 0.5J / cm². 2 ~1.5J / cm 2 .

[0017] Optionally, the amorphous silicon layer is formed by low-pressure chemical vapor deposition, and the concentration of the first element doped into the amorphous silicon layer is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0018] Optionally, it also includes:

[0019] A mask layer is formed on the side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate;

[0020] A metal electrode is formed by electroplating in the first region, the material of the metal electrode including copper;

[0021] After the mask layer is removed, a diffusion barrier layer is formed to cover the surface of the metal electrode; the material of the diffusion barrier layer includes at least one of nickel or tin;

[0022] Wherein, the contact resistance between the semiconductor doped layer and the metal electrode is less than or equal to a first resistance; the first resistance is 1 mΩ·cm. 2 .

[0023] Optionally, forming a diffusion barrier layer includes forming a first sublayer and a second sublayer stacked sequentially.

[0024] Secondly, this application provides a solar cell manufactured using the solar cell manufacturing method described in the first aspect; the solar cell includes:

[0025] Base;

[0026] A tunneling oxide layer is disposed on the surface of the substrate, and the interface state density of the tunneling oxide layer is below a preset density; the preset density is 1×10⁻⁶. 11 cm -2 ·eV -1 ;

[0027] A semiconductor doped layer is disposed on the side of the tunneling oxide layer away from the substrate, and the semiconductor doped layer is doped with a first element.

[0028] Optionally, the interface state density of the tunneling oxide layer is 5 × 10⁻⁶. 10 cm -2 ·eV -1 ~1×10 11 cm -2 ·eV -1 .

[0029] Optionally, the solar cell further includes a metal electrode and a diffusion barrier layer, wherein the metal electrode is disposed on the side of the semiconductor doped layer away from the substrate, and the diffusion barrier layer covers the surface of the metal electrode; the material of the metal electrode includes copper; and the material of the diffusion barrier layer includes at least one of nickel or tin.

[0030] The contact resistance between the semiconductor doped layer and the metal electrode is less than or equal to a first resistance; the first resistance is 1 mΩ·cm. 2 .

[0031] Thirdly, this application provides a stacked battery, including a bottom battery and a top battery stacked on the bottom battery;

[0032] The bottom cell includes a solar cell manufactured by the solar cell manufacturing method described in the first aspect, or a solar cell as described in the second aspect; the top cell includes a perovskite cell.

[0033] Fourthly, this application provides a photovoltaic module, including a solar cell manufactured by the method for manufacturing a solar cell as described in the first aspect, or a solar cell as described in the second aspect, or a tandem cell as described in the third aspect.

[0034] The solar cells, their fabrication methods, tandem cells, and photovoltaic modules disclosed in this application have the following beneficial effects: the use of atomic layer deposition to form a tunneling oxide layer improves the uniformity of the tunneling oxide layer thickness, and plasma treatment of the tunneling oxide layer repairs lattice damage, thus improving the interface problems caused by uneven tunneling oxide layer thickness and high interface state density, which is beneficial to improving the passivation effect of the tunneling oxide layer and the semiconductor doped layer; the in-situ doping of the first element followed by annealing to activate the semiconductor doped layer during the deposition of the amorphous silicon layer simplifies the doping process of the semiconductor doped layer, and laser annealing replaces high-temperature diffusion, which is beneficial to reducing the breakage rate of solar cells and improving the sheet resistance uniformity. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a process flow diagram of a method for manufacturing a solar cell provided in one embodiment;

[0037] Figure 2 This is a schematic diagram of the structure after the formation of the tunneling oxide layer in one embodiment;

[0038] Figure 3 This is a schematic diagram of the structure after the formation of the semiconductor doped layer in one embodiment;

[0039] Figure 4 This is a schematic diagram of the structure after the mask layer is formed, as provided in one embodiment;

[0040] Figure 5 This is a schematic diagram of the structure after the metal electrode is formed, as provided in one embodiment;

[0041] Figure 6 This is a schematic diagram of the structure after the diffusion barrier layer is formed in one embodiment;

[0042] Figure 7 This is a schematic diagram of the structure after the metal electrode is formed, provided in another embodiment;

[0043] Figure 8 This is a schematic diagram of the structure of a solar cell provided in one embodiment;

[0044] Figure 9 This is a schematic diagram showing the connection between the top and bottom cells of a stacked battery provided in one embodiment;

[0045] Figure 10 This is a schematic diagram showing the connection between the top and bottom cells of a stacked battery provided in another embodiment;

[0046] Figure 11 This is a schematic diagram showing the connection between the top and bottom cells of a stacked battery provided in another embodiment. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] As described in the background section, the fabrication of existing solar cells still faces numerous challenges, impacting their applications. Taking the Tunnel Oxide Passivated Contact (TOPCON) cell as an example, the back of the TOPCON cell features an ultra-thin tunnel oxide layer and a semiconductor doped layer, providing a passivation effect by significantly reducing carrier recombination. TOPCON cells can also achieve a photoelectric conversion efficiency exceeding 24%. However, the fabrication of TOPCON cells typically employs thermal oxidation and chemical oxidation methods to create the tunnel oxide layer. Thermal oxidation is affected by the surface condition of the silicon wafer, resulting in significant thickness variations and unevenness in the tunnel oxide layer. Chemical oxidation, due to inhomogeneous reaction kinetics, leads to an interface state density as high as 1×10⁻⁶. 12 cm -2 This significantly affects the passivation effect.

[0050] In the fabrication of TOPCon cells, after depositing intrinsic polycrystalline silicon, high-temperature phosphorus diffusion is carried out. The high-temperature process may cause silicon wafer warping, leading to an increase in the breakage rate. Moreover, the lateral doping effect of the diffusion process leads to an increase in sheet resistance deviation, resulting in an increase in contact resistivity.

[0051] Furthermore, existing TOPCon cells are manufactured using a traditional high-temperature silver paste system to create metal electrodes. The electrode manufacturing process requires high-temperature sintering at 550°C to 600°C. This high-temperature process may cause the polycrystalline silicon layer to recrystallize, increasing the contact resistivity. At the same time, the high temperature causes the silver element to diffuse to a greater depth into the silicon substrate, forming a Schottky contact with the silicon wafer and reducing the fill factor.

[0052] Therefore, the photovoltaic field urgently needs to provide a solar cell and its fabrication method that combine process compatibility, cost-effectiveness, and optimized electrical performance.

[0053] According to an exemplary embodiment, such as Figure 1 As shown, in conjunction with reference Figures 2-7 This embodiment provides a method for manufacturing a solar cell, including the following steps:

[0054] Step S101: Provide substrate 10. In this embodiment, substrate 10 can be a silicon substrate 10, and substrate 10 includes a front side 10a and a back side 10b disposed opposite to each other. In this embodiment, substrate 10 is an n-type substrate with a resistivity of 1 Ω·cm.-3 Ω·cm. Substrate 10 can be doped with Group 5 elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc.

[0055] Step S102: A tunneling oxide layer 11 is formed on the surface of the substrate 10 by atomic layer deposition. The tunneling oxide layer 11 is then treated with plasma to reduce the interface state density of the tunneling oxide layer 11 to below a preset density.

[0056] Step S103: Deposit an amorphous silicon layer on the side of the tunneling oxide layer 11 away from the substrate 10, and simultaneously dope the amorphous silicon layer with a first element in situ.

[0057] Step S104: The amorphous silicon layer is annealed using a laser to form polycrystalline silicon and activate doped atoms to form a semiconductor doped layer 12. The contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is less than or equal to the first resistance.

[0058] The solar cell fabrication method of this embodiment uses atomic layer deposition to form a tunneling oxide layer 11, which improves the thickness uniformity of the tunneling oxide layer 11. Plasma treatment is used to repair lattice damage in the tunneling oxide layer 11, which improves the interface problems caused by uneven thickness of the tunneling oxide layer 11 and high interface state density, and is conducive to improving the passivation effect of the passivation contact structure of the solar cell. During the deposition of the amorphous silicon layer, the first element is doped in situ and then annealed to activate the semiconductor doped layer 12, which simplifies the doping process of the semiconductor doped layer 12. Laser annealing replaces high-temperature diffusion, which is conducive to reducing the breakage rate of the solar cell and improving the sheet resistance uniformity.

[0059] In step S102, as Figure 2 As shown, the surface of substrate 10 is cleaned and the native oxide layer on the surface of substrate 10 is removed to expose a uniform silicon crystal surface of substrate 10. For example, dilute hydrofluoric acid (DHF) can be used to clean substrate 10. Then, atomic layer deposition (ALD) is used to form a tunneling oxide layer 11 on the surface of substrate 10. Atomic layer deposition can precisely control the thickness of the formed tunneling oxide layer 11, and the thickness of the tunneling oxide layer 11 formed by atomic layer deposition has high uniformity. The surface roughness of the tunneling oxide layer 11 is low, which is beneficial to improving cell efficiency.

[0060] After depositing and forming the tunneling oxide layer 11, plasma treatment is used to repair the lattice damage on the surface of the tunneling oxide layer 11. This can reduce the interface state density of the tunneling oxide layer 11 to below the preset density, which is beneficial to the transmission of tunneling current and increases the tunneling current.

[0061] In this embodiment, the tunneling oxide layer 11 can be deposited only on the back side 10b of the substrate 10, or the tunneling oxide layer 11 can be formed on both the front side 10a and the back side 10b of the substrate 10.

[0062] The thickness of the tunneling oxide layer 11 is 1 nm to 2 nm; the material of the tunneling oxide layer 11 can be silicon oxide.

[0063] In some embodiments, the atomic layer deposition temperature of the tunneling oxide layer 11 is below 300°C. For example, the deposition temperature can be controlled between 200°C and 250°C. This allows for more precise control over the thickness of the tunneling oxide layer 11, enabling atomic-level thickness uniformity control with a thickness deviation of <±0.1 nm. Simultaneously, limiting the deposition temperature to below 300°C helps suppress thermal damage to the substrate 10.

[0064] For example, SiH4 can be used as the silicon source gas and O2 as the oxygen source gas, and the deposition temperature can be controlled at 200~250℃ to form a tunneling oxide layer 11 by atomic layer deposition.

[0065] In some embodiments, plasma treatment of the tunneling oxide layer 11 includes: ionizing hydrogen gas at a power of 50W to 100W to obtain hydrogen plasma, and treating the tunneling oxide layer 11 with hydrogen plasma for a treatment time of 30s to 60s. In this embodiment, hydrogen plasma can be obtained by inductively coupling ionization of hydrogen gas.

[0066] The ionization pressure is 50W~100W, for example, it can be 50W, 52W, 54W, 56W, 58W, 60W, 60W, 62W, 64W, 66W, 68W, 70W, 72W, 74W, 76W, 78W, 80W, 80W, 82W, 84W, 86W, 88W, 90W, 92W, 94W, 96W, 98W or 100W.

[0067] The processing time is 30s to 60s, for example, it can be 30s, 32s, 34s, 36s, 37s, 38s, 39s, 40s, 42s, 44s, 45s, 46s, 47s, 48s, 49s, 50s, 52s, 54s, 56s, 57s, 58s, 59s or 60s.

[0068] The cavity pressure for ionizing hydrogen gas to obtain hydrogen plasma is 0.3 Torr to 1.5 Torr, for example, it can be 0.3 Torr, 0.4 Torr, 0.5 Torr, 0.6 Torr, 0.7 Torr, 0.8 Torr, 0.9 Torr, 1.0 Torr, 1.1 Torr, 1.2 Torr, 1.3 Torr, 1.4 Torr or 1.5 Torr.

[0069] In this embodiment, the preset density is 1×10 11 cm -2 ·eV -1 In this embodiment, before treating the tunneling oxide layer 11 with hydrogen plasma, the defect energy levels of the tunneling oxide layer 11 were quantitatively analyzed using deep level transient spectroscopy (DLTS). The initial interface state density of the tunneling oxide layer 11 was 1 × 10⁻⁶. 13 cm -2 ·eV -1 After treating the tunneling oxide layer 11 with hydrogen plasma, the substrate 10 containing the tunneling oxide layer 11 was transferred again to a deep-level transient spectroscopy instrument. The defect energy levels of the tunneling oxide layer 11 were quantitatively analyzed using deep-level transient spectroscopy. The interface state density of the tunneling oxide layer 11 increased from an initial 1 × 10⁻⁶. 13 cm -2 ·eV -1 Reduce to a preset density of 1×10 11 cm -2 ·eV -1 the following.

[0070] The conditions for testing the tunneling oxide layer 11 using deep-level transient spectroscopy are as follows: the tunneling oxide layer 11 is tested in a nitrogen or vacuum environment, the tunneling oxide layer 11 is scanned at a scan rate of 0.1K / s to 1K / s, the forward voltage is 0.1V to 1V, the duration is 10μs to 1ms; and the reverse bias voltage is 1V to 10V.

[0071] In some embodiments, the interface state density of the tunneling oxide layer 11 is 5 × 10⁻⁶. 10 cm -2 ·eV -1 -1×10 11 cm -2 ·eV -1 For example, the interface state density of the tunneling oxide layer 11 can be 5 × 10⁻⁶. 10 cm -2 ·eV -1 5.3×10 10 cm -2 ·eV -1 7.2×10 10 cm -2 ·eV -1 9.8×10 10 cm -2 ·eV -1 1×10 11 cm -2 ·eV -1 .

[0072] In this embodiment, atomic layer deposition is used to form the tunneling oxide layer 11 to ensure high thickness uniformity. Hydrogen plasma treatment removes dangling bonds on the surface of the tunneling oxide layer 11. In the hydrogen plasma, highly reactive particles generated by the ionization of hydrogen diffuse to the surface of the tunneling oxide layer 11 and combine with the unsaturated silicon dangling bonds to form stable Si-H bonds, eliminating unpaired electrons and reducing charge traps on the surface of the tunneling oxide layer 11. The hydrogen plasma can also fill oxygen vacancies on the surface of the tunneling oxide layer 11. The combination of hydrogen plasma and oxygen vacancies further improves the integrity and uniformity of the surface of the tunneling oxide layer 11, thereby significantly reducing interface defects and facilitating the achievement of an open-circuit voltage (Voc) of over 740mV for the solar cell.

[0073] In step S103, as Figure 3 As shown, chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD) can be used to deposit the tunnel oxide layer 11 on the side away from the substrate 10, and the first element can be in situ doped into the amorphous silicon layer during the deposition process.

[0074] In some embodiments, an amorphous silicon layer is formed by low-pressure chemical vapor deposition, and the concentration of the first element doped into the amorphous silicon layer is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0075] In this embodiment, the first element can be phosphorus or boron. A low-pressure chemical vapor deposition (LPCVD) is used to deposit an amorphous silicon layer with a thickness of 80 nm to 50 nm. During the deposition process, phosphine (PH3) or borane (B2H6) is introduced into the deposition chamber to achieve in-situ doping, and the first element is doped into the amorphous silicon layer at a concentration controlled at 1 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0076] In step S104, an ultraviolet laser is used to scan the amorphous silicon layer at a speed of 10 mm / s to 50 mm / s to perform annealing treatment on the amorphous silicon layer. For example, the scanning speed of the ultraviolet laser can be 10 mm / s, 12 mm / s, 14 mm / s, 15 mm / s, 16 mm / s, 18 mm / s, 20 mm / s, 22 mm / s, 24 mm / s, 25 mm / s, 26 mm / s, 28 mm / s, 30 mm / s, 32 mm / s, 34 mm / s, 35 mm / s, 36 mm / s, 38 mm / s, 40 mm / s, 42 mm / s, 44 mm / s, 45 mm / s, 46 mm / s, 48 ​​mm / s, or 50 mm / s.

[0077] In one embodiment, the wavelength of the ultraviolet laser is 300 nm to 380 nm, and the energy density of the ultraviolet laser is 0.5 J / cm². 2 ~1.5J / cm 2 .

[0078] For example, the wavelength of the ultraviolet laser can be 300nm, 305nm, 310nm, 312nm, 315nm, 318nm, 320nm, 322nm, 323nm, 325nm, 327nm, 329nm, 330nm, 331nm, 332nm, 335nm, 336nm, 338nm, 340nm, 341nm, 342nm, 345nm, 348nm, 350nm, 352nm, 353nm, 354nm, 355nm, 358nm, 360nm, 362nm, 364nm, 366nm, 368nm, 370nm, 372nm, 374nm, 376nm, 378nm, or 380nm.

[0079] In this embodiment, the deposition and doping of the amorphous silicon layer are completed simultaneously. In-situ doping avoids the high damage associated with traditional ion implantation. Ultraviolet laser is used to rapidly anneal the amorphous silicon layer instead of traditional high-temperature annealing, transforming the amorphous silicon into a polycrystalline silicon structure. Simultaneously, the first element is activated to form a semiconductor doped layer 12. This overcomes the thermal budget limitations of traditional high-temperature annealing on the substrate 10, reduces the number of high-temperature annealing steps, lowers energy consumption, and mitigates the problem of silicon wafer warping that may occur during high-temperature processes, thereby reducing the breakage rate. Laser annealing excites and activates the first element to crystallize the amorphous silicon layer into a semiconductor doped layer 12, preserving the integrity of the tunneling oxide layer 11. It also limits the problem of increased sheet resistance deviation caused by the lateral doping effect of the first element, which helps to reduce the contact resistance between the semiconductor doped layer 12 and the subsequently formed metal electrode 13, improves resistance uniformity, and can increase the fill factor of the battery, thereby improving battery efficiency.

[0080] In some embodiments, during the process of forming a semiconductor doped layer 12 by scanning an amorphous silicon layer with an ultraviolet laser, the entire amorphous silicon layer is scanned to form the semiconductor doped layer 12.

[0081] In some other embodiments, during the process of forming the semiconductor doped layer 12 by scanning the amorphous silicon layer with an ultraviolet laser, only the metallized region in contact with the metal electrode 13 can be scanned, without scanning other areas, thus saving processing time.

[0082] In some embodiments, after step S104, the following steps are also performed:

[0083] Step S105: As Figure 4 As shown, a mask layer 20 is formed on the side of the semiconductor doped layer 12 away from the substrate 10, exposing a first region of the substrate 10. In this embodiment, the mask layer 20 can be formed by deposition or printing on the side of the semiconductor doped layer 12 away from the substrate 10. The material of the mask layer 20 includes an inorganic insulating material, such as silicon oxide. Then, through photolithography, etching, and other steps, a mask pattern is etched on the mask layer 20 to expose the first region of the substrate 10.

[0084] Step S106: As Figure 5 As shown, a metal electrode 13 is formed by electroplating in the first region. The material of the metal electrode 13 includes copper. In this embodiment, a cyanide-free copper electroplating solution is used to electroplat copper grid lines in the first region to form the metal electrode 13. The height of the metal electrode 13 is 15μm to 25μm, and the width is 20μm to 40μm. For example, the height of the metal electrode 13 can be 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, or 25μm; the width of the metal electrode 13 can be 20μm, 22μm, 24μm, 25μm, 26μm, 28μm, 30μm, 31μm, 33μm, 35μm, 36μm, 37μm, 38μm, 39μm, or 40μm.

[0085] Step S107: As Figure 6 or Figure 7 As shown, after removing the mask layer 20, a diffusion barrier layer 14 is formed to cover the surface of the metal electrode 13; the material of the diffusion barrier layer 14 includes at least one of nickel or tin.

[0086] In this embodiment, after the metal electrode 13 is formed, the mask layer 20 can be removed by wet etching. Then, a diffusion barrier layer 14 can be formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition, covering the surface of the metal electrode 13. The diffusion barrier layer 14 can be a single layer or multiple layers, for example, such as... Figure 6As shown, the diffusion barrier layer 14 may include a single nickel layer, or the diffusion barrier layer 14 may include a single tin layer.

[0087] Alternatively, in some embodiments, such as Figure 7 As shown, forming the diffusion barrier layer 14 includes forming a first sublayer 141 and a second sublayer 142 stacked sequentially. In one example, the first sublayer 141 is a nickel layer and the second sublayer 142 is a tin layer; in another example, the first sublayer 141 is a tin layer and the second sublayer 142 is a nickel layer.

[0088] The thickness of the diffusion barrier layer 14 is 50nm to 100nm. For example, the thickness of the diffusion barrier layer 14 can be 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, or 100nm. The diffusion barrier layer 14 is used to prevent copper diffusion in the metal electrode 13 and improve the welding performance of the metal electrode 13.

[0089] In this embodiment, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is less than or equal to the first resistance, which is 1 mΩ·cm. 2 In this embodiment, by improving the fabrication process of the semiconductor doped layer 12 and the tunneling oxide layer 11, the interface state density of the tunneling oxide layer 11 is reduced to 10 by hydrogen plasma repair. 11 Below the order quantity, copper electroplating is used instead of silver paste to fabricate the metal electrode 13, which improves the conductivity of the metal electrode 13 by more than 20%, allowing the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 to be reduced to 1 mΩ·cm. 2 The following shows the contact resistance value between the semiconductor doped layer 12 and the metal electrode 13, which has broken through the bottleneck of traditional processes.

[0090] The contact resistance between the semiconductor doped layer 12 and the metal electrode 13 can be detected using a four-point probe method. Four probes are arranged at equal intervals on the surface of the metal electrode 13. A measurement current and a measurement voltage are applied to each of the four probes, and the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is calculated.

[0091] Alternatively, an improved transmission line model can be used to detect the contact resistance between the semiconductor doped layer 12 and the metal electrode 13. The total resistance between the metal electrodes 13 with different spacings can be measured, and a curve of total resistance versus length can be plotted. After fitting a straight line, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 can be calculated using an algorithm model.

[0092] In some embodiments, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is in the range of 0.5 mΩ·cm. 2 ~1mΩ·cm 2For example, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 can be 0.5 mΩ·cm. 2 0.52mΩ·cm 2 0.55mΩ·cm 2 0.58mΩ·cm 2 0.63mΩ·cm 2 0.7mΩ·cm 2 0.8mΩ·cm 2 0.9mΩ·cm 2 or 1mΩ·cm 2 .

[0093] In this embodiment, the solar cell fabrication method uses copper electroplating instead of silver paste to fabricate the metal electrode 13. This reduces the cost of the metal electrode 13 by more than 50%, improves its conductivity by more than 20%, and the copper electroplating process for forming the metal electrode 13 is performed at a lower temperature, eliminating the need for high-temperature sintering. This addresses the problem of increased contact resistivity caused by polycrystalline silicon recrystallization of the semiconductor doped layer 12 due to high temperatures. Furthermore, this embodiment uses a mask layer to create a mold, forming the metal electrode 13 in the molded area to achieve selective contact with the semiconductor doped layer 12. This reduces metal-semiconductor interface recombination and increases the fill factor of the solar cell to over 83%.

[0094] In some embodiments, prior to step S102, the surface (front 10a and / or back 10b) of the substrate 10 can be texturized to form a pyramid structure on the surface (front 10a and / or back 10b) of the substrate 10, thereby increasing the light-receiving area and photoelectric conversion efficiency of the solar cell.

[0095] In some embodiments, the battery manufactured in this example is a TOPCon battery, and the battery manufactured in this example is as follows: Figure 8 As shown, in this embodiment, the front side 10a of the substrate 10 includes multiple metallized regions 101. In this embodiment, a front electrode 15 and a front passivation antireflection layer 16 are also formed on the front side 10a of the substrate 10. The front passivation antireflection layer 16 covers the front side 10a of the substrate 10, and the front electrode 15 penetrates the front passivation antireflection layer 16 to directly contact and connect with the metallized regions 101. The front passivation antireflection layer 16 can be a single-layer or multi-layer structure, and can include a single layer or multiple layers of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0096] like Figure 8 As shown, the front passivation antireflection layer 16 includes a first passivation layer 161 and a second passivation layer 162 sequentially stacked on the front side 10a. The first passivation layer 161 is a silicon nitride layer, and the second passivation layer 162 is an aluminum oxide layer.

[0097] The solar cell fabrication method of this embodiment optimizes the fabrication process by employing atomic layer deposition combined with hydrogen plasma treatment to create a tunneling oxide layer 11. This achieves atomic-level thickness uniformity and low interface state density in the tunneling oxide layer 11, significantly improving the open-circuit voltage of the solar cell, which can be increased to over 740mV. Furthermore, in-situ doping low-pressure chemical vapor deposition and laser annealing techniques are used to complete amorphous silicon crystallization and doping activation below 600℃ to form a semiconductor doped layer 12. This reduces the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 to 1mΩ·cm. 2 The sheet resistance deviation is less than 5%; combined with the cyanide-free copper electroplating metallization process, the traditional silver paste is used to make metal electrodes 13, reducing the cost by more than 50%. At the same time, by reducing interfacial recombination through selective contact structure, the fill factor (FF) of the solar cell is increased to more than 83%, and the cell efficiency of the solar cell is increased by 0.3%~0.5%.

[0098] The solar cell manufacturing method of this embodiment reduces the overall process temperature by 30% and the production cost by 40%. The manufacturing method is suitable for mass production line upgrades and has good process compatibility with existing battery production lines, low cost and high production efficiency.

[0099] Based on the descriptions of the above embodiments, more specific embodiments are described below in detail.

[0100] In one exemplary embodiment, this embodiment provides a method for manufacturing a solar cell, including the following steps:

[0101] Step S201: Provide a substrate 10, which is a silicon substrate 10. The substrate 10 includes a front side 10a and a back side 10b disposed opposite to each other. The substrate 10 is an n-type substrate 10 with a resistivity of 1.5 Ω·cm.

[0102] Step S202: A tunneling oxide layer 11 is formed on the surface of the substrate 10 by atomic layer deposition at a temperature of 200℃~250℃. The thickness of the tunneling oxide layer 11 is 1.5nm. The tunneling oxide layer 11 is treated with hydrogen plasma to reduce the interface state density of the tunneling oxide layer 11 to a preset density of 1×10⁻⁶. 11 cm -2 ·eV -1 In this embodiment, the interface state density of the tunneling oxide layer 11 is 5 × 10⁻⁶. 10 cm -2 ·eV -1 ~1×10 11 cm -2 ·eV -1 .

[0103] Step S203: Amorphous silicon layer is deposited on the side of the tunnel oxide layer 11 away from the substrate 10 using low-pressure chemical vapor deposition. The thickness of the amorphous silicon layer is 120 nm. At the same time as depositing the amorphous silicon layer, PH3 gas is introduced into the deposition chamber at a flow rate of 50 sccm to dope phosphorus in situ into the amorphous silicon layer.

[0104] Step S204: Anneal the amorphous silicon layer using ultraviolet laser. The scanning speed of the ultraviolet laser is 10 mm / s, the wavelength is 350 nm, and the energy density is 1 J / cm². 2 The ultraviolet laser causes amorphous silicon to recrystallize into polycrystalline silicon and activates doped atoms to form a semiconductor doped layer 12.

[0105] Step S205: A mask layer 20 is formed on the side of the semiconductor doped layer 12 away from the substrate 10, and the mask layer 20 exposes a first region of the substrate 10.

[0106] Step S206: Electroplating is performed in the first region to form a metal electrode 13. The material of the metal electrode 13 includes copper, and the metal electrode 13 has a height of 20 μm and a width of 30 μm.

[0107] Step S207: After removing the mask layer 20, a diffusion barrier layer 14 is formed to cover the surface of the metal electrode 13; the diffusion barrier layer 14 includes a single nickel layer, and the thickness of the diffusion barrier layer 14 is 70 nm. In this embodiment, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is less than or equal to a first resistance of 1 mΩ·cm. 2 In this embodiment, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is in the range of 0.5 mΩ·cm. 2 ~1mΩ·cm 2 .

[0108] The solar cell produced in this embodiment has an efficiency of 24.5%~25.2%, an open-circuit voltage of 740mV, a fill factor of more than 83%, a manufacturing cost of metal electrode 13 reduced by 50% or more, and a conductivity of metal electrode 13 increased by 20%.

[0109] In another exemplary embodiment, this embodiment provides a method for manufacturing a solar cell, including the following steps:

[0110] Step S301: Provide a substrate 10, which is a silicon substrate 10. The substrate 10 includes a front side 10a and a back side 10b disposed opposite to each other. The substrate 10 is an n-type substrate 10 with a resistivity of 2 Ω·cm.

[0111] Step S302: A tunneling oxide layer 11 is formed on the surface of the substrate 10 by atomic layer deposition at a temperature of 200℃~250℃. The thickness of the tunneling oxide layer 11 is 2nm. The tunneling oxide layer 11 is treated with hydrogen plasma to reduce the interface state density of the tunneling oxide layer 11 to a preset density of 1×10⁻⁶. 11 cm -2 ·eV -1 In this embodiment, the interface state density of the tunneling oxide layer 11 is 5 × 10⁻⁶. 10 cm -2 ·eV -1 ~1×10 11 cm -2 ·eV -1 .

[0112] Step S303: Amorphous silicon layer is deposited on the side of the tunneling oxide layer 11 away from the substrate 10 using low-pressure chemical vapor deposition. The thickness of the amorphous silicon layer is 150 nm. While depositing the amorphous silicon layer, B2H6 gas is introduced into the deposition chamber at a flow rate of 560 sccm to dope boron in situ into the amorphous silicon layer.

[0113] Step S304: Anneal the amorphous silicon layer using ultraviolet laser. The scanning speed of the ultraviolet laser is 20 mm / s, the wavelength is 330 nm, and the energy density is 1.2 J / cm². 2 The ultraviolet laser causes amorphous silicon to recrystallize into polycrystalline silicon and activates doped atoms to form a semiconductor doped layer 12.

[0114] Step S305: A mask layer 20 is formed on the side of the semiconductor doped layer 12 away from the substrate 10, and the mask layer 20 exposes a first region of the substrate 10.

[0115] Step S306: Electroplating is performed in the first region to form a metal electrode 13. The material of the metal electrode 13 includes copper, and the metal electrode 13 has a height of 15 μm and a width of 40 μm.

[0116] Step S307: After removing the mask layer 20, a diffusion barrier layer 14 is formed to cover the surface of the metal electrode 13; the diffusion barrier layer 14 includes a single nickel layer, and the thickness of the diffusion barrier layer 14 is 80 nm. In this embodiment, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is less than or equal to the first resistance 1 mΩ·cm. 2 In this embodiment, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is in the range of 0.5 mΩ·cm. 2 ~1mΩ·cm 2 .

[0117] The solar cell fabricated in this embodiment has an efficiency of 24.5%~25.2%, an open-circuit voltage of 740mV, a fill factor of more than 83%, a manufacturing cost of 50% or more for the metal electrode, and a 20% increase in conductivity of the metal electrode.

[0118] To further illustrate the method for fabricating the solar cells according to the embodiments of this application, the embodiments of this application and comparative examples are listed below. Table 1 shows the fabrication conditions and test performance of the solar cells of the embodiments of this application and comparative examples.

[0119] Comparative Example 1: A tunneling oxide layer was formed by thermal oxidation, an amorphous silicon layer was deposited, and then a semiconductor doped layer was formed by thermal diffusion doping. A silver metal electrode was formed by printing with silver paste.

[0120] Comparative Example 2: A tunneling oxide layer was formed using atomic layer deposition. After formation, the tunneling oxide layer was treated with hydrogen plasma to reduce the interface state density of the tunneling oxide layer to a preset density of 1×10⁻⁶. 11 cm -2 ·eV -1 The following steps involve depositing an amorphous silicon layer followed by thermal diffusion doping to form a semiconductor doped layer, and then printing a silver metal electrode using silver paste.

[0121] Comparative Example 3: A tunneling oxide layer was formed by thermal oxidation, an amorphous silicon layer was formed by low-pressure chemical vapor deposition, boron was in situ doped into the amorphous silicon layer during deposition, the amorphous silicon layer was annealed by ultraviolet laser to form a semiconductor doped layer, and silver metal electrodes were formed by silver paste printing.

[0122] Comparative Example 4: A tunneling oxide layer was formed by thermal oxidation, followed by deposition of an amorphous silicon layer and thermal diffusion doping to form a semiconductor doped layer. A copper metal electrode in contact with the semiconductor doped layer was formed by electroplating, and a diffusion barrier layer was formed to cover the surface of the copper metal electrode.

[0123] Comparative Example 5: A tunneling oxide layer was formed using atomic layer deposition. After formation, the tunneling oxide layer was treated with hydrogen plasma to reduce the interface state density of the tunneling oxide layer to a preset density of 1×10⁻⁶. 11 cm -2 ·eV -1 The following steps involve using low-pressure chemical vapor deposition to deposit an amorphous silicon layer, simultaneously doping the amorphous silicon layer with boron in situ, annealing the amorphous silicon layer with ultraviolet laser to form a semiconductor doped layer, and printing silver metal electrodes using silver paste.

[0124] Comparative Example 6: A tunneling oxide layer was formed using atomic layer deposition. After formation, the tunneling oxide layer was treated with hydrogen plasma to reduce the interface state density of the tunneling oxide layer to a preset density of 1×10⁻⁶.11 cm -2 ·eV -1 The following steps involve depositing an amorphous silicon layer, followed by thermal diffusion doping to form a semiconductor doped layer, electroplating to form a copper metal electrode in contact with the semiconductor doped layer, and finally forming a diffusion barrier layer to cover the surface of the copper metal electrode.

[0125] Comparative Example 7: A tunneling oxide layer was formed by thermal oxidation, an amorphous silicon layer was deposited by low-pressure chemical vapor deposition, boron was in situ doped into the amorphous silicon layer during deposition, the amorphous silicon layer was annealed by ultraviolet laser to form a semiconductor doped layer, a copper metal electrode in contact with the semiconductor doped layer was formed by electroplating, and a diffusion barrier layer was formed to cover the surface of the copper metal electrode.

[0126] Example 1: A tunneling oxide layer was formed by atomic layer deposition. Hydrogen was ionized with 50W to obtain hydrogen plasma to treat the tunneling oxide layer 11 for 60s, reducing the interface state density of the tunneling oxide layer to 1×10⁻⁶. 11 cm -2 ·eV -1 Amorphous silicon layers were deposited using low-pressure chemical vapor deposition (LPCVD). During deposition, boron was in-situ doped into the amorphous silicon layer. The layer was then annealed using a 300 nm wavelength ultraviolet laser at a speed of 10 mm / s to form a semiconductor-doped layer. The energy density of the ultraviolet laser was 0.5 J / cm². 2 / cm 2 A metal electrode 13 in contact with the semiconductor doped layer is formed by electroplating in a first region of the substrate 10. The material of the metal electrode 13 includes copper, and the metal electrode 13 has a height of 15 μm and a width of 40 μm. A diffusion barrier layer 14 is formed to cover the surface of the metal electrode 13.

[0127] Example 2: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 100W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 30s, reducing the interface state density of the tunneling oxide layer to 9.8 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 50 mm / s. The wavelength of the ultraviolet laser was 380 nm, and the energy density of the ultraviolet laser was 1.5 J / cm². 2 / cm 2 The metal electrode 13 has a height of 25 μm and a width of 20 μm.

[0128] Example 3: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 60W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 35s, reducing the interface state density of the tunneling oxide layer to 9.5 × 10⁻⁶.10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 55 mm / s. The wavelength of the ultraviolet laser was 310 nm, and the energy density of the ultraviolet laser was 0.6 J / cm². 2 / cm 2 The metal electrode 13 has a height of 15 μm and a width of 25 μm.

[0129] Example 4: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 60W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 35s, reducing the interface state density of the tunneling oxide layer 11 to 9.5 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 55 mm / s. The wavelength of the ultraviolet laser was 310 nm, and the energy density of the ultraviolet laser was 0.6 J / cm². 2 / cm 2 The metal electrode 13 has a height of 15 μm and a width of 30 μm.

[0130] Example 5: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 70W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 40s, reducing the interface state density of the tunneling oxide layer 11 to 7.2 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 55 mm / s. The wavelength of the ultraviolet laser was 320 nm, and the energy density of the ultraviolet laser was 0.7 J / cm². 2 / cm 2 The metal electrode 13 has a height of 18 μm and a width of 35 μm.

[0131] Example 6: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 80W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 45s, reducing the interface state density of the tunneling oxide layer 11 to 6.8 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer with an ultraviolet laser at a speed of 60 mm / s. The wavelength of the ultraviolet laser was 330 nm, and the energy density of the ultraviolet laser was 0.8 J / cm². 2 / cm 2 The metal electrode 13 has a height of 19 μm and a width of 30 μm.

[0132] Example 7: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 85W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 48s, reducing the interface state density of the tunneling oxide layer 11 to 6.5 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 65 mm / s. The wavelength of the ultraviolet laser was 340 nm, and the energy density of the ultraviolet laser was 0.9 J / cm². 2 / cm 2 The metal electrode 13 has a height of 20 μm and a width of 38 μm.

[0133] Example 8: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 90W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 50s, reducing the interface state density of the tunneling oxide layer 11 to 6.0 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 70 mm / s. The wavelength of the ultraviolet laser was 350 nm, and the energy density of the ultraviolet laser was 1.0 J / cm². 2 / cm 2 The metal electrode 13 has a height of 22 μm and a width of 42 μm.

[0134] Example 9: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 95W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 55s, reducing the interface state density of the tunneling oxide layer 11 to 5.5 × 10⁻⁶. 10 cm -2 ·eV -1 A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 80 mm / s. The wavelength of the ultraviolet laser was 360 nm, and the energy density of the ultraviolet laser was 1.2 J / cm². 2 / cm 2 The metal electrode 13 has a height of 23 μm and a width of 45 μm.

[0135] Example 10: The only difference between this example and Example 1 is that hydrogen gas was ionized at a power of 95W to obtain hydrogen plasma for treating the tunneling oxide layer 11, with a treatment time of 60s, reducing the interface state density of the tunneling oxide layer 11 to 5.0 × 10⁻⁶. 10 cm -2 ·eV -1A semiconductor doped layer was formed by annealing an amorphous silicon layer using an ultraviolet laser at a speed of 90 mm / s. The wavelength of the ultraviolet laser was 370 nm, and the energy density of the ultraviolet laser was 1.4 J / cm². 2 / cm 2 The metal electrode 13 has a height of 24 μm and a width of 48 μm.

[0136] Table 1. Fabrication conditions and test performance of solar cells in the examples and comparative examples.

[0137]

[0138] The solar cell fabrication method of this application achieves an open-circuit voltage of 740mV by optimizing the tunneling oxide layer; the amorphous silicon crystallization and doping activation technology reduces the contact resistance to below 1mΩ·cm², and the sheet resistance deviation is controlled within 5%; the cyanide-free copper electroplating metallization process reduces the manufacturing cost of the metal electrode by up to 50%, while increasing the fill factor to over 83% and improving the efficiency by 0.3%~0.5%; furthermore, through process compatibility optimization, the overall temperature is reduced by 30% and the production cost is reduced by 40%, achieving a comprehensive improvement in open-circuit voltage, fill factor, and efficiency.

[0139] It should be noted that the type of solar cell is not specifically limited in this embodiment. For example, the types of solar cells in the above embodiments include, but are not limited to, tunnel oxide passivated contact (TOPCON) cells or back contact (BC) cells.

[0140] In some examples, the solar cell is a TOPCon cell. Along its thickness direction, a TOPCon cell sequentially includes a front metal electrode, a front surface silicon nitride passivation layer, a boron-doped emitter, an N-type substrate silicon layer, a diffused doped layer, a tunneling oxide layer, a semiconductor doped layer, silicon nitride, and a back metal electrode. The back of the cell consists of a tunneling oxide layer (1nm~2nm) and a phosphorus-doped polycrystalline silicon thin film, which together form a passivation contact structure. The tunneling oxide layer can be an ultrathin silicon oxide layer. This structure can block minority carrier recombination, increasing the cell's open-circuit voltage and short-circuit current. The ultrathin oxide layer allows majority carrier electrons to tunnel into the polycrystalline silicon layer while blocking minority carrier hole recombination. The excellent passivation effect of the ultrathin silicon oxide layer and the heavily doped silicon thin film causes band bending on the silicon wafer surface, creating a field passivation effect. This significantly increases the probability of electron tunneling, reduces contact resistance, and improves the cell's open-circuit voltage and short-circuit current, thereby increasing the cell's conversion efficiency. In this example, the tunneling oxide layer, semiconductor doped layer, and back metal electrode of the TOPCon cell are fabricated using the fabrication method described in this embodiment.

[0141] In other examples, for BC cells, the emitter, surface field, and metal electrodes are all located on the back of the cell and are distributed in a cross-directional manner, while the front of the cell uses SiN. x / SiO x A double-layer anti-reflection passivation film ensures that the front of the battery is unobstructed by metal electrodes, allowing the battery to receive more incident light, reducing optical losses, and improving photoelectric conversion efficiency. The back of the BC battery has alternating n-regions and p-regions. The n-regions are sequentially stacked with a first tunneling oxide layer and a first semiconductor doped layer. The first semiconductor doped layer is n-type, and a first metal electrode is disposed on the side of the first semiconductor doped layer facing away from the n-region. The p-regions are sequentially stacked with a second tunneling oxide layer and a second semiconductor doped layer. The second semiconductor doped layer is p-type, and a second metal electrode is disposed on the side of the second semiconductor doped layer facing away from the p-region. In this example, the first tunneling oxide layer, the first semiconductor doped layer, and the first metal electrode are all fabricated using the method described in this embodiment; the second tunneling oxide layer, the second semiconductor doped layer, and the second metal electrode are also fabricated using the method described in this embodiment.

[0142] Secondly, this application provides a solar cell manufactured using the solar cell manufacturing method described in the above embodiments; Figure 6 or Figure 7 As shown, the solar cell includes a substrate 10, a tunneling oxide layer 11, and a semiconductor doped layer 12.

[0143] The substrate 10 may be a silicon substrate 10, which includes a front side 10a and a back side 10b disposed opposite to each other.

[0144] A tunneling oxide layer 11 is disposed on the surface of the substrate 10. The tunneling oxide layer 11 is disposed at least on the back side 10b of the substrate 10, or it may be disposed on the front side 10a of the substrate 10. The thickness of the tunneling oxide layer 11 is 1 nm to 2 nm. The material of the tunneling oxide layer 11 may include silicon oxide. The interface state density of the tunneling oxide layer 11 is below a preset density, which is 1 × 10⁻⁶. 11 cm -2 ·eV -1 .

[0145] The semiconductor doped layer 12 is disposed on the side of the tunneling oxide layer 11 away from the substrate 10. The semiconductor doped layer 12 is disposed on the back side 10b of the substrate 10. The thickness of the semiconductor doped layer 12 is 80nm~150nm. The semiconductor doped layer 12 and the tunneling oxide layer 11 on the back side 10b of the substrate 10 together form a passivation contact structure. The semiconductor doped layer 12 is doped with a first element, which can be phosphorus or boron.

[0146] The solar cell of this embodiment has a cell efficiency of 24.5%~25.2%, an open circuit voltage of 740mV, a fill factor of more than 83%, a manufacturing cost of metal electrode 13 reduced by 50% or more, and a conductivity of metal electrode 13 increased by 20%.

[0147] In one embodiment, such as Figure 6 or Figure 7 As shown, the interface state density of the tunneling oxide layer 11 is 1×10⁻⁶. 13 cm -2 ·eV -1 -1×10 11 cm -2 ·eV -1 For example, the interface state density of the tunneling oxide layer 11 can be 5 × 10⁻⁶. 10 cm -2 ·eV -1 5.3×10 10 cm -2 ·eV -1 7.2×10 10 cm -2 ·eV -1 9.8×10 10 cm -2 ·eV -1 1×10 11 cm -2 ·eV -1 .

[0148] In one embodiment, such as Figure 6 or Figure 7 As shown, the concentration of the first element in the semiconductor doped layer 12 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0149] In one embodiment, such as Figure 6 or Figure 7 As shown, the solar cell also includes a metal electrode 13 and a diffusion barrier layer 14. The metal electrode 13 is disposed on the side of the semiconductor doped layer 12 away from the substrate 10, and the diffusion barrier layer 14 covers the surface of the metal electrode 13.

[0150] For example, the height of the metal electrode 13 is 15μm to 25μm, and the width is 20μm to 40μm. For example, the height of the metal electrode 13 can be 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, or 25μm; the width of the metal electrode 13 can be 20μm, 22μm, 24μm, 25μm, 26μm, 28μm, 30μm, 31μm, 33μm, 35μm, 36μm, 37μm, 38μm, 39μm, or 40μm.

[0151] The thickness of the diffusion barrier layer 14 is 50nm to 100nm. For example, the thickness of the diffusion barrier layer 14 can be 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, or 100nm. The diffusion barrier layer 14 is used to prevent copper diffusion in the metal electrode 13 and improve the welding performance of the metal electrode 13.

[0152] In one embodiment, the metal electrode 13 is made of copper; the diffusion barrier layer 14 is made of at least one of nickel or tin.

[0153] The diffusion barrier layer 14 can be a single layer or multiple layers, for example, such as Figure 6 As shown, the diffusion barrier layer 14 may include a single nickel layer, or the diffusion barrier layer 14 may include a single tin layer, or, as... Figure 7 As shown, the diffusion barrier layer 14 may include a first sublayer 141 and a second sublayer 142 stacked together. The first sublayer 141 is a nickel layer and the second sublayer 142 is a tin layer. Alternatively, the first sublayer 141 is a tin layer and the second sublayer 142 is a nickel layer.

[0154] In some embodiments, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is less than or equal to a first resistance. The first resistance is 1 mΩ·cm. 2 .

[0155] Furthermore, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 is in the range of 0.5 mΩ·cm. 2 ~1mΩ·cm 2 For example, the contact resistance between the semiconductor doped layer 12 and the metal electrode 13 can be 0.5 mΩ·cm. 2 0.52mΩ·cm 2 0.55mΩ·cm 2 0.58mΩ·cm 2 0.63mΩ·cm 2 0.7mΩ·cm 2 0.8mΩ·cm 2 0.9mΩ·cm2 or 1mΩ·cm 2 .

[0156] According to an exemplary embodiment, this embodiment provides a stacked battery 100, referring to... Figure 9 , Figure 10 , Figure 11 As shown, the tandem solar cell 100 includes a bottom cell 200 and a top cell 500 stacked on the bottom cell 200. The bottom cell 200 includes a solar cell from the above embodiments or a solar cell fabricated using the method described in the above embodiments. The top cell 500 includes a perovskite cell. The perovskite cell comprises a transparent electrode layer, an electron transport layer, a perovskite light-absorbing layer, and a hole transport layer sequentially stacked on the solar cell. The tandem solar cell 100 in this embodiment can be a two-terminal, three-terminal, or four-terminal tandem solar cell. The tandem solar cell 100 of this embodiment is compatible with both solar and perovskite cells, offering advantages such as high current compatibility, high process tolerance, and wider applicability in outdoor scenarios, thus possessing greater development and application potential.

[0157] In one example, such as Figure 9 As shown, the tandem solar cell 100 is a two-terminal tandem solar cell. The perovskite cell is disposed on one side of the back of the solar cell, and the perovskite cell and the solar cell are connected in series. The positive electrode of the solar cell is connected to the negative electrode of the perovskite cell, with the positive electrode of the perovskite cell serving as the positive electrode of the tandem solar cell 100, and the negative electrode of the solar cell serving as the negative electrode of the tandem solar cell 100. An intermediate connecting layer may also be provided between the perovskite cell and the solar cell, with the negative electrode of the perovskite cell connected to the positive electrode of the solar cell through the intermediate connecting layer. The intermediate connecting layer can be a transparent conductive oxide layer or a composite layer.

[0158] In another example, such as Figure 10 As shown, the tandem solar cell 100 is a three-terminal tandem solar cell. The tandem solar cell 100 includes a solar cell, a perovskite cell, and a common electrode layer. The perovskite cell is stacked on top of the solar cell, and the common electrode layer is located between the perovskite cells. The first metal electrode of the solar cell is the positive electrode, and the second metal electrode is the negative electrode. The negative electrode of the perovskite cell and the positive electrode of the solar cell are connected to the common electrode layer. The common electrode layer is a transparent conductive material or a composite material layer with specific optical properties, used to optimize the transmission and distribution of photogenerated charge. The positive electrode of the perovskite cell is connected to its transparent electrode layer. Thus, the top cell 500 and the bottom cell 200 of the tandem solar cell 100 each have independent output electrodes, and both share some charge with the common electrode layer through optical coupling or electrical connection; the photogenerated current of the top cell 500 and the bottom cell 200 can be output partially independently, or integrated through the current of the common electrode layer.

[0159] In yet another example, such as Figure 11 As shown, the tandem solar cell 100 is a four-terminal tandem solar cell. The tandem solar cell 100 includes a solar cell and a perovskite cell stacked on top of the solar cell. The solar cell and the perovskite cell achieve efficient utilization of light energy through optical coupling, but are completely independent electrically. The perovskite cell and the solar cell each have independent positive and negative electrodes, used for collecting and transmitting photogenerated charges, respectively; the electrodes of the perovskite cell and the solar cell are independently connected to external circuits to achieve their respective photogenerated current outputs; there is no direct electrical connection between the perovskite cell and the solar cell, and spectral segmentation and light energy distribution are achieved only through optical design.

[0160] According to an exemplary embodiment, this application provides a photovoltaic module, including a solar cell as described in the above embodiments, or a solar cell manufactured by a method for manufacturing solar cells, or, alternatively, a tandem cell as described in the above embodiments.

[0161] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0162] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a solar cell, characterized in that, The method comprises: providing a substrate; A tunneling oxide layer with a thickness of 1 nm to 2 nm is formed on the surface of the substrate by atomic layer deposition, hydrogen plasma is obtained by ionizing hydrogen gas at a power of 50 W to 100 W, and the tunneling oxide layer is treated by using the hydrogen plasma, with a treatment time of 30 s to 60 s, so that the interface state density of the tunneling oxide layer is reduced to 5*10 10 cm -2 ·eV -1 ~1*10 11 cm -2 ·eV -1 ; wherein the temperature for atomic layer deposition of the tunneling oxide layer is 200 DEG C to 250 DEG C; depositing an amorphous silicon layer on a side of the tunneling oxide layer distal from the substrate using low pressure chemical vapor deposition, and simultaneously doping the amorphous silicon layer in situ with a first element, the concentration of the first element doped into the amorphous silicon layer being in a range of 1 x 1018cm-3 to 5 x 1020cm-3. 19 cm -3 ~5×10 20 cm -3 ; The amorphous silicon layer is annealed by using ultraviolet laser with wavelength of 300nm-380nm, scanning speed is 10mm / s-50mm / s, and energy density is 0.5J / cm 2 -1.5J / cm 2 . The amorphous silicon is formed into polycrystalline silicon, and the doping atoms are activated to form a semiconductor doped layer, and the energy density of the ultraviolet laser is 0.5J / cm 2 -1.5J / cm 2 .

2. The method of producing a solar cell according to claim 1, wherein The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The contact resistance between the semiconductor doped layer and the metal electrode is less than or equal to a first resistance; the first resistance is 1 mΩ·cm 2 .

3. The method of producing a solar cell according to claim 2, wherein the forming of the diffusion barrier layer comprises forming a first sub-layer and a second sub-layer stacked in sequence.

4. A solar cell, characterized by, The solar cell is made by the method of any one of claims 1-3, and comprises: a substrate; A tunnel oxide layer is disposed on the surface of the substrate, and an interface state density of the tunnel oxide layer is below a preset density; the preset density is 1×10 11 cm -2 ·eV -1 ; a semiconductor doped layer provided on a side of the tunneling oxide layer away from the substrate, the semiconductor doped layer doped with a first element.

5. The solar cell according to claim 4, characterized in that, The interface state density of the tunneling oxide layer is 5 x 1011 cm-2 eV-1. 10 cm -2 ·eV -1 ~1 x 1011 cm-2 eV-1 11 cm -2 ·eV -1 .

6. The solar cell according to claim 5, characterized in that, The solar cell further comprises a metal electrode provided on a side of the semiconductor doped layer away from the substrate, and a diffusion barrier layer covering a surface of the metal electrode; the metal electrode comprises copper; and the diffusion barrier layer comprises at least one of nickel or tin. The contact resistance of the semiconductor doped layer and the metal electrode is less than or equal to a first resistance; the first resistance is 1 mΩ·cm 2 .

7. A stacked battery characterized by comprising: The method comprises: providing a substrate; 8. A photovoltaic module, characterized by, The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a surface of the metal electrode, the diffusion barrier layer comprising at least one of nickel or tin; The method comprises: providing a substrate; The method further comprises: forming a mask layer on a side of the semiconductor doped layer away from the substrate, the mask layer exposing a first region of the substrate; forming a metal electrode on the first region by electroplating, the metal electrode comprising copper; after removing the mask layer, forming a diffusion barrier layer covering a

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