Wafer, method for inspecting light-emitting element, display device, and method for manufacturing display device

Abstract

The invention provides a wafer, an inspection method of a light-emitting element, a display device, and a manufacturing method of the display device. The wafer comprises a substrate; a plurality of light emitting elements on the substrate, each of the plurality of light emitting elements including a semiconductor stack, a first contact electrode, and a second contact electrode; a plurality of pin pads on the substrate, and each of the plurality of pin pads includes a semiconductor stack; and a plurality of connectors respectively connecting the different pin pads to the first contact electrode and the second contact electrode of the light emitting element among the plurality of light emitting elements.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0055950, filed on April 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a method for inspecting wafers and light-emitting elements, a display device, a method for manufacturing a display device, and an apparatus for inspecting light-emitting elements. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays.

[0004] Light-emitting display devices can include organic light-emitting display devices that use organic light-emitting diode (OLED) elements as light-emitting elements, and micro light-emitting display devices that use micro light-emitting diode elements (hereinafter referred to as micro light-emitting elements) as light-emitting elements. Because micro light-emitting diode elements are made of inorganic materials, they have the advantages of less degradation problems and longer lifespan compared with organic light-emitting diode (OLED) elements.

[0005] In display devices manufactured by bonding micro-light-emitting elements to a display panel, defect inspection of the micro-light-emitting elements is performed after the display device manufacturing process is completed. If defects in the micro-light-emitting elements are found after the display device manufacturing process is completed, conventional illumination inspection methods suffer from reduced process efficiency and consequently reduced productivity because it is not easy to replace the defective micro-light-emitting elements with high-quality ones. Summary of the Invention

[0006] The aspects and features of embodiments of this disclosure are to provide a wafer, inspection method, etc., that can inspect defects in light-emitting elements on a wafer.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0008] According to one or more embodiments of the present disclosure, a wafer includes: a substrate; a plurality of light-emitting elements, each of the plurality of light-emitting elements including a semiconductor stack, a first contact electrode and a second contact electrode on the substrate; a plurality of lead pads, each of the plurality of lead pads including a semiconductor stack; and a plurality of connectors for connecting different lead pads to the first contact electrode and the second contact electrode of the light-emitting elements, respectively.

[0009] The semiconductor stack comprises a third semiconductor layer, a second semiconductor layer, an active layer, and a first semiconductor layer stacked sequentially.

[0010] The plurality of pin pads includes a first pin pad and a second pin pad, wherein the plurality of connectors includes a first connector that connects a first contact electrode and a first pin pad and a second connector that connects a second contact electrode and a second pin pad.

[0011] The first pin pad, the light-emitting element, and the second pin pad are aligned with each other in a first direction.

[0012] The first pin pad and the second pin pad are not aligned in the first direction, and the light-emitting element is not aligned with the first pin pad and the second pin pad.

[0013] Each of the multiple pin pads also includes a contact pad on the semiconductor stack, wherein the contact pad, the first contact electrode, the second contact electrode, and the multiple connectors are integrally formed together.

[0014] Multiple light-emitting elements are arranged along a first direction and a second direction, wherein multiple pin pads are arranged alternately with the multiple light-emitting elements along the second direction, wherein the pin pads located between the first light-emitting element and the second light-emitting element in the second direction are connected to the second contact electrode of the first light-emitting element and connected to the first contact electrode of the second light-emitting element.

[0015] The semiconductor stack of the light-emitting element includes a concave groove that exposes a second semiconductor layer of the semiconductor stack in a region overlapping with a second contact electrode, wherein the second contact electrode is electrically connected to the second semiconductor layer exposed through the concave groove, and wherein a first contact electrode is electrically connected to a first semiconductor layer of the semiconductor stack.

[0016] In one or more embodiments, the display device includes: a substrate; pixel electrodes and a common electrode, spaced apart from each other on the substrate; a light-emitting element, on the pixel electrodes and the common electrode; a first contact electrode, on the light-emitting element and the pixel electrodes; and a second contact electrode, on the light-emitting element and the common electrode, wherein the light-emitting element includes: a semiconductor stack; a protective layer surrounding all sides of the semiconductor stack except one side; a reflective layer surrounding the semiconductor stack on the protective layer; a first tip extending from the first contact electrode and projecting outwardly perpendicular to a side surface of the semiconductor stack; and a second tip extending from the second contact electrode and projecting outwardly perpendicular to a side surface of the semiconductor stack.

[0017] The display device further includes a first connection electrode that electrically connects the first contact electrode and the pixel electrode, and a second connection electrode that electrically connects the second contact electrode and the common electrode.

[0018] The reflective layer includes a first reflective layer between the first contact electrode and the protective layer and a second reflective layer between the second contact electrode and the protective layer, wherein the first reflective layer and the second reflective layer are spaced apart from each other.

[0019] The semiconductor stack includes a recessed groove that exposes a second semiconductor layer of the semiconductor stack in a region overlapping with a second contact electrode, wherein the second contact electrode is electrically connected to the second semiconductor layer exposed through the recessed groove, and wherein a first contact electrode is electrically connected to a first semiconductor layer of the semiconductor stack.

[0020] In one or more embodiments, the method for inspecting a light-emitting element includes the following steps: forming a plurality of semiconductor stacks by stacking and etching a plurality of semiconductor material layers on a substrate; forming a protective layer covering a portion of the top and side surfaces of the plurality of semiconductor stacks; forming contact electrodes and contact pads on the protective layer to form a light-emitting element and lead pads, wherein the lead pads are electrically connected to the contact electrodes via connectors; and contacting a first probe and a second probe respectively with a first lead pad and a second lead pad connected to the contact electrodes of the same light-emitting element in the lead pads, and applying a test power supply.

[0021] In the step of forming contact electrodes and contact pads on a protective layer to form a light-emitting element and a lead pad, the lead pad is electrically connected to the contact electrode by a connector. The light-emitting element is formed by forming a first contact electrode and a second contact electrode on the protective layer of a first semiconductor stack in a plurality of semiconductor stacks. The first lead pad is formed by forming a contact pad on the protective layer of a second semiconductor stack in a plurality of semiconductor stacks. The second lead pad is formed by forming a contact pad on the protective layer of a third semiconductor stack in a plurality of semiconductor stacks. The connector includes a first connector and a second connector. The inspection method further includes forming a first connector connecting the first contact electrode and the first lead pad, and a second connector connecting the second contact electrode and the second lead pad.

[0022] The first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are arranged in a straight line relative to each other in a first direction.

[0023] The inspection method further includes acquiring an image of the light emitted from the light-emitting element under a test power supply; and comparing the acquired image with a reference image by a control unit to determine the characteristics of the light-emitting element.

[0024] In one or more embodiments, a method for manufacturing a display device including multiple light-emitting elements includes the following steps: forming multiple semiconductor stacks by stacking and etching multiple semiconductor material layers on a wafer substrate; forming a protective layer covering a portion of the top surface and side surface of the multiple semiconductor stacks; forming contact electrodes and contact pads on the protective layer to form light-emitting elements and pin pads among the multiple light-emitting elements, wherein the pin pads are electrically connected to the contact electrodes via connectors; contacting a first probe and a second probe respectively with a first pin pad and a second pin pad connected to the contact electrode of the same light-emitting element in the pin pads, and inspecting the light-emitting elements; and transferring the multiple light-emitting elements to a circuit board.

[0025] In the step of forming contact electrodes and contact pads on a protective layer to form a light-emitting element and a lead pad, the lead pad is electrically connected to the contact electrode by a connector including a first connector and a second connector. The contact electrode includes a first contact electrode and a second contact electrode. The light-emitting element is formed by forming the first contact electrode and the second contact electrode on the protective layer of a first semiconductor stack in a plurality of semiconductor stacks. The first lead pad is formed by forming a contact pad on the protective layer of a second semiconductor stack in a plurality of semiconductor stacks. The second lead pad is formed by forming a contact pad on the protective layer of a third semiconductor stack in a plurality of semiconductor stacks. The first connector connects the first contact electrode and the first lead pad, and the second connector connects the second contact electrode and the second lead pad.

[0026] The steps of contacting the first probe and the second probe with the first pin pad and the second pin pad connected to the contact electrode of the same light-emitting element and inspecting the light-emitting element include: contacting the first probe and the second probe with the first pin pad and the second pin pad connected to the contact electrode of the same light-emitting element and applying a test power supply; acquiring an image of the light emitted from the light-emitting element under the applied test power supply; and comparing the acquired image with a reference image by a control section to determine the characteristics of the light-emitting element.

[0027] The circuit board includes multiple pixel circuit sections, pixel electrodes connected to each of the multiple pixel circuit sections, and a common electrode spaced apart from the pixel electrodes. The light-emitting elements include a first contact electrode and a second contact electrode. After the multiple light-emitting elements are transferred to the circuit board, the manufacturing method further includes forming a first connection electrode that connects the first contact electrode and the pixel electrode, and a second connection electrode that connects the second contact electrode and the common electrode.

[0028] According to one or more embodiments of the display device and the manufacturing method thereof, the element characteristics of flip-chip light-emitting elements or lateral light-emitting elements can be detected on a wafer.

[0029] However, the effects, aspects and features of this disclosure are not limited to those described above, and various other effects, aspects and features are included in this disclosure. Attached Figure Description

[0030] These and / or other aspects of the embodiments of this disclosure will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings.

[0031] Figure 1 It is a perspective view of a display device according to one or more embodiments.

[0032] Figure 2 It is a layout diagram of a display device according to one or more embodiments.

[0033] Figure 3 It is a block diagram of a display device according to one or more embodiments.

[0034] Figure 4 It is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0035] Figure 5 It is a layout diagram showing the pixels of a display area according to one or more embodiments.

[0036] Figure 6 It shows a display panel and Figure 5 The sectional view of the example section corresponding to line I1-I1' in the diagram.

[0037] Figure 7 It is shown in detail Figure 6 A cross-sectional view of an example of region A.

[0038] Figure 8 It is shown in detail Figure 7 A plan view of the light-emitting element.

[0039] Figure 9 and Figure 10 It is a plan view showing details of a light-emitting element according to one or more embodiments.

[0040] Figure 11 It is a layout diagram showing the pixels of a display area according to one or more embodiments.

[0041] Figure 12 It shows the display panel and Figure 11 A sectional view of an example of the sections corresponding to lines I1-I1', I2-I2', and I3-I3'.

[0042] Figure 13 It is shown in detail Figure 12 A cross-sectional view of an example of region B in the diagram.

[0043] Figure 14 This is a layout diagram showing the light-emitting elements and lead pads (or "soldering pads") on a wafer according to one or more embodiments.

[0044] Figure 15 It is shown in detail Figure 14 A layout diagram of an example of region C in the diagram.

[0045] Figure 16 It is shown in detail Figure 14 A plan view of a test block.

[0046] Figure 17 It is shown in detail Figure 16 A cross-sectional view of the test block.

[0047] Figure 18 and Figure 19 It is illustrated in detail according to one or more embodiments Figure 14 A layout diagram of an example of region C in the diagram.

[0048] Figure 20 This is a schematic diagram illustrating a light-emitting element inspection apparatus according to one or more embodiments.

[0049] Figure 21 This is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments.

[0050] Figure 22 This is a flowchart illustrating a method for manufacturing a wafer according to one or more embodiments.

[0051] Figures 23 to 30 This is a diagram illustrating a method for manufacturing a wafer and a method for transferring light-emitting elements according to one or more embodiments.

[0052] Figure 31 This is an example diagram of a smartwatch that includes a display device according to one or more embodiments.

[0053] Figure 32 and Figure 33 This is an example diagram of a virtual reality (VR) device that includes a display device according to one or more embodiments.

[0054] Figure 34 This is an example diagram of a VR device that includes a display device according to one or more embodiments.

[0055] Figure 35 This is an example diagram illustrating a vehicle instrument cluster and a central dashboard that include a display device according to one or more embodiments.

[0056] Figure 36This is an example diagram of a transparent display device including a display device according to one or more embodiments. Detailed Implementation

[0057] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0058] In order to describe embodiments of this disclosure, some parts that are not essential to a full understanding of this disclosure by those skilled in the art may not be provided.

[0059] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or an intermediary layer may be present. Conversely, when an element is referred to as being "directly on" another element, an intermediary element may not be present.

[0060] Furthermore, the phrase "in a plan view" refers to the view of an object portion from above, and the phrase "in a schematic sectional view" refers to the view of a schematic section taken by vertically cutting through an object portion from the side. The terms "overlapping" or "overlapping" indicate that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlapping" can include layering, stacking, facing or oriented, extending over, covering or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "spaced apart from," "next to," or "offset from," and any other suitable equivalents that will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can indicate that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0061] For ease of description, the spatial relative terms “below,” “under,” “lower,” “above,” “upper,” etc., as shown in the accompanying drawings, are used to describe the relationship between one element or component and another. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. For example, in the case where the device shown in the drawings is flipped, the device located “below” or “under” another device may be placed “above” said other device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0062] When an element is referred to as being “connected” or “joined” to another element, the element may be “directly connected” or “directly joined” to said other element, or “electrically connected” or “electrically joined” to said other element with one or more intermediary elements placed between them. It will also be understood that when the terms “comprising,” “having,” “including,” and / or variations thereof are used, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0063] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or to facilitate its description and explanation. For example, when “first element” is discussed in the specification, it may be referred to as “second element” or “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teaching herein.

[0064] The term “about” or “approximately” as used herein includes the stated value and means: within an acceptable deviation of the particular value, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0065] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctional or disjunctive sense and can be understood as equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0066] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined in the specification.

[0067] Those skilled in the art will understand that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or partially or completely combined with each other, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in any suitable combination with each other.

[0068] Figure 1 This is a perspective view of a display device 10 according to one or more embodiments.

[0069] Reference Figure 1 The display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen in portable electronic devices (such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)) and various products (such as televisions, laptops, monitors, billboards, and / or Internet of Things (IoT) devices).

[0070] Display device 10 may be a light-emitting display, such as an organic light-emitting display using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, or a micro-light-emitting display or nano-light-emitting display using micro-light-emitting diodes (LEDs) or nano-light-emitting diodes (LEDs). The following description will primarily focus on the case where display device 10 is a micro-light-emitting display or a nano-light-emitting display, but this disclosure is not limited thereto. For ease of description, micro-LEDs or nano-LEDs will be referred to as light-emitting elements.

[0071] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply unit 500.

[0072] The display panel 100 can be shaped similarly to a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. Each corner where the short side extending in the first direction DR1 intersects the long side extending in the second direction DR2 can be rounded to have a suitable curvature (e.g., a predetermined curvature) or can be right angled. The planar shape of the display panel 100 is not limited to a quadrilateral shape, but can also be other polygonal shapes, circular shapes, and / or elliptical shapes. The display panel 100 can be formed as a flat surface, but this disclosure is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having constant or varying curvatures. Furthermore, the display panel 100 can be formed as flexible, such that it can be bent, folded, and / or rolled up.

[0073] The base SUB of the display panel 100 may include a main area MA and a sub-area SBA.

[0074] The main region MA may include a display region DA for displaying an image and a non-display region NDA disposed around the display region DA along its edge or periphery. The display region DA may include multiple pixels for displaying the image. Each pixel may include multiple sub-pixels. For example, each pixel may include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color, but this disclosure is not limited thereto.

[0075] The subregion SBA can protrude from one side of the main region MA in the second direction DR2. Although the subregion SBA is in Figure 1 The sub-region SBA can be unfolded, but it can be bent. In this case, the sub-region SBA can be placed on the lower surface of the display panel 100. When the sub-region SBA is bent, it can be superimposed on the main region MA on the third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 can be provided in the sub-region SBA.

[0076] The display driving circuit 250 can generate signals and voltages for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, and / or ultrasonic bonding method. However, this disclosure is not limited thereto. For example, the display driving circuit 250 can also be attached to the circuit board 300 using a chip-on-film (COF) method.

[0077] The circuit board 300 can be attached to the end of a sub-region SBA of the display panel 100. Therefore, the circuit board 300 can be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as chip on film (COF).

[0078] The power supply unit 500 can generate multiple panel driving voltages based on the power supply voltage from an external source. The power supply unit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0079] Figure 2 This is a layout diagram of a display device 10 according to one or more embodiments. Figure 2 This shows the state where the subregion SBA unfolds without bending.

[0080] Reference Figure 2 The display panel 100 may include a main area MA and a sub-area SBA.

[0081] The main region MA may include a display area DA for displaying the image and a non-display area NDA surrounding the display area DA. The display area DA may occupy most of the main region MA. The display area DA may be located at the center of the main region MA.

[0082] The display area DA may include multiple pixels PX for displaying images, and each of the pixels PX may include multiple sub-pixels SPX. A pixel PX can be defined as the smallest group of sub-pixels that can represent a grayscale level.

[0083] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be around the display area DA (e.g., surrounding the display area DA). The non-display area NDA can be an edge area of ​​the display panel 100.

[0084] The first scan driver SDC1 and the second scan driver SDC2 can be located in the non-display area NDA. The first scan driver SDC1 can be located on one side of the display panel 100 (e.g., the left side), and the second scan driver SDC2 can be located on the other side of the display panel 100 (e.g., the right side). However, this disclosure is not limited thereto.

[0085] Each of the first scan driver SDC1 and the second scan driver SDC2 can be electrically connected to the display driver circuit 250 via a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 can receive a scan control signal from the display driver circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0086] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be bent and placed below the display panel 100. In this case, the sub-region SBA may be superimposed on the main region MA in the third direction DR3.

[0087] The sub-region SBA can include the connection region CA, the pad (or "solder pad") region PA, and the bend region BA.

[0088] The connecting area CA is a region that protrudes from one side of the main area MA in the second direction DR2. One side of the connecting area CA can contact the non-display area NDA of the main area MA, and the other side of the connecting area CA can contact the curved area BA.

[0089] The pad area PA is the area where the pad PD and the display driving circuit 250 are mounted. The display driving circuit 250 can be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA can contact the curved area BA.

[0090] The bending region BA is a flexible region. When the bending region BA bends, the pad region PA can be placed below the connecting region CA and the main region MA. The bending region BA can be positioned between the connecting region CA and the pad region PA. One side of the bending region BA can contact the connecting region CA, and the other side of the bending region BA can contact the pad region PA.

[0091] Figure 3 This is a block diagram of a display device 10 according to one or more embodiments.

[0092] Reference Figure 3 The display area DA includes multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL.

[0093] Pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, pixels PX can be arranged along the rows and columns of a matrix along the first direction DR1 and the second direction DR2. Scan lines SL and emit control lines EL can extend along the first direction DR1 and can be arranged along the second direction DR2. Data lines DL can extend along the second direction DR2 and can be arranged along the first direction DR1. Scan lines SL include multiple write scan lines GWL, multiple initialization scan lines GIL, and multiple bias scan lines GBL.

[0094] Each sub-pixel SPX can be connected to one of the write scan lines GWL, one of the control scan lines, one of the initialization scan lines GIL, one of the bias scan lines GBL, one of the emission control lines EL, and one of the data lines DL. Each sub-pixel SPX can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0095] The non-display area NDA includes a first scan driver SDC1, a second scan driver SDC2, and a display driver circuit 250.

[0096] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, an initialization scan signal output unit 612, a bias scan signal output unit 613, and a transmit signal output unit 614. Each of the write scan signal output unit 611, the initialization scan signal output unit 612, the bias scan signal output unit 613, and the transmit signal output unit 614 may receive a scan timing control signal SCS from the timing controller 251. The write scan signal output unit 611 can generate a write scan signal according to the scan timing control signal SCS from the timing controller 251, and sequentially output the write scan signal to the write scan line GWL. The initialization scan signal output unit 612 can generate an initialization scan signal according to the scan timing control signal SCS, and sequentially output the initialization scan signal to the initialization scan line GIL. The bias scan signal output unit 613 can generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL. The transmit signal output unit 614 can generate transmit control signals according to the scan timing control signal SCS, and sequentially output the transmit control signals to the transmit control line EL. In one or more embodiments, the control scan signal output unit of each of the first scan driver SDC1 and the second scan driver SDC2 can generate control scan signals according to the scan timing control signal SCS and sequentially output the control scan signals to the control scan line.

[0097] The display driver circuit 250 includes a timing controller 251 and a data driver 252.

[0098] Data driver 252 can receive digital video data DATA and data timing control signal DCS from timing controller 251. Data driver 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to data line DL. In this case, sub-pixel SPX can be selected by the write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data voltage can be supplied to the selected sub-pixel SPX.

[0099] The timing controller 251 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing controller 251 can generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100. The timing controller 251 can output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing controller 251 can also output the digital video data DATA and the data timing control signal DCS to the data driver 252.

[0100] The power supply unit 500 can generate multiple panel driving voltages based on the power supply voltage from an external source. For example, the power supply unit 500 can generate a first driving voltage VDD, a second driving voltage VSS, a third driving voltage VINT, and a fourth driving voltage VAINT, and supply them to the display panel 100.

[0101] Figure 4 It is an equivalent circuit diagram of a sub-pixel SPX according to one or more embodiments.

[0102] Reference Figure 4 According to one or more embodiments, the subpixel SPX can be connected to scan lines GWL, GIL, and GBL, emission control line EL, and data line DL. For example, the subpixel SPX can be connected to the write scan line GWL, the initialization scan line GIL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0103] According to an embodiment, the sub-pixel SPX includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes first transistors ST1 through sixth transistors ST6.

[0104] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current Ids (hereinafter referred to as the "driving current") flowing between the first and second electrodes based on the data voltage applied to the gate electrode.

[0105] The light-emitting element (LE) can be a micro-LED.

[0106] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE can be proportional to the driving current Ids. The anode of the light-emitting element LE can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode of the light-emitting element LE can be connected to the second power supply line VSL to which the second driving voltage VSS is applied.

[0107] A capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power supply line VDL to which a first driving voltage VDD is applied. The first driving voltage VDD can be at a level higher than the second driving voltage VSS. One electrode of capacitor C1 can be connected to the gate electrode of the driving transistor DT, and the other electrode of capacitor C1 can be connected to the first power supply line VDL.

[0108] like Figure 4 As shown, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can all be formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layer of each of the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can be made of polysilicon.

[0109] The gate electrodes of the first transistor ST1 and the second transistor ST2 can be connected to the write scan line GWL. The gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL. The gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 can be connected to the emitter control line EL. Because the first transistor ST1 to the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on when a scan signal with a low gate voltage and an emitter control signal with a low gate voltage are transmitted to the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emitter control line EL. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 can be connected to the initialization voltage line VIL and another voltage line VAIL, respectively.

[0110] Optionally, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed as p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be formed as n-type MOSFETs. The active layer of each of the driving transistors DT, ST2, ST4, ST5, and ST6 formed as p-type MOSFETs can be made of polysilicon, and the active layer of each of the first transistor ST1 and ST3 formed as n-type MOSFETs can be made of oxide semiconductor.

[0111] In this configuration, because the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can turn on in response to a scan signal with a high gate voltage, and the third transistor ST3 can turn on in response to an initial scan signal with a high gate voltage. On the other hand, because the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can turn on in response to a scan signal with a low gate voltage and a emitter control signal with a low gate voltage.

[0112] Optionally, the fourth transistor ST4 can be formed as an n-type MOSFET. In this case, the active layer of the fourth transistor ST4 can be made of oxide semiconductor. When the fourth transistor ST4 is formed as an n-type MOSFET, it can turn on in response to a scan signal with a high gate voltage.

[0113] Optionally, the first transistor ST1 through the sixth transistor ST6 and the driving transistor DT can all be formed as n-type MOSFETs. In this case, the active layer of each of the first transistor ST1 through the sixth transistor ST6 and the driving transistor DT can be made of oxide semiconductor.

[0114] Figure 5 It is a layout diagram showing the pixels of a display area according to one or more embodiments.

[0115] Reference Figure 5 Each of the plurality of pixels PX in the display area DA may include three sub-pixels SPX1, SPX2, and SPX3, but this disclosure is not limited thereto; each of the plurality of pixels PX in the display area DA may include four sub-pixels. When each of the plurality of pixels PX includes three sub-pixels, the sub-pixels may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0116] Multiple pixels PX can be arranged in a matrix. In each of the multiple pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along the first direction DR1.

[0117] When each of the multiple pixels PX comprises three sub-pixels SPX1, SPX2, and SPX3, the first sub-pixel SPX1 can emit a first light, the second sub-pixel SPX2 can emit a second light, and the third sub-pixel SPX3 can emit a third light. Here, the first light can be light in the red band, the second light can be light in the green band, and the third light can be light in the blue band. For example, light in the blue band can refer to light with a main peak wavelength in the band from approximately 370 nm to 460 nm, light in the green band can refer to light with a main peak wavelength in the band from approximately 480 nm to 560 nm, and light in the red band can refer to light with a main peak wavelength in the band from approximately 600 nm to 750 nm.

[0118] Optionally, when each of the multiple pixels PX comprises four sub-pixels, the first sub-pixel can emit a first light, the second and fourth sub-pixels can emit a second light, and the third sub-pixel can emit a third light. Alternatively, the first sub-pixel can emit the first light, the second sub-pixel can emit the second light, the third sub-pixel can emit the third light, and the fourth sub-pixel can emit a fourth light. In this case, the fourth light can be white light.

[0119] The first sub-pixel SPX1 includes a first pixel electrode PXE1, a first common electrode CE1, multiple light-emitting elements LE, and a first light conversion layer QDL1. The second sub-pixel SPX2 includes a second pixel electrode PXE2, a second common electrode CE2, multiple light-emitting elements LE, and a second light conversion layer QDL2. The third sub-pixel SPX3 includes a third pixel electrode PXE3, a third common electrode CE3, multiple light-emitting elements LE, and a light transmission layer (or a third light conversion layer) TPL.

[0120] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can have a rectangular planar shape with a short side in the first direction DR1 and a long side in the second direction DR2. The area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 can be set according to the light conversion efficiency of the first light conversion layer QDL1 and the light conversion efficiency of the second light conversion layer QDL2. For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0121] For example, such as Figure 5As shown, when the light conversion efficiency of the second light conversion layer QDL2 is lower than that of the first light conversion layer QDL1, the area of ​​the second pixel electrode PXE2 can be larger than the area of ​​the first pixel electrode PXE1. Furthermore, because the light transmission layer TPL transmits light from the light-emitting element LE as is, while the first light conversion layer QDL1 needs to convert the light, the area of ​​the first pixel electrode PXE1 can be larger than the area of ​​the third pixel electrode PXE3.

[0122] Each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to at least one transistor via pixel connection holes CT1, CT2, and CT3. For example, each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to a fourth transistor of the corresponding sub-pixel. Figure 4 The first electrode and the sixth transistor (ST4) in the middle Figure 4 The second electrode of ST6 in the middle.

[0123] Each of the pixel electrodes PXE1, PXE2, and PXE3, and the common electrodes CE1, CE2, and CE3, can have a rectangular planar shape. The area of ​​the first pixel electrode PXE1 can be the same as the area of ​​the first common electrode CE1, the area of ​​the second pixel electrode PXE2 can be the same as the area of ​​the second common electrode CE2, and the area of ​​the third pixel electrode PXE3 can be the same as the area of ​​the third common electrode CE3, but this disclosure is not limited thereto.

[0124] In the first sub-pixel SPX1, the first pixel electrode PXE1 and the first common electrode CE1 can be arranged to be spaced apart (e.g., separated) in the second direction DR2. In the second sub-pixel SPX2, the second pixel electrode PXE2 and the second common electrode CE2 can be arranged to be spaced apart (e.g., separated) in the second direction DR2. In the third sub-pixel SPX3, the third pixel electrode PXE3 and the third common electrode CE3 can be arranged to be spaced apart (e.g., separated) in the second direction DR2.

[0125] The first common electrode CE1 can be connected to the second power line VSL, to which the second driving voltage VSS is applied, via the first common connection hole CT4. The second common electrode CE2 can be connected to the second power line VSL via the second common connection hole CT5. The third common electrode CE3 can be connected to the second power line VSL via the third common connection hole CT6. Therefore, the second driving voltage VSS can be applied to each of the common electrodes CE1, CE2, and CE3.

[0126] Multiple light-emitting elements (LEs) can be disposed on each of the pixel electrodes PXE1, PXE2, and PXE3 and the common electrodes CE1, CE2, and CE3. At least a portion of the pixel electrodes PXE1, PXE2, and PXE3 and the common electrodes CE1, CE2, and CE3 can be exposed without any light-emitting elements (LEs) disposed thereon. The same number of light-emitting elements (LEs) can be disposed on each of the pixel electrodes PXE1, PXE2, and PXE3 and the common electrodes CE1, CE2, and CE3. For example, two light-emitting elements (LEs) can be disposed on each of the pixel electrodes PXE1, PXE2, and PXE3. The multiple light-emitting elements (LEs) can emit a third light, such as light in the blue band, but this disclosure is not limited thereto. When the light-emitting elements (LEs) of the first sub-pixel SPX1 emit a first light, the light-emitting elements (LEs) of the second sub-pixel SPX2 emit a second light, and the light-emitting elements (LEs) of the third sub-pixel SPX3 emit a third light, the light conversion layers QDL1 and QDL2 and the light transmission layer TPL can be omitted.

[0127] The first light conversion layer QDL1 can be completely stacked with the first pixel electrode PXE1 and multiple light-emitting elements LE of the first sub-pixel SPX1. The area of ​​the first light conversion layer QDL1 can be larger than the sum of the areas of the first pixel electrode PXE1 and the first common electrode CE1. The first light conversion layer QDL1 can convert or shift the peak wavelength of the incident light to light with another specific peak wavelength and emit it. For example, the first light conversion layer QDL1 can convert or shift the third light emitted from the multiple light-emitting elements LE of the first sub-pixel SPX1 into the first light.

[0128] The second light conversion layer QDL2 can be completely stacked with the second pixel electrode PXE2 and multiple light-emitting elements LE of the second sub-pixel SPX2. The area of ​​the second light conversion layer QDL2 can be larger than the sum of the areas of the second pixel electrode PXE2 and the second common electrode CE2. The second light conversion layer QDL2 can convert or shift the peak wavelength of the incident light to another specific peak wavelength and emit it. For example, the second light conversion layer QDL2 can convert or shift the third light emitted from the multiple light-emitting elements LE of the second sub-pixel SPX2 into a second light.

[0129] The light-transmitting layer TPL can be completely stacked with the third pixel electrode PXE3 and multiple light-emitting elements LE of the third sub-pixel SPX3. The area of ​​the light-transmitting layer TPL can be larger than the sum of the areas of the third pixel electrode PXE3 and the third common electrode CE3. For example, the light-transmitting layer TPL can directly transmit the third light emitted from the multiple light-emitting elements LE of the third sub-pixel SPX3.

[0130] Figure 6 It shows a display panel and Figure 5 The sectional view of the example section corresponding to line I1-I1' in the diagram. Figure 7 It is shown in detail Figure 6 A cross-sectional view of an example of region A. Figure 8 It is shown in detail Figure 7 A plan view of the light-emitting element. Figure 9 and Figure 10 It is a plan view showing details of a light-emitting element according to one or more other embodiments.

[0131] Reference Figure 6 and Figure 7 The substrate SUB can be made of insulating materials such as glass or polymer resin. If the substrate SUB is made of polymer resin, it can be a flexible substrate that can be stretched. Polymer resins can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0132] The barrier film BR can be disposed on the substrate SUB. The barrier film BR is a membrane that protects the transistors in the thin-film transistor layer (TFTL) and the light-emitting elements (LEs) disposed on the TFTL from the effects of moisture that permeates through the substrate SUB (which is susceptible to moisture penetration). The barrier film BR can be composed of multiple inorganic films stacked alternately.

[0133] The thin-film transistor TFT1 can be disposed on the barrier film BR. The thin-film transistor TFT1 can be... Figure 4 Either the fourth transistor ST4 or the sixth transistor ST6 shown. The thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0134] The first active layer ACT1 of the thin-film transistor TFT1 can be disposed on the barrier film BR. The first active layer ACT1 of the thin-film transistor TFT1 may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, and / or amorphous silicon. Optionally, the first active layer ACT1 of the thin-film transistor TFT1 may include an oxide semiconductor, including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0135] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region on the third direction DR3, which is the thickness direction of the substrate SUB, that is stacked with the first gate electrode G1. The first source region S1 may be located on one side of the first channel region CHA1, and the first drain region D1 may be located on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third direction DR3 that are not stacked with the first gate electrode G1. The first source region S1 and the first drain region D1 may be conductive regions in which the semiconductor material is doped with ions.

[0136] The first gate insulating film 131 can be disposed on the first channel region CHA1, the first source region S1, the first drain region D1, and the blocking film BR of the thin film transistor TFT1.

[0137] A first gate metal layer may be disposed on a first gate insulating film 131. The first gate metal layer may include a first gate electrode G1 and a first capacitor electrode CAE1 of a thin-film transistor TFT1. The first gate electrode G1 may be stacked on a third-direction DR3 with a first active layer ACT1. Figure 6 In the diagram, the first gate electrode G1 and the first capacitor electrode CAE1 are shown spaced apart from each other, but when the thin-film transistor TFT1 is... Figure 4 When the driving transistor DT is used, the first gate electrode G1 and the first capacitor electrode CAE1 can be electrically or physically connected to each other. Optionally, in another embodiment, the first gate electrode G1 and the first capacitor electrode CAE1 may not be electrically or physically connected to each other. Optionally, when the thin-film transistor TFT1 is Figure 4 When one of the first transistor ST1 to the sixth transistor ST6 is used, the first gate electrode G1 and the first capacitor electrode CAE1 may not be electrically or physically connected to each other.

[0138] The second gate insulating film 132 can be disposed on the first gate electrode G1, the first capacitor electrode CAE1 and the first gate insulating film 131 of the thin film transistor TFT1.

[0139] A second gate metal layer can be disposed on the second gate insulating film 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may be stacked with the first capacitor electrode CAE1 on the third-direction DR3. Because the second gate insulating film 132 has a suitable dielectric constant (e.g., a predetermined dielectric constant), the capacitor ( Figure 4 C1 in the figure can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2 and a second gate insulating film 132 disposed between them.

[0140] The first interlayer insulating film 141 can be disposed on the second capacitor electrode CAE2 and the second gate insulating film 132.

[0141] A first data metal layer may be disposed on a first interlayer insulating film 141. The first data metal layer may include a first source connection electrode PCE1. The first source connection electrode PCE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating film 131, the second gate insulating film 132 and the first interlayer insulating film 141.

[0142] The first planarization film 160 can be disposed on the first source connection electrode PCE1 and the first interlayer insulating film 141 to planarize the steps caused by the thin film transistor TFT1.

[0143] A second data metal layer may be disposed on the first planarization film 160. The second data metal layer may include a second source connection electrode PCE2. The second source connection electrode PCE2 may be connected to the first source connection electrode PCE1 through a second source contact hole PCT2 penetrating the first planarization film 160.

[0144] The second planarization film 180 can be disposed on the second source connection electrode PCE2 and the first planarization film 160.

[0145] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, and the first interlayer insulating film 141 can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x Inorganic membrane formation.

[0146] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof.

[0147] The first planarization film 160 and the second planarization film 180 can be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0148] The light-emitting element layer can be disposed on the second planarization film 180. The light-emitting element layer may include pixel electrodes PXE1, PXE2, PXE3, light-emitting element LE, common electrode CE (CE1, CE2, CE3), and organic films 210, 211, and 212.

[0149] A pixel electrode layer can be disposed on the second planarization film 180. The pixel electrode layer may include pixel electrodes PXE1, PXE2, and PXE3, and common electrodes CE1, CE2, and CE3. Each of the pixel electrodes PXE1, PXE2, and PXE3 can be disposed through a pixel connection hole penetrating the second planarization film 180. Figure 5 The pixel electrodes PXE1, PXE2, and PXE3 are connected to the second source connection electrode PCE2. Each of the pixel electrodes PXE1, PXE2, and PXE3 can be connected to the first source region S1 or the first drain region D1 of the thin-film transistor TFT1 via the first source connection electrode PCE1 and the second source connection electrode PCE2. Therefore, a voltage controlled by the thin-film transistor TFT1 can be applied to each of the pixel electrodes PXE1, PXE2, and PXE3.

[0150] The pixel electrode layer can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof. For example, the pixel electrode layer can be made of copper (Cu) with low sheet resistance to reduce the resistance of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0151] The first organic film 210 can be disposed on each of the pixel electrodes PXE1, PXE2, and PXE3 and the second planarization film 180. The first organic film 210 is used to temporarily fix or adhere multiple light-emitting elements LE to prevent the multiple light-emitting elements LE from tipping over or falling off during the process of transferring the multiple light-emitting elements LE to the display panel 100. That is, the first organic film 210 can be a film used to temporarily adhere multiple light-emitting elements LE to each of the pixel electrodes PXE1, PXE2, and PXE3. To facilitate temporary adhesion, the thickness of the first organic film 210 can be greater than the thickness of each of the pixel electrodes PXE1, PXE2, and PXE3 and greater than the thickness of the contact electrodes CTE (CTE1, CTE2).

[0152] The first organic film 210 may be a photosensitive organic layer such as a photoresist. Optionally, the first organic film 210 may be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0153] Multiple light-emitting elements LE can be disposed on the first organic film 210. Figure 6 The diagram shows that each of the multiple light-emitting elements (LEs) is a flip-chip microLED.

[0154] A flip-chip microLED refers to an LED in which contact electrodes CTE1 and CTE2 are formed on at least one side (e.g., the bottom side) of the light-emitting element LE.

[0155] The semiconductor stack STC of the light-emitting element LE may include a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a third semiconductor layer SEM3.

[0156] Each of the multiple light-emitting elements (LEs) can be formed from an inorganic material such as gallium nitride (GaN). Each of the multiple light-emitting elements (LEs) can have a length of several μm to several hundred μm in a first direction DR1, a length in a second direction DR2, and a length in a third direction DR3, respectively.

[0157] Each of the plurality of light-emitting elements (LEs) can be formed by growth on a semiconductor substrate such as a silicon substrate and / or a sapphire substrate. The plurality of light-emitting elements (LEs) can be directly transferred from the semiconductor substrate to the pixel electrodes PXE1, PXE2, and PXE3 and the common electrodes CE1, CE2, and CE3 of the display panel 100. Alternatively, the plurality of light-emitting elements (LEs) can be transferred to the pixel electrodes PXE1, PXE2, and PXE3 and the common electrodes CE1, CE2, and CE3 of the display panel 100 by an electrostatic method using an electrostatic head and / or by an imprinting method using an elastic polymeric material such as PDMS or silicone resin as a transfer substrate.

[0158] The light-emitting element LE may include a conductive layer E1, a semiconductor stack STC, contact electrodes CTE1 and CTE2, a first reflective layer RF1, and a protective film INS.

[0159] The conductive layer E1 can be disposed on the lower surface of the first semiconductor layer SEM1. Although Figure 7 The diagram shows a conductive layer E1 covering the entire lower surface of the first semiconductor layer SEM1, but this disclosure is not limited thereto. In one example, the conductive layer E1 may be disposed on a portion of the lower surface of the first semiconductor layer SEM1. The conductive layer E1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0160] The semiconductor stack STC may include a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a third semiconductor layer SEM3 arranged sequentially along the third direction DR3.

[0161] The first semiconductor layer SEM1 can be disposed on the conductive layer E1. The length of the bottom surface of the first semiconductor layer SEM1 in the first direction DR1 and / or the length in the second direction DR2 can be less than the length of the contact electrode CTE in the first direction DR1 and / or the length in the second direction DR2. The first semiconductor layer SEM1 may include a semiconductor material layer doped with a first conductive dopant (such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc.), such as gallium nitride (GaN).

[0162] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW may include the same semiconductor material layer as the first semiconductor layer SEM1 and the second semiconductor layer SEM2. For example, when the first semiconductor layer SEM1 and the second semiconductor layer SEM2 include gallium nitride (GaN), the active layer MQW may also include gallium nitride (GaN). For example, the active layer MQW may include gallium nitride (GaN), indium gallium nitride (InGaN), and / or aluminum gallium nitride (AlGaN). The active layer MQW can emit light by causing electron-hole pair recombination according to the electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0163] The active layer MQW can include materials having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material with a multiple quantum well structure, it can have a structure in which multiple well layers and blocking layers are stacked alternately. In this case, the well layers can be formed of InGaN, and the blocking layers can be formed of GaN and / or AlGaN, but are not limited thereto. Optionally, the active layer MQW can have a structure in which semiconductor materials with high band gaps and semiconductor materials with low band gaps are stacked alternately, and can include other group III to group V semiconductor materials depending on the wavelength range of the emitted light.

[0164] When the active layer MQW includes InGaN, the color of the emitted light can vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength of the light emitted by the active layer MQW can shift towards the red band, and as the indium (In) content decreases, the wavelength of the light emitted by the active layer MQW can shift towards the blue band. For example, the indium (In) content in the active layer MQW of a light-emitting element LE that emits a third light (e.g., light in the blue band) can be approximately 10 wt% to 20 wt%.

[0165] The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be a semiconductor material layer doped with a second conductivity type dopant (such as silicon (Si), germanium (Ge), tin (Sn), etc.), for example, gallium nitride (GaN).

[0166] The third semiconductor layer SEM3 can be disposed on the second semiconductor layer SEM2.

[0167] The third semiconductor layer SEM3 can be a semiconductor material layer in which the amount of n-type dopant is below a suitable threshold (e.g., a predetermined threshold), and can be referred to as an undoped semiconductor layer. For example, the third semiconductor layer SEM3 can be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN) in which the amount of n-type dopant is below a suitable threshold (e.g., a predetermined threshold).

[0168] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer used to suppress or prevent excessive electron inflow into the active layer MQW. For example, the electron blocking layer can be AlGaN and / or p-AlGaN doped with p-type Mg. The electron blocking layer can be omitted.

[0169] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be a layer used to alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be formed of InGaN and / or GaN. The superlattice layer can be omitted.

[0170] The protective film INS can be disposed on the side surface (e.g., outer peripheral surface) of the conductive layer E1, the side surface (e.g., outer peripheral surface) of the first semiconductor layer SEM1, the side surface (e.g., outer peripheral surface) of the active layer MQW, the side surface (e.g., outer peripheral surface) of the second semiconductor layer SEM2, and the side surface (e.g., outer peripheral surface) of the third semiconductor layer SEM3. The protective film INS can be a film used to protect the side surfaces of the light-emitting element LE. The protective film INS can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x Inorganic membrane formation.

[0171] exist Figure 7 In this embodiment, the protective film INS is disposed on the side surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 of the semiconductor stack STC, but this disclosure is not limited thereto. In one example, the protective film INS is disposed on the side surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2, but not on the side surface of the third semiconductor layer SEM3 of the semiconductor stack STC.

[0172] A hole LEH can be formed through the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW of the light-emitting element LE, exposing the second semiconductor layer SEM2. The hole LEH can have a circular planar shape, but this disclosure is not limited thereto. For example, the hole LEH can have a polygonal planar shape such as a rectangle or an elliptical planar shape.

[0173] Furthermore, the protective film INS can be disposed on the sidewalls of the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW exposed in the LEH. The protective film INS can be disposed without covering the second semiconductor layer SEM2 in the LEH. Therefore, the second semiconductor layer SEM2 can be exposed without being covered by the protective film INS.

[0174] The first reflective layer RF1 can be disposed on the protective layer (i.e., protective film) INS, and can be disposed on one side of the conductive layer E1 around the side surface of the conductive layer E1 and the side surface of the semiconductor stack STC.

[0175] The first reflective layer RF1 may extend from the side of the semiconductor stack STC on the protective layer INS and may protrude outward from the top surface of the semiconductor stack STC. The protrusion direction may be perpendicular to the direction of the extending surface. For example, the first reflective layer RF1 may protrude outward in a direction perpendicular to the side surface of the light-emitting element LE.

[0176] The first reflective layer RF1 can be set such that its height is less than the thickness of the protective layer INS. The first reflective layer RF1 can protrude slightly beyond the protective layer INS. One end of the first reflective layer RF1 can be located inside the protective layer INS. For example, when viewed from the top of the light-emitting element LE, the width W of the first reflective layer RF1... RF1 It can be wider than the protective layer INS by W. INS narrow.

[0177] The first reflective layer RF1 may have a region spaced apart (e.g., separated) from the first contact electrode CTE1 and the second contact electrode CTE2. For example, the first reflective layer RF1 may include a 1-1 reflective layer RF1-1 in contact with the first contact electrode CTE1 and a 1-2 reflective layer RF1-2 in contact with the second contact electrode CTE2. One end of the 1-1 reflective layer RF1-1 and one end of the 1-2 reflective layer RF1-2 are disposed on a surface of the light-emitting element LE, and one end of the 1-1 reflective layer RF1-1 and one end of the 1-2 reflective layer RF1-2 are spaced apart (e.g., separated) from each other. For example, the 1-1 reflective layer RF1-1 and the 1-2 reflective layer RF1-2 are not electrically connected. The other ends of the 1-1 reflective layer RF1-1 and the 1-2 reflective layer RF1-2 protrude outward from the top surface of the light-emitting element LE.

[0178] In one embodiment, the 1-1 reflective layer RF1-1 may be disposed on the conductive layer E1 exposed through the first opening OP1 of the protective layer INS. The 1-1 reflective layer RF1-1 is electrically connected to the conductive layer E1.

[0179] The 1-2 reflective layer RF1-2 can be disposed on the second semiconductor layer SEM2 exposed in the aperture LEH, and can extend to the side of the aperture LEH. The 1-2 reflective layer RF1-2 is electrically connected to the second semiconductor layer SEM2 through the aperture LEH.

[0180] In one or more embodiments, the first reflective layer RF1 may comprise a conductive metallic material having high light reflectivity (e.g., reflectivity greater than 90%). The first reflective layer RF1 may comprise, for example, aluminum (Al), chromium (Cr), and / or silver (Ag), and / or alloys thereof, and may comprise a single layer or multiple layers thereof. Multiple layers may be, for example, two layers of titanium / copper, two layers of titanium / aluminum, two layers of nickel / aluminum, two layers of silver / aluminum-silicon alloy, etc. The first reflective layer RF1 allows light emitted from the light-emitting element LE to be directed to the top.

[0181] The first contact electrode CTE1 can be disposed on the pixel electrode PXE of each sub-pixel SPX. For example, the first contact electrode CTE1 can be disposed between the pixel electrode PXE of each sub-pixel SPX and the light-emitting element LE.

[0182] A first contact electrode CTE1 is disposed on a first reflective layer RF1 to follow the first reflective layer RF1, for example, a 1-1 reflective layer RF1-1. One end of the first contact electrode CTE1 is disposed on a surface of the semiconductor stack STC and is electrically connected to the conductive layer E1 through the 1-1 reflective layer RF1-1 on the first opening OP1. One end of the first contact electrode CTE1 extends along the side surface of the semiconductor stack STC, while the other end of the first contact electrode CTE1 protrudes outward from the top surface of the semiconductor stack STC. The protrusion direction can be perpendicular to the extension direction. For example, the first contact electrode CTE1 can protrude in an outward direction perpendicular to the side surface of the semiconductor stack STC. For ease of explanation, the protruding portion of the first contact electrode CTE1 in the outward direction perpendicular to the side surface of the semiconductor stack STC can be referred to as a protrusion.

[0183] The other end of the first contact electrode CTE1 can be configured to be lower than the height of the 1-1 reflective layer RF1-1 by the thickness of the 1-1 reflective layer RF1-1. The first contact electrode CTE1 can protrude further than the 1-1 reflective layer RF1-1. For example, the protrusion length of the 1-1 reflective layer RF1-1 can be from about 0.6 μm to 2.4 μm, and the protrusion length of the first contact electrode CTE1 can be from about 1.2 μm to 4.8 μm.

[0184] The other end of the first contact electrode CTE1 may protrude further outward than the other end of the 1-1 reflective layer RF1-1. For example, the other end of the first contact electrode CTE1 may be aligned with the other end of the protective layer INS. The other end of the first contact electrode CTE1 may be arranged around the other end of the 1-1 reflective layer RF1-1 (e.g., surrounding the other end of the 1-1 reflective layer RF1-1). The other end of the 1-1 reflective layer RF1-1 may be completely surrounded by the first contact electrode CTE1 and the protective layer INS.

[0185] The first contact electrode CTE1 can electrically connect the conductive layer E1 and the first semiconductor layer SEM1 of the light-emitting element LE to the pixel electrode PXE of each sub-pixel SPX via the first connection electrode BE1, which will be described later.

[0186] The first contact electrode CTE1 may include a first tip T-1. The first tip T-1 may be integral with the first contact electrode CTE1. The first tip T-1 may extend in the protruding direction of the protrusion of the first contact electrode CTE1 and may be disposed on the first surface of the first contact electrode CTE1. The width of the first tip T-1 may be smaller than the width of the semiconductor stack STC.

[0187] The second contact electrode CTE2 can be disposed on the common electrode CE of each sub-pixel SPX. For example, the second contact electrode CTE2 can be disposed between the common electrode CE of each sub-pixel SPX and the light-emitting element LE. The second contact electrode CTE2 is disposed on the first reflective layer RF1 to follow the first reflective layer RF1, for example, 1-2 reflective layers RF1-2. One end of the second contact electrode CTE2 can be disposed on one side of the semiconductor stack STC and extend to the side of the aperture LEH. The second contact electrode CTE2 is electrically connected to the second semiconductor layer SEM2 through the 1-2 reflective layers RF1-2 in the aperture LEH. One end of the second contact electrode CTE2 extends along the side of the semiconductor stack STC, while the other end of the second contact electrode CTE2 protrudes outward from the top surface of the semiconductor stack STC. The protrusion direction can be perpendicular to the direction of the extending surface. For example, the second contact electrode CTE2 can protrude in an outward direction perpendicular to the side surface of the semiconductor stack STC. For ease of explanation, the protruding portion of the second contact electrode CTE2 in the outward direction perpendicular to the side surface of the semiconductor stack STC can be referred to as a protrusion.

[0188] Furthermore, one end of the first contact electrode CTE1 and one end of the second contact electrode CTE2 can be configured to be spaced apart from each other (e.g., separated). The first contact electrode CTE1 and the second contact electrode CTE2 are not electrically connected.

[0189] The other end of the second contact electrode CTE2 can be configured to be lower than the height of the 1-2 reflective layer RF1-2 by the thickness of the 1-2 reflective layer RF1-2. The second contact electrode CTE2 can protrude further than the 1-2 reflective layer RF1-2. The protrusion length of the 1-2 reflective layer RF1-2 can be from approximately 0.6 μm to 2.4 μm, and the protrusion length of the second contact electrode CTE2 can be from approximately 1.2 μm to 4.8 μm.

[0190] The other end of the second contact electrode CTE2 may protrude outward from the other end of the 1-2 reflective layer RF1-2. For example, the other end of the second contact electrode CTE2 may be aligned with the other end of the protective layer INS. The other end of the second contact electrode CTE2 may be arranged around (e.g., around) the other end of the 1-2 reflective layer RF1-2. The other end of the 1-2 reflective layer RF1-2 may be completely surrounded by the second contact electrode CTE2 and the protective layer INS.

[0191] The second contact electrode CTE2 can electrically connect the second semiconductor layer SEM2 of the light-emitting element LE to the common electrode CE of each sub-pixel SPX via the second connection electrode BE2, which will be described later.

[0192] The second contact electrode CTE2 may include a second tip T-2. The second tip T-2 may be integral with the second contact electrode CTE2. The second tip T-2 may extend in the protruding direction of the protrusion of the second contact electrode CTE2 and may be disposed on the first surface of the second contact electrode CTE2.

[0193] Reference Figure 8 The long side L of the semiconductor stack STC STC _ L The length is approximately 25 μm and the short side L of the semiconductor stack STC STC-S The length is approximately 10 μm, and the long side L of the first contact electrode CTE1 CTE1 The length of _2 can be approximately 13 μm to 17 μm, and the short side L of the first contact electrode CTE1 CTE1 The length of _1 can be approximately 13 μm to 15 μm. The spacing d1 between the first contact electrode CTE1 and the second contact electrode CTE2 can be approximately 6 μm.

[0194] Reference Figure 8 and Figure 9 The second tip T-2 and the first tip T-1 can be set as a straight line on a plane. The second tip T-2 and the first tip T-1 can be set on a straight line parallel to the long side of the light-emitting element LE.

[0195] Reference Figure 8 The widths of the first tip T-1 and the second tip T-2 can be smaller than the width of the semiconductor stack STC. Furthermore, the first tip T-1 and the second tip T-2 can have irregular single-sided surfaces. Additionally, refer to... Figure 9 The first tip T-1 and the second tip T-2 can have the same characteristics as... Figure 8 Compared to a smooth end surface.

[0196] In addition, refer to Figure 10 The width of the first tip T-1 and the second tip T-2 can be greater than the width of the semiconductor stack STC.

[0197] The first contact electrode CTE1 and the second contact electrode CTE2 may comprise a metal, metal oxide, and / or other conductive material having a higher conductivity than the first reflective layer RF1. For example, the first contact electrode CTE1 and the second contact electrode CTE2 may comprise gold (Au), copper (Cu), and / or chromium (Cr).

[0198] Although Figure 6 and Figure 7The illustration shows a first contact electrode CTE1 and a second contact electrode CTE2 disposed on a first organic film 210 for each of the light-emitting elements LE, but the present disclosure is not limited thereto. For example, the first organic film 210 may be disposed on a portion of the bottom surface and side surface of the first contact electrode CTE1 and a portion of the bottom surface and side surface of the second contact electrode CTE2 in each of the light-emitting elements LE. Optionally, the first organic film 210 may be disposed on a side surface of the conductive layer E1 of each light-emitting element LE. Optionally, the first organic film 210 may be disposed on a side surface of the first semiconductor layer SEM1, a side surface of the active layer MQW, and a side surface of the second semiconductor layer SEM2 in each of the light-emitting elements LE. In this case, the first organic film 210 may be disposed on a portion of each side of the second semiconductor layer SEM2.

[0199] Each of the first contact electrode CTE1 and the second contact electrode CTE2 can be disposed on three sides of the semiconductor stack STC. For example, when the semiconductor stack STC includes a first side to a fourth side, the first contact electrode CTE1 can be disposed on the first side, the second side, and the third side, and the second contact electrode CTE2 can be disposed on the second side, the third side, and the fourth side. However, in one or more embodiments, each of the first contact electrode CTE1 and the second contact electrode CTE2 can be disposed on both sides of the semiconductor stack STC (e.g., Figure 7 ).

[0200] Contact electrode CTE may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu).

[0201] The first connecting electrode BE1 connects the first contact electrode CTE1 of the light-emitting element LE to the pixel electrodes PXE1, PXE2, and PXE3. The first connecting electrode BE1 can be connected to the exposed pixel electrodes PXE1, PXE2, and PXE3 through the first connecting hole BH1 penetrating the first organic film 210. Furthermore, the first connecting electrode BE1 can be disposed on the top surface of the first organic film 210 and on the first contact electrode CTE1.

[0202] The second connecting electrode BE2 connects the second contact electrode CTE2 of the light-emitting element LE to the common electrodes CE1, CE2, and CE3. The second connecting electrode BE2 can be connected to the exposed common electrodes CE1, CE2, and CE3 through the second connecting hole BH2 penetrating the first organic film 210. Furthermore, the second connecting electrode BE2 can be disposed on the top surface of the first organic film 210 and on the second contact electrode CTE2.

[0203] The first connecting electrode BE1 and the second connecting electrode BE2 may comprise molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Optionally, each of the first connecting electrode BE1 and the second connecting electrode BE2 may be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0204] like Figure 6 and Figure 7 As shown, the conductive layer E1 of the light-emitting element LE can be connected to the pixel electrodes PXE1, PXE2, and PXE3 via the first reflective layer RF1, the first contact electrode CTE1, and the first connection electrode BE1. Furthermore, the second semiconductor layer SEM2 of the light-emitting element LE can be connected to the common electrodes CE1, CE2, and CE3 via the first reflective layer RF1 and the second contact electrode CTE2 formed in the hole LEH, and the second connection electrode BE2.

[0205] Return to reference Figure 6 and Figure 7 The third organic film 211 may partially cover the side surface of the light-emitting element LE. In addition, the third organic film 211 may cover the connecting electrodes BE (BE1, BE2), but at least a portion of each of the connecting electrodes BE (BE1, BE2) may be exposed and not covered by the third organic film 211.

[0206] A fourth organic film 212 may be disposed on the third organic film 211. The fourth organic film 212 may partially cover the side surface of each of the light-emitting elements LE. The fourth organic film 212 may be disposed on at least a portion of each of the connecting electrodes BE (BE1, BE2) that is exposed and not covered by the third organic film 211. The upper surface of each of the light-emitting elements LE may be exposed and not covered by the fourth organic film 212.

[0207] The third organic membrane 211 and the fourth organic membrane 212 may be made of organic layers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0208] The third organic film 211 and the fourth organic film 212 are layers used to flatten the steps caused by the light-emitting element LE. If the third organic film 211 is high enough to cover most of the side surface of each of the light-emitting elements LE, the fourth organic film 212 can be omitted.

[0209] The first capping layer CAP1 can be disposed on the upper surface of each of the light-emitting elements LE and on the upper surface of the fourth organic film 212. The first capping layer CAP1 can be a common layer formed in the first sub-pixel SPX1, the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0210] The light-blocking layers BM (BM1, BM2), the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be disposed on the first capping layer CAP1. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be separated and / or divided by the light-blocking layer BM. Therefore, the first light conversion layer QDL1 can be disposed on the first capping layer CAP1 in the first sub-pixel SPX1, the second light conversion layer QDL2 can be disposed on the first capping layer CAP1 in the second sub-pixel SPX2, and the light transmission layer TPL can be disposed on the first capping layer CAP1 in the third sub-pixel SPX3. The light-blocking layer BM can be stacked on the third-direction DR3 with the third organic film 211 and the fourth organic film 212, and can be disposed without being stacked with the light-emitting element LE.

[0211] The first light conversion layer QDL1 can convert a portion of the third-color light (e.g., light in the blue band) incident from the light-emitting element LE into first-color light (e.g., light in the red band). The first light conversion layer QDL1 may include a first matrix resin BRS1 and first wavelength conversion particles WCP1. The first matrix resin BRS1 may include a light-transmitting organic material. The first wavelength conversion particles WCP1 can convert a portion of the third-color light (e.g., light in the blue band) incident from the light-emitting element LE into first-color light (e.g., light in the red band).

[0212] The second light conversion layer QDL2 can convert a portion of the third-color light (e.g., light in the blue band) incident from the light-emitting element LE into second-color light (e.g., light in the green band). The second light conversion layer QDL2 may include a second matrix resin BRS2 and second wavelength conversion particles WCP2. The second matrix resin BRS2 may include a light-transmitting organic material. The second wavelength conversion particles WCP2 can convert a portion of the third-color light (e.g., light in the blue band) incident from the light-emitting element LE into second-color light (e.g., light in the green band).

[0213] The light-transmitting layer (TPL) can include light-transmitting organic materials.

[0214] For example, the first matrix resin BRS1, the second matrix resin BRS2, ​​and the light-transmitting layer TPL may include epoxy resin, acrylic resin, cardo resin, and / or imide resin. The first wavelength conversion particle WCP1 and the second wavelength conversion particle WCP2 may be quantum dots, quantum rods, fluorescent materials, and / or phosphorescent materials.

[0215] The light-blocking layer BM may include a first light-blocking layer BM1 and a second light-blocking layer BM2 stacked sequentially. The length of the first light-blocking layer BM1 in the first direction DR1 and / or the length of the first light-blocking layer BM1 in the second direction DR2 may be greater than the length of the second light-blocking layer BM2 in the first direction DR1 and / or the length of the second light-blocking layer BM2 in the second direction DR2. The first light-blocking layer BM1 and the second light-blocking layer BM2 may be made of organic layers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin. The first light-blocking layer BM1 and the second light-blocking layer BM2 may include a light-blocking material to prevent light from the light-emitting element LE of any sub-pixel from traveling to an adjacent sub-pixel. For example, the first light-blocking layer BM1 and the second light-blocking layer BM2 may include inorganic black pigments such as carbon black and / or organic black pigments.

[0216] The second capping layer CAP2 can be disposed on the first capping layer CAP1 and the light blocking layer BM. The second capping layer CAP2 can be disposed on the side surface and the top surface of the light blocking layer BM. For example, the second capping layer CAP2 can be disposed on the side surface of the first light blocking layer BM1, the side surface and the top surface of the second light blocking layer BM2, and on the first capping layer CAP1.

[0217] The second reflective layer RF2 can be disposed between the light-blocking layer BM and the first light conversion layer QDL1, between the light-blocking layer BM and the second light conversion layer QDL2, and between the light-blocking layer BM and the light-transmitting layer TPL. The second reflective layer RF2 can be disposed on the second capping layer CAP2 disposed on the side surfaces of the first light-blocking layer BM1 and the second light-blocking layer BM2. The second reflective layer RF2 can reflect light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0218] The second reflective layer RF2 may include a metallic material with high reflectivity, such as aluminum (Al). The thickness of the second reflective layer RF2 may be approximately 0.1 μm.

[0219] Optionally, for use as a distributed Bragg reflector, the second reflective layer RF2 may comprise M (M is an integer of 2 or greater) pairs of first and second layers with different refractive indices. In this case, the M first layers and M second layers may be arranged alternately. The first and second layers may be made of inorganic layers (e.g., silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide).

[0220] The third capping layer CAP3 can be disposed on the second reflective layer RF2, the second capping layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0221] The first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3 can be made of inorganic layers (e.g., silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer, and / or aluminum oxide layer). The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3.

[0222] The fifth organic membrane 213 can be disposed on the third capping layer CAP3. Multiple color filters CF1 to CF3 can be disposed on the fifth organic membrane 213. Color filters CF1 to CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0223] The first color filter CF1, disposed in the first sub-pixel SPX1, can transmit light of a first color (e.g., light in the red band) and absorb and / or block light of a third color (e.g., light in the blue band). Therefore, the first color filter CF1 can transmit light of the first color (e.g., light in the red band) from a portion of the third color light (e.g., light in the blue band) emitted from the light-emitting element LE, which has been converted by the first light conversion layer QDL1, and can absorb and / or block third color light (e.g., light in the blue band) that has not been converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can output light of the first color (e.g., light in the red band).

[0224] The second color filter CF2, disposed in the second sub-pixel SPX2, can transmit light of the second color (e.g., light in the green band) and absorb and / or block light of the third color (e.g., light in the blue band). Therefore, the second color filter CF2 can transmit light of the second color (e.g., light in the green band) from which a portion of the third color light (e.g., light in the blue band) emitted from the light-emitting element LE has been converted by the second light conversion layer QDL2, and can absorb or block third color light (e.g., light in the blue band) that has not been converted by the second light conversion layer QDL2. Therefore, the second sub-pixel SPX2 can output light of the second color (e.g., light in the green band).

[0225] A third color filter CF3 disposed in the third sub-pixel SPX3 can transmit light of a third color (e.g., light in the blue band). Therefore, the third color filter CF3 can transmit light of a third color (e.g., light in the blue band) that has passed through the light transmission layer TPL after being emitted from the light-emitting element LE. Therefore, the third sub-pixel SPX3 can emit light of a third color (e.g., light in the blue band).

[0226] The first color filter CF1, the second color filter CF2, and the third color filter CF3, which are superimposed on each other on the third-direction DR3, can be superimposed on the light blocking layer BM on the third-direction DR3.

[0227] The sixth organic membrane 214 for planarization can be placed on color filters CF1 to CF3.

[0228] The fifth organic membrane 213 and the sixth organic membrane 214 may be made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0229] Figure 11 It is a layout diagram showing the pixels of a display area according to one or more embodiments.

[0230] Figure 11 Implementation examples and Figure 5 The difference in the embodiment is that the light-emitting element LE in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is disposed on common electrodes CE1, CE2, and CE3 having substantially the same size as pixel electrodes PXE1, PXE2, and PXE3 having substantially the same size. Figure 11 In the embodiment, the omission and Figure 5 The embodiments are described repeatedly.

[0231] Reference Figure 11 The pixel electrodes PXE1, PXE2, and PXE3, and the common electrodes CE1, CE2, and CE3 in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along the second direction DR2. The first pixel electrode PXE1 and the first common electrode CE1 can be arranged spaced apart from each other (e.g., separated). The second pixel electrode PXE2 and the second common electrode CE2 can be arranged spaced apart from each other (e.g., separated). The third pixel electrode PXE3 and the third common electrode CE3 can be arranged spaced apart from each other (e.g., separated).

[0232] The first pixel electrode PXE1, the second pixel electrode PXE2, the third pixel electrode PXE3, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may each have a rectangular planar shape, but this disclosure is not limited thereto. Furthermore, the area of ​​the first pixel electrode PXE1 may be the same as the area of ​​the first common electrode CE1, the area of ​​the second pixel electrode PXE2 may be the same as the area of ​​the second common electrode CE2, and the area of ​​the third pixel electrode PXE3 may be the same as the area of ​​the third common electrode CE3, but this disclosure is not limited thereto.

[0233] The first common electrode CE1 can be connected to the second power line VSL, to which the second driving voltage VSS is applied, via the first common connection hole CT4. The second common electrode CE2 can be connected to the second power line VSL via the second common connection hole CT5. The third common electrode CE3 can be connected to the second power line VSL via the third common connection hole CT6. Therefore, the second driving voltage VSS can be applied to each of the common electrodes CE1, CE2, and CE3.

[0234] The first connecting electrode BE1 is connected to the conductive layer E1 of the light-emitting element LE and the pixel electrodes PXE1, PXE2, and PXE3. The first connecting electrode BE1 may be stacked with a first opening OP1 that exposes the conductive layer E1. The first connecting electrode BE1 may be stacked with at least a portion of the pixel electrodes PXE1, PXE2, and PXE3.

[0235] The second connecting electrode BE2 can be connected to the second semiconductor layer SEM2 of the light-emitting element LE and the common electrodes CE1, CE2 and CE3. The second connecting electrode BE2 can be stacked with the via LEH that exposes the second semiconductor layer SEM2. The second connecting electrode BE2 can be stacked with at least a portion of the common electrodes CE1, CE2 and CE3.

[0236] Each of the second power lines VSL may include a line portion WP extending in the first direction DR1 and a protrusion PP protruding from the line portion WP in the second direction DR2, the protrusion PP being stacked with common connection holes CT4, CT5, CT6.

[0237] Figure 12 It shows the display panel and Figure 11 A sectional view of an example of the sections corresponding to lines I1-I1', I2-I2', and I3-I3'. Figure 13 It is shown in detail Figure 12 A cross-sectional view of an example of region B in the diagram.

[0238] Figure 12 and Figure 13 Implementation examples and Figure 6 and Figure 7 The difference in this embodiment is that the light-emitting element LE is a lateral micro-LED. Figure 12 and Figure 13 In the embodiment, the omission and Figure 6 and Figure 7 The description of the embodiments is repeated.

[0239] Reference Figure 12 and Figure 13The light-emitting element LE can be disposed on the first organic film 210 in each of the sub-pixels SPX1, SPX2, and SPX3. The light-emitting element LE is illustrated as a lateral micro-LED that allows current to flow in the lateral direction.

[0240] The light-emitting element LE may include a conductive layer E1, a semiconductor stack STC, contact electrodes CTE1 and CTE2, a first reflective layer RF1, and a protective film INS.

[0241] Although Figure 13 A protective film INS is shown disposed on the side surfaces of the conductive layer E1, the first semiconductor layer SEM1 of the semiconductor stack STC, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3, but this disclosure is not limited thereto. In one example, the protective film may be disposed on the side surfaces of the conductive layer E1, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2, but not on the side surface of the third semiconductor layer SEM3 of the semiconductor stack STC.

[0242] A via LEH can be formed through the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW of the light-emitting element LE to expose the second semiconductor layer SEM2. The via LEH can have a circular planar shape, but this disclosure is not limited thereto. For example, the via LEH can have a polygonal planar shape such as a rectangle or an elliptical planar shape.

[0243] Furthermore, the protective film INS can be disposed on the sidewalls of the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW exposed in the LEH. The protective film INS can be disposed without covering the second semiconductor layer SEM2 in the LEH. Therefore, the second semiconductor layer SEM2 can be exposed without being covered by the protective film INS.

[0244] The first reflective layer RF1 can be disposed on the protective layer INS, and can be disposed on one side of the conductive layer E1 around the sides of the conductive layer E1 and the semiconductor stack STC (e.g., around the sides of the conductive layer E1 and the semiconductor stack STC).

[0245] The first reflective layer RF1 can extend from the side of the semiconductor stack STC on the protective layer INS and can protrude outward from one side of the semiconductor stack STC. The protruding direction can be perpendicular to the direction of the extending surface. For example, the first reflective layer RF1 can protrude outward in a direction perpendicular to the side surface of the light-emitting element LE.

[0246] The first reflective layer RF1 may protrude less than the protective layer INS. One end of the first reflective layer RF1 may be disposed inside the protective layer INS. For example, when viewed from the top of the light-emitting element LE, the width W of the first reflective layer RF1 is... RF1 (For example, see) Figure 7 It can be wider than the protective layer INS by W. INS (For example, see) Figure 7 )narrow.

[0247] The first reflective layer RF1 may have a region spaced apart (e.g., separated) from the first contact electrode CTE1 and the second contact electrode CTE2. For example, the first reflective layer RF1 may include a 1-1 reflective layer RF1-1 in contact with the first contact electrode CTE1 and a 1-2 reflective layer RF1-2 in contact with the second contact electrode CTE2. One end of the 1-1 reflective layer RF1-1 and one end of the 1-2 reflective layer RF1-2 are disposed on a first side of the light-emitting element LE, and one end of the 1-1 reflective layer RF1-1 and one end of the 1-2 reflective layer RF1-2 are spaced apart (e.g., separated) from each other. For example, the 1-1 reflective layer RF1-1 and the 1-2 reflective layer RF1-2 are not electrically connected. The other ends of the 1-1 reflective layer RF1-1 and the 1-2 reflective layer RF1-2 protrude outward from the surface of the light-emitting element LE.

[0248] In one or more embodiments, the 1-1 reflective layer RF1-1 may be disposed through the first opening OP1 of the protective layer INS (see Figure 7 The 1-1 reflective layer RF1-1 is electrically connected to the conductive layer E1 on the exposed conductive layer E1.

[0249] The 1-2 reflective layer RF1-2 can be disposed on the second semiconductor layer SEM2 exposed in the aperture LEH, and can extend to the side of the aperture LEH. The 1-2 reflective layer RF1-2 is electrically connected to the second semiconductor layer SEM2 through the aperture LEH.

[0250] In one or more embodiments, the first reflective layer RF1 may comprise a conductive and highly reflective metallic material (e.g., reflectivity greater than 90%). The first reflective layer RF1 may comprise, for example, aluminum (Al), chromium (Cr), and / or silver (Ag), and / or alloys thereof, and may comprise a single layer or multiple layers thereof. Multiple layers may be, for example, two layers of titanium / copper, two layers of titanium / aluminum, two layers of nickel / aluminum, two layers of silver / aluminum-silicon alloy, etc. The first reflective layer RF1 allows light emitted from the light-emitting element LE to be directed to the top.

[0251] The first contact electrode CTE1 can be disposed on at least one side of the semiconductor stack STC and on at least one side and top of the conductive layer E1. The first contact electrode CTE1 can be disposed on the exposed top surface of the conductive layer E1 that is not covered by the protective film INS. Therefore, the first contact electrode CTE1 can be electrically connected to the conductive layer E1 through the 1-1 reflective layer RF1-1.

[0252] The second contact electrode CTE2 can be disposed on at least one side of the semiconductor stack STC and on at least one side and top of the conductive layer E1. In this case, the first contact electrode CTE1 can be disposed on the first side of the semiconductor stack STC and the first side of the conductive layer E1, while the second contact electrode CTE2 can be disposed on the second side of the semiconductor stack STC and the second side of the conductive layer E1.

[0253] The second contact electrode CTE2 can be disposed on the protective film INS disposed in the aperture LEH and on the second semiconductor layer SEM2 exposed in the aperture LEH but not covered by the protective film INS. Therefore, the second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 in the aperture LEH through the 1-2 reflective layers RF1-2.

[0254] exist Figure 12 and Figure 13 In this embodiment, the third semiconductor layer SEM3 of each of the light-emitting elements LE is disposed on the first organic film 210, but this disclosure is not limited thereto. For example, the first organic film 210 may be disposed on a side surface of the third semiconductor layer SEM3 of each of the light-emitting elements LE. Optionally, the first organic film 210 may be disposed on a portion of each side of the second semiconductor layer SEM2 of each of the light-emitting elements LE.

[0255] Each of the first contact electrode CTE1 and the second contact electrode CTE2 may be disposed on three sides of the semiconductor stack STC. For example, when the semiconductor stack STC includes a first side to a fourth side, the first contact electrode CTE1 may be disposed on the first side, the second side, and the third side, and the second contact electrode CTE2 may be disposed on the second side, the third side, and the fourth side. However, in one or more embodiments, each of the first contact electrode CTE1 and the second contact electrode CTE2 may be disposed on both sides of the semiconductor stack STC.

[0256] The first contact electrode CTE1 may include a first tip T-1 (e.g., see...) Figure 7 First tip T-1 (e.g., see...) Figure 7The first tip T-1 can be integrated with the first contact electrode CTE1. The first tip T-1 can extend in the protruding direction of the protrusion of the first contact electrode CTE1 and can be disposed on the first surface of the first contact electrode CTE1. The width of the first tip T-1 can be smaller than the width of the semiconductor stack STC.

[0257] The second contact electrode CTE2 may include a second tip T-2. The second tip T-2 may be integral with the second contact electrode CTE2. The second tip T-2 may extend in the protruding direction of the protrusion of the second contact electrode CTE2 and may be disposed on the first surface of the second contact electrode CTE2.

[0258] The first connecting electrode BE1 connects the first contact electrode CTE1 of the light-emitting element LE and the pixel electrodes PXE1, PXE2, and PXE3. The first connecting electrode BE1 can be connected to the exposed pixel electrodes PXE1, PXE2, and PXE3 through the first connecting hole BH1 penetrating the first organic film 210. Furthermore, the first connecting electrode BE1 can be disposed on the top surface of the first organic film 210, on the side surface of the second semiconductor layer SEM2, on the side surface of the third semiconductor layer SEM3, on the side surface of the active layer MQW, and on the protective film INS, as well as on the first contact electrode CTE1.

[0259] The second connecting electrode BE2 connects the second contact electrode CTE2 of the light-emitting element LE to the common electrodes CE1, CE2, and CE3. The second connecting electrode BE2 can be connected to the exposed common electrodes CE1, CE2, and CE3 through the second connecting hole BH2 penetrating the first organic film 210. Furthermore, the second connecting electrode BE2 can be disposed on the top surface of the first organic film 210, on the side surface of the second semiconductor layer SEM2, on the side surface of the third semiconductor layer SEM3, on the side surface of the active layer MQW, and on the second contact electrode CTE2.

[0260] Each of the first connecting electrode BE1 and the second connecting electrode BE2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Optionally, each of the first connecting electrode BE1 and the second connecting electrode BE2 may be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0261] like Figure 12 and Figure 13As shown, the conductive layer E1 of the light-emitting element LE can be connected to the pixel electrodes PXE1, PXE2, and PXE3 via the first reflective layer RF1, the first contact electrode CTE1, and the first connection electrode BE1. Furthermore, the second semiconductor layer SEM2 of the light-emitting element LE can be connected to the common electrodes CE1, CE2, and CE3 via the first reflective layer RF1 and the second contact electrode CTE2 formed in the hole LEH, and the second connection electrode BE2.

[0262] Figure 14 This is a layout diagram showing the light-emitting elements and lead pads on a wafer according to one or more embodiments. Figure 15 It is shown in detail Figure 14 A layout diagram of an example of region C in the diagram.

[0263] Reference Figure 14 and Figure 15 The wafer EWF may include a wafer substrate (WAF), multiple light-emitting elements (LEs) disposed on the wafer substrate (WAF), multiple lead pads (FPDs), and multiple connectors (CNTs).

[0264] A wafer substrate (WAF) can be a semiconductor substrate suitable for the epitaxial growth of semiconductors. For example, a wafer substrate (WAF) can be a substrate containing materials such as silicon (Si), sapphire, SiC, GaN, GaAs, and / or ZnO. The type, material, and shape of the wafer substrate (WAF) are not particularly limited, as long as they can facilitate epitaxial growth to fabricate light-emitting elements (LEs).

[0265] The wafer substrate (WAF) may include at least one of a flat region (FZ) indicating the crystal orientation of the wafer and a notch.

[0266] A flat region (FZ) is a flat area on the crystal surface of a wafer. A notch is a triangular groove indicating the crystal orientation of a wafer. In another variation, alignment marks can be used instead of flat regions (FZ) or notches.

[0267] In one or more embodiments, the diameter of the wafer substrate WAF can be approximately 8 inches, 10 inches, or 12 inches. The wafer substrate WAF can be from a few micrometers (μm) to several hundred micrometers (μm) thick. Each length on the third-direction DR3 can be approximately 100 μm or less.

[0268] The light-emitting element (LE) can be placed on the wafer substrate (WAF).

[0269] Multiple light-emitting elements (LEs) can be arranged in a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 that intersects the first direction DR1.

[0270] The light-emitting elements LE can be arranged adjacent to each other along the first direction DR1.

[0271] Because the light-emitting element (LE) can correspond to a reference. Figure 7 The description focuses on the light-emitting element LE, so redundant descriptions will be omitted.

[0272] The lead pads (FPDs) can be arranged in a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The lead pads (FPDs) have a minimum size for electrical measurements. For example, the area of ​​each of the lead pads (FPDs) can be larger than the area of ​​the light-emitting element (LE).

[0273] The pin pads FPD can be arranged adjacent to each other along the first direction DR1.

[0274] The lead pad FPD and the light-emitting element LE can be arranged alternately along a second direction DR2 that intersects the first direction DR1. For example, the light-emitting element LE can be arranged adjacent to the lead pad FPD on the second direction DR2.

[0275] Each light-emitting element (LE) is connected in series with a lead pad (FPD) via a connector (CNT). The LEs can be electrically connected to adjacent lead pads (FPDs) on the second direction (DR2). Furthermore, LEs positioned on the second direction (DR2) can share adjacent lead pads (FPDs). For example, in the order on the second direction (DR2), a first lead pad (FPD1), a first light-emitting element (LE1), a second lead pad (FPD2), a second light-emitting element (LE2), and a third lead pad (FPD3) can be arranged.

[0276] The first light-emitting element LE1 can be connected to the first pin pad FPD1 via the first connector CNT1, and can be connected to the second pin pad FPD2 via the second connector CNT2. The second light-emitting element LE2 can be connected to the second pin pad FPD2 via the third connector CNT3, and can be connected to the third pin pad FPD3 via the fourth connector CNT4.

[0277] The first contact electrode CTE1 of the first light-emitting element LE1 can be connected to the first lead pad FPD1 via the first connector CNT1, and the second contact electrode CTE2 of the first light-emitting element LE1 can be connected to the second lead pad FPD2 via the second connector CNT2. The first contact electrode CTE1 of the second light-emitting element LE2 can be connected to the second lead pad FPD2 via the third connector CNT3, and the second contact electrode CTE2 of the second light-emitting element LE2 can be connected to the third lead pad FPD3 via the fourth connector CNT4. In this way, the second lead pad FPD2 can be connected to the adjacent first light-emitting element LE1 and second light-emitting element LE2.

[0278] Figure 16 It is shown in detail Figure 14 A plan view of a test block. Figure 17 It is shown in detail Figure 16 A cross-sectional view of the test block. Figure 17 It shows the relationship with Figure 16 The cross section corresponding to line I3-I3' in the middle.

[0279] Reference Figure 16 and Figure 17 The light-emitting element (LE) may include a conductive layer E1, a semiconductor stack STC, contact electrodes CTE1 and CTE2, a first reflective layer RF1, and a protective film INS. The semiconductor stack STC may include a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 sequentially disposed and / or stacked along a third direction DR3. The lead pad FPD may include a conductive layer E1, a semiconductor stack STC, a contact pad CPD, and a protective film INS.

[0280] The conductive layer E1 can be disposed on the semiconductor stack STC. Figure 17 In the illustration, conductive layer E1 is shown covering the entire upper side of the first semiconductor layer SEM1, but this disclosure is not limited thereto. In one example, conductive layer E1 may be disposed on a portion of the upper surface of the first semiconductor layer SEM1. Conductive layer E1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Furthermore, conductive layer E1 may be made of a transparent conductive material (TCO) that can transmit light (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)).

[0281] The semiconductor stack STC of the lead pad FPD can be formed in the same process as the semiconductor stack STC of the light-emitting element (LE). Therefore, the lead pad FPD can include a semiconductor stack STC having the same structure as the semiconductor stack STC of the light-emitting element (LE). For example, the semiconductor stack STC of the lead pad FPD can include a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 sequentially disposed and / or stacked along the third direction DR3.

[0282] The third semiconductor layer SEM3 is a semiconductor material layer in which the amount of n-type dopant is below a suitable threshold (e.g., a predetermined threshold), and may be referred to as an undoped semiconductor layer. For example, the third semiconductor layer SEM3 may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN) in which the amount of n-type dopant is below a suitable threshold (e.g., a predetermined threshold).

[0283] The second semiconductor layer SEM2 can be a semiconductor material layer doped with a second type of conductivity dopant (such as silicon (Si), germanium (Ge), tin (Sn), etc.), for example, gallium nitride (GaN).

[0284] The active layer MQW may include a layer of the same semiconductor material as the first semiconductor layer SEM1 and the second semiconductor layer SEM2. For example, when the first semiconductor layer SEM1 and the second semiconductor layer SEM2 include gallium nitride (GaN), the active layer MQW may also include gallium nitride (GaN). For example, the active layer MQW may include gallium nitride (GaN), indium gallium nitride (InGaN), and / or aluminum gallium nitride (AlGaN). The active layer MQW can emit light by causing electron-hole pair recombination based on an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0285] The length of the bottom surface of the first semiconductor layer SEM1 in the first direction DR1 and / or the length in the second direction DR2 may be less than the length of the contact electrode CTE in the first direction DR1 or the length in the second direction DR2. The first semiconductor layer SEM1 may include a semiconductor material layer doped with a first conductive dopant (such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc.), for example, gallium nitride (GaN).

[0286] The protective film INS can be disposed on the sides of the conductive layer E1, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. The protective film INS can extend from the protective film INS of the light-emitting element LE. The protective film INS can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x Inorganic membrane formation.

[0287] The contact pad CPD can be set on the protective film INS and can extend from either the first contact electrode CTE1 or the second contact electrode CTE2 of the light-emitting element LE.

[0288] The contact pad CPD can be formed in the same process as the first contact electrode CTE1 and the second contact electrode CTE2 of the light-emitting element LE.

[0289] The contact pad CPD may include a metal, metal oxide, and / or other conductive material having a higher conductivity than the first reflective layer RF1 of the light-emitting element LE. For example, the contact pad CPD may include gold (Au), copper (Cu), and / or chromium (Cr).

[0290] In this way, the lead pad FPD and the light-emitting element (LE) have the same height of semiconductor stack (STC) in the same process. Therefore, it facilitates contact between the test pin and the lead pad FPD during testing.

[0291] On the other hand, since the connector CNT does not have a semiconductor stack STC, it can be set to be lower than the height of the lead pad FPD and the light-emitting element LE.

[0292] like Figure 16 and Figure 17 As shown, a light-emitting element (LE) and two pin pads FPD1 and FPD2 connected to each contact electrode CTE1 and CTE2 of the LE can be referred to as a test block TB. Independent electrical tests can be performed on each test block TB. The first pin pad FPD1 and the second pin pad FPD2 connected to a light-emitting element LE can be electrodes of different polarities.

[0293] Because the lead pads FPD, contact electrodes CTE1 and CTE2, and connectors CNT1 and CNT2 are formed in the same process, they can include the same materials. For example, the lead pads FPD, contact electrodes CTE1 and CTE2, and connectors CNT1 and CNT2 can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0294] The widths of connectors CNT1 and CNT2 can be narrower than the width of the light-emitting element LE.

[0295] Figure 18 and Figure 19 It is illustrated in detail according to one or more other embodiments. Figure 14 A layout diagram of an example of region C in the diagram.

[0296] Reference Figure 18 , and Figure 15 The difference in the embodiments is that the widths of the connectors CNT1 and CNT2 are the same as or wider than the width of the light-emitting element LE. Figure 18 and Figure 19 In the embodiment, the omission and Figure 15 The embodiments are described repeatedly.

[0297] For example, the widths of connectors CNT1 and CNT2 can be the same as the widths of contact electrodes CTE1 and CTE2. If the widths of connectors CNT1 and CNT2 are formed to be equal to or wider than the width of the light-emitting element LE, it can be advantageous to reduce the possibility of short circuits in connectors CNT1 and CNT2.

[0298] Reference Figure 19 ,and Figure 15 The difference in this embodiment is that the first pin pad FPD1 and the second pin pad FPD2 connected to a light-emitting element LE are not aligned in a straight line in the second direction DR2. The first pin pad FPD1 and the second pin pad FPD2 are not aligned in a straight line with the light-emitting element LE in the second direction DR2.

[0299] The first light-emitting element LE1 and the second light-emitting element LE2 are arranged on the second direction DR2, and the first pin pad FPD1 connected to the first contact electrode CTE1 of the first light-emitting element LE1 is not arranged in a straight line with the first light-emitting element LE1 on the second direction DR2, and the second pin pad FPD2 connected to the second contact electrode CTE2 of the first light-emitting element LE1 is not arranged in a straight line with the first light-emitting element LE1 on the second direction DR2.

[0300] In this way, the two pin pads included in a test block TB are not aligned with the light-emitting element LE in the second direction DR2, but can be offset (e.g., offset from each other). When the two pin pads are arranged such that the light-emitting element LE is misaligned, the advantage is that the possibility of contact between the test probes due to the thickness of the probes can be reduced during testing.

[0301] Figure 20 This is a schematic diagram illustrating a light-emitting element inspection apparatus according to one or more embodiments. Figure 20 The wafer can be compared with a reference Figures 14 to 19 The described wafer EWF is the same.

[0302] The light-emitting element inspection device may include a wafer EWF with lead pads FPD and light-emitting elements LE, a power application section 50, an image sensor 30, and a control section 60.

[0303] The power application section 50 includes multiple probes 51 and 52, and uses the multiple probes 51 and 52 to apply a test power to the light-emitting element LE to be inspected.

[0304] For example, after contacting the first probe 51 with the first pin pad FPD1 connected to the first contact electrode CTE1 of the light-emitting element LE, and after contacting the second probe 52 with the second pin pad FPD2 connected to the second contact electrode CTE2 of the light-emitting element LE, the power application section 50 applies test power to multiple light-emitting elements LE through the first probe 51 and the second probe 52. The power application section 50 can be driven by an externally applied signal, and when power is applied, the test power is applied to the multiple light-emitting elements LE to be inspected to check for defects. When the test power is applied, a normal light-emitting element LE can light up.

[0305] One or more image sensors 30 are disposed on one side of the light-emitting element to acquire images of the light emitted from the light-emitting element. The image sensor 30 may be, for example, a camera. Here, the camera may include, but is not limited to, an area scan camera or a line scan camera, and any device capable of photographing an object other than a camera may be used.

[0306] The control unit 60 can be electrically connected to the image sensor 30 and the power application unit 50 to send and receive information. The control unit 60 can control the operation of the image sensor 30 and the power application unit 50. The information sent and received by the control unit 60 may include, for example, a reference image for determining defects in the light-emitting element. The reference image can be stored in the control unit 60 before inspection. The control unit 60 can determine lighting defects from the image acquired via the image sensor 30.

[0307] For example, the control unit 60 can determine a defect in the light-emitting element by comparing at least one of the brightness and illuminance in the acquired image with a preset reference. For example, if any light-emitting element in the acquired image has significantly lower brightness and illuminance than other light-emitting elements, then the light-emitting element can be determined to be defective.

[0308] In one or more embodiments, when a defect is detected in some light-emitting elements (LEs), a process for removing the corresponding light-emitting element (LE) can be performed individually.

[0309] According to one or more embodiments, defects in the light-emitting elements (LEs) on the wafer EWF can be inspected.

[0310] Figure 21 This is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments. Figure 22 This is a flowchart illustrating a method for manufacturing a wafer according to one or more embodiments. Figures 23 to 30 This is a diagram illustrating a method for manufacturing a wafer and a method for transferring light-emitting elements according to one or more embodiments.

[0311] Reference Figure 22 The described method for manufacturing wafers is for detailed explanation and reference. Figure 21 A flowchart describing a method for inspecting light-emitting elements on a wafer. (See reference...) Figures 21 to 30 The wafers mentioned can be used as a reference. Figures 14 to 19 The wafer being described. (Refer to...) Figures 21 to 30 The light-emitting element inspection device mentioned can be referred to Figure 20 The described light-emitting element inspection device.

[0312] To manufacture a display device, the light-emitting elements on the wafer can be inspected first. (For example, Figure 21 (S110 in the middle) For example, refer to Figure 23 and Figure 24 A semiconductor stack (STC) is formed on the wafer substrate (WAF). (For example, Figure 22 (S111 in the middle) First, prepare the wafer substrate WAF. The wafer substrate WAF can be a sapphire substrate Al2O3 and / or a silicon wafer including silicon. However, it is not limited to this, and in one or more embodiments, the case where the wafer substrate WAF is a sapphire substrate will be described as an example.

[0313] Multiple semiconductor material layers are formed on a wafer substrate (WAF). These multiple semiconductor material layers, grown epitaxially, can be formed by growing seed crystals. Methods for forming the semiconductor material layers include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-mode thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and are preferably formed by MOCVD. However, they are not limited to these methods.

[0314] The precursor materials used to form multiple semiconductor material layers are not particularly limited within the range that can be conventionally selected for forming the subject material. In one example, the precursor material may be a metal precursor including alkyl groups such as methyl and / or ethyl. For example, it may be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), triethyl phosphate ((C2H5)3PO4), but is not limited thereto.

[0315] A third semiconductor material layer, SEM3L, is formed on a wafer substrate (WAF). In the accompanying drawings, the third semiconductor material layer, SEM3L, is shown as a single layer, but this disclosure is not limited to this, and multiple layers may be formed. The third semiconductor material layer, SEM3L, can be configured to reduce the difference in lattice constant between the second semiconductor material layer, SEM2L, and the wafer substrate (WAF). In one example, the third semiconductor material layer, SEM3L, may comprise an undoped semiconductor, and may be an undoped n-type or p-type material. In one or more embodiments, the third semiconductor material layer, SEM3L, may be undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, but is not limited to these.

[0316] Using the method described above, a second semiconductor material layer SEM2L, an active material layer MQWL, and a first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L. In another modified example, a superlattice material layer can be formed between the second semiconductor material layer SEM2L and the active material layer MQWL. Furthermore, an electron blocking material layer can be formed between the active material layer MQWL and the first semiconductor material layer SEM1L.

[0317] A conductive material layer ELL can be further formed on the semiconductor stack STC. The conductive material layer ELL may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu), and / or may be made of a transparent conductive material (TCO) capable of transmitting light (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)).

[0318] Next, refer to Figure 24 Semiconductor stacks (STCs) are formed by mesa etching of multiple semiconductor material layers using an etching process that uses a mask.

[0319] Specifically, a mask pattern is formed on the conductive material layer ELL. The mask pattern can be a hard mask containing inorganic materials and / or a photoresist mask containing organic materials. The mask pattern prevents the underlying multiple semiconductor material layers from being etched. Then, a portion of the multiple semiconductor material layers is etched using the multiple mask patterns as masks to form multiple semiconductor stacks STC.

[0320] Semiconductor material layers can be etched using conventional methods. For example, processes used to etch semiconductor material layers include dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), and inductively coupled plasma reactive ion etching (ICP-RIE). In the case of dry etching, anisotropic etching is feasible and can be applied to vertical etching. When using the above etching methods, the etchant can be Cl2 and / or O2. However, it is not limited to these methods.

[0321] Multiple semiconductor material layers superimposed on the mask pattern are not etched to form a semiconductor stack STC. Thus, a semiconductor stack STC including a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 is formed.

[0322] Reference Figure 25 A protective layer INS (e.g., ) is formed on a wafer substrate WAF on which a semiconductor stack STC is formed. Figure 22 (S112 in the middle).

[0323] For example, such as Figure 25 As shown, a portion of the semiconductor stack STC is etched to form a via LEH. For example, the via LEH is formed within the semiconductor stack STC, but not within the third semiconductor layer SEM3. The via LEH penetrates the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW, and exposes the second semiconductor layer SEM2.

[0324] Hole LEH can be formed only on the semiconductor stack STC of the light-emitting element LE.

[0325] For example, a protective material layer can be applied entirely to the wafer substrate (WAF). The protective material layer can be disposed on the top and side surfaces of the semiconductor stack (STC).

[0326] Next, etching is performed to partially remove the protective material layer on the top surface of the semiconductor stack STC to form a protective layer INS with a first opening OP1 and a second opening OP2 on the top surface of the semiconductor stack STC of the light-emitting element LE. For example, openings OP1 and OP2 may be formed in the semiconductor stack STC of the light-emitting element LE, and openings OP1 and OP2 may not be formed in the semiconductor stack STC of the lead pad FPD. The first opening OP1 and the second opening OP2 are formed to be spaced apart (e.g., separated), and the second opening OP2 may be located at the center of the via LEH. In this process, a portion of the protective material layer can be removed from the top surface of the conductive layer E1. Furthermore, a portion of the protective material layer can be removed from the bottom of the via LEH to expose the second semiconductor layer SEM2. The process of partially removing the protective material layer can be performed by anisotropic dry etching followed by an etch-back process, but is not limited to this.

[0327] Next, refer to Figure 26 This forms the light-emitting element (LE), lead pad (FPD), and connector (CNT). (For example, Figure 22 (S113 in the middle) First, a first reflective layer RF1 can be formed on the protective layer INS of the semiconductor stack STC. For example, the first reflective material layer is formed on the semiconductor stack STC of the light-emitting element LE, but not on the semiconductor stack STC of the lead pad FPD. The first reflective material layer can be deposited by processes such as sputtering, but is not limited thereto.

[0328] The first reflective layer RF1 can be formed by etching a portion of the first reflective material layer using a photolithography process.

[0329] Optical processing is a process used to form a desired structure by applying a photoresist (PR) to a substrate and then passing light through a mask with a desired pattern. In this way, optical processing tolerances may occur due to the mask and the light passing through it. For example, a photoresist can be formed on a semiconductor stack STC. When a first reflective layer RF1 is formed using a first photoresist as a mask, a portion of the first reflective layer RF1 protrudes outward from the bottom of the semiconductor stack STC due to optical processing tolerances. Optical processing tolerances can vary depending on the photographic equipment but can be from about 0.5 μm to 2 μm. Therefore, the protruding length of the first reflective layer RF1 can be formed in the range of 0.6 μm to 2.4 μm, including a margin of about 20% within the optical processing tolerances.

[0330] Next, contact electrodes CTE1 and CTE2 or contact pads CPD are formed. For example, contact electrodes CTE1 and CTE2 are formed on the first reflective layer RF1 on the semiconductor stack STC of the light-emitting element LE, and contact pads CPD are formed on the semiconductor stack STC of the lead pads FPD.

[0331] For example, a conductive material layer is formed on the entire surface of a wafer substrate (WAF) on which multiple semiconductor stacks (STCs) are formed. The conductive material layer can be deposited by processes such as sputtering, but is not limited to these.

[0332] By forming a conductive material layer on the entire surface of the wafer substrate WAF, contact electrodes CTE1 and CTE2 or contact pads CPD can be formed on the semiconductor stack STC, and connectors CNT can be formed on the wafer substrate WAF on which no semiconductor stack STC is disposed.

[0333] Contact electrodes CTE1 and CTE2 can be formed by etching a portion of the conductive material layer using a photolithography process.

[0334] Subsequently, the photoresist remaining on the wafer substrate WAF can be removed by stripping or ashing.

[0335] Next, refer to Figure 27 The light-emitting element (LE) can be inspected by contact probes (e.g., Figure 22 (S114 in the middle).

[0336] After the first probe 51 is brought into contact with the first pin pad FPD1 associated with the first contact electrode CTE1 of the light-emitting element LE, and the second probe 52 is brought into contact with the second pin pad FPD2 associated with the second contact electrode CTE2 of the light-emitting element LE, a test power supply can be applied.

[0337] Test power can be applied to the light-emitting element LE through the power application section 50 to check for defects in multiple light-emitting elements.

[0338] Image sensor 30 acquires an image of the light emitted from light-emitting element LE, which is powered by a test power supply. The acquired image can be transmitted to control unit 60.

[0339] The control unit 60 can determine the characteristics of the light-emitting element by comparing the acquired image with a suitable (e.g., pre-stored) reference image.

[0340] Reference Figure 28 and Figure 29 The light-emitting elements (LEs) located on the wafer EWF, which are determined to be good by the control section 60, are transferred to the circuit board substrate SUB (i.e., the substrate SUB). (For example, Figure 21 (S120 in the middle) For example, an insulating film FL is formed between light-emitting elements LE, the light-emitting elements LE are transferred to a first organic film 210 disposed on a pixel electrode PXE, and the wafer substrate WAF is removed.

[0341] An insulating film FL can be formed between the light-emitting elements (LEs) to prevent the LEs from separating from or moving from the wafer substrate (WAF) due to external impacts during the transfer process. The insulating film FL can be formed of organic and / or inorganic films.

[0342] although Figure 28 The illustration shows an insulating film FL filling the entire space between light-emitting elements LE, but this disclosure is not limited thereto. In one example, the insulating film FL may fill only a portion of the space between the light-emitting elements LE.

[0343] The light-emitting element LE can be transferred to the first organic film 210 disposed on the pixel electrode PXE. At this time, the light-emitting element LE can be embedded in the first organic film 210 and temporarily fixed to the first organic film 210. Figure 28 The illustration shows a first contact electrode CTE1 and a second contact electrode CTE2 disposed on a first organic film 210 for each of the light-emitting elements LE, but the present disclosure is not limited thereto. For example, the first organic film 210 may be disposed on a portion of the bottom surface and side surface of the first contact electrode CTE1 and a portion of the bottom surface and side surface of the second contact electrode CTE2 for each of the light-emitting elements LE. Optionally, the first organic film 210 may be disposed on a side surface of the conductive layer E1 for each of the light-emitting elements LE. Optionally, the first organic film 210 may be disposed on a side surface of the first semiconductor layer SEM1, a side surface of the active layer MQW, and a side surface of the second semiconductor layer SEM2 for each of the light-emitting elements LE. In this case, the first organic film 210 may be disposed on a portion of each side of the second semiconductor layer SEM2.

[0344] When the first organic film 210 has low fluidity or is rigid, the depth to which the light-emitting element LE is inserted or embedded in the first organic film 210 will be very small, or the light-emitting element LE can be placed on the first organic film 210 without being inserted or embedded in the first organic film 210.

[0345] When the first organic film 210 is a photosensitive organic film such as a photoresist, the first organic film 210 can be soft-baked at a first temperature, and then at least a portion of each of the plurality of light-emitting elements LE can be inserted into the first organic film 210. The first organic film 210 can then be fully cured at a second temperature higher than the first temperature. The first temperature can be approximately 100 degrees Celsius, and the second temperature can be approximately 230 degrees Celsius, but this disclosure is not limited thereto. Furthermore, the process of fully curing the first organic film 210 at the second temperature can be performed for approximately 30 minutes.

[0346] Then, a laser lift-off process is used to remove the wafer substrate WAF. When the laser lift-off process separates the light-emitting elements (LEs) from the wafer substrate WAF, a laser is applied to the connector CNT portion between the light-emitting elements (LEs) on the wafer substrate WAF, so that the light-emitting elements (LEs) can have tips T-1 and T-2.

[0347] Alternatively, when the light-emitting element (LE) is transferred to a separate transfer substrate instead of the wafer substrate WAF, the transfer substrate instead of the wafer substrate WAF can be removed. In another modification, a mask can be formed on the light-emitting element (LE), the pin pad area can be etched, and then the light-emitting element (LE) can be transferred.

[0348] like Figure 29 As shown, the insulating film FL is removed to form a first connecting electrode BE1 and a second connecting electrode BE2, and a third organic film 211 and a fourth organic film 212 are formed. (For example, Figure 21 (S130 in the middle) The insulating film FL can be removed using a chemical solution. The insulating film FL can be an organic film and / or an inorganic film, and the chemical solution can be hydrochloric acid (HCl) and tetramethylammonium hydroxide (TMAH), but this disclosure is not limited thereto.

[0349] When the first contact electrode CTE1 and the second contact electrode CTE2 are arranged to cover the entire side surface of the semiconductor stack STC, the first contact electrode CTE1 and the second contact electrode CTE2 exposed on the top surface of the semiconductor stack STC are exposed to a chemical solution. The chemical solution permeates between the first contact electrode CTE1 and the protective film INS and between the second contact electrode CTE2 and the protective film INS, thereby causing the first contact electrode CTE1 and the second contact electrode CTE2 to peel off from the protective film INS.

[0350] However, in one or more embodiments of this disclosure, each of the first contact electrode CTE1 and the second contact electrode CTE2 is spaced apart (e.g., separated) from the top surface of the semiconductor stack STC, such that the first contact electrode CTE1 and the second contact electrode CTE2 are protected by the insulating film FL and are not exposed to the chemical solution. Therefore, it is possible to prevent the first contact electrode CTE1 and the second contact electrode CTE2 from being stripped by the chemical solution.

[0351] Then, a first connection electrode BE1 for connecting the pixel electrode PXE and the first contact electrode CTE1 for connecting the light-emitting element LE, and a second connection electrode BE2 for connecting the second contact electrode CTE2 and the common electrode CE, are formed on the first organic film 210.

[0352] Then, a third organic film 211 and a fourth organic film 212 are formed to fix the light-emitting element LE and flatten the step caused by the light-emitting element LE.

[0353] like Figure 30 As shown, a light-blocking layer, a wavelength conversion layer, a light-transmitting layer, and a color filter layer are formed sequentially.

[0354] A first capping layer CAP1 is formed on the fourth organic film 212 and the light-emitting element LE, and a first light-blocking layer BM1 and a second light-blocking layer BM2 are formed on the first capping layer CAP1 to prevent it from overlapping with the light-emitting element LE on the third-direction DR3. Then, a second capping layer CAP2 is formed to cover the first light-blocking layer BM1, the second light-blocking layer BM2, and the first capping layer CAP1. Then, a second reflective layer RF2 is formed to cover the second capping layer CAP2 disposed on the first light-blocking layer BM1 and the second light-blocking layer BM2.

[0355] Then, a first light conversion layer QDL1 is formed in each of the first sub-pixels SPX1, a second light conversion layer QDL2 is formed in each of the second sub-pixels SPX2, and a light transmission layer TPL is formed in each of the third sub-pixels SPX3. A third capping layer CAP3 is then formed to cover the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL. Finally, a fifth organic film 213 is formed on the third capping layer CAP3.

[0356] Then, on the fifth organic film 213, a first color filter CF1 is formed on the third-direction DR3 and stacked with the first light conversion layer QDL1, a second color filter CF2 is formed on the third-direction DR3 and stacked with the second light conversion layer QDL2, and a third color filter CF3 is formed on the third-direction DR3 and stacked with the light transmission layer TPL. In the region where the first light blocking layer BM1 and the second light blocking layer BM2 are stacked along the third-direction DR3, all three color filters can be formed: the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0357] Then, a sixth organic film 214 is formed on the first color filter CF1, the second color filter CF2 and the third color filter CF3.

[0358] Figure 31 This is an example diagram of a smartwatch that includes a display device according to one or more embodiments.

[0359] Reference Figure 31 The display device 10_1 according to one or more embodiments can be applied to a smartwatch 1000_1, which is a type of smart device.

[0360] Figure 32 and Figure 33 This is an example diagram of a virtual reality (VR) device that includes a display device according to one or more embodiments.

[0361] Reference Figure 32 and Figure 33 The head-mounted display device 1000_2 according to one or more embodiments includes a first display device 10_2, a second display device 10_3, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0362] The first display device 10_2 provides an image to the user's left eye, and the second display device 10_3 provides an image to the user's right eye. Each of the first display device 10_2 and the second display device 10_3 is associated with a reference... Figure 1 and Figure 2 The described display devices 10 are substantially the same. Therefore, the description of the first display device 10_2 and the second display device 10_3 will be omitted.

[0363] The first optical component 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0364] The intermediate frame 1400 can be disposed between the first display device 10_2 and the control circuit board 1600, and can also be disposed between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 supports and fixes the first display device 10_2, the second display device 10_3, and the control circuit board 1600.

[0365] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 via connectors. The control circuit board 1600 can convert image sources received from external sources into digital video data DATA, and transmit the digital video data DATA to the first display device 10_2 and the second display device 10_3 via connectors.

[0366] The control circuit board 1600 can transmit digital video data DATA corresponding to a left image optimized for the user's left eye to the first display device 10_2, and digital video data DATA corresponding to a right image optimized for the user's right eye to the second display device 10_3. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_2 and the second display device 10_3.

[0367] The display device housing 1100 houses a first display device 10_2, a second display device 10_3, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is positioned to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Although the first eyepiece 1210 and the second eyepiece 1220 are... Figure 33 and Figure 34 The first eyepiece 1210 and the second eyepiece 1220 can be set up separately, but this disclosure is not limited to this.

[0368] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_2 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_3 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0369] The headband 1300 secures the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively positioned over the user's left and right eyes. When the display device housing 1100 is made lightweight and compact, the head-mounted display device 1000_2 may include, for example... Figure 34 The eyeglasses frame shown is not the headband 1300.

[0370] In addition, the head-mounted display device 1000_2 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0371] Figure 34 This is an example diagram of a VR device that includes a display device according to one or more embodiments. Figure 34 A VR device 1000_3 is shown, in which a display device 10_4 according to one or more embodiments has been applied.

[0372] Reference Figure 34 The VR device 1000_3 according to one or more embodiments may be a device in the form of glasses. The VR device 1000_3 according to the embodiments may include a display device 10_4, a left lens 10a, a right lens 10b, a support frame 20, eyeglass frame temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0373] exist Figure 34 The example shown is of a VR device 1000_3 that is an eyeglass-type display device including eyeglass frame temples 30a and 30b. That is, the VR device 1000_3 according to the embodiment is not limited to... Figure 32 and Figure 33 The VR device shown is not limited to VR devices; it can be applied to a variety of other electronic devices in various forms.

[0374] The display device housing 50 can accommodate the display device 10_4 and the reflective member 40. The image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's right eye through the right lens 10b. Therefore, the user can view the VR image displayed on the display device 10_4 through their right eye.

[0375] Despite Figure 34The display device housing 50 is located at the right end of the support frame 20, but this disclosure is not limited thereto. For example, the display device housing 50 may also be located at the left end of the support frame 20. In this case, the image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. Therefore, the user can view the VR image displayed on the display device 10_4 through their left eye. Alternatively, the display device housing 50 may be located at both the right and left ends of the support frame 20. In this case, the user can view the VR image displayed on the display device 10_4 through both their left and right eyes.

[0376] Figure 35 This is an example diagram illustrating a vehicle instrument cluster and a central dashboard that include a display device according to one or more embodiments. Figure 35 The vehicle shown is equipped with display devices 10_a to 10_e according to one or more embodiments.

[0377] Reference Figure 35 The display devices 10_a to 10_c according to the embodiments can be applied to the instrument cluster of a vehicle, the central instrument panel of a vehicle, and / or the central information display (CID) mounted on the instrument panel of a vehicle. Furthermore, the display devices 10_d and 10_e according to the embodiments can be applied to interior mirror displays that replace the side mirrors of a vehicle.

[0378] Figure 36 This is an example diagram of a transparent display device including a display device according to one or more embodiments.

[0379] Reference Figure 36 The display device 10_5 according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can view not only the image IM displayed on the display device 10_5, but also the object RS or background located behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion or may be made of a light-transmitting material.

[0380] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles and scope of this disclosure. Therefore, the embodiments of this disclosure are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A wafer, the wafer comprising: Base; A plurality of light-emitting elements are provided on the substrate, each of the plurality of light-emitting elements comprising a semiconductor stack, a first contact electrode, and a second contact electrode; Multiple pin pads are provided on the substrate, and each of the multiple pin pads includes a semiconductor stack. as well as Multiple connectors connect different pin pads to the first contact electrode and the second contact electrode of the light-emitting element among the multiple light-emitting elements.

2. The wafer according to claim 1, wherein, Both the semiconductor stack of the light-emitting element and the semiconductor stack of the lead pad include a third semiconductor layer, a second semiconductor layer, an active layer, and a first semiconductor layer stacked sequentially.

3. The wafer according to claim 1, wherein, The plurality of pin pads includes a first pin pad and a second pin pad, and The plurality of connectors include a first connector that connects the first contact electrode and the first pin pad, and a second connector that connects the second contact electrode and the second pin pad.

4. The wafer according to claim 3, wherein, The first pin pad, the light-emitting element, and the second pin pad are aligned with each other in a first direction.

5. The wafer according to claim 3, wherein, The first pin pad and the second pin pad are not aligned in a first direction, and the light-emitting element is not aligned with the first pin pad and the second pin pad.

6. The wafer according to claim 1, wherein, Each of the plurality of pin pads also includes a contact pad on the semiconductor stack, and The contact pad, the first contact electrode, the second contact electrode, and the plurality of connectors are integrally formed together.

7. The wafer according to claim 1, wherein, The plurality of light-emitting elements are arranged along a first direction and a second direction. The plurality of pin pads are arranged alternately with the plurality of light-emitting elements along the second direction, and In this configuration, the pin pad located between the first light-emitting element and the second light-emitting element in the second direction is connected to the second contact electrode of the first light-emitting element and to the first contact electrode of the second light-emitting element.

8. The wafer according to claim 7, wherein, The semiconductor stack of the light-emitting element includes a concave groove that exposes a second semiconductor layer of the semiconductor stack in the region overlapping with the second contact electrode. The second contact electrode is electrically connected to the second semiconductor layer exposed through the concave groove, and The first contact electrode is electrically connected to the first semiconductor layer of the semiconductor stack.

9. A display device, the display device comprising: Base; Pixel electrodes and common electrodes are located on the substrate and spaced apart from each other; A light-emitting element is located on the pixel electrode and the common electrode; The first contact electrode is located on the light-emitting element and the pixel electrode; as well as The second contact electrode is located on the light-emitting element and the common electrode. The light-emitting element includes: Semiconductor stack; A protective layer is placed around all sides of the semiconductor stack except one side. A reflective layer is located on the protective layer around the semiconductor stack; A first tip extends from the first contact electrode and protrudes outward perpendicular to the side surface of the semiconductor stack; and The second tip extends from the second contact electrode and protrudes outward perpendicular to the side surface of the semiconductor stack.

10. The display device according to claim 9, further comprising a first connection electrode electrically connecting the first contact electrode and the pixel electrode, and a second connection electrode electrically connecting the second contact electrode and the common electrode.

11. The display device according to claim 9, wherein, The reflective layer includes a first reflective layer between the first contact electrode and the protective layer and a second reflective layer between the second contact electrode and the protective layer, and The first reflective layer and the second reflective layer are spaced apart from each other.

12. The display device according to claim 9, wherein, The semiconductor stack includes a concave groove that exposes a second semiconductor layer of the semiconductor stack in the region overlapping with the second contact electrode. The second contact electrode is electrically connected to the second semiconductor layer exposed through the concave groove, and The first contact electrode is electrically connected to the first semiconductor layer of the semiconductor stack.

13. A method for inspecting a light-emitting element, the method comprising the following steps: Multiple semiconductor stacks are formed by stacking multiple semiconductor material layers on a substrate and etching the multiple semiconductor material layers; A protective layer is formed covering a portion of the top and side surfaces of the plurality of semiconductor stacks; Contact electrodes and contact pads are formed on the protective layer to form a light-emitting element and a lead pad, wherein the lead pad is electrically connected to the contact electrode via a connector; as well as The first probe and the second probe are respectively brought into contact with the first pin pad and the second pin pad connected to the contact electrode of the light-emitting element in the pin pad, and a test power is applied.

14. The inspection method according to claim 13, wherein, In the step of forming the contact electrode and the contact pad on the protective layer to form the light-emitting element and the lead pad, the lead pad is electrically connected to the contact electrode by the connector including a first connector and a second connector. The light-emitting element is formed by forming a first contact electrode and a second contact electrode on the protective layer of the first semiconductor stack in the plurality of semiconductor stacks. The first pin pad is formed by forming the contact pad on the protective layer of the second semiconductor stack in the plurality of semiconductor stacks; The second pin pad is formed by forming the contact pad on the protective layer of the third semiconductor stack among the plurality of semiconductor stacks. The method further includes forming a first connector that connects the first contact electrode and the first pin pad, and a second connector that connects the second contact electrode and the second pin pad.

15. The inspection method according to claim 14, wherein, The first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are arranged in a straight line relative to each other in a first direction.

16. The inspection method of claim 14, further comprising acquiring an image of light emitted from the light-emitting element under the applied test power; and The characteristics of the light-emitting element are determined by comparing the acquired image with a reference image through the control section.

17. A method for manufacturing a display device comprising a plurality of light-emitting elements, the method comprising the following steps: Multiple semiconductor stacks are formed by stacking multiple semiconductor material layers on a wafer substrate and etching the multiple semiconductor material layers. A protective layer is formed covering a portion of the top and side surfaces of the plurality of semiconductor stacks; Contact electrodes and contact pads are formed on the protective layer to form light-emitting elements and lead pads among the plurality of light-emitting elements, wherein the lead pads are electrically connected to the contact electrodes via connectors; Make the first probe and the second probe contact the first pin pad and the second pin pad in the pin pad that are connected to the contact electrode of the light-emitting element, respectively, and inspect the light-emitting element; as well as The plurality of light-emitting elements are transferred to the circuit board.

18. The manufacturing method according to claim 17, wherein, In the step of forming the contact electrode and the contact pad on the protective layer to form the light-emitting element and the lead pad, the lead pad is electrically connected to the contact electrode by the connector including a first connector and a second connector, wherein the contact electrode includes a first contact electrode and a second contact electrode. The light-emitting element is formed by forming the first contact electrode and the second contact electrode on the protective layer of the first semiconductor stack in the plurality of semiconductor stacks. The first pin pad is formed by forming the contact pad on the protective layer of the second semiconductor stack in the plurality of semiconductor stacks. The second pin pad is formed by forming the contact pad on the protective layer of the third semiconductor stack in the plurality of semiconductor stacks, and The first connector connects the first contact electrode and the first pin pad, and the second connector connects the second contact electrode and the second pin pad.

19. The manufacturing method according to claim 17, wherein, The steps of contacting the first probe and the second probe with the first pin pad and the second pin pad respectively connected to the contact electrode of the light-emitting element and inspecting the light-emitting element include: Make the first probe and the second probe contact the first pin pad and the second pin pad that are connected to the contact electrode of the light-emitting element, respectively, and apply a test power supply; Acquire an image of the light emitted from the light-emitting element under the applied test power; and The characteristics of the light-emitting element are determined by comparing the acquired image with a reference image through the control section.

20. The manufacturing method according to claim 17, wherein, The circuit board includes multiple pixel circuit sections, pixel electrodes connected to each of the multiple pixel circuit sections, and a common electrode spaced apart from the pixel electrodes. The light-emitting element includes a first contact electrode and a second contact electrode. The method further includes, after the plurality of light-emitting elements are transferred to the circuit board: A first connection electrode is formed to connect the first contact electrode and the pixel electrode, and a second connection electrode is formed to connect the second contact electrode and the common electrode.

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