Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a plurality of dies stacked in a vertical direction; a thermally conductive layer deposited on a top surface of the topmost die; a base die on a bottom surface of the bottommost die; and a first contact structure extending vertically through the plurality of dies. The first contact structure includes one or more first channels. Each first channel has a first end in contact with the base die and has a second end in contact with the thermally conductive layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to International Application No. PCT / CN2024 / 078561, filed on February 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of semiconductor technology, and more specifically, to the packaging of semiconductor devices and methods of manufacturing the same. Background Technology

[0004] As the power consumption of semiconductor chips continues to increase, the requirements for heat dissipation in packaging become more stringent. However, on the one hand, packaging structures have poor thermal conductivity, and on the other hand, existing heat dissipation methods are mainly implemented at the system level. There is a need for specialized heat dissipation within semiconductor packages. Summary of the Invention

[0005] In one aspect, a semiconductor device is provided. The semiconductor device includes: a plurality of dies stacked in a vertical direction; a thermally conductive layer deposited on a top surface of the topmost die; a substrate die located on a bottom surface of the bottommost die; and a first contact structure extending vertically through the plurality of dies. The first contact structure includes one or more first channels, each first channel having a first end in contact with the substrate die and a second end in contact with the thermally conductive layer.

[0006] In some embodiments, the semiconductor device further includes a second contact structure extending vertically within a plurality of dies. The second contact structure includes one or more second channels, each extending vertically and contacting the substrate die but not the thermally conductive layer.

[0007] In some embodiments, the substrate die includes a wiring structure comprising a first wiring structure and a second wiring structure. The first wiring structure is configured to deliver heat, and the second wiring structure is configured to transmit electronic signals.

[0008] In some embodiments, the semiconductor device further includes an interposer layer located on the side of the substrate die opposite to a plurality of dies. The interposer layer includes a ball grid array located on the side of the interposer layer opposite to the substrate die.

[0009] In some implementations, the ball grid array includes one or more hot solder balls connected to a first wiring structure and one or more signal solder balls connected to a second wiring structure.

[0010] In some implementations, each of the first and second channels is a continuous structure along the vertical direction.

[0011] In some implementations, the second contact structure is surrounded by the first contact structure.

[0012] In some implementations, each first channel has a first lateral dimension at its first end and a second lateral dimension at its second end, and the first lateral dimension is greater than the second lateral dimension.

[0013] In some embodiments, each second channel has a first end in contact with the substrate die, the first end of each second channel has a third lateral dimension, and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel.

[0014] In some implementations, the first lateral dimension is 2-3 μm, and the third lateral dimension is less than 2 μm.

[0015] In some embodiments, the semiconductor device further includes a high-power operating region and a low-power operating region. The number of first channels in the high-power operating region is greater than the number of first channels in the low-power operating region.

[0016] In some implementations, the material of the thermally conductive layer has a thermal conductivity of not less than 20 W / mK.

[0017] In some implementations, the thermally conductive layer is made of one of silicon nitride, aluminum oxide, and silicon carbide.

[0018] In some implementations, the plurality of dies includes at least one memory die, and the plurality of dies are stacked by direct bonding.

[0019] In another aspect, another semiconductor device is provided. This semiconductor device includes: a plurality of dies stacked vertically; an interposer located on the bottom surface of a substrate die, wherein the interposer includes wiring structures, including a first wiring structure and a second wiring structure; and a first contact structure extending vertically through the plurality of dies. The first contact structure includes one or more first channels, each first channel having a first end contacting the interposer and a second end contacting the top surface of the topmost die.

[0020] In some embodiments, the semiconductor device includes a second contact structure extending vertically within a plurality of dies. The second contact structure includes one or more second channels, each extending vertically and contacting an interposer but not the top surface of the topmost die.

[0021] In some embodiments, the semiconductor device includes a ball grid array located on one side of the interposer opposite to a plurality of dies.

[0022] In some embodiments, the ball grid array includes: one or more hot solder balls in contact with a first wiring structure configured to deliver heat; and one or more signal solder balls in contact with a second wiring structure configured to transmit electronic signals.

[0023] In some implementations, each of the first and second channels is a continuous structure along the vertical direction.

[0024] In some implementations, the second contact structure is surrounded by the first contact structure.

[0025] In some implementations, each first channel has a first lateral dimension at its first end and a second lateral dimension at its second end, and the first lateral dimension is greater than the second lateral dimension.

[0026] In some implementations, each second channel has a first end that contacts the interposer layer, and the first end of each second channel has a third lateral dimension, which is smaller than the first lateral dimension of the first end of each first channel.

[0027] In some implementations, the first lateral dimension is 2-3 μm, and the third lateral dimension is less than 2 μm.

[0028] In some embodiments, the semiconductor device includes a high-power operating region and a low-power operating region. The number of first channels in the high-power operating region is greater than the number of first channels in the low-power operating region.

[0029] In some implementations, the material of the first channel has a thermal conductivity of not less than 20 W / mK.

[0030] In some implementations, the material of the first channel is one of silicon nitride, aluminum oxide, and silicon carbide.

[0031] In some implementations, the plurality of dies includes at least one memory die, and the plurality of dies are stacked by direct bonding.

[0032] In another aspect, a method is provided. The method includes: stacking a plurality of dies in a vertical direction; depositing a sacrificial layer on a first surface of the stacked dies and forming a plurality of first vias in the sacrificial layer; forming a first contact structure extending vertically through the stacked dies using the plurality of first vias, wherein the first contact structure includes one or more first channels; bonding a substrate die to the first surface of the stacked dies by hybrid bonding; bonding an interposer layer to the substrate die, wherein the interposer layer includes wiring structures; connecting each first channel to the wiring structures; and forming a thermally conductive layer on a second surface of the stacked dies, wherein the second surface is vertically opposite the first surface, and the thermally conductive layer is physically connected to each first channel.

[0033] In some embodiments, the method further includes: forming a plurality of second holes in the sacrificial layer; forming a second contact structure extending vertically inside the stacked die using the plurality of second holes, wherein the second contact structure includes one or more second channels; and connecting each second channel to an interlayer without physically contacting the thermally conductive layer.

[0034] In some embodiments, the method further includes forming a ball grid array on the side of the interlayer opposite to the stacked dies.

[0035] In some embodiments, the wiring structure includes: a first wiring structure configured to deliver heat; and a second wiring structure configured to transmit electronic signals; and forming a ball grid array includes: forming a plurality of thermal solder balls in contact with the first wiring structure; and forming a plurality of signal solder balls in contact with the second wiring structure.

[0036] In some embodiments, forming a first contact structure includes forming each first channel that extends continuously in a vertical direction; and forming a second contact structure includes forming each second channel that extends continuously in a vertical direction.

[0037] In some embodiments, forming the second contact structure includes forming a second contact structure surrounded by the first contact structure.

[0038] In some embodiments, the method further includes forming each first channel having a first end and a second end, the first end having a first lateral dimension and the second end having a second lateral dimension. The first end of each first channel contacts a substrate die, the second end of each first channel contacts a thermally conductive layer, and the first lateral dimension is larger than the second lateral dimension.

[0039] In some embodiments, the method further includes forming each second channel having a first end having a third lateral dimension. The first end of each second channel contacts a substrate die, and the third lateral dimension is smaller than the first lateral dimension.

[0040] In some embodiments, forming the thermally conductive layer includes using a material having a thermal conductivity of not less than 20 W / mK.

[0041] In some embodiments, forming the thermally conductive layer includes using one of silicon nitride, aluminum oxide, and silicon carbide.

[0042] In some implementations, stacking multiple dies includes stacking at least one memory die with other dies by direct bonding. Attached Figure Description

[0043] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure and enable those skilled in the art to implement and use the present disclosure.

[0044] Figure 1A A schematic diagram of a first exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view.

[0045] Figure 1B A schematic diagram of a second exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view.

[0046] Figure 1C A schematic diagram of a third exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view.

[0047] Figures 2A-2F A manufacturing process for forming a first semiconductor device according to some aspects of this disclosure is shown.

[0048] Figures 3A-3F A manufacturing process for forming a second semiconductor device according to some aspects of this disclosure is shown.

[0049] Figures 4A-4G A manufacturing process for forming a third semiconductor device according to some aspects of this disclosure is shown.

[0050] Figures 5A-5B A schematic diagram of an exemplary semiconductor device according to some other embodiments of the present disclosure is shown in plan view.

[0051] Figure 6 A flowchart is shown of an exemplary method for forming a first semiconductor device according to some embodiments of the present disclosure.

[0052] Figure 7 A flowchart is shown of an exemplary method for forming a second semiconductor device according to some embodiments of the present disclosure.

[0053] Figure 8 A flowchart is shown of an exemplary method for forming a third semiconductor device according to some embodiments of the present disclosure.

[0054] Figure 9 A block diagram of an exemplary system having one or more semiconductor devices according to some embodiments of the present disclosure is shown.

[0055] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0056] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0057] Note that references to "one embodiment," "implementation," "exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0058] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0059] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0060] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0061] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The front surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the front surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0062] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is adjacent to the substrate, and the top side is relatively distant from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0063] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0064] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0065] This disclosure provides a semiconductor device with high thermal conductivity. In the era of powerful computing and artificial intelligence (AI), the von Neumann architecture, which combines high-bandwidth memory (HBM) with GPUs, remains mainstream in the high-performance chip market. However, the significant heat generated by stacked HBMs is a problem that urgently needs to be addressed. In traditional HBM architectures, as the number of stacked DRAM layers increases, the heat dissipation of different DRAM layers varies, which can easily lead to slow heat dissipation of the DRAM located in the middle layer, resulting in performance degradation. Because DRAM needs to perform continuous read and write operations, it is prone to generating heat during operation. The stacking structure of HBMs limits the heat dissipation of the DRAM located in the middle layer.

[0066] In the semiconductor device disclosed herein, heat generated during HBM operation can be rapidly dissipated, thereby preventing localized overheating. The number of I / O channels can be significantly increased. Compared to some existing semiconductor devices, the disclosed semiconductor device can achieve better internal heat dissipation within the stacked dies without increasing the HBM chip area.

[0067] Figure 1A A schematic diagram of a first exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 1A As shown, semiconductor device 100A may include an interposer 120, a substrate die 140 located on a first side of the interposer 120, stacked dies 110 located on the first side of the substrate die 140, and a ball grid array (BGA) 130 located on a second side of the interposer 120 opposite to the first side. It should be noted that semiconductor device 100A may also include... Figure 1A Any other suitable components not shown. For example, the semiconductor device may also include a printed circuit board (PCB) on which the semiconductor device 100A is mounted via a BGA 130.

[0068] Intermediate layer 120 can be any suitable semiconductor material with any suitable structure, such as single-crystal monolayer material, polycrystalline silicon (polysilicon) monolayer material, polycrystalline silicon and metal multilayer material, etc.

[0069] The substrate die 140 may include a wiring structure 144, which includes a first wiring structure 146 and a second wiring structure 148 embedded in the substrate die. The first wiring structure 146 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers) and is configured to transport heat. The second wiring structure 148 may include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second wiring structure 148 may be configured to transmit both electronic signals and heat. The first wiring structure 146 and the second wiring structure 148 may be isolated from each other.

[0070] In some embodiments, the first wiring structure 146 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second wiring structure 148 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the first wiring structure 146 and the second wiring width of the second wiring structure 148 may be in the range of approximately 1.5:1 to approximately 2:1.

[0071] The stacked dies 110 may include a plurality of dies vertically stacked by direct bonding, which forms a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive). The stacked dies may be attached to a first side of a substrate die 140 via an adhesive film (not shown). Exemplarily, the stacked dies 110 includes dies 102, 103, 104, and 105. In some embodiments, the stacked dies 110 may be any (multiple / one) suitable semiconductor die including one or more memory dies. The stacked dies 110 may include low-power chips with a maximum operating power below a threshold power value. The stacked dies may include high-power chips with a maximum operating power above a threshold power value. For example, the stacked dies 110 may include at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and may also include at least one of a memory chip and a sensing chip. In some embodiments, the adhesive film may be any suitable die attachment film (DAF).

[0072] In some embodiments, the semiconductor device includes a first contact structure 180 extending vertically within a stack of dies. The first contact structure may include one or more first channels 182, each first channel 182 being a continuous channel having a first end connected to a first wiring structure 146 and a second end contacting the top surface of the topmost die in the stack. The first end of each first channel 182 has a first lateral dimension (e.g., in the x-direction), and the second end of each first channel 182 has a second lateral dimension (e.g., in the x-direction), with the first lateral dimension being larger than the second lateral dimension. In some embodiments, the first lateral dimension is approximately 2-3 μm. In some embodiments, the material of each first channel has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of each first channel is one of a metal, a ceramic material, or a silicon material. In some embodiments, the material of each first channel may be one of silicon nitride, alumina, and silicon carbide.

[0073] In some embodiments, the semiconductor device includes a second contact structure 185 extending vertically within a stack of dies. The second contact structure 185 may be sandwiched between two first contact structures 180 (e.g., Figure 5A (as shown), or can be surrounded by the first contact structure 180 (as shown). Figure 5B (As shown). The second contact structure 185 may include a plurality of second channels, and each second channel of the second contact structure 185 is a continuous channel having a first end that contacts the second wiring structure 148 and a second end located inside the stacked dies that does not contact the top surface of the topmost die in the stack. The first end of each second channel of the second contact structure 185 has a third lateral dimension (e.g., in the x-direction), and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel. In some embodiments, the third lateral dimension is less than 2 μm. In some embodiments, the plurality of second channels have different dimensions along the vertical direction. For example, second channel 185-1 has a first end that contacts the second wiring structure 148 and a second end located inside die 105 that does not contact the top surface of die 105; second channel 185-2 has a first end that contacts the second wiring structure 148 and a second end located inside die 104 that does not contact the top surface of die 104; second channel 185-3 has a first end that contacts the second wiring structure 148 and a second end located inside die 103 that does not contact the top surface of die 103; and second channel 185-4 has a first end that contacts the second wiring structure 148 and a second end located inside die 102 that does not contact the top surface of die 102. In some embodiments, each second channel is made of a metal, a ceramic material, or a silicon material.

[0074] In some embodiments, the thermally conductive layer 106 may cover the top surface of the topmost die, such that the thermally conductive layer 106 is in contact with each first channel 182. The material of the thermally conductive layer 106 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of the thermally conductive layer 106 is one of a metal, a ceramic material, or a silicon material. In some embodiments, the material of each first channel may be one of silicon nitride, alumina, and silicon carbide.

[0075] In some embodiments, the ball grid array (BGA) 130 may include a plurality of solder balls 132 / 135 attached to a second side of the interposer opposite to the first side. The BGA 130 may include a plurality of thermal solder balls 132 configured to deliver heat and a plurality of signal solder balls 135 configured to transmit electronic signals.

[0076] In some embodiments, the hot solder ball 132 and the signal solder ball 135 may comprise the same material and may be formed in the same process. For example, the hot solder ball 132 and the signal solder ball 135 may comprise any suitable metallic material (e.g., aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc.), and any suitable alloys thereof. In some other embodiments, the hot solder ball 132 and the signal solder ball 135 may comprise different materials. For example, the hot solder ball 132 may comprise a first material having a high thermal conductivity, while the signal solder ball 135 may comprise a second material having a high electrical conductivity.

[0077] Figure 1B A schematic diagram of a second exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 1B As shown, semiconductor device 100B may include an interposer 120, a substrate die 140 located on a first side of the interposer 120, stacked dies 110 located on the first side of the substrate die 140, and a ball grid array (BGA) 130 located on a second side of the interposer 120 opposite to the first side. It should be noted that semiconductor device 100B may also include... Figure 1B Any other suitable components not shown. For example, the semiconductor device may also include a printed circuit board (PCB) on which the semiconductor device 100B is mounted via a BGA 130.

[0078] Interposer 120 can be any suitable semiconductor material having any suitable structure, such as a single-crystal monolayer, a polycrystalline silicon (polysilicon) monolayer, a polycrystalline silicon and metal multilayer, etc. Interposer 120 may include interconnect structures 124, including a first interconnect structure 126 and a second interconnect structure 128 embedded in interposer 120. The first interconnect structure 126 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The second interconnect structure 128 may include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second interconnect structure 128 may be configured to transmit both electronic signals and heat. The first interconnect structure 126 and the second interconnect structure 128 may be isolated from each other.

[0079] In some embodiments, the first connection structure 126 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second connection structure 128 may include any suitable electrically conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art.

[0080] The substrate die 140 may include a wiring structure 144, which includes a first wiring structure 146 and a second wiring structure 148 embedded in the substrate die. The first wiring structure 146 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers) and is configured to transport heat. The second wiring structure 148 may include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second wiring structure 148 may be configured to transmit both electronic signals and heat. In some embodiments, the first wiring structure 146 is physically connected to a first connection structure 126, and the second wiring structure 148 is physically connected to a second connection structure 128. The first wiring structure 146 and the second wiring structure 148 may be isolated from each other.

[0081] In some embodiments, the first wiring structure 146 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second wiring structure 148 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the first wiring structure 146 and the second wiring width of the second wiring structure 148 may be in the range of approximately 1.5:1 to approximately 2:1.

[0082] The stacked dies 110 may include a plurality of dies vertically stacked by direct bonding, which forms a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive). The stacked dies are attached to a first side of a substrate die 140 via an adhesive film (not shown). Exemplarily, the stacked dies 110 includes dies 102, 103, 104, and 105. In some embodiments, the stacked dies 110 may be any (multiple / one) suitable semiconductor die including one or more memory dies. The stacked dies 110 may include low-power chips with a maximum operating power below a threshold power value. The stacked dies may include high-power chips with a maximum operating power above a threshold power value. For example, the stacked dies 110 may include at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and may also include at least one of a memory chip and a sensing chip. In some embodiments, the adhesive film may be any suitable die attachment film (DAF).

[0083] In some embodiments, the semiconductor device includes a first contact structure 180 extending vertically within a stack of dies. The first contact structure may include one or more first channels 182, each first channel 182 being a continuous channel having a first end connected to a first wiring structure 146 and a second end contacting the top surface of the topmost die in the stack. The first end of each first channel 182 has a first lateral dimension (e.g., in the x-direction), and the second end of each first channel 182 has a second lateral dimension (e.g., in the x-direction), with the first lateral dimension being larger than the second lateral dimension. In some embodiments, the first lateral dimension is approximately 2-3 μm. In some embodiments, the material of each first channel has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of each first channel is one of a metal, a ceramic material, or a silicon material. In some embodiments, the material of each first channel may be one of silicon nitride, alumina, and silicon carbide.

[0084] In some embodiments, the semiconductor device includes a second contact structure 185 extending vertically within a stack of dies. The second contact structure 185 may be sandwiched between two first contact structures 180 (e.g., Figure 5A (as shown), or can be surrounded by the first contact structure 180 (as shown). Figure 5B (As shown). The second contact structure 185 may include a plurality of second channels, and each second channel of the second contact structure 185 is a continuous channel having a first end that contacts the second wiring structure 148 and a second end located inside the stacked dies that does not contact the top surface of the topmost die in the stack. The first end of each second channel 185 has a third lateral dimension (e.g., in the x-direction), and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel. In some embodiments, the third lateral dimension is less than 2 μm. In some embodiments, the plurality of second channels have different dimensions along the vertical direction. For example, second channel 185-1 has a first end that contacts the second wiring structure 148 and a second end located inside die 105 that does not contact the top surface of die 105; second channel 185-2 has a first end that contacts the second wiring structure 148 and a second end located inside die 104 that does not contact the top surface of die 104; second channel 185-3 has a first end that contacts the second wiring structure 148 and a second end located inside die 103 that does not contact the top surface of die 103; and second channel 185-4 has a first end that contacts the second wiring structure 148 and a second end located inside die 102 that does not contact the top surface of die 102. In some embodiments, each second channel is made of a metal, a ceramic material, or a silicon material.

[0085] In some embodiments, the ball grid array (BGA) 130 may include a plurality of solder balls 132 / 135 attached to a second side of the interposer opposite to the first side. The BGA 130 may include a plurality of thermal solder balls 132 in contact with a first connection structure 126 and a plurality of signal solder balls 135 in contact with a second connection structure 128. That is, the thermal solder balls 132 may be coupled to the first contact structure 180 via the first wiring structure 146 and the first connection structure 126, and are configured to dissipate heat in the stacked dies. The signal solder balls 135 may be coupled to the second contact structure 185 via the second wiring structure 148 and the second connection structure 128, and are configured to transmit electronic signals between the stacked dies and the PCB.

[0086] In some embodiments, the hot solder ball 132 and the signal solder ball 135 may comprise the same material and may be formed in the same process. For example, the hot solder ball 132 and the signal solder ball 135 may comprise any suitable metallic material (e.g., aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc.), and any suitable alloys thereof. In some other embodiments, the hot solder ball 132 and the signal solder ball 135 may comprise different materials. For example, the hot solder ball 132 may comprise a first material having a high thermal conductivity, while the signal solder ball 135 may comprise a second material having a high electrical conductivity.

[0087] Figure 1C A schematic diagram of a third exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 1C As shown, semiconductor device 100C may include an interposer 120, a substrate die 140 located on a first side of the interposer 120, stacked dies 110 located on the first side of the substrate die 140, and a ball grid array (BGA) 130 located on a second side of the interposer 120 opposite to the first side. It should be noted that semiconductor device 100C may also include... Figure 1C Any other suitable components not shown. For example, the semiconductor device may also include a printed circuit board (PCB) on which the semiconductor device 100C is mounted via a BGA 130.

[0088] Interposer 120 can be any suitable semiconductor material having any suitable structure, such as a single-crystal monolayer, a polycrystalline silicon (polysilicon) monolayer, a polycrystalline silicon and metal multilayer, etc. Interposer 120 may include interconnect structures 124, including a first interconnect structure 126 and a second interconnect structure 128 embedded in interposer 120. The first interconnect structure 126 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The second interconnect structure 128 may include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second interconnect structure 128 may be configured to transmit both electronic signals and heat. The first interconnect structure 126 and the second interconnect structure 128 may be isolated from each other.

[0089] In some embodiments, the first connection structure 126 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second connection structure 128 may include any suitable electrically conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art.

[0090] The substrate die 140 may include a wiring structure 144, which includes a first wiring structure 146 and a second wiring structure 148 embedded in the substrate die. The first wiring structure 146 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers) and is configured to transport heat. The second wiring structure 148 may include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second wiring structure 148 may be configured to transmit both electronic signals and heat. In some embodiments, the first wiring structure 146 is physically connected to a first connection structure 126, and the second wiring structure 148 is physically connected to a second connection structure 128. The first wiring structure 146 and the second wiring structure 148 may be isolated from each other.

[0091] In some embodiments, the first wiring structure 146 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second wiring structure 148 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the first wiring structure 146 and the second wiring width of the second wiring structure 148 may be in the range of approximately 1.5:1 to approximately 2:1.

[0092] The stacked dies 110 may include a plurality of dies vertically stacked by direct bonding, which forms a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive). The stacked dies 110 may be attached to a first side of a substrate die 140 via an adhesive film (not shown). Exemplarily, the stacked dies 110 includes dies 102, 103, 104, and 105. In some embodiments, the stacked dies 110 may be any (multiple / one) suitable semiconductor die including one or more memory dies. The stacked dies may include low-power chips with a maximum operating power below a threshold power value. The stacked dies may include high-power chips with a maximum operating power above a threshold power value. For example, the stacked dies 110 may include at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and may also include at least one of a memory chip and a sensing chip. In some embodiments, the adhesive film may be any suitable die attachment film (DAF).

[0093] In some embodiments, the semiconductor device includes a first contact structure 180 extending vertically within a stack of dies. The first contact structure may include one or more first channels 182, each first channel 182 being a continuous channel having a first end connected to a first wiring structure 146 and a second end contacting the top surface of the topmost die in the stack. The first end of each first channel 182 has a first lateral dimension (e.g., in the x-direction), and the second end of each first channel 182 has a second lateral dimension (e.g., in the x-direction), with the first lateral dimension being larger than the second lateral dimension. In some embodiments, the first lateral dimension is approximately 2-3 μm. In some embodiments, the material of each first channel has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of each first channel is one of a metal, a ceramic material, or a silicon material. In some embodiments, the material of each first channel may be one of silicon nitride, alumina, and silicon carbide.

[0094] In some embodiments, the semiconductor device includes a second contact structure 185 extending vertically within a stack of dies. The second contact structure 185 may be sandwiched between two first contact structures 180 (e.g., Figure 5A (as shown), or can be surrounded by the first contact structure 180 (as shown). Figure 5B (As shown). The second contact structure 185 may include a plurality of second channels, and each second channel of the second contact structure 185 is a continuous channel having a first end that contacts the second wiring structure 148 and a second end located inside the stacked dies that does not contact the top surface of the topmost die in the stack. The first end of each second channel 185 has a third lateral dimension (e.g., in the x-direction), and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel. In some embodiments, the third lateral dimension is less than 2 μm. In some embodiments, the plurality of second channels have different dimensions along the vertical direction. For example, second channel 185-1 has a first end that contacts the second wiring structure 148 and a second end located inside die 105 that does not contact the top surface of die 105; second channel 185-2 has a first end that contacts the second wiring structure 148 and a second end located inside die 104 that does not contact the top surface of die 104; second channel 185-3 has a first end that contacts the second wiring structure 148 and a second end located inside die 103 that does not contact the top surface of die 103; and second channel 185-4 has a first end that contacts the second wiring structure 148 and a second end located inside die 102 that does not contact the top surface of die 102. In some embodiments, each second channel is made of a metal, a ceramic material, or a silicon material.

[0095] In some embodiments, the thermally conductive layer 106 may cover the top surface of the topmost die, such that the thermally conductive layer 106 is in contact with each first channel. The material of the thermally conductive layer 106 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of the thermally conductive layer 106 is one of a metal, a ceramic material, or a silicon material.

[0096] In some embodiments, the ball grid array (BGA) 130 may include a plurality of solder balls 132 / 135 attached to a second side of the interposer opposite to the first side. The BGA 130 may include a plurality of thermal solder balls 132 in contact with a first connection structure 126 and a plurality of signal solder balls 135 in contact with a second connection structure 128. That is, the thermal solder balls 132 may be coupled to the first contact structure 180 via the first wiring structure 146 and the first connection structure 126, and are configured to dissipate heat in the stacked dies. The signal solder balls 135 may be coupled to the second contact structure 185 via the second wiring structure 148 and the second connection structure 128, and are configured to transmit electronic signals between the stacked dies and the PCB.

[0097] In some embodiments, the hot solder ball 132 and the signal solder ball 135 may comprise the same material and may be formed in the same process. For example, the hot solder ball 132 and the signal solder ball 135 may comprise any suitable metallic material (e.g., aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc.), and any suitable alloys thereof. In some other embodiments, the hot solder ball 132 and the signal solder ball 135 may comprise different materials. For example, the hot solder ball 132 may comprise a first material having a high thermal conductivity, while the signal solder ball 135 may comprise a second material having a high electrical conductivity.

[0098] refer to Figure 6 A flowchart illustrating an exemplary method for forming a first semiconductor device according to some embodiments of the present disclosure is shown. It should be understood that... Figure 6 The operations and / or steps shown are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Figures 2A-2F An exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 6 A schematic diagram of a specific manufacturing step in the method shown.

[0099] like Figure 6As shown, method 600 begins with operation 602, in which a plurality of dies are stacked vertically. A first contact structure is formed in the stacked dies. The first contact structure includes a plurality of first channels, each of the plurality of first channels extending vertically through the stacked dies. Figures 2A-2C An exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 6 A schematic diagram of operation 602 of method 600 shown.

[0100] like Figure 2A As shown, in some embodiments, multiple dies are stacked vertically on carrier wafer 215 by direct bonding (bonding between their forming surfaces without the use of intermediate layers (e.g., solder or adhesive)). Exemplarily, as... Figure 2A As shown, dies 202, 203, 204, and 205 are vertically stacked on a carrier wafer 215 by direct bonding (bonding between their forming surfaces without the use of an intermediate layer (e.g., solder or adhesive)) to form a stacked die 210. In some embodiments, the stacked die 210 may be any (multiple / one) suitable semiconductor die including one or more memory dies. The stacked die 210 may include low-power chips with a maximum operating power below a threshold power value. The stacked die 210 may include high-power chips with a maximum operating power above a threshold power value. For example, the stacked die 210 includes at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and may also include at least one of a memory chip and a sensing chip.

[0101] like Figure 2B As shown, in some embodiments, a sacrificial layer 212 is deposited on a first surface of the stacked dies, and a plurality of first vias 270 are formed in the sacrificial layer 212 and extend vertically through the stacked dies 210. In some embodiments, a carrier wafer 215 is removed before the sacrificial layer 212 is formed. In some embodiments, the carrier wafer 215 is used as the sacrificial layer 212, and a plurality of first vias 270 are formed in the carrier wafer 215. A photolithography process can be performed to pattern the first vias using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed to etch the first vias in the sacrificial layer 212. Thus, first vias 270 extending vertically in the sacrificial layer 212 can be formed.

[0102] like Figure 2BAs shown, in some embodiments, a plurality of second holes 272 are formed in the sacrificial layer 212 and extend vertically within the stacked die 210. A photolithography process can be performed to pattern the second holes using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed to etch the second holes in the sacrificial layer 212. Thus, second holes 272 extending vertically in the sacrificial layer 212 can be formed. In some embodiments, the plurality of second holes 272 have different dimensions along the vertical direction. The vertical dimensions of the second holes can be controlled by etching each second hole for different durations or by backfilling the second holes to achieve a specific vertical dimension. In some embodiments, the formation of the second holes 272 can be performed in the same process as the formation of the first holes 270. The lateral dimension (e.g., in the x-direction) of each first hole 270 is larger than the lateral dimension (e.g., in the x-direction) of each second hole 272. In some embodiments, the second hole 272 may be sandwiched between two sets of first holes 270, or the second hole 272 may be surrounded by a plurality of first holes 270.

[0103] like Figure 2C As shown, in some embodiments, a first contact structure 280 including a plurality of first channels 282 is formed inside a plurality of first holes 270, for example, by depositing a metal, ceramic, or silicon material using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Each first channel 282 is a continuous channel extending through the stacked dies. That is, each first channel 282 has a first end contacting the bottom surface of the bottommost die in the stack and a second end contacting the top surface of the topmost die. The first end of each first channel 282 has a first lateral dimension (e.g., in the x-direction), and the second end of each first channel 282 has a second lateral dimension (e.g., in the x-direction), and the first lateral dimension is larger than the second lateral dimension. In some embodiments, the first lateral dimension of each first channel 282 is approximately 2-3 μm. The material of each first channel 282 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of each first channel is one of a metal, a ceramic, or a silicon material. In some implementations, the material of each first channel may be one of silicon nitride, aluminum oxide, and silicon carbide. A planarization process (e.g., CMP) is performed to remove excess first channels 282 deposited outside the top surface of the topmost die.

[0104] In some implementations, such as Figure 2CAs shown, a second contact structure 285 comprising multiple second channels can be formed within multiple second holes 272, for example, by depositing metal, ceramic, or silicon material using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Each second channel is a continuous channel extending vertically within the stacked dies. That is, each second channel has a first end contacting the bottom surface of the bottommost die and a second end located within the stacked dies that does not contact the top surface of the topmost die. The first end of each second channel of the second contact structure 285 has a third lateral dimension (e.g., in the x-direction), and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel 282. In some embodiments, the third lateral dimension is less than 2 μm. In some embodiments, the multiple second channels have different dimensions along the vertical direction. For example, second channel 285-1 has a first end that contacts the bottom surface of die 202 and a second end located inside die 202 that does not contact the top surface of die 202; second channel 285-2 has a first end that contacts the bottom surface of die 202 and a second end located inside die 203 that does not contact the top surface of die 203; second channel 285-3 has a first end that contacts the bottom surface of die 202 and a second end located inside die 203 that does not contact the top surface of die 203; and second channel 285-4 has a first end that contacts the top surface of die 202 and a second end located inside die 205 that does not contact the top surface of die 205. In some embodiments, each second channel is made of a metal, a ceramic material, or a silicon material.

[0105] In some embodiments, the first contact structure 280 and the second contact structure 285 are formed in the same process; or the first contact structure 280 and the second contact structure 285 may be formed in different processes. The first contact structure 280 and the second contact structure 285 may be made of the same material; or the first contact structure 280 and the second contact structure 285 may be made of different materials. In some embodiments, the first channel 282 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second channel 285-1 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some implementations, the ratio between the first width of the first channel 282 and the second width of the second channel 285-1 can be in the range of approximately 1.5:1 to approximately 2:1.

[0106] The first contact structure 280 and the second contact structure 285 can then be polished so that the surfaces of the first contact structure 280 and the second contact structure 285 are flush with the bottom surface of the die 202. In some embodiments, chemical mechanical polishing (CMP) is performed to polish the first contact structure 280 and the second contact structure 285.

[0107] Return to reference Figure 6 Method 600 can proceed to operation 604, in which the substrate die is bonded to the stacked dies. Figure 2D A perspective side view illustrates some embodiments of the present disclosure. Figure 6 A schematic diagram of an exemplary semiconductor device following operation 604 of method 600 shown.

[0108] like Figure 2DAs shown, the substrate die 240 can be bonded to the first surface (bottom surface) of the stacked die 210 via hybrid bonding or direct bonding, such that the surface of the substrate die 240 contacts the first end of each first channel 282 of the first contact structure 280 and the first end of each second channel of the second contact structure 285. The substrate die 240 can be bonded to the stacked die 210 via hybrid bonding or direct bonding, which is not limited herein. The substrate die 240 may be provided with a wiring structure 244, which includes a first wiring structure 246 and a second wiring structure 248 embedded in the substrate die. The first wiring structure 246 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The first wiring structure 246 is physically connected to the first contact structure 280. For example, as Figure 2D As shown, the first wiring structure is physically connected to the first channel 282. The second wiring structure 248 is physically connected to the second contact structure 285. For example, as... Figure 2D As shown, the second wiring structure is physically connected to the second channel 285-1. The second wiring structure 248 may include any suitable conductive interconnect structure (e.g., a conductive channel) and is configured to transmit electronic signals. In some embodiments, the second wiring structure 248 may be configured to transmit both electronic signals and heat. The first wiring structure 246 and the second wiring structure 248 may be isolated from each other.

[0109] In some embodiments, the first wiring structure 246 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second wiring structure 248 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the first wiring structure 246 and the second wiring width of the second wiring structure 248 may be in the range of approximately 1.5:1 to approximately 2:1.

[0110] Return to reference Figure 6 Method 600 can proceed to operation 606, in which the interlayer is bonded to the substrate die. Figure 2E A perspective side view illustrates some embodiments of the present disclosure. Figure 6 A schematic diagram of an exemplary semiconductor device following operation 606 of method 600 shown.

[0111] like Figure 2E As shown, the interposer 220 can be bonded to the surface (bottom surface) of the substrate die 240, such that the surface of the interposer 220 contacts the wiring structure 244. The interposer 220 can be bonded to the substrate die 240 by hybrid bonding or direct bonding, which is not limited herein. The interposer 220 can be any suitable semiconductor material having any suitable structure, such as a single-crystal monolayer material, a polycrystalline silicon monolayer material, a polycrystalline silicon and metal multilayer material, etc. In some embodiments, the interposer 220 is provided with a ball grid array (BGA) 230.

[0112] Return to reference Figure 6 Method 600 can proceed to operation 608, wherein a thermally conductive layer is formed on the second surface (top surface) of the stacked dies. The second surface of the stacked dies is opposite to the first surface of the stacked dies in the vertical direction. Figure 2F A perspective side view illustrates some embodiments of the present disclosure. Figure 6 A schematic diagram of an exemplary semiconductor device following operation 608 of the method 600 shown.

[0113] like Figure 2F As shown, the thermally conductive layer 206 can be formed by depositing a thermally conductive material to cover the top surface of the topmost die in the stacked dies 210, such that the thermally conductive layer 206 contacts each first channel 282. The material of the thermally conductive layer 206 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of the thermally conductive layer 206 is one of a metal, a ceramic material, or a silicon material. In some embodiments, the material of each first channel may be one of silicon nitride, alumina, and silicon carbide.

[0114] refer to Figure 7 A flowchart illustrating an exemplary method for forming a second semiconductor device according to some embodiments of the present disclosure is shown. It should be understood that... Figure 7 The operations and / or steps shown are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Figures 3A-3F An exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 7 A schematic diagram of a specific manufacturing step in the method shown.

[0115] like Figure 7 As shown, method 700 begins with operation 702, in which a plurality of dies are stacked vertically. A first contact structure is formed in the stacked dies. The first contact structure includes a plurality of first channels, each of the plurality of first channels extending vertically through the stacked dies. Figures 3A-3C An exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 7 The diagram shows a schematic of operation 702 of method 700.

[0116] like Figure 3A As shown, in some embodiments, multiple dies are stacked vertically on carrier wafer 315 by direct bonding (bonding between their forming surfaces without the use of intermediate layers (e.g., solder or adhesive)). Exemplarily, as... Figure 3A As shown, dies 302, 303, 304, and 305 are vertically stacked on a carrier wafer 315 to form a stacked die 310. In some embodiments, the stacked die 310 may be any (multiple / one) suitable semiconductor die including one or more memory dies. The stacked die 310 may include low-power chips with a maximum operating power below a threshold power value. The stacked die 310 may include high-power chips with a maximum operating power above a threshold power value. For example, the stacked die 310 includes at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and may also include at least one of a memory chip and a sensing chip.

[0117] like Figure 3B As shown, in some embodiments, a sacrificial layer 312 is deposited on a first surface of the stacked dies 310, and a plurality of first vias 370 are formed in the sacrificial layer 312 and extend vertically through the stacked dies 310. In some embodiments, a carrier wafer 315 is removed before the sacrificial layer 312 is formed. In some embodiments, the carrier wafer 315 is used as the sacrificial layer 312, and a plurality of first vias 270 are formed in the carrier wafer 315. A photolithography process can be performed to pattern the first vias using an etch mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed to etch the first vias 370 in the sacrificial layer 312. Thus, first vias 370 extending vertically in the sacrificial layer 312 can be formed.

[0118] like Figure 3BAs shown, in some embodiments, a plurality of second vias 372 are formed in the sacrificial layer 312 and extend vertically within the stacked die 310. A photolithography process can be performed to pattern the second vias 372 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed to etch the second vias 372 in the sacrificial layer 312. Thus, second vias 372 extending vertically in the sacrificial layer 312 can be formed. In some embodiments, the plurality of second vias 372 have different dimensions along the vertical direction. The vertical dimensions of the second vias 372 can be controlled by etching each second via 372 for different durations or by backfilling the second vias 372 to achieve a specific vertical dimension. In some embodiments, the formation of the second vias 372 can be performed in the same process as the formation of the first vias 370. The lateral dimension (e.g., in the x-direction) of each first via 370 is greater than the lateral dimension (e.g., in the x-direction) of each second via 372. In some embodiments, the second hole 372 may be sandwiched between two sets of first holes 370, or the second hole 372 may be surrounded by a plurality of first holes 370.

[0119] like Figure 3C As shown, in some embodiments, a first contact structure 380 including a plurality of first channels 382 is formed inside a plurality of first holes 370, for example, by depositing a metal, ceramic, or silicon material using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Each first channel 382 is a continuous channel extending through the stacked dies 310. That is, each first channel 382 has a first end contacting the bottom surface of the bottommost die in the stacked dies 310 and a second end contacting the top surface of the topmost die. The first end of each first channel 382 has a first lateral dimension (e.g., in the x-direction), and the second end of each first channel 382 has a second lateral dimension (e.g., in the x-direction), and the first lateral dimension is larger than the second lateral dimension. In some embodiments, the first lateral dimension is approximately 2-3 μm. The material of each first channel 382 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of each first channel 382 is one of a metal, a ceramic, or a silicon material. In some implementations, the material of each first channel 382 may be one of silicon nitride, aluminum oxide, and silicon carbide. A planarization process (e.g., CMP) may be performed to remove excess first channels 382 deposited outside the top surface of the topmost die.

[0120] In some implementations, such as Figure 3CAs shown, a second contact structure 385 comprising multiple second channels can be formed within multiple second holes 372, for example, by depositing metal, ceramic, or silicon material using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Each second channel is a continuous channel extending vertically within the stacked dies 310. That is, each second channel has a first end contacting the bottom surface of the bottommost die and a second end located within the stacked dies that does not contact the top surface of the topmost die in the stack. The first end of each second channel of the second contact structure 385 has a third lateral dimension (e.g., in the x-direction), and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel. In some embodiments, the third lateral dimension is less than 2 μm. In some embodiments, the multiple second channels have different dimensions along the vertical direction. For example, second channel 385-1 has a first end that contacts the bottom surface of die 302 and a second end located inside die 302 that does not contact the top surface of die 302; second channel 385-2 has a first end that contacts the bottom surface of die 302 and a second end located inside die 303 that does not contact the top surface of die 303; second channel 385-3 has a first end that contacts the bottom surface of die 302 and a second end located inside die 303 that does not contact the top surface of die 303; and second channel 385-4 has a first end that contacts the top surface of die 302 and a second end located inside die 305 that does not contact the top surface of die 305. In some embodiments, each second channel is made of a metal, a ceramic material, or a silicon material.

[0121] In some embodiments, the first contact structure 380 and the second contact structure 385 are formed in the same process; or the first contact structure 380 and the second contact structure 385 may be formed in different processes. The first contact structure 380 and the second contact structure 385 may be made of the same material; or the first contact structure 380 and the second contact structure 385 may be made of different materials. In some embodiments, the first channel 382 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second channel 385-1 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some implementations, the ratio between the first width of the first channel 382 and the second width of the second channel 385-1 can be in the range of approximately 1.5:1 to approximately 2:1.

[0122] The first contact structure 380 and the second contact structure 385 can then be polished so that the surfaces of the first contact structure 380 and the second contact structure 385 are flush with the bottom surface of the die 302. In some embodiments, chemical mechanical polishing (CMP) is performed to polish the first contact structure 380 and the second contact structure 385.

[0123] Return to reference Figure 7 Method 700 can proceed to operation 704, in which the substrate die is bonded to the stacked dies. Figure 3D A perspective side view illustrates some embodiments of the present disclosure. Figure 7 A schematic diagram of an exemplary semiconductor device following operation 704 of the method 700 shown.

[0124] like Figure 3DAs shown, the substrate die 340 can be bonded to the first surface (bottom surface) of the stacked die 310 via hybrid bonding or direct bonding, such that the surface of the substrate die 340 contacts the first end of each first channel 382 of the first contact structure 380 and the first end of each second channel of the second contact structure 385. The substrate die 340 can be bonded to the stacked die 310 via hybrid bonding or direct bonding, which is not limited herein. The substrate die 340 may be provided with a wiring structure 344, which includes a first wiring structure 346 and a second wiring structure 348 embedded in the substrate die 340. The first wiring structure 346 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The first wiring structure 346 is physically connected to the first contact structure 380. For example, as Figure 3D As shown, the first wiring structure 346 is physically connected to the first channel 382. The second wiring structure 348 is physically connected to the second contact structure 385. For example, as... Figure 3D As shown, the second wiring structure 348 is physically connected to the second channel 385-1. The second wiring structure 348 may include any suitable conductive interconnect structure (e.g., a conductive channel) and is configured to transmit electronic signals. In some embodiments, the second wiring structure 348 may be configured to transmit both electronic signals and heat. The first wiring structure 346 and the second wiring structure 348 may be isolated from each other.

[0125] In some embodiments, the first wiring structure 346 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second wiring structure 348 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the first wiring structure 346 and the second wiring width of the second wiring structure 348 may be in the range of approximately 1.5:1 to approximately 2:1.

[0126] Return to reference Figure 7 Method 700 can proceed to operation 706, in which the interlayer is bonded to the substrate die. Figure 3E A perspective side view illustrates some embodiments of the present disclosure. Figure 7 A schematic diagram of an exemplary semiconductor device following operation 706 of the method 700 shown.

[0127] like Figure 3E As shown, the interposer 320 can be bonded to the surface (bottom surface) of the substrate die 340, such that the surface of the interposer 320 contacts the wiring structure 344. The interposer 320 can be bonded to the substrate die 340 by hybrid bonding or direct bonding, which is not limited herein. The interposer 320 can be any suitable semiconductor material having any suitable structure, such as a single-crystal monolayer material, a polycrystalline silicon (polysilicon) monolayer material, a polycrystalline silicon and metal multilayer material, etc. The interposer 320 can be provided with interconnect structures 324, including a first interconnect structure 326 and a second interconnect structure 328 embedded in the interposer 320. The first interconnect structure 326 can include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The second interconnect structure 328 can include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second interconnect structure 328 can be configured to transmit both electronic signals and heat. The first connecting structure 326 and the second connecting structure 328 can be isolated from each other.

[0128] Return to reference Figure 7 Method 700 can proceed to operation 708, wherein a ball grid array (BGA) is formed on the side of the interlayer opposite to the substrate die. Figure 3F A perspective side view illustrates some embodiments of the present disclosure. Figure 7 A schematic diagram of an exemplary semiconductor device following operation 708 of the method 700 shown.

[0129] like Figure 7 As shown in Figure F, a ball grid array (BGA) 330 is formed on the side of the interposer 320 opposite to the substrate die 340. The BGA 330 includes thermal solder balls 332 physically connected to a first connection structure 326 and signal solder balls 335 physically connected to a second connection structure 328. The thermal solder balls 332 and signal solder balls 335 may comprise the same material and may be formed in the same process. For example, the thermal solder balls 332 and signal solder balls 335 may comprise any suitable metallic material (e.g., aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc.), and any suitable alloys thereof. In some other embodiments, the thermal solder balls 332 and signal solder balls 335 may comprise different materials. For example, the hot solder ball 332 may include a first material with high thermal conductivity, while the signal solder ball 335 may include a second material with high electrical conductivity.

[0130] refer to Figure 8 A flowchart illustrating an exemplary method for forming a third semiconductor device according to some embodiments of the present disclosure is shown. It should be understood that... Figure 8 The operations and / or steps shown are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Figures 4A-4G An exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 8 A schematic diagram of a specific manufacturing step in the method shown.

[0131] like Figure 8 As shown, method 800 begins with operation 802, in which a plurality of dies are stacked vertically. A first contact structure is formed in the stacked dies. The first contact structure includes a plurality of first channels, each of the plurality of first channels extending vertically through the stacked dies. Figures 4A-4C An exemplary semiconductor device according to some embodiments of the present disclosure is shown in a perspective side view. Figure 8 The diagram shows a schematic of operation 802 of method 800.

[0132] like Figure 4A As shown, in some embodiments, multiple dies are stacked vertically on carrier wafer 415 by direct bonding (bonding between their forming surfaces without the use of intermediate layers (e.g., solder or adhesive)). Exemplarily, as... Figure 4A As shown, dies 402, 403, 404, and 405 are vertically stacked on a carrier wafer 415 to form a stacked die 410. In some embodiments, the stacked die 410 may be any (multiple / one) suitable semiconductor die including one or more memory dies. The stacked die 410 may include low-power chips with a maximum operating power below a threshold power value. The stacked die 410 may include high-power chips with a maximum operating power above a threshold power value. For example, the stacked die 410 includes at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and may also include at least one of a memory chip and a sensing chip.

[0133] like Figure 4BAs shown, in some embodiments, a sacrificial layer 412 is deposited on a first surface of the stacked dies 410, and a plurality of first vias 470 are formed in the sacrificial layer 412 and extend vertically through the stacked dies 410. In some embodiments, a carrier wafer 415 is removed prior to the formation of the sacrificial layer 412. In some embodiments, the carrier wafer 415 is used as the sacrificial layer 412, and a plurality of first vias 470 are formed in the carrier wafer 415. A photolithography process can be performed to pattern the first vias using an etch mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed to etch the first vias 470 in the sacrificial layer 412. Thus, first vias 470 extending vertically in the sacrificial layer 412 can be formed.

[0134] like Figure 4B As shown, in some embodiments, a plurality of second vias 472 are formed in the sacrificial layer 412 and extend vertically within the stacked die 410. A photolithography process can be performed to pattern the second vias 472 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed to etch the second vias 472 in the sacrificial layer 412. Thus, second vias 472 extending vertically in the sacrificial layer 412 can be formed. In some embodiments, the plurality of second vias 472 have different dimensions along the vertical direction. The vertical dimensions of the second vias 472 can be controlled by etching each second via 472 for different durations or by backfilling the second vias 472 to achieve a specific vertical dimension. In some embodiments, the formation of the second vias 472 can be performed in the same process as the formation of the first vias 470. The lateral dimension (e.g., in the x-direction) of each first via 470 is greater than the lateral dimension (e.g., in the x-direction) of each second via 472. In some embodiments, the second hole 472 may be sandwiched between two sets of first holes 470, or the second hole 472 may be surrounded by a plurality of first holes 470.

[0135] like Figure 4CAs shown, in some embodiments, a first contact structure 480 including a plurality of first channels 482 is formed inside a plurality of first holes 470, for example, by depositing a metal, ceramic, or silicon material using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Each first channel 482 is a continuous channel extending through the stacked dies 410. That is, each first channel 482 has a first end contacting the bottom surface of the bottommost die in the stacked dies 410 and a second end contacting the top surface of the topmost die. The first end of each first channel 482 has a first lateral dimension (e.g., in the x-direction), and the second end of each first channel 482 has a second lateral dimension (e.g., in the x-direction), and the first lateral dimension is larger than the second lateral dimension. In some embodiments, the first lateral dimension is approximately 2-3 μm. The material of each first channel 482 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of each first channel 482 is one of a metal, a ceramic, or a silicon material. In some implementations, the material of each first channel 482 may be one of silicon nitride, aluminum oxide, and silicon carbide. A planarization process (e.g., CMP) may be performed to remove excess first channels 482 deposited outside the top surface of the topmost die.

[0136] In some implementations, such as Figure 4CAs shown, a second contact structure 485 comprising multiple second channels can be formed within multiple second holes 472, for example, by depositing metal, ceramic, or silicon material using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Each second channel is a continuous channel extending vertically within the stacked dies 410. That is, each second channel has a first end contacting the bottom surface of the bottommost die and a second end located within the stacked dies that does not contact the top surface of the topmost die in the stack. The first end of each second channel of the second contact structure 485 has a third lateral dimension (e.g., in the x-direction), and the third lateral dimension is smaller than the first lateral dimension of the first end of each first channel. In some embodiments, the third lateral dimension is less than 2 μm. In some embodiments, the multiple second channels have different dimensions along the vertical direction. For example, second channel 485-1 has a first end that contacts the bottom surface of die 402 and a second end located inside die 402 that does not contact the top surface of die 402; second channel 485-2 has a first end that contacts the bottom surface of die 402 and a second end located inside die 403 that does not contact the top surface of die 403; second channel 485-3 has a first end that contacts the bottom surface of die 402 and a second end located inside die 403 that does not contact the top surface of die 403; and second channel 485-4 has a first end that contacts the top surface of die 402 and a second end located inside die 405 that does not contact the top surface of die 405. In some embodiments, each second channel is made of a metal, a ceramic material, or a silicon material.

[0137] In some embodiments, the first contact structure 480 and the second contact structure 485 are formed in the same process; or the first contact structure 480 and the second contact structure 485 may be formed in different processes. The first contact structure 480 and the second contact structure 485 may be made of the same material; or the first contact structure 480 and the second contact structure 485 may be made of different materials. In some embodiments, the first channel 482 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second channel 485-1 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some implementations, the ratio between the first width of the first channel 482 and the second width of the second channel 485-1 can be in the range of approximately 1.5:1 to approximately 2:1.

[0138] The first contact structure 480 and the second contact structure 485 can then be polished so that the surfaces of the first contact structure 480 and the second contact structure 485 are flush with the bottom surface of the die 402. In some embodiments, chemical mechanical polishing (CMP) is performed to polish the first contact structure 480 and the second contact structure 485.

[0139] Return to reference Figure 8 Method 800 can proceed to operation 804, in which the substrate die is bonded to the stacked dies. Figure 4D A perspective side view illustrates some embodiments of the present disclosure. Figure 8 A schematic diagram of an exemplary semiconductor device following operation 804 of the method 800 shown.

[0140] like Figure 4DAs shown, the substrate die 440 can be bonded to the first surface (bottom surface) of the stacked die 410 via hybrid bonding or direct bonding, such that the surface of the substrate die 440 contacts the first end of each first channel 482 of the first contact structure 480 and the first end of each second channel of the second contact structure 485. The substrate die 440 can be bonded to the stacked die 410 via hybrid bonding or direct bonding, which is not limited herein. The substrate die 440 may be provided with a wiring structure 444, which includes a first wiring structure 446 and a second wiring structure 448 embedded in the substrate die 440. The first wiring structure 446 may include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The first wiring structure 446 is physically connected to the first contact structure 480. For example, as Figure 4D As shown, the first wiring structure 446 is physically connected to the first channel 482. The second wiring structure 448 is physically connected to the second contact structure 485. For example, as... Figure 4D As shown, the second wiring structure 448 is physically connected to the second channel 485-1. The second wiring structure 448 may include any suitable conductive interconnect structure (e.g., a conductive channel) and is configured to transmit electronic signals. In some embodiments, the second wiring structure 448 may be configured to transmit both electronic signals and heat. The first wiring structure 446 and the second wiring structure 448 may be isolated from each other.

[0141] In some embodiments, the first wiring structure 446 may include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The second wiring structure 448 may include any suitable conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the first wiring structure 446 and the second wiring width of the second wiring structure 448 may be in the range of approximately 1.5:1 to approximately 2:1.

[0142] Return to reference Figure 8 Method 800 can proceed to operation 806, in which the interlayer is bonded to the substrate die. Figure 4E A perspective side view illustrates some embodiments of the present disclosure. Figure 8 A schematic diagram of an exemplary semiconductor device following operation 806 of the method 800 shown.

[0143] like Figure 4E As shown, the interposer 420 can be bonded to the surface (bottom surface) of the substrate die 440, such that the surface of the interposer 420 contacts the wiring structure 444. The interposer 420 can be bonded to the substrate die 440 by hybrid bonding or direct bonding, which is not limited herein. The interposer 420 can be any suitable semiconductor material having any suitable structure, such as a single-crystal monolayer material, a polycrystalline silicon (polysilicon) monolayer material, a polycrystalline silicon and metal multilayer material, etc. The interposer 420 can be provided with interconnect structures 424, including a first interconnect structure 426 and a second interconnect structure 428 embedded in the interposer 420. The first interconnect structure 426 can include any suitable thermally conductive interconnect structure (e.g., thermally conductive vias and patterned thermally conductive layers, etc.) and is configured to transport heat. The second interconnect structure 428 can include any suitable conductive interconnect structure (e.g., conductive channels) and is configured to transmit electronic signals. In some embodiments, the second interconnect structure 428 can be configured to transmit both electronic signals and heat. The first connecting structure 426 and the second connecting structure 328 can be isolated from each other.

[0144] Return to reference Figure 8 Method 800 can proceed to operation 808, wherein a ball grid array (BGA) is formed on the side of the interlayer opposite to the substrate die. Figure 4F A perspective side view illustrates some embodiments of the present disclosure. Figure 8 A schematic diagram of an exemplary semiconductor device following operation 808 of the method 800 shown.

[0145] like Figure 4F As shown, a ball grid array (BGA) 430 is formed on the side of the interposer layer 420 opposite to the substrate die 440. The BGA 430 includes thermal solder balls 432 physically connected to a first connection structure 426 and signal solder balls 435 physically connected to a second connection structure 428. The thermal solder balls 432 and signal solder balls 435 may comprise the same material and may be formed in the same process. For example, the thermal solder balls 432 and signal solder balls 435 may comprise any suitable metallic material (e.g., aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc.), and any suitable alloys thereof. In some other embodiments, the thermal solder balls 432 and signal solder balls 435 may comprise different materials. For example, the hot solder ball 432 may include a first material with high thermal conductivity, while the signal solder ball 435 may include a second material with high electrical conductivity.

[0146] Return to reference Figure 8 Method 800 can proceed to operation 810, wherein a thermally conductive layer is formed on the second surface (top surface) of the stacked dies. The second surface of the stacked dies is opposite to the first surface of the stacked dies in the vertical direction. Figure 4G A perspective side view illustrates some embodiments of the present disclosure. Figure 8 A schematic diagram of an exemplary semiconductor device following operation 810 of the method 800 shown.

[0147] like Figure 4G As shown, the thermally conductive layer 406 can be formed by depositing a thermally conductive material to cover the top surface of the topmost die in the stacked dies 410, such that the thermally conductive layer 406 contacts each first channel 482. The material of the thermally conductive layer 406 has a thermal conductivity of not less than 20 W / mK. In some embodiments, the material of the thermally conductive layer 406 is one of a metal, a ceramic material, or a silicon material. In some embodiments, the material of each first channel can be one of silicon nitride, alumina, and silicon carbide. In some embodiments, the thermally conductive layer 406 can include any suitable thermally conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art.

[0148] As described in International Application No. PCT / CN2024 / 078561, filed on February 26, 2024 and incorporated herein by reference, this disclosure also provides a system. Figure 9 A block diagram of an exemplary system 900 having one or more semiconductor devices (e.g., memory devices) according to some embodiments of the present disclosure is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 9As shown, system 900 may include one or more memory dies 902, a substrate device 904, a computing device 908, and an external host device 912. In some embodiments, each of devices 902, 904, 908, and 912 may be a die or multiple dies stacked together. Each of devices 902, 904, 908, and 912 may be fabricated by depositing multiple layers of various materials and etching them onto a semiconductor wafer in a complex pattern defined by a chip design. After the wafer fabrication process is completed, the wafer, including a single circuit, is diced and divided into individual blocks, each block being a die. Each die may include fully functional electronic circuitry, which may be a microprocessor, memory, sensor, or any other suitable type of integrated circuit. In some embodiments, each die is encapsulated in a protective package, thereby providing physical support, protection from environmental factors, and connectivity to external devices or systems (e.g., via pins or solder balls).

[0149] Memory die 902 may include any memory device disclosed herein, such as those based on the information disclosed herein. Figures 1A-1C , Figures 2A-2F , Figures 3A-3F and Figures 4A-4G Memory devices (e.g., 3D memory devices) of any of the described semiconductor structures. In some embodiments, memory die 902 includes one or more dynamic random access memory (DRAM) devices. In some embodiments, memory die 902 includes one or more NAND flash memory devices. In some embodiments, memory die 902 may include high bandwidth memory (HBM). In some embodiments, for example, as per [reference to...] Figures 1A-1C , Figures 2A-2F , Figures 3A-3F and Figures 4A-4G In more detail, memory dies 902 may be stacked together. In some embodiments, memory die 902 may include a combination of one or more HBM devices.

[0150] The substrate die 904 (also referred to as a logic die or buffer die) may include buffer circuitry and test logic units for the memory die 902. The substrate die 904 may be configured to provide a physical layer communication protocol (e.g., IEEE-1500) between the memory die 902 and the compute die 908. The substrate die 904 may be configured to transfer data between the memory die 902 and the compute die 908 based on commands and addresses from the compute die 908.

[0151] The computing die 908 may be a logic device and may include at least one processor of an electronic device, such as a central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC), or system-on-a-chip (SoC) (e.g., application processor (AP)). The computing die 908 may be configured to send data to or receive data from the memory die 902. The computing die 908 is coupled to the substrate die 904 via an interface (IF) 906. The interface 906 may include connections provided by bonding contacts or an interposer (e.g., as per [reference to...]). Figures 1A-1C , Figures 2A-2F , Figures 3A-3F and Figures 4A-4G (As described). In some implementations, interface 906 includes connectivity provided by any suitable combination of the foregoing techniques.

[0152] System 900 may also include an external host die 912 coupled to computing die 908 via interface (IF) 910. For example, external host die 912 may be a computer, and computing die 908 may be the CPU of the computer. In this example, interface 910 includes a connection provided by the computer's motherboard, coupled to the CPU. As another example, external host die 912 is a graphics card, computing die 908 is the GPU of the graphics card, and interface 910 includes a connection provided by the graphics card's printed circuit board (PCB), coupled to the GPU.

[0153] System 900 may also include a memory controller (also known as controller circuitry) coupled to memory die 902. Figure 9 (Not shown in the diagram). In some embodiments, the memory controller is located within the computing die 908. Consistent with embodiments of this disclosure, the memory controller may include conductive interconnects that pass through a cover layer and contact conductive pads located in a conductive pad layer, and the memory controller may be coupled to the memory die 902 via at least one of the conductive interconnects. The memory controller is configured to control the memory die 902. For example, the memory controller may be configured to operate a channel structure via word lines. The memory controller may manage data stored in the memory die 902 and communicate with the computing die 908.

[0154] In some embodiments, the memory controller is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller can be configured to control the operation of the memory die 902 (e.g., read operations, erase operations, and programming (or write) operations). The memory controller can also be configured to manage various functions regarding data stored or to be stored in the memory die 902, including but not limited to: bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller is also configured to process error correction codes (ECC) regarding data read from or written to the memory die 902. In some other implementations, the substrate die 904 (instead of the memory controller) is configured to handle ECC. The memory controller may also perform any other appropriate function, such as formatting the memory die 902.

[0155] The memory controller can communicate with external devices (e.g., the computing die 908) according to specific communication protocols. For example, the memory controller can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe or PCI-e), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0156] The memory controller and one or more memory dies 902 can be integrated into various types of storage devices, such as being included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the system 900 can be implemented and packaged into different types of end electronic products. For example, the memory controller and a single memory die 902 can be integrated into a memory card. Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0157] It should be noted that, although not shown, the above method may include any other suitable operations to further form a semiconductor device. For example, the formed semiconductor device may be attached to a printed circuit board (PCB).

[0158] This disclosure provides a semiconductor device with high thermal conductivity. In the era of powerful computing and artificial intelligence (AI), the von Neumann architecture, which combines high-bandwidth memory (HBM) with GPUs, remains mainstream in the high-performance chip market. However, the significant heat generated by stacked HBMs is a problem that urgently needs to be addressed. In traditional HBM architectures, as the number of stacked DRAM layers increases, the heat dissipation of different DRAM layers varies, which can easily lead to slow heat dissipation of the DRAM located in the middle layer, resulting in performance degradation. Because DRAM needs to perform continuous read and write operations, it is prone to generating heat during operation. The stacking structure of HBMs limits the heat dissipation of the DRAM located in the middle layer.

[0159] In the semiconductor device disclosed herein, heat generated during HBM operation can be rapidly dissipated through a first channel, thereby preventing localized overheating. The number of I / O channels can be significantly increased. The first channel has a relatively large lateral dimension, extends through the entire stacked die, does not perform data transmission functions, and acts as a heat pipe to transfer heat. Compared to the prior art, the current solution achieves better internal heat dissipation within the stacked die without increasing the HBM chip area.

[0160] The foregoing description of specific embodiments so fully reveals the general nature of this disclosure that others, by applying knowledge within the scope of the art, can readily modify and / or adapt such specific embodiments for various applications without excessive experimentation and without departing from the overall conception of this disclosure. Therefore, based on the disclosure and guidance provided herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It will be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0161] The embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined as long as the specified functions and relationships are performed appropriately.

[0162] The summary and abstract section may set forth one or more exemplary embodiments of this disclosure conceived by (multiple) inventors, but not all exemplary embodiments, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0163] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: Multiple dies, which are stacked vertically; A thermally conductive layer is deposited on the top surface of the topmost die; A base die, the base die being located on the bottom surface of the bottommost die; as well as A first contact structure extends vertically through the plurality of dies. The first contact structure includes one or more first channels, each first channel having a first end in contact with the substrate die and a second end in contact with the thermally conductive layer.

2. The semiconductor device of claim 1, further comprising a second contact structure extending vertically within the plurality of dies, wherein, The second contact structure includes one or more second channels, each extending vertically and contacting the base die without contacting the thermally conductive layer.

3. The semiconductor device according to claim 2, wherein, The substrate die includes a wiring structure, which includes a first wiring structure and a second wiring structure, wherein the first wiring structure is configured to deliver heat and the second wiring structure is configured to transmit electronic signals.

4. The semiconductor device according to claim 3, further comprising: An intermediate layer is located on the side of the substrate die opposite to the plurality of dies, wherein the intermediate layer includes a ball grid array located on the side of the intermediate layer opposite to the substrate die.

5. The semiconductor device according to claim 4, wherein, The ball grid array includes: One or more hot solder balls connected to the first wiring structure; and One or more signal solder balls connected to the second wiring structure.

6. The semiconductor device according to claim 2, wherein, Each of the first channel and the second channel is a continuous structure along the vertical direction.

7. The semiconductor device according to claim 2, wherein, The second contact structure is surrounded by the first contact structure.

8. The semiconductor device according to claim 1, wherein, The first end of each first channel has a first lateral dimension, the second end of each first channel has a second lateral dimension, and the first lateral dimension is greater than the second lateral dimension.

9. The semiconductor device according to claim 2, wherein, Each second channel has a first end in contact with the substrate die, and the first end of each second channel has a third lateral dimension, which is smaller than the first lateral dimension of the first end of each first channel.

10. The semiconductor device according to claim 9, wherein, The first lateral dimension is 2-3 μm, and the third lateral dimension is less than 2 μm.

11. The semiconductor device according to claim 1, further comprising: The high operating power consumption region and the low operating power consumption region, wherein the number of first channels in the high operating power consumption region is greater than the number of first channels in the low operating power consumption region.

12. The semiconductor device according to claim 1, wherein, The material of the thermally conductive layer has a thermal conductivity of not less than 20 W / mK.

13. The semiconductor device according to claim 12, wherein, The material of the thermally conductive layer is one of silicon nitride, aluminum oxide, and silicon carbide.

14. The semiconductor device according to claim 1, wherein, The plurality of dies includes at least one memory die, and the plurality of dies are stacked by direct bonding.

15. A semiconductor device, comprising: Multiple dies, which are stacked vertically; An interposer layer, located on the bottom surface of a substrate die, wherein the interposer layer includes a wiring structure, the wiring structure comprising a first wiring structure and a second wiring structure; and A first contact structure extends vertically through the plurality of dies, wherein the first contact structure includes one or more first channels, each first channel having a first end in contact with the interposer layer and a second end in contact with the top surface of the topmost die.

16. The semiconductor device of claim 15, further comprising: A second contact structure extends vertically within the plurality of dies, wherein the second contact structure includes one or more second channels, each extending vertically and contacting the interlayer but not the top surface of the topmost die.

17. The semiconductor device of claim 15, further comprising: A ball grid array, located on the side of the interposer layer opposite to the plurality of dies.

18. The semiconductor device according to claim 17, wherein, The ball grid array includes: One or more hot solder balls in contact with the first wiring structure, wherein the first wiring structure is configured to deliver heat; and One or more signal solder balls in contact with the second wiring structure, wherein the second wiring structure is configured to transmit electronic signals.

19. The semiconductor device according to claim 16, wherein, Each of the first channel and the second channel is a continuous structure along the vertical direction.

20. The semiconductor device of claim 16, wherein, The second contact structure is surrounded by the first contact structure.

21. The semiconductor device according to claim 15, wherein, The first end of each first channel has a first lateral dimension, the second end of each first channel has a second lateral dimension, and the first lateral dimension is greater than the second lateral dimension.

22. The semiconductor device according to claim 16, wherein, Each second channel has a first end that contacts the interposer layer, and the first end of each second channel has a third lateral dimension, which is smaller than the first lateral dimension of the first end of each first channel.

23. The semiconductor device according to claim 22, wherein, The first lateral dimension is 2-3 μm, and the third lateral dimension is less than 2 μm.

24. The semiconductor device of claim 15, further comprising: The high operating power consumption region and the low operating power consumption region, wherein the number of first channels in the high operating power consumption region is greater than the number of first channels in the low operating power consumption region.

25. The semiconductor device according to claim 15, wherein, The material of the first channel has a thermal conductivity of not less than 20 W / mK.

26. The semiconductor device of claim 25, wherein, The material of the first channel is one of silicon nitride, aluminum oxide, and silicon carbide.

27. The semiconductor device according to claim 15, wherein, The plurality of dies includes at least one memory die, and the plurality of dies are stacked by direct bonding.

28. A method of forming a semiconductor device, comprising: Multiple tubes are stacked vertically; A sacrificial layer is deposited on the first surface of the stacked dies, and a plurality of first pores are formed in the sacrificial layer; The plurality of first holes are used to form a first contact structure that extends vertically through the stacked dies, wherein the first contact structure includes one or more first channels; The substrate die is bonded to the first surface of the stacked dies by hybrid bonding; An intermediate layer is bonded to the substrate die, wherein the intermediate layer includes a wiring structure; Connect each first channel to the wiring structure; and A thermally conductive layer is formed on the second surface of the stacked dies, wherein the second surface is opposite to the first surface in the vertical direction, and the thermally conductive layer is physically connected to each first channel.

29. The method of claim 28, further comprising: Multiple second holes are formed in the sacrificial layer; The plurality of second holes are used to form a second contact structure extending vertically inside the stacked die, wherein the second contact structure includes one or more second channels; as well as Each second channel is connected to the intermediary layer without physically contacting the thermally conductive layer.

30. The method of claim 29, further comprising: A ball grid array is formed on the side of the intermediate layer opposite to the stacked dies.

31. The method according to claim 30, wherein, The wiring structure includes a first wiring structure configured to transport heat and a second wiring structure configured to transmit electronic signals, and forming the ball grid array includes: Forming a plurality of hot solder balls in contact with the first wiring structure; and Multiple signal solder balls are formed that are in contact with the second wiring structure.

32. The method according to claim 29, wherein, Forming the first contact structure includes: forming each first channel that extends continuously along the vertical direction; and Forming the second contact structure includes forming each second channel that extends continuously along the vertical direction.

33. The method according to claim 29, wherein, Forming the second contact structure includes: forming a second contact structure surrounded by the first contact structure.

34. The method of claim 29, further comprising: Each first channel is formed having a first end and a second end, the first end having a first lateral dimension and the second end having a second lateral dimension, wherein the first end of each first channel is in contact with the substrate die, the second end of each first channel is in contact with the thermally conductive layer, and the first lateral dimension is larger than the second lateral dimension.

35. The method of claim 34, further comprising: Each second channel is formed having a first end having a third lateral dimension, wherein the first end of each second channel contacts the substrate die, and the third lateral dimension is smaller than the first lateral dimension.

36. The method according to claim 28, wherein, Forming the thermally conductive layer includes using a material having a thermal conductivity of not less than 20 W / mK.

37. The method of claim 36, wherein, Forming the thermally conductive layer includes using one of silicon nitride, aluminum oxide, and silicon carbide.

38. The method according to claim 28, wherein, Stacking the plurality of dies includes stacking at least one memory die with other dies by direct bonding.

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