Bonding structure for high-density metal-to-metal bonding and forming method thereof

Abstract

The bonded assembly includes a first semiconductor die that is bonded to a second semiconductor die. The first semiconductor die includes: a first dielectric material layer on the first semiconductor device; a first metal interconnect structure embedded in the first dielectric material layer and electrically connected to the first semiconductor device; a first bonding level dielectric layer on the first dielectric material layer and embedded with a first conductive bonding structure, the first conductive bonding structure being electrically connected to one of the first metal interconnect structures, the first bonding level dielectric layer is further embedded into a first dummy conductive bonding structure, and the first dummy conductive bonding structure has a smaller vertical range than the first conductive bonding structure and is electrically isolated from the first metal interconnection structure; and a first type of insulating spacer embedded in the first bonding level dielectric layer and laterally surrounding the first conductive bonding structure, and vertically spaced apart from the second semiconductor die and the first dielectric material layer.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Application No. 18 / 509,010, filed November 14, 2023; U.S. Non-Provisional Application No. 18 / 509,035, filed November 14, 2023; U.S. Non-Provisional Application No. 18 / 509,051, filed November 14, 2023; and Continuing Partial Application No. 18 / 530,953, filed December 6, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates in general to the field of semiconductor devices, and more particularly to semiconductor dies including bonding structures for high-density metal-to-metal bonding and methods for forming the same. Background Technology

[0004] Metal-to-metal bonding can be used to provide electrical connections between a pair of mating semiconductor dies having opposing bonding pads. However, the methods for fabricating bonding pads typically involve multiple steps. Summary of the Invention

[0005] According to one aspect of this disclosure, a bonding assembly includes a first semiconductor die bonded to a second semiconductor die. The first semiconductor die includes: a first dielectric material layer located on a first semiconductor device; a first metal interconnect structure embedded in the first dielectric material layer and electrically connected to the first semiconductor device; a first bonding-level dielectric layer located on the first dielectric material layer and embedded with a first conductive bonding structure electrically connected to a first metal interconnect structure within the first metal interconnect structure, and the first bonding-level dielectric layer further embedding a first pseudo-conductive bonding structure having a smaller vertical extent than the first conductive bonding structure and electrically isolated from the first metal interconnect structure; and a first type of insulating spacer embedded in the first bonding-level dielectric layer and laterally surrounding the first conductive bonding structure, and vertically spaced from the second semiconductor die and the first dielectric material layer.

[0006] According to another aspect of the present invention, a method of forming a semiconductor structure includes: forming a first semiconductor device over a first substrate; forming a first metal interconnect structure embedded in a first dielectric material layer over the first semiconductor device; forming a first bonding level dielectric layer over the first dielectric material layer; forming a first cavity and a first dummy cavity in the first bonding level dielectric layer, the first dummy cavity having a smaller lateral extent than the first cavity; forming an insulating spacer material layer in the first cavity and the first dummy cavity and over the first bonding level dielectric layer; and performing an anisotropic etching process to etch the insulating spacer material layer and the first bonding level dielectric layer. The material is used to form a first type of insulating spacer in the peripheral portion of the first recess and a second type of insulating spacer in the peripheral portion of the first pseudo-recess, such that a first stepped via extends through the first type of insulating spacer and through the first bonding level dielectric layer to reach the top surface of a first metal interconnect structure in the first metal interconnect structure, and a second stepped via extends through the second type of insulating spacer and has a bottom surface covering the bottom surface of the first bonding level dielectric layer; and a first conductive bonding structure is formed in the first stepped via and a first pseudo-conductive bonding structure is formed in the second stepped via to form a first semiconductor die. Attached Figure Description

[0007] Figure 1A , Figure 1B , Figure 1D , Figure 1F , Figure 1G and Figure 1H This is a sequential vertical cross-sectional view of a first exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of the present disclosure. Figure 1C yes Figure 1B A top view of the first exemplary structure. Figure 1C The vertical plane B-B' in is Figure 1B The cutting plane of the vertical cross-section diagram. Figure 1E yes Figure 1D A top view of the first exemplary structure. Figure 1E The vertical plane D-D' in is Figure 1D The cutting plane of the vertical cross-section diagram. Figure 1F This is a vertical cross-sectional view of the second semiconductor die before it is bonded to the first semiconductor die.

[0008] Figures 2A to 2C This is a sequential vertical cross-sectional view of a second exemplary structure during the formation of a first semiconductor die, according to an embodiment of this disclosure.

[0009] Figure 3This is a vertical cross-sectional view of a third exemplary structure according to an embodiment of the present disclosure.

[0010] Figure 4 This is a vertical cross-sectional view of a fourth exemplary structure according to an embodiment of the present disclosure.

[0011] Figure 5A , Figure 5D , Figure 5E , Figure 5F , Figure 5I and Figure 5L This is a sequential vertical cross-sectional view of a fifth exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of this disclosure. Figure 5B and Figure 5C yes Figure 5A Top views of two configurations of the illustrated fifth semiconductor die. Figure 5B and Figure 5C The vertical plane A-A' in is Figure 5A The cutting plane of the vertical cross-section diagram. Figure 5G and Figure 5H yes Figure 5F Top views of two configurations of the illustrated fifth semiconductor die. Figure 5G and Figure 5H The vertical plane FF in is Figure 5F The cutting plane of the vertical cross-section diagram. Figure 5J yes Figure 5I A top view of the fifth exemplary structure. Figure 5J The vertical plane I-I' in is Figure 5I The cutting plane of the vertical cross-section diagram. Figure 5K This is a vertical cross-sectional view of the second semiconductor die before it is bonded to the first semiconductor die.

[0012] Figure 6A and Figure 6B This is a sequential vertical cross-sectional view of a sixth exemplary structure during the formation of a first semiconductor die, according to an embodiment of the present disclosure.

[0013] Figure 7A , Figure 7D , Figure 7E , Figure 7F and Figure 7G This is a sequential vertical cross-sectional view of a seventh exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of the present disclosure. Figure 7B and Figure 7C yes Figure 7A Top views of two configurations of the seventh exemplary structure. Figure 7B and Figure 7C The vertical plane A-A' in is Figure 7AThe cutting plane of the vertical cross-section diagram.

[0014] Figure 8A , Figure 8C , Figure 8D , Figure 8E , Figure 8F , Figure 8G and Figure 8H This is a sequential vertical cross-sectional view of an eighth exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of the present disclosure. Figure 8B yes Figure 8A A top view of the eighth exemplary structure. Figure 8B The vertical plane A-A' in is Figure 8A The cutting plane of the vertical cross-section diagram.

[0015] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E This is a sequential vertical cross-sectional view of a ninth exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of this disclosure.

[0016] Figure 10A , Figure 10D and Figure 10G This is a sequential vertical cross-sectional view of a tenth exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of this disclosure. Figure 10B and Figure 10C yes Figure 10A Top views of two configurations of the illustrated tenth semiconductor die. Figure 10B and Figure 10C The vertical plane A-A' in is Figure 10A The cutting plane of the vertical cross-section diagram. Figure 10E and Figure 10G yes Figure 10D Top views of two configurations of the illustrated tenth semiconductor die. Figure 10E and Figure 10F The vertical plane D-D' in is Figure 10B The cutting plane of the vertical cross-section diagram.

[0017] Figures 11A to 11F This is a sequential vertical cross-sectional view of an eleventh exemplary structure during the formation of a bonding assembly for a first semiconductor die and a second semiconductor die, according to an embodiment of the present disclosure.

[0018] Figure 11G This is a vertical cross-sectional view of an alternative configuration of the eleventh exemplary structure according to an embodiment of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure relate to a semiconductor die including a bonding structure for high-density metal-to-metal bonding and a method for forming the same, various aspects of which are now described in detail. Embodiments of this disclosure can be used to form semiconductor devices, such as three-dimensional memory devices comprising multiple memory strings.

[0020] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0021] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or with each other, the two elements are “separated” from each other or “separated from each other”. As used herein, a first element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the surfaces of the second element, the first element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0022] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend throughout the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the first continuous structure. For example, a layer may be located between the top and bottom surfaces of the first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0023] As used herein, the first and second surfaces are “vertically coincident” if the second surface covers or lies beneath the first surface and a vertical or substantially vertical plane comprising the first and second surfaces is present. A substantially vertical plane is a plane extending along a straight line at an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0024] As used herein, a “memory level” or “memory array level” refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) of the topmost surface of the array of memory elements and a second horizontal plane of the bottommost surface of the array of memory elements. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0025] As used herein, "semiconductor material" refers to a material in which electrical conductivity is greater than 1.0 x 10⁻⁶ in the absence of electrical dopants. -5 Materials in the range of S / m to 1.0 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity in the range of 1.0 S / m to 1.0 x 10⁻⁶. 7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1.0 x 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a conductivity less than 1.0 x 10⁻⁶. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a value greater than 1.0 x 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1.0 × 10⁻⁶. -5 S / m to 1.0×10 7Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0026] Generally speaking, a semiconductor package (or "package") refers to a single semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips fully bonded, for example, by flip-chip bonding or chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit capable of independently executing external commands or reporting status. Typically, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of dies contained therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but some limitations may exist. When the die is a memory die (i.e., a die containing memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0027] refer to Figure 1A The first exemplary structure according to an embodiment of the present disclosure is illustrated. The first exemplary structure includes a first semiconductor die 100. The first semiconductor die includes a first substrate 108, a first semiconductor device 120, a first dielectric material layer 130, and a first bonding level dielectric layer 180. The first semiconductor device is formed on, above, and / or in the first substrate 108. The first dielectric material layer is formed above the first semiconductor device 120 and embedded in a first metal interconnect structure 140. The first bonding level dielectric layer is formed above the first dielectric material layer 130.

[0028] The first substrate 108 may include a semiconductor substrate, such as a monocrystalline silicon substrate or a semiconductor-on-insulator substrate comprising at least a monocrystalline semiconductor layer in its upper portion. In one embodiment, the first substrate 108 may include a commercially available monocrystalline silicon substrate on which a two-dimensional array of memory dies is formed. In some embodiments, the first substrate 108 may be a carrier substrate that is subsequently removed from the first semiconductor device 120 (e.g., by grinding, polishing, and / or etching) after the first semiconductor die 100 has been bonded to the second semiconductor die.

[0029] The first semiconductor device 120 may include any type of semiconductor device known in the art. Generally speaking, the first semiconductor device 120 may include logic devices (such as CMOS transistors), memory devices (such as two-dimensional or three-dimensional memory arrays comprising alternating stacks of insulating and conductive layers and vertical stacks of memory elements and vertical stacks of memory elements and vertical semiconductor channels extending through a corresponding alternating stack), or any other type of semiconductor device.

[0030] The first metal interconnect structure 140 may include a metal line structure and a metal via structure. The approximate location of the first metal interconnect structure 140 is indicated by a dashed rectangle, and for clarity, structural details of the first metal interconnect structure 140 are not illustrated in the figures. The first metal interconnect structure 140 may have any configuration known in the art. In some embodiments, a combination of a metal line structure and at least one metal via structure may be formed as an integrated metal line and via structure. The first metal interconnect structure 140 may be electrically connected to a first semiconductor device 120. The first metal interconnect structure 140 may provide electrical connections between the first semiconductor devices 120 and between the first semiconductor devices 120 and first metal bonding structures subsequently formed in the first bonding stage dielectric layer 180. A first topmost metal interconnect structure 148 is illustrated, which is a subset of the first metal interconnect structure 140. In one embodiment, the first topmost metal interconnect structure 148 may have the same pattern as the pattern of a two-dimensional array of the first metal bonding structures subsequently formed in the first bonding stage dielectric layer 180. In one embodiment, the first topmost metal interconnect structure 148 may be arranged in a rectangular array pattern or in a hexagonal array pattern.

[0031] In one embodiment, the first bonding-level dielectric layer 180 includes a first etch-stop dielectric layer 182, a first silicate glass layer 184, and a first dielectric bonding material layer 186. The first etch-stop dielectric layer 182 includes a dielectric material that can be used as an etch-stop structure. For example, the first etch-stop dielectric layer 182 may include silicon nitride, silicon carbide, silicon carbonitride (i.e., silicon carbonitride), and / or dielectric metal oxide. The thickness of the first etch-stop dielectric layer 182 may range from 10 nm to 50 nm, but smaller and larger thicknesses are also possible. The first silicate glass layer 184 includes a silicate glass material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass. The thickness of the first silicate glass layer 184 may range from 200 nm to 3000 nm (e.g., 500 nm to 1000 nm), but smaller and larger thicknesses are also possible.

[0032] The first dielectric bonding material layer 186 includes a dielectric material that can be used for dielectric-to-dielectric bonding with another dielectric material and can be selectively etched relative to the material of the first silicate glass layer 184, i.e., selectively etched relative to undoped silicate glass material or selectively etched relative to doped silicate glass material. In one embodiment, the first dielectric bonding material layer 186 may include silicon carbonitride (i.e., silicon carbonitride) and / or may consist substantially of silicon carbonitride (i.e., silicon carbonitride). In one embodiment, the first dielectric bonding material layer 186 includes a first silicon carbonitride layer and / or consists of a first silicon carbonitride layer. The thickness of the first dielectric bonding material layer 186 may be in the range of 200 nm to 2000 nm (such as 300 nm to 600 nm), but smaller and larger thicknesses are also possible.

[0033] refer to Figure 1B and Figure 1C A hard mask layer 188 may be formed over a first dielectric bonding material layer 186. The hard mask layer 188 may comprise a carbon-based material, a conductive material, or an insulating material, and may have a thickness ranging from 50 nm to 200 nm, but may also have smaller and larger thicknesses. In one embodiment, the hard mask layer 188 may comprise a carbon-based material and / or may be substantially composed of a carbon-based material comprising an atomic percentage greater than 80% carbon. In an exemplary example, the hard mask layer 188 may comprise amorphous carbon, diamond-like carbon, or doped carbon and / or may be substantially composed of amorphous carbon, diamond-like carbon, or doped carbon. Alternatively, the hard mask layer 188 may comprise a bilayer of a lower carbon-based material sublayer and an upper silicate glass (e.g., spin-coated glass) sublayer.

[0034] The hard mask layer 188 can be patterned to form an array of openings therethrough. For example, a photoresist layer (not shown) can be applied over the hard mask layer 188 and can be photolithographically patterned to form openings therein. A first anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the hard mask layer 188. In one embodiment, the pattern of the openings in the hard mask layer 188 may be identical to the pattern of the first topmost metal interconnect structure 148. In one embodiment, each opening in the hard mask layer 188 may be completely formed within the corresponding area of ​​the first topmost metal interconnect structure 148 below it. The photoresist layer can be removed, for example, by ashing.

[0035] A second anisotropic etching process can be performed to transfer the pattern of openings in the hard mask layer 188 through the first bonding-level dielectric layer 180. The hard mask layer 188 can be used as an etching mask to perform the second anisotropic etching process. Via cavities 189' are formed through the first bonding-level dielectric layer 180, such that the top surface of the corresponding first topmost metal interconnect structure 148 is physically exposed beneath each via cavity 189'. In one embodiment, each via cavity 189' extends vertically through the first dielectric bonding material layer 186, the first silicate glass layer 184, and the first etch-stop dielectric layer 182. At least one via cavity 189' may have tapered sidewalls to provide a variable lateral range for the corresponding via cavity 189', which increases with a vertical distance from the first substrate 108. The lateral extent (such as diameter or sidewall-to-sidewall distance) at the bottom of each via cavity 189' can be in the range of 150 nm to 1000 nm (such as 300 nm to 700 nm), but smaller and larger lateral extents are also possible.

[0036] refer to Figure 1D and Figure 1E The hard mask layer 188 can be selectively removed relative to the material of the first bonding stage dielectric layer 180. In one embodiment, the hard mask layer 188 can be removed by ashing.

[0037] A selective etching process can be performed to selectively recess the material of the first dielectric bonding material layer 186 relative to the material of the first silicate glass layer 184, the first etch-stop dielectric layer 182, and the first topmost metal interconnect structure 148. In one embodiment, the selective etching process may include an isotropic etching process. When the first dielectric bonding material layer 186 comprises silicon carbonitride, wet etching chemicals that can be used to selectively etch the silicon carbonitride relative to the silicate glass material of the first silicate glass layer 184 include, but are not limited to, wet etching chemicals employing one or more of hot phosphoric acid, potassium hydroxide, tetramethylammonium hydroxide (TMAH), and organic solvents such as n-methyl-2-pyrrolidone (NMP) or dimethyl sulfoxide (DMSO). Alternatively, a dry etching process using NF3 / Ar plasma and optionally incorporating SiCl4 can be used to selectively etch the silicon carbonitride.

[0038] As used herein, an etching process is selective for the second material if the etching rate of the first material during an etching process is at least three times the etching rate of the second material during the same etching process. As used herein, the “selectivity” of an etching process for etching the first material relative to the second material is defined as the ratio of the etching rate of the first material to the etching rate of the second material. The selectivity of a selective etching process relative to the material of the first silicate glass layer 184 (i.e., the ratio of the etching rate of the material of the first dielectric bonding material layer 186 to the etching rate of the material of the first silicate glass layer 184 during a selective etching process) can be at least 3, and / or at least 5, and / or at least 10, and / or at least 30 (such as 3 to 100).

[0039] In one embodiment, the selective etching process is isotropic. In this case, the selective etching process reduces the thickness of the first dielectric bonding material layer 186 to the same size as the lateral etching distance of the sidewalls of the first dielectric bonding material layer 186 surrounding the via cavity 189. Without extending or significantly extending the via cavity 189' at the level of the first silicate glass layer 184, the selective etching process laterally extends the space of the via cavity 189' at the level of the first dielectric bonding material layer 186 to form the pad cavity portion 189P of the first integrated pad and via cavity 189I. Thus, the via cavity 189' can be converted into the first integrated pad and via cavity 189I by performing a selective etching process that selectively etches the material of the first dielectric bonding material layer 186 relative to the material of the first silicate glass layer 184. Each integrated pad and via cavity 189I in the first integrated pad and via cavity includes a corresponding via cavity 189V that is laterally surrounded by a first silicate glass layer 184, and also includes a corresponding pad cavity 189P that is laterally surrounded by a first dielectric bonding material layer 186.

[0040] In one embodiment, at least one of the first integrated pads and via 189I may include a corresponding first sidewall (which is a sidewall of the first dielectric bonding material layer 186), a corresponding second sidewall (which is a sidewall of the first silicate glass layer 184), and a horizontal connection surface connecting the bottom periphery of the first sidewall (referred to herein as the first periphery P1) and the top periphery of the second sidewall (referred to herein as the second periphery P2). In one embodiment, the selective etching process is isotropic. In this case, the first periphery P1 may be laterally offset outward from the second periphery P2 by a uniform lateral offset distance LOD, which is the same for each pair of first periphery P1 and second periphery P2 for any first integrated pad and via 189I. This uniform lateral offset distance LOD may be in the range of 100 nm to 600 nm (such as 200 nm to 500 nm), but smaller and larger lateral offset distances may also be used.

[0041] refer to Figure 1FAt least one conductive (e.g., metallic) material can be deposited in the integrated pads and via cavities 189I, and excess portions of the at least one metallic material can be removed from a horizontal plane above the top surface of the top surface including the first dielectric bonding material layer 186 by performing a planarization process. In one embodiment, the at least one metallic material may comprise a combination of a conductive metal barrier material and a metal filler material. The conductive metal barrier material may comprise a metal nitride or carbide material, such as WN, TiN, TaN, MoN, TiC, TaC, and / or WC, and may have a thickness in the range of 5 nm to 50 nm, but smaller and larger thicknesses are also possible. The conductive metal barrier material may be deposited by physical vapor deposition or by chemical vapor deposition. The metal filler material comprises highly conductive metals, such as W, Cu, Al, Mo, Co, Ru, and alloys thereof (such as Cu-Al), etc. The metal filler material may be deposited by physical vapor deposition, electroplating, electroless plating, and / or chemical vapor deposition. A planarization process that can be used to remove excess portions of at least one metallic material above a horizontal plane including the top surface of the first dielectric bonding material layer 186 can be employed by chemical mechanical polishing.

[0042] The filling of each remaining portion of the corresponding first integrated pad and via cavity 189I with at least one metallic material constitutes a first integrated pad and via bonding structure 190I, which is a type of first metal bonding structure 190. In one embodiment, each first integrated pad and via bonding structure 190I includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material). In one embodiment, each first integrated pad and via bonding structure 190I includes a corresponding metal via portion 190V laterally surrounded by a first silicate glass layer 184 and a corresponding metal pad portion 190P laterally surrounded by a first dielectric bonding material layer 186. In one embodiment, the bottom surface of the metal pad portion 190P of the first integrated pad and via bonding structure 190I may be formed in a horizontal plane including the interface between the first silicate glass layer 184 and the first dielectric bonding material layer 186 (which may be a first silicon carbon nitride layer).

[0043] In one embodiment, at least one of the first integrated pad and via bonding structures 190I may include a corresponding first metal barrier pad 190B that contacts the sidewall of the first silicate glass layer 184, the horizontal surface of the first silicate glass layer 184, and the sidewall of the first dielectric bonding material layer 186 (which may be a first silicon carbonitride layer). In one embodiment, the first bonding-level dielectric layer 180 further includes a first etch-stop dielectric layer 182 located below the first silicate glass layer 184 and contacting and laterally surrounding the first metal barrier pad 190B.

[0044] refer to Figure 1G A second semiconductor die 200 may be provided. This second semiconductor die includes a second substrate 208, a second semiconductor device 220, a second dielectric material layer 230, and a second bonding level dielectric layer 280. The second semiconductor device is formed above, over, and / or within the second substrate 208. The second dielectric material layer is formed above the second semiconductor device 220 and embedded in a second metal interconnect structure 240. The second bonding level dielectric layer is formed above the second dielectric material layer 230. The second substrate 208 may include any substrate that can be used with the first substrate 108. The second semiconductor device 220 may include any type of semiconductor device known in the art. In one embodiment, the first semiconductor device 220 may include a memory array, and the second semiconductor device 220 may include peripheral (i.e., driver) circuitry configured to control the operation of the memory array, or vice versa. The second metal interconnect structure 240 may be electrically connected to the second semiconductor device 220.

[0045] Figure 1G The diagram also illustrates a second topmost metal interconnect structure 248, which is a subset of the second metal interconnect structure 240. In one embodiment, the second topmost metal interconnect structure 248 may have the same pattern as the pattern of a two-dimensional array of second metal bonding structures subsequently formed in the second bonding stage dielectric layer 280. In one embodiment, the second topmost metal interconnect structure 248 may be arranged in a rectangular array pattern or in a hexagonal array pattern. In one embodiment, the pattern of the second topmost metal interconnect structure 248 may be a mirror image of the pattern of the first integrated pad and via bonding structure 190I.

[0046] The second bonding-stage dielectric layer 280 includes a second etch-stop dielectric layer 282, a second silicate glass layer 284, and a second dielectric bonding material layer 286. The second etch-stop dielectric layer 282 includes a dielectric material that can be used as an etch-stop structure. For example, the second etch-stop dielectric layer 282 may include silicon nitride, silicon carbide, silicon carbonitride, and / or dielectric metal oxide. The thickness of the second etch-stop dielectric layer 282 may range from 10 nm to 50 nm, but smaller and larger thicknesses are also possible. The second silicate glass layer 284 includes a silicate glass material, such as undoped silicate glass or doped silicate glass. The thickness of the second silicate glass layer 284 may be the same as the thickness of the first silicate glass layer 184. The second dielectric bonding material layer 286 may include the same material (e.g., silicon carbonitride) and the same thickness as the first dielectric bonding material layer 186.

[0047] Reference can be performed on the second semiconductor die 200 Figures 1B to 1E The described processing steps are modified as needed to form a second integrated pad and via bonding structure 290I through the second bonding stage dielectric layer 280. The second integrated pad and via bonding structure 290I is a second metal bonding structure 290. In one embodiment, each second integrated pad and via bonding structure 290I includes a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). In one embodiment, each second integrated pad and via bonding structure 290I includes a corresponding metal via portion 290V laterally surrounded by a second silicate glass layer 284 and a corresponding metal pad portion 290P laterally surrounded by a second dielectric bonding material layer 286. In one embodiment, the bottom surface of the metal pad portion 290P of the second integrated pad and via bonding structure 290I may be formed in a horizontal plane including the interface between the second silicate glass layer 284 and the second dielectric bonding material layer 286 (which may be a second silicon carbon nitride layer).

[0048] In one embodiment, at least one of the second integrated pad and via bonding structures 290I may include a corresponding second metal barrier pad 290B that contacts the sidewall of the second silicate glass layer 284, the horizontal surface of the second silicate glass layer 284, and the sidewall of the second dielectric bonding material layer 286 (which may be a second silicon carbonitride layer). In one embodiment, the second bonding-level dielectric layer 280 further includes a second etch-stop dielectric layer 282 located below the second silicate glass layer 284 and contacting and laterally surrounding the second metal barrier pad 290B.

[0049] In summary, a second semiconductor die 200 may be provided, which includes a second dielectric material layer 230 located on the second semiconductor device 220 and embedded in a second metal interconnect structure 240, and also includes a second bonding level dielectric layer 280 embedded in a metal bonding structure (such as a second metal bonding structure 290).

[0050] refer to Figure 1H The second metal bonding structure 290 (which may include a second integrated pad and a via bonding structure 290I) can be bonded to the first metal bonding structure 190 (which may include a first integrated pad and a via bonding structure 190I) via metal-to-metal bonding. As used herein, "metal-to-metal" bonding refers to a direct bonding between pairs of mating bonding pads. Therefore, there is no intervening metal material (such as solder material) between the pairs of mating bonding pads, which are bonded to each other via metal-to-metal bonding. In one embodiment, the second metal bonding structure 290 (which may include a second integrated pad and a via bonding structure 290I) can be bonded to the first integrated pad and via bonding structure 190I via copper-to-copper bonding, which is a metal-to-metal bonding between at least one pair of copper pads. In this case, the first metal filler portion 190F and the second metal filler portion 290F may be substantially composed of copper or a copper alloy.

[0051] In one embodiment, in addition to metal-to-metal bonding, dielectric-to-dielectric bonding may also be performed between the second bonding-level dielectric layer 280 and the first dielectric bonding material layer 186. Generally, each of the second dielectric bonding material layer 286 and the first dielectric bonding material layer 186 includes and / or is substantially composed of a corresponding dielectric material that can be used for dielectric-to-dielectric bonding. In one embodiment, the first dielectric bonding material and the second dielectric bonding material layers (186, 286) include and / or are substantially composed of silicon carbonitride.

[0052] In one embodiment, at least one of the first integrated pad and via bonding structures 190I may include a corresponding first sidewall (which contacts the first dielectric bonding material layer 186), a corresponding second sidewall (which contacts the first silicate glass layer 184), and a horizontal connection surface connecting the bottom periphery of the first sidewall (referred to herein as the first periphery P1) and the top periphery of the second sidewall (referred to herein as the second periphery P2). According to one aspect of this disclosure, for any first integrated pad and via bonding structure 190I, the first periphery P1 may be laterally offset outward from the second periphery P2 by a uniform lateral offset distance LOD. In one embodiment, the first pad and via bonding structure 190I includes a wider metal pad portion 190P and a narrower metal via portion 190V. The wider metal pad portion 190P may have a critical diameter greater than 400 nm (such as 500 nm to 1000 nm) at its top surface to improve overlap with the second pad and via bonding structure 290I. In contrast, the narrower metal via portion 190V may have a critical diameter of 200 nm or less (such as 140 nm to 200 nm) at its bottom surface to improve coverage and contact with the relatively narrow underlying first topmost metal interconnect structure 148, which has a critical diameter of less than 300 nm (such as 200 to 250 nm) at its top surface. In one embodiment, the entire bottom surface of the narrower metal via portion 190V is in contact with the top surface of the underlying first topmost metal interconnect structure 148, while no portion of the bottom surface of the narrower metal via portion 190V lies outside the periphery of the top surface of the underlying first topmost metal interconnect structure 148 (i.e., there is complete coverage between the bottom of portion 190V and the top of structure 148).

[0053] Figures 2A to 2C This is a sequential vertical cross-sectional view of a second exemplary structure during the formation of a first semiconductor die 100, according to an embodiment of the present disclosure.

[0054] refer to Figure 2A It can be obtained from the following methods Figure 1B and Figure 1C The first exemplary structure illustrated leads to a second exemplary structure: the thickness of the first dielectric bonding material layer 186 is selected to be similar to... Figure 1D and Figure 1E The final thickness of the first dielectric bonding material layer 186 after the processing steps is the same. For example, the thickness of the first dielectric bonding material layer 186 can be in the range of 200 nm to 1000 nm (such as 300 nm to 600 nm), but smaller and larger thicknesses are also possible. The hard mask layer 188 can be compared with the reference. Figure 1B and Figure 1CThe hard mask layer described is the same.

[0055] refer to Figure 2B Executable reference Figure 1B and Figure 1C The second anisotropic etching process is described to form the through-hole cavity 189'.

[0056] refer to Figure 2C Executable reference Figure 1D and Figure 1E The described selective etching process converts via cavity 189' into first integrated pads and via cavities 189I, while a hard mask layer 188 is present on the top surface of a first dielectric bonding material layer 186. Each first integrated pad and via cavity 189I may include a corresponding via cavity 189V laterally surrounded by a first silicate glass layer 184, and also includes a corresponding pad cavity 189P laterally surrounded by the first dielectric bonding material layer 186. In this case, the thickness of the first dielectric bonding material layer 186 remains constant during the selective etching process.

[0057] Subsequently, the hard mask layer 188 can be selectively removed relative to the first dielectric bonding material layer 186, the first silicate glass layer 184, the first etch-stop dielectric layer 182, and the first topmost metal interconnect structure 148, for example, by ashing. In one embodiment, at least one of the first integrated pads and via cavities 189I may include a corresponding first sidewall (which is a sidewall of the first dielectric bonding material layer 186), a corresponding second sidewall (which is a sidewall of the first silicate glass layer 184), and a horizontal connection surface connecting the bottom periphery of the first sidewall (referred to herein as the first periphery P1) and the top periphery of the second sidewall (referred to herein as the second periphery P2). According to one aspect of this disclosure, the selective etching process is isotropic. Therefore, the first periphery P1 may be laterally offset outward from the second periphery P2 by a uniform lateral offset distance LOD, which is the same for each pair of first peripheries P1 and second peripheries P2 for any first integrated pad and via cavity 189I. The uniform lateral offset distance (LOD) can be in the range of 200nm to 600nm (such as 300nm to 500nm), but smaller and larger lateral offset distances are also possible.

[0058] Then execution relative to Figure 1F , Figure 1G and Figure 1H The described processing steps are to form a first semiconductor die 100 including a first integrated pad and a through-hole bonding structure 190I, to form a second semiconductor die 200, and to form a bonding assembly of the first semiconductor die 100 and the second semiconductor die 200. From Figure 2CThe bonding component derived from the second exemplary structure illustrated herein can be coupled with Figure 1H The bonding components shown in the example are the same.

[0059] refer to Figure 3 This can be achieved by using a through-hole bonding structure 290V' as the second metal bonding structure 290. Figure 1H The first exemplary structure illustrated herein leads to a third exemplary structure. In this case, the via bonding structure 290V' can be formed by: forming a two-dimensional array of via cavities through the second bonding stage dielectric layer 280; filling the two-dimensional array of via cavities with at least one metal material; and removing portions of at least one metal material located outside the space of the two-dimensional array of via cavities. Each via bonding structure in the via bonding structure 290V' can be composed of a corresponding metal via portion, which can include a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). The first integrated pad of the first semiconductor die 100 and the two-dimensional array of via bonding structures 190I can be bonded to the two-dimensional array of via bonding structures 290V' (which is a two-dimensional array of second metal bonding structures) by metal-to-metal bonding.

[0060] In this embodiment, the second metal bonding structure 290 includes a through-hole bonding structure 290V', which does not include the pad portion 290P of the previous embodiment. In one embodiment, each through-hole bonding structure 290V' includes a corresponding straight sidewall extending through the entire second silicate glass layer 284 and through the entire second dielectric bonding material layer 286. In one embodiment, at least one sidewall of the straight sidewall of the through-hole bonding structure 290V' may extend vertically from the bonding interface between the first semiconductor die 100 and the second semiconductor die 200 to the surface of the corresponding second topmost metal interconnect structure 248.

[0061] refer to Figure 4 The fourth exemplary structure can be derived from the third exemplary structure by replacing the combination of the second silicate glass layer 284 and the second dielectric bonding material layer 286 with a second silicate glass layer 284. The thickness of the second silicate glass layer 284 in the fourth exemplary structure can be... Figure 3 In the illustrated third exemplary structure, the thickness of the second silicate glass layer 284 is the same as the sum of the thickness of the second dielectric bonding material layer 286.

[0062] In this embodiment, the second bonding-level dielectric layer 280 includes a layer stack comprising a second silicate glass layer 284 and an etch-stop dielectric layer (such as a second etch-stop dielectric layer 282). In one embodiment, the second metal bonding structure 290 includes via bonding structures 290V'. Each via bonding structure 290V' includes a corresponding straight sidewall extending through the entire second silicate glass layer 284 and through the entire etch-stop dielectric layer.

[0063] Common Reference Figures 1A to 1H , Figures 2A to 2C , Figure 3 and Figure 4 This illustrates a bonding assembly for a first semiconductor die 100 and a second semiconductor die 200. The first semiconductor die 100 includes: a first dielectric material layer 130 located on a first semiconductor device 120; a first metal interconnect structure 140 embedded in the first dielectric material layer 130 and electrically connected to the first semiconductor device 120; and a first bonding-level dielectric layer 180 located on the first dielectric material layer 130 and including a layer stack comprising a first silicate glass layer 184 and a first silicon carbonitride layer (which...). This is manifested as a first dielectric bonding material layer 186) and a first integrated pad and via bonding structure 190I, the first integrated pad and via bonding structure including a corresponding metal via portion 190V and a corresponding metal pad portion 190P, the corresponding metal via portion being laterally surrounded by a first silicate glass layer 184, the corresponding metal pad portion being laterally surrounded by the first silicon carbon nitride layer and bonded to a corresponding second metal bonding structure 290 of the second semiconductor die 200 by metal-to-metal bonding. At least one of the first integrated pad and via bonding structures 190I includes a first metal barrier pad 190B, the first metal barrier pad contacting the sidewall of the first silicate glass layer 184, the horizontal surface of the first silicate glass layer 184 and the entire sidewall of the first silicon carbon nitride layer 186. The first metal barrier pad 190B includes a conductive metal nitride or conductive metal carbide layer that extends from the bottom surface to the top surface of the first silicon carbon nitride layer 186 and surrounds the metal or metal alloy filler portion 190F.

[0064] In one embodiment, the second semiconductor die 200 includes a second bonding-level dielectric layer 280 embedded in a second metal bonding structure 290 and bonded to the first silicon carbon nitride layer via dielectric-to-dielectric bonding. In one embodiment, the second bonding-level dielectric layer 280 includes a second dielectric bonding material layer 286 bonded to the first silicon carbon nitride layer via dielectric-to-dielectric bonding. In one embodiment, the second bonding-level dielectric layer 280 includes a second silicate glass layer 284 bonded to the first silicon carbon nitride layer via dielectric-to-dielectric bonding.

[0065] In one embodiment, the bottom surface of the metal pad portion 190P of the first integrated pad and via bonding structure 190I lies within a horizontal plane including the interface between the first silicate glass layer 184 and the first silicon carbonitride layer. In one embodiment, at least one of the first integrated pad and via bonding structures 190I includes a first metal barrier pad 190B that contacts the sidewall of the first silicate glass layer 184, the horizontal surface of the first silicate glass layer 184, and the sidewall of the first silicon carbonitride layer. In one embodiment, the first bonding-level dielectric layer 180 includes a first etch-stop dielectric layer 182 that lies beneath the first silicate glass layer 184 and contacts and laterally surrounds the first metal barrier pad 190B.

[0066] refer to Figure 5A , Figure 5B and Figure 5C The fifth exemplary structure according to the embodiments of this disclosure can be obtained from the following methods: Figure 1A The illustrated first exemplary structure leads to the following: a hard mask layer 188 is formed on the top surface of the first bonding level dielectric layer 180, and the hard mask layer 188 is patterned by utilizing composite patterns, including patterns of via openings 187 and pseudo via openings 187D. Figure 5A It is a vertical cross-sectional view. Figure 5B yes Figure 5A A top view of the first configuration of the fifth exemplary structure. Figure 5C yes Figure 5A A top view of the second configuration of the fifth exemplary structure. The through-hole opening 187 may be formed as a first two-dimensional periodic array, and the pseudo-through-hole opening 187D may be formed as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array. The through-hole opening 187 is wider than the pseudo-opening 187D.

[0067] In one embodiment, each repeating unit in the first periodic array may consist of a single via opening 187 having a first width, which may be the maximum lateral dimension of the single via opening 187. The first width of the via opening 187 may be in the range of 200 nm to 1000 nm (such as 300 nm to 600 nm), but smaller and larger dimensions are also possible. In one embodiment, each repeating unit in the first periodic array may have a circular, rectangular, rounded rectangular shape or any two-dimensional shape with a single closed perimeter. In one embodiment, each repeating unit in the second periodic array may include one or more pseudo-via openings 187D, each of which has a corresponding width less than half of the first width (such as one-tenth to one-third of the first width). In one embodiment, each repeating unit in the second periodic array may include a one-dimensional array of pseudo-via openings 187D or a two-dimensional array of pseudo-via openings 187D, such as... Figure 5B As illustrated. In another embodiment, each repeating unit in the second periodic array may include a plurality of openings nested within each other. For example, each repeating unit may include a central opening and at least one generally annular (e.g., circular, elliptical, or rectangular) opening laterally surrounding the central opening, such as... Figure 5C As illustrated, each pseudo-via opening 187D within the repeating cell of the second periodic array may have a corresponding width, which is less than half the first width of the via opening 187 in the repeating cell of the first periodic array.

[0068] In one embodiment, the first two-dimensional periodic array of the through-hole opening 187 may have a first spacing p1 along a first horizontal direction hd1 and a second spacing p2 along a second horizontal direction hd2. The second two-dimensional periodic array of the pseudo-opening 187D may have a first spacing p1 along the first horizontal direction hd1 and a second spacing p2 along the second horizontal direction hd2. The second two-dimensional periodic array may be laterally offset from the first two-dimensional periodic array along the first horizontal direction hd1 by half of the first spacing p1 along the first horizontal direction hd1, and / or may be laterally offset from the first two-dimensional periodic array along the second horizontal direction hd2 by half of the second spacing p2 along the second horizontal direction hd2. Generally, the first two-dimensional periodic array of the through-hole opening 187 may intersect with the second two-dimensional periodic array of the pseudo-through-hole opening 187D along the first horizontal direction hd1 and / or along the second horizontal direction hd2. The first horizontal direction hd1 and the second horizontal direction hd2 may be perpendicular to each other or may not be perpendicular to each other.

[0069] refer to Figure 5DAn anisotropic etching process can be performed to etch the unmasked portions of the first dielectric bonding material layer 186, the first silicate glass layer 184, and the first etch-stop dielectric layer 182. The anisotropic etching process may employ a hard mask layer 188 as the etching mask. According to one aspect of this disclosure, the etching rate of the anisotropic etching process may be geometry-dependent, and specifically, aspect ratio-dependent. As used herein, aspect ratio refers to the ratio of the cavity height to the cavity width. If the anisotropic etching process is depletive (i.e., insufficient etching gas is supplied) and / or if the anisotropic etching process generates a passivating polymer material as a byproduct of the anisotropic etching process, the chemistry of the anisotropic etching process may be aspect ratio-dependent. In this case, a cavity with a low aspect ratio can be etched to a greater etching depth relative to a cavity with a high aspect ratio.

[0070] A via cavity 189' is formed below the first via opening 187 in the hard mask layer 188, and a pseudo via cavity 189D' is formed below the first pseudo via opening 187D in the hard mask layer 188. The duration and etching chemicals of the anisotropic etching process can be selected such that the materials of the first dielectric bonding material layer 186, the first silicate glass layer 184, and the first etch-stop dielectric layer 182 are sequentially etched below the first via opening 187, and each via cavity 189' extends vertically from the top surface of the first bonding level dielectric layer 180 to the bottom surface of the first bonding level dielectric layer 180. Therefore, the top surface of the first topmost metal interconnect structure 148 is physically exposed below each via cavity 189'.

[0071] The etching rate of the materials of the first dielectric bonding material layer 186 and the first silicate glass layer 184 below the first pseudo-via opening 187D is less than the etching rate of the first dielectric bonding material layer 186 and the first silicate glass layer 184 below the first via opening 187D. Therefore, the pseudo-via cavity 189D' formed below the first pseudo-via opening 187D has a depth less than the depth of the via cavity 189', i.e., a depth less than the total thickness of the first bonding level dielectric layer 180. In one embodiment, the height of each pseudo-via cavity 189D' can be in the range of 20% to 80% (e.g., 30% to 70%) of the thickness of the first bonding level dielectric layer 180. Therefore, the first topmost metal interconnect structure 148 is not exposed to the pseudo-via cavity 189'. Generally speaking, the via cavity 189' extends vertically from the top surface of the first bonding level dielectric layer 180 to the bottom surface of the first bonding level dielectric layer 180, and the pseudo via cavity 189D' has a smaller vertical range than the via cavity 189'.

[0072] refer to Figure 5EThe hard mask layer 188 can be selectively removed relative to the materials of the first dielectric bonding material layer 186, the first silicate glass layer 184, and the first etch stop dielectric layer 182. If the hard mask layer 188 comprises a carbon-based material, it can be removed by ashing.

[0073] refer to Figure 5F , Figure 5G and Figure 5H A selective etching process can be performed to selectively recess the material of the first dielectric bonding material layer 186 relative to the materials of the first silicate glass layer 184, the first etch-stop dielectric layer 182, and the first topmost metal interconnect structure 148. Figure 5F It is a vertical cross-sectional view. Figure 5G yes Figure 5F A top view of the first configuration of the fifth exemplary structure. Figure 5H yes Figure 5F A top view of the second configuration of the fifth exemplary structure.

[0074] In one implementation, the selective etching process may be related to the above-mentioned... Figure 1D or Figure 2C The selective etching process described is the same. A via cavity 189' can be converted into a first integrated pad and via cavity 189I by performing a selective etching process that selectively etches the material of the first dielectric bonding material layer 186 relative to the material of the first silicate glass layer 184. Each integrated pad and via cavity 189I includes a corresponding via cavity 189V laterally surrounded by the first silicate glass layer 184, and also includes a corresponding pad cavity 189P laterally surrounded by the first dielectric bonding material layer 186.

[0075] Without extending or significantly extending the pseudo-via cavities 189D' at the level of the first silicate glass layer 184, a selective etching process extends the space of the pseudo-via cavities 189D' at the level of the first dielectric bonding material layer 186. Multiple pseudo-via cavities 189D' within each repeating unit of the second two-dimensional periodic array can be merged at the level of the first dielectric bonding material layer 186 and can be converted into first pseudo-integrated pads and via cavities 189DI. Each pseudo-integrated pad and via cavity 189DI includes a corresponding plurality of pseudo-via cavities 189DV laterally surrounded by the first silicate glass layer 184, and also includes a corresponding pseudo-pad cavity 189DP laterally surrounded by the first dielectric bonding material layer 186. Therefore, multiple pseudo-via cavities 189DV are located below each pseudo-pad cavity 189DP.

[0076] In one embodiment, the pseudo-pad cavity 189DP may include a corresponding first pseudo-cavity sidewall, which is a sidewall of the first dielectric bonding material layer 186. A set of lower pseudo-via cavities 189DV may include a second pseudo-cavity sidewall, which is a sidewall of the first silicate glass layer 184. The bottom periphery of the first via cavity sidewall may be laterally offset from the proximal segment of the top periphery of the second pseudo-cavity sidewall by a uniform lateral offset distance LOD. The segments of the top periphery of each adjacent pair of pseudo-via cavities 189DV in each unit repeating region may be laterally spaced from each other by a corresponding lateral spacing less than twice the lateral offset distance. Thus, each pseudo-pad cavity 189DP may be formed as a single continuous space, which is derived by incorporating the lateral extension of the pseudo-via cavity 189D' at the layer level of the first dielectric bonding material layer 186.

[0077] refer to Figure 5I and Figure 5J At least one metallic material can be deposited in the first integrated pad and via 189I and the first pseudo-integrated pad and via 189DI, and excess portions of the at least one metallic material can be removed from above a horizontal plane including the top surface of the first dielectric bonding material layer 186 by performing a planarization process. In one embodiment, the at least one metallic material may comprise a combination of a conductive metal barrier material and a metal filler material. The conductive metal barrier material may comprise a metal nitride material, such as WN, TiN, TaN, MoN, TiC, TaC and / or WC, and may have a thickness in the range of 5 nm to 50 nm, but smaller and larger thicknesses are also possible. The conductive metal barrier material may be deposited by physical vapor deposition or by chemical vapor deposition. The metal filler material comprises highly conductive metals, such as W, Cu, Al, Mo, Co, Ru, and alloys thereof (such as Cu-Al). The metal filler material may be deposited by physical vapor deposition, electroplating, electroless plating and / or chemical vapor deposition. A planarization process that can be used to remove excess portions of at least one metallic material above a horizontal plane including the top surface of the first dielectric bonding material layer 186 can be employed by chemical mechanical polishing.

[0078] The remaining portion of each of the corresponding first integrated pads and via cavities 189I filled with at least one metallic material constitutes a first integrated pad and via bonding structure 190I, which is a type of first metal bonding structure 190. The remaining portion of each of the corresponding first pseudo-integrated pads and via cavities 189DI filled with at least one metallic material constitutes a first pseudo-integrated pad and via bonding structure 190DI, which is a type of first pseudo-metal bonding structure 190D. Each first integrated pad and via bonding structure in the first integrated pad and via bonding structure 190I electrically contacts the first topmost metal interconnect structure 148, while each first pseudo-metal bonding structure in the first pseudo-metal bonding structure 190D does not electrically contact any of the underlying interconnect structures 140. In one embodiment, each of the first integrated pad and via bonding structures 190I includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material). In one embodiment, each of the first integrated pad and via bonding structures 190DI includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material).

[0079] In one embodiment, each of the first integrated pad and via bonding structures 190I includes a corresponding metal via portion 190V laterally surrounded by a first silicate glass layer 184 and a corresponding metal pad portion 190P laterally surrounded by a first dielectric bonding material layer 186. In one embodiment, each of the first pseudo-integrated pad and via bonding structures 190DI includes a corresponding pseudo-metallic via portion 190DV laterally surrounded by a first silicate glass layer 184 and a corresponding plurality of metal pad portions 190DP laterally surrounded by a first dielectric bonding material layer 186. In one embodiment, the bottom surface of the metal pad portion 190P of the first integrated pad and via bonding structure 190I may be formed in a horizontal plane including the interface between the first silicate glass layer 184 and the first dielectric bonding material layer 186 (which may be a first silicon carbonitride layer). In one embodiment, the bottom surface of the pseudo-metallic pad portion 190DP of the first pseudo-integrated pad and via bonding structure 190DI may be formed in a horizontal plane including the interface between the first silicate glass layer 184 and the first dielectric bonding material layer 186 (which may be a first silicon carbon nitride layer).

[0080] In one embodiment, at least one of the first integrated pad and via bonding structures 190I may include a corresponding first metal barrier pad 190B that contacts the top surface of the first topmost metal interconnect structure 148, the sidewalls of the first silicate glass layer 184, the horizontal surface of the first silicate glass layer 184, and the sidewalls of the first dielectric bonding material layer 186 (which may be a first silicon carbonitride layer). In one embodiment, the first bonding-level dielectric layer 180 further includes a first etch-stop dielectric layer 182 located below the first silicate glass layer 184 and contacting and laterally surrounding the first metal barrier pad 190B. In one embodiment, at least one of the first pseudo-integrated pad and via bonding structures 190DI may include a corresponding first metal barrier pad 190B, which does not contact any of the first interconnects 140, but contacts the sidewalls of the first silicate glass layer 184, the horizontal surface of the first silicate glass layer 184, and the sidewalls of the first dielectric bonding material layer 186 (which may be a first silicon carbon nitride layer).

[0081] In one embodiment, the first integrated pad and via bonding structure 190I and the first pseudo-integrated pad and via bonding structure 190DI comprise the same set of materials. For example, the first integrated pad and via bonding structure and the first pseudo-integrated pad and via bonding structure may each include a metal nitride barrier pad 190B and a copper or copper alloy filler portion 190F.

[0082] refer to Figure 5K A second semiconductor die 200 may be provided. This second semiconductor die includes a second substrate 208, a second semiconductor device 220, a second dielectric material layer 230, and a second bonding level dielectric layer 280. The second semiconductor device is formed above, over, and / or within the second substrate 208. The second dielectric material layer is formed above the second semiconductor device 220 and embedded in a second metal interconnect structure 240. The second bonding level dielectric layer is formed above the second dielectric material layer 230. The second substrate 208 may include any substrate that can be used with the first substrate 108. The second semiconductor device 220 may include any type of semiconductor device known in the art. In one embodiment, the first semiconductor device 120 may include a memory array, and the second semiconductor device 220 may include peripheral circuitry configured to control the operation of the memory array, or vice versa. The second metal interconnect structure 240 may be electrically connected to the second semiconductor device 220.

[0083] In one embodiment, the second integrated pad and via bonding structure 290I and the second pseudo-integrated pad and via bonding structure 290DI comprise the same set of materials. For example, the second integrated pad and via bonding structure and the second pseudo-integrated pad and via bonding structure may each comprise a metal nitride barrier pad 290B and a copper or copper alloy filler portion 290F.

[0084] Figure 5K The diagram illustrates a second topmost metal interconnect structure 248, which is a subset of the second metal interconnect structure 240. In one embodiment, the second topmost metal interconnect structure 248 may be arranged in a rectangular array pattern or in a hexagonal array pattern. In one embodiment, the pattern of the second topmost metal interconnect structure 248 may be a mirror image of the pattern of the first integrated pad and via bonding structure 190I.

[0085] The second bonding-level dielectric layer 280 includes a second etch-stop dielectric layer 282, a second silicate glass layer 284, and a second dielectric bonding material layer 286. The second etch-stop dielectric layer 282 includes a dielectric material that can be used as an etch-stop structure. For example, the second etch-stop dielectric layer 282 may include silicon nitride, silicon carbide, silicon carbonitride, and / or dielectric metal oxide. The thickness of the second etch-stop dielectric layer 282 may range from 10 nm to 50 nm, but smaller and larger thicknesses are also possible. The second silicate glass layer 284 includes a silicate glass material, such as undoped silicate glass or doped silicate glass.

[0086] Reference can be performed on the second semiconductor die 200 Figures 5A to 5JThe described processing steps are modified, with any necessary alterations, to form a second integrated pad and via bonding structure 290I through the second bonding level dielectric layer 280, and a second pseudo-integrated pad and via bonding structure 290DI in the upper portion of the second bonding level dielectric layer 280. The second integrated pad and via bonding structure 290I is a second metal bonding structure 290. The second pseudo-integrated pad and via bonding structure 290DI is a second pseudo-metal bonding structure 290D. In one embodiment, each second integrated pad and via bonding structure 290I includes a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). In one embodiment, each of the second integrated pad and via bonding structures 290I includes a corresponding metal via portion 290V laterally surrounded by a second silicate glass layer 284 and a corresponding metal pad portion 290P laterally surrounded by a second dielectric bonding material layer 286. In one embodiment, the bottom surface of the metal pad portion 290P of the second integrated pad and via bonding structure 290I may be formed in a horizontal plane including the interface between the second silicate glass layer 284 and the second dielectric bonding material layer 286 (which may be a second silicon carbonitride layer).

[0087] In one embodiment, at least one of the second integrated pad and via bonding structures 290I may include a corresponding second metal barrier pad 290B that contacts the top surface of the second interconnect 240 (e.g., 248), the sidewalls of the second silicate glass layer 284, the horizontal surface of the second silicate glass layer 284, and the sidewalls of the second dielectric bonding material layer 286 (which may be a second silicon carbon nitride layer). The second pseudo-integrated pad and via bonding structure 290DI does not electrically contact any of the second interconnects 240. In one embodiment, the second bonding-level dielectric layer 280 includes a second etch-stop dielectric layer 282 located below the second silicate glass layer 284 and contacting and laterally surrounding the second metal barrier pad 290B.

[0088] refer to Figure 5LThe second metal bonding structure 290 (which may include a second integrated pad and a via bonding structure 290I) can be bonded to the first integrated pad and via bonding structure 190I via metal-to-metal bonding. Furthermore, the second pseudo-metal bonding structure 290D (which may include a second pseudo-integrated pad and a via bonding structure 290DI) can be bonded to the first pseudo-integrated pad and via bonding structure 190DI via metal-to-metal bonding. In one embodiment, the second metal bonding structure 290 (which may include a second integrated pad and a via bonding structure 290I) can be bonded to the first integrated pad and via bonding structure 190I via copper-to-copper bonding, where the copper-to-copper bonding is a metal-to-metal bonding between at least one pair of copper pads. In this case, the first metal filler portion 190F and the second metal filler portion 290F may be substantially composed of copper. In one embodiment, a second pseudo-metal bonding structure 290D (which may include a second pseudo-integrated pad and via bonding structure 290DI) may be bonded to a first pseudo-integrated pad and via bonding structure 190DI via copper-to-copper bonding, wherein the copper-to-copper bonding is a metal-to-metal bonding between at least one pair of copper pads.

[0089] In one embodiment, in addition to metal-to-metal bonding, dielectric-to-dielectric bonding may be performed between the second bonding-level dielectric layer 280 and the first dielectric bonding material layer 186. Generally, each of the second dielectric bonding material layer 286 and the first dielectric bonding material layer 186 includes and / or is substantially composed of a corresponding dielectric material that can be used for dielectric-to-dielectric bonding. In one embodiment, the first dielectric bonding material layer 186 includes and / or is substantially composed of silicon carbonitride.

[0090] In one embodiment, the first metal bonding structure 190 includes a first metal via portion 190V, and the first dummy metal bonding structure 190D includes a first dummy metal via portion 190DV, the first dummy metal via portion having a smaller height than the first metal via portion 190V. In one embodiment, all top peripheries of the first metal via portion 190V and all top peripheries of the first dummy metal via portion 190DV lie in a horizontal plane.

[0091] In one embodiment, each of the first metal bonding structures 190 includes a corresponding first metal pad portion 190P connected to a corresponding first metal via portion 190V, and each of the first pseudo metal bonding structures 190D includes a corresponding first pseudo metal pad portion 190DP connected to a corresponding subset of the first pseudo metal via portions 190DV, the corresponding subset including a plurality of corresponding first pseudo metal via portions 190DV.

[0092] In one embodiment, the first metal pad portion 190P and the first pseudo-metal pad portion 190DP have the same height as the thickness of the first dielectric bonding material layer 186. In one embodiment, the first dielectric bonding material layer 186 includes a first silicon carbon nitride layer that is bonded to a second dielectric bonding material layer 286 in the second semiconductor die 200 via dielectric-to-dielectric bonding.

[0093] In one embodiment, each of the first pseudo-metallic via portions 190DV has a corresponding maximum lateral dimension, which is less than 1 / 3 of the maximum lateral dimension of one of the first pseudo-metallic via portions 190V. In one embodiment, the corresponding subset of the first pseudo-metallic via portions 190DV comprises a corresponding two-dimensional array of the first pseudo-metallic via portions 190DV, each of the first pseudo-metallic via portions having a maximum lateral extent smaller than any of the first pseudo-metallic via portions 190V. In one embodiment, the corresponding subset of the first pseudo-metallic via portions 190DV comprises a corresponding set of two or more first pseudo-metallic via portions 190DV nested within each other, such that each of the two or more first pseudo-metallic via portions 190DV laterally surrounds or is laterally surrounded by any other first pseudo-metallic via portion within the corresponding set of the two or more first pseudo-metallic via portions 190DV.

[0094] Figure 6A and Figure 6B This is a sequential vertical cross-sectional view of a sixth exemplary structure during the formation of a first semiconductor die 100 according to an embodiment of the present disclosure.

[0095] refer to Figure 6A It can be obtained from the following methods Figure 5D The first exemplary structure illustrated leads to a sixth exemplary structure: the thickness of the first dielectric bonding material layer 186 is selected to be similar to... Figure 5F , Figure 5G and Figure 5H The final thickness of the first dielectric bonding material layer 186 after the processing steps is the same. The hard mask layer 188 can be compared with the reference layer. Figures 5A to 5C The described hard mask layer is the same. Executable Reference Figure 5D The anisotropic etching process described is used to form via cavity 189' and pseudo via cavity 189D'.

[0096] refer to Figure 6B Executable reference Figures 5F to 5H The described selective etching process converts via cavity 189' into first integrated pad and via cavity 189I, and pseudo via cavity 189D' into first pseudo integrated pad and via cavity 189DI, while a hard mask layer 188 is present on the top surface of the first dielectric bonding material layer 186. Each first integrated pad and via cavity 189I may include a corresponding via cavity 189V laterally surrounded by a first silicate glass layer 184, and also includes a corresponding pad cavity 189P laterally surrounded by the first dielectric bonding material layer 186.

[0097] Each first pseudo-integrated pad and via cavity 189DI may include a corresponding pseudo-via cavity 189DV laterally surrounded by a first silicate glass layer 184, and a corresponding set of pseudo-pad cavities 189DP laterally surrounded by a first dielectric bonding material layer 186. In this case, the thickness of the first dielectric bonding material layer 186 remains unchanged during the selective etching process.

[0098] Subsequently, the hard mask layer 188 can be selectively removed, for example, by ashing, relative to the first dielectric bonding material layer 186, the first silicate glass layer 184, the first etch stop dielectric layer 182, and the first topmost metal interconnect structure 148.

[0099] Then execution relative to Figure 5I , Figure 5J , Figure 5K and Figure 5L The described processing steps are to form a first semiconductor die 100 including a first integrated pad and a through-hole bonding structure 190I, provide a second semiconductor die 200, and form a bonding assembly between the first semiconductor die 100 and the second semiconductor die 200. The bonding assembly can be coupled with... Figure 5L The bonding components shown are the same.

[0100] refer to Figure 7A , Figure 7B , Figure 7C This illustrates a seventh exemplary structure according to an embodiment of the present disclosure. The seventh exemplary structure can be obtained from... Figure 5A , Figure 5B and Figure 5CThe illustrated fifth exemplary structure derives from this: the first dielectric bonding material layer 186 from the first bonding stage dielectric layer 180 is omitted. The hard mask layer 188 may be referenced. Figures 5A to 5C The hard mask layer described is identical. Therefore, the hard mask layer 188 has a composite pattern comprising a pattern of via openings 187 and a pattern of pseudo-via openings 187D. The hard mask layer 188 may be formed on the top surface of the first silicate glass layer 184.

[0101] refer to Figure 7D It can execute the above-mentioned... Figure 5D The described anisotropic etching process transfers the pattern of openings in the hard mask layer 188 into the first bonding-level dielectric layer 180. Via cavities 189V and pseudo via cavities 189DV are formed in the first bonding-level dielectric layer 180, as described above. Each via cavity 189V in the seventh exemplary structure comprises a via cavity portion and does not include any pad cavity portion. Each via cavity 189V in the seventh exemplary structure is a type of via cavity 189. In one embodiment, cavities formed below a cluster of pseudo via openings 187D may be merged to form a continuous space of voids constituting a corresponding pseudo via cavity in the pseudo via cavity 189DV. Each pseudo via cavity 189DV in the seventh exemplary structure is a type of pseudo via cavity 189D.

[0102] refer to Figure 7E The hard mask layer 188 is removed from the first bonding stage dielectric layer 180, as described above.

[0103] refer to Figure 7F At least one metallic material can be deposited in the via cavity 189V and the pseudo via cavity 189DV, and excess portions of the at least one metallic material can be removed from above a horizontal plane including the top surface of the first dielectric bonding material layer 186 by performing a planarization process, as described above.

[0104] The at least one metallic material filling each remaining portion of the corresponding via cavity 189V constitutes a first metal bonding structure 190. The at least one metallic material filling each remaining portion of the corresponding pseudo-via cavity 189DV constitutes a first pseudo-metal bonding structure 190D. In one embodiment, each first metal bonding structure in the first metal bonding structure 190 includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material). The first metal bonding structure 190 includes via-only bonding structures (lacking pad portions).

[0105] refer to Figure 7GA second semiconductor die 200 may be provided as described above. A second metal bonding structure 290 may include a via-only bonding structure similar to the first metal bonding structure 190. Alternatively, the second metal bonding structure 290 may include a pad and via bonding structure (290P, 290V). As described above, the second semiconductor die 200 is bonded to the first semiconductor die 100 to form a bonding assembly.

[0106] refer to Figure 8A and Figure 8B It can be obtained from the following methods Figure 5A and Figure 5B The illustrated seventh exemplary structure leads to an eighth exemplary structure: a modified pattern of the pseudo-via opening 187D. Specifically, a single pseudo-via opening 187D with a horizontal cross-sectional shape (corresponding to the via opening 187) is formed in each unit region of the second two-dimensional array of pseudo-via openings 187D, instead of multiple pseudo-via openings 187D. Each pseudo-via opening 187D may have a horizontal cross-sectional area within 20% of the horizontal cross-sectional area of ​​each via opening 187.

[0107] Subsequently, an anisotropic etching process can be performed to transfer the pattern of the openings in the hard mask layer 188 through the first dielectric bonding material layer 186 and into the upper portion of the first silicate glass layer 184. A via cavity 189' is formed below the via opening 187 in the hard mask layer 188, and a pseudo via cavity 189D' is formed below the pseudo via opening 187D in the hard mask layer 188. In one embodiment, the via cavity 189' and the pseudo via cavity 189D' may have the same or similar (e.g., within 20% of each other) lateral dimensions and may have the same or similar (e.g., within 20% of each other) depth.

[0108] refer to Figure 8C A photoresist layer 175 may be applied over a hard mask layer 188 and may be photolithographically patterned to fill pseudo via cavities 189D' without covering via cavities 189'. An additional anisotropic etching process may be performed to allow via cavities 189' to extend vertically through the lower portion of the first silicate glass layer 184 and the first etch-stop dielectric layer 182, exposing the top surface of the corresponding first topmost metal interconnect structure 148. After the additional anisotropic etching process, each via cavity 189' includes a corresponding straight sidewall extending through the entire second silicate glass layer 284 and through the entire second dielectric bonding material layer 286. In one embodiment, the straight sidewall of at least one via cavity 189' may extend vertically from the topmost surface of the first dielectric bonding material layer 186 to the surface of the corresponding first topmost metal interconnect structure 148.

[0109] refer to Figure 8D It is possible to remove the photoresist layer 175, for example, by ashing.

[0110] refer to Figure 8E A selective etching process can be performed to selectively recess the material of the first dielectric bonding material layer 186 relative to the materials of the first silicate glass layer 184, the first etch-stop dielectric layer 182, and the first topmost metal interconnect structure 148, as described above regarding... Figure 6B As described, via cavity 189' can be converted into first integrated pads and via cavities 189I by performing a selective etching process that selectively etches the material of the first dielectric bonding material layer 186 relative to the material of the first silicate glass layer 184. Each integrated pad and via cavity 189I includes a corresponding via cavity 189V laterally surrounded by the first silicate glass layer 184, and also includes a corresponding pad cavity 189P laterally surrounded by the first dielectric bonding material layer 186.

[0111] The pseudo-via cavity 189D' can be converted into a first pseudo-integrated pad and via cavity 189DI by performing a selective etching process. Each pseudo-integrated pad and via cavity in the first pseudo-integrated pad and via cavity 189DI includes a corresponding pseudo-via cavity 189DV that is laterally surrounded by a first silicate glass layer 184, and also includes a corresponding pseudo-pad cavity 189DP that is laterally surrounded by a first dielectric bonding material layer 186.

[0112] In one embodiment, at least one of the first pseudo-integrated pads and via cavities 189DI may include a corresponding third sidewall (which is a sidewall of the first dielectric bonding material layer 186), a corresponding fourth sidewall (which is a sidewall of the first silicate glass layer 184), and a horizontal connection surface connecting the bottom periphery (referred to as the third periphery) of the corresponding third sidewall and the top periphery (referred to as the fourth periphery) of the corresponding fourth sidewall. According to one aspect of this disclosure, the selective etching process is isotropic, and therefore, the third periphery may be laterally offset outward from the fourth periphery by a uniform lateral offset distance LOD.

[0113] refer to Figure 8F The hard mask layer 188 can be selectively removed relative to the materials of the first dielectric bonding material layer 186, the first silicate glass layer 184, the first etch stop dielectric layer 182, and the first topmost metal interconnect structure 148.

[0114] refer to Figure 8GAt least one metal material can be deposited in the first integrated pad and via 189I and the first pseudo-integrated pad and via 189DI, and excess portions of the at least one metal material can be removed from above a horizontal plane including the top surface of the first dielectric bonding material layer 186 by performing a planarization process, as described above.

[0115] The at least one metallic material filling each remaining portion of the corresponding first integrated pad and via cavity 189I constitutes a first integrated pad and via bonding structure 190I, which is a first metal bonding structure 190. The at least one metallic material filling each remaining portion of the corresponding first pseudo-integrated pad and via cavity 189DI constitutes a first pseudo-integrated pad and via bonding structure 190DI, which is a first pseudo-metal bonding structure 190D. In one embodiment, each first integrated pad and via bonding structure 190I includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material).

[0116] refer to Figure 8H A second semiconductor die 200 may be provided as described above. Reference spectroscopy can be performed on the second semiconductor die 200. Figures 8A to 8G The described processing steps are modified, with any necessary alterations, to form a second integrated pad and via bonding structure 290I and a second pseudo-integrated pad and via bonding structure 290DI. The second integrated pad and via bonding structure 290I is a second metal bonding structure 290. The second pseudo-integrated pad and via bonding structure 290DI is a second pseudo-metal bonding structure 290D. In one embodiment, each second metal bonding structure in the second metal bonding structure 290 includes a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). In one embodiment, at least one second metal bonding structure in the second metal bonding structure 290 may include a corresponding second metal barrier pad 290B and a second metal filler portion 290F. In one embodiment, at least one second metal bonding structure in the second pseudo-metal bonding structure 290D may include a corresponding second metal barrier pad 290B and a second metal filler portion 290F.

[0117] The second metallic bonding structure 290 can be bonded to the first metallic bonding structure 190 via metal-to-metal bonding, as described above. The second pseudo-metallic bonding structure 290D can be bonded to the first pseudo-metallic bonding structure 190D via additional metal-to-metal bonding, as described above.

[0118] refer to Figure 9A The ninth exemplary structure can be derived from the eighth exemplary structure: the first dielectric bonding material layer 186 is omitted and a first silicate glass layer 184 is formed instead. Figure 8A The stacking of the first silicate glass layer 184 and the first dielectric bonding material layer 186 in the first semiconductor die 100 of the ninth exemplary structure. The thickness of the first silicate glass layer 184 in the first semiconductor die 100 of the ninth exemplary structure may be the same as the sum of the thickness of the first silicate glass layer 184 and the thickness of the first dielectric bonding material layer 186 in the eighth exemplary structure. A via cavity 189' is formed below the via opening 187 in the hard mask layer 188, and a pseudo via cavity 189D' is formed below the pseudo via opening 187D in the hard mask layer 188. The depth of the via cavity 189' and the pseudo via cavity 180D' in the ninth exemplary structure may be the same as the sum of the thickness of the first silicate glass layer 184 and the thickness of the first dielectric bonding material layer 186 in the eighth exemplary structure. Figure 8A In the eighth exemplary structure, the depths of the through-hole cavity 189' and the pseudo-through-hole cavity 180D' are the same.

[0119] refer to Figure 9B Executable reference Figure 8C The described processing steps cover the pseudo via cavity 189D' with a patterned photoresist layer 175 and make the via cavity 189D' extend vertically through the lower portion of the first silicate glass layer 184 and the first etch stop dielectric layer 182.

[0120] refer to Figure 9C The patterned photoresist layer 175 and hard mask layer 188 can be selectively removed relative to the first silicate glass layer 184, the first etch stop dielectric layer 182 and the first topmost metal interconnect structure 148.

[0121] refer to Figure 9D At least one metallic material can be deposited in the through-hole cavity 189' and the pseudo-through-hole cavity 189D', and excess portions of the at least one metallic material can be removed from above a horizontal plane including the top surface of the first silicate glass layer 184 by performing a planarization process, as described above.

[0122] The at least one metallic material filling each remaining portion of the corresponding via cavity 189' constitutes a first metal bonding structure 190. The at least one metallic material filling each remaining portion of the corresponding pseudo-via cavity 189V' constitutes a first pseudo-metal bonding structure 190D. In one embodiment, each first metal bonding structure in the first metal bonding structure 190 includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material). In one embodiment, each first metal bonding structure in the first metal bonding structure 190 consists of a corresponding metal via portion 190V, which is laterally surrounded by a first silicate glass layer 184. In one embodiment, each first pseudo-metal bonding structure in the first pseudo-metal bonding structure 190D includes a combination of a first metal barrier pad 190B (which is a patterned portion of a conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of a metal filler material). In one embodiment, each of the first pseudo-metal bonding structures 190D includes only a metal via portion 190DV, which has a smaller vertical extent than the first metal bonding structure 190.

[0123] refer to Figure 9E A second semiconductor die 200 can be provided as described above.

[0124] Reference can be performed on the second semiconductor die 200 Figures 9A to 9D The described processing steps are modified, with any necessary alterations, to form a second metal bond structure 290 and a second pseudo-metal bond structure 290D in the second bonding stage dielectric layer 280. In one embodiment, each second metal bond structure in the second metal bond structure 290 includes a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). In one embodiment, each second metal bond structure in the second metal bond structure 290 comprises a corresponding metal via portion 290V. In one embodiment, at least one second metal bond structure in the second pseudo-metal bond structure 290D may include a corresponding second metal barrier pad 290B and a second metal filler portion 290F. In one embodiment, each second pseudo-metal bond structure in the second pseudo-metal bond structure 290D comprises a corresponding metal via portion 290DV.

[0125] The second semiconductor die 200 can be bonded to the first semiconductor die 100. Specifically, the second metal bonding structure 290 can be bonded to the first metal bonding structure 190 via metal-to-metal bonding. The second pseudo-metal bonding structure 290D can be bonded to the first pseudo-metal bonding structure 190D via additional metal-to-metal bonding. In one embodiment, the second metal bonding structure 290 can be bonded to the first metal bonding structure 190 via copper-to-copper bonding. The second pseudo-metal bonding structure 290D can be bonded to the first pseudo-metal bonding structure 190D via additional copper-to-copper bonding. In one embodiment, in addition to metal-to-metal bonding, dielectric-to-dielectric bonding can be performed between the second bonding level dielectric layer 280 and the first bonding level dielectric layer 180.

[0126] The pseudo-metallic bonding structures (190D, 290D) improve the bonding between the first semiconductor die (100) and the second semiconductor die (200) by providing additional bonding points, providing a more uniform bonding pad density, and improving the flatness between the bonding pads and the surrounding dielectric material after chemical mechanical polishing. The likelihood of short circuits between the pseudo-metallic bonding structures (190D, 290D) and the corresponding interconnects (140, 240) is reduced by making the pseudo-metallic bonding structures (190D, 290D) shallower than the corresponding metallic bonding structures (190, 290). Furthermore, in some embodiments, the shallower pseudo-metallic bonding structures (190D, 290D) can be formed without using dedicated etch stop layers terminating on these structures, thereby simplifying the manufacturing process.

[0127] Common Reference Figures 5A to 9E The diagram illustrates a bonding assembly for a first semiconductor die 100 and a second semiconductor die 200. The first semiconductor die 100 includes: a first dielectric material layer 130 located on a first semiconductor device 120; a first metal interconnect structure 140 embedded in the first dielectric material layer 130 and electrically connected to the first semiconductor device 120; and a first bonding level dielectric layer 180 located on the first dielectric material layer 130 and embedded in a first metal bonding structure 190 electrically connected to a corresponding first metal interconnect structure in the first metal interconnect structure 140. The first bonding level dielectric layer further embeds a first pseudo-metal bonding structure 190D, which has a smaller vertical extent than the first metal bonding structure 190 and is electrically isolated from the first metal interconnect structure 140.

[0128] In one embodiment, the first metal bonding structure 190 includes a first metal via portion 190V; the first pseudo-metal bonding structure 190D includes a first pseudo-metal via portion 190DV, the first pseudo-metal via portion having a smaller height than the first metal via portion 190V; and all top peripheries of the first metal via portion 190V and all top peripheries of the first pseudo-metal via portion 190DV are located in a horizontal plane. In one embodiment, the first bonding-level dielectric layer 180 includes a stack of a first silicate glass layer 184 and a first dielectric bonding material layer 186. In one embodiment, each first metal bonding structure in the first metal bonding structure 190 includes a corresponding first metal pad portion connected to a corresponding first metal via portion in the first metal via portion 190V; and each first pseudo-metal bonding structure in the first pseudo-metal bonding structure 190D includes a corresponding first pseudo-metal pad portion connected to a corresponding subset of the first pseudo-metal via portions 190DV.

[0129] In one embodiment, the horizontal interface between the first silicate glass layer 184 and the first dielectric bonding material layer 186 lies within the horizontal plane. In one embodiment, the first metal pad portion and the first dummy metal pad portion have the same height as the thickness of the first dielectric bonding material layer 186. In one embodiment, the first dielectric bonding material layer 186 includes a first silicon carbon nitride layer, which is bonded to a second dielectric bonding material layer 286 in the second semiconductor die 200 via dielectric-to-dielectric bonding.

[0130] In one embodiment, each of the first pseudo-metallic via portions 190DV has a corresponding maximum lateral dimension, which is less than 1 / 3 of the maximum lateral dimension of one of the first pseudo-metallic via portions 190V. In one embodiment, the corresponding subset of the first pseudo-metallic via portions 190DV comprises a corresponding two-dimensional array of the first pseudo-metallic via portions 190DV, each of the first pseudo-metallic via portions having a maximum lateral extent smaller than any of the first pseudo-metallic via portions 190V. In one embodiment, the corresponding subset of the first pseudo-metallic via portions 190DV comprises a corresponding set of two or more first pseudo-metallic via portions 190DV nested within each other, such that each of the first pseudo-metallic via portions 190DV within the corresponding set laterally surrounds or is laterally surrounded by any other first pseudo-metallic via portion within the corresponding set of the two or more first pseudo-metallic via portions 190DV.

[0131] In one embodiment, the first metal bonding structure 190 comprises a first metal via portion 190V; the first pseudo-metal bonding structure 190D comprises a first pseudo-metal via portion 190DV, the first pseudo-metal via portion having a smaller height than the first metal via portion 190V; and all top peripheries of the first metal via portion 190V and all top peripheries of the first pseudo-metal via portion 190DV lie within a horizontal plane including the bonding interface between the first semiconductor die 100 and the second semiconductor die 200. In one embodiment, the first dielectric bonding material layer 186 includes a horizontal surface located within the horizontal plane and is bonded to the second dielectric bonding material layer 286 within the second semiconductor die 200 via dielectric-to-dielectric bonding.

[0132] In one embodiment, the first bonding-level dielectric layer 180 includes a first silicate glass layer 184 that laterally surrounds a first metal via portion 190V and a first pseudo-metal via portion 190DV; and wherein the top surface of the first silicate glass layer 184 lies within the horizontal plane. In one embodiment, the first silicate glass layer 184 is bonded to a second dielectric bonding material layer 286 within a second semiconductor die 200 via dielectric-to-dielectric bonding.

[0133] refer to Figures 10A to 10C The tenth exemplary structure includes a first semiconductor die 100, which can be obtained from... Figure 1A The illustrated first semiconductor die 100 implies that the combination of the first silicate glass layer 184 and the first dielectric bonding material layer 186 is replaced by a first dielectric bonding material layer 185. The first dielectric bonding material layer 185 may comprise any material that can be used in the first dielectric bonding material layer 186 and the first silicate glass layer 184. For example, the first dielectric bonding material layer 185 may comprise the first silicate glass layer (e.g., doped silicate glass or undoped silicate glass). The thickness of the first dielectric bonding material layer 185 may be in the range of 400 nm to 2000 nm (such as 500 nm to 1000 nm), but smaller and larger thicknesses are also possible.

[0134] An etch mask layer (not shown) may be applied over the first dielectric bonding material layer 185 and may be patterned to form a first opening covering the first topmost metal interconnect structure 148 and optionally a second opening covering the first topmost metal interconnect structure 148. According to one aspect of this disclosure, the area of ​​each first opening may be at least twice the area of ​​each second opening, such as four to ten times, such as five to six times. In one embodiment, each of the first and second openings may have a corresponding horizontal cross-sectional shape that is rectangular, rounded rectangular, or circular.

[0135] An anisotropic etching process can be performed to form via cavities (179, 179D) in the upper portion of the first dielectric bonding material layer 185. In one embodiment, the via cavities (179, 179D) may include first via cavities 179 arranged in a two-dimensional array, which may be a two-dimensional periodic array. Each first via cavity 179 may cover a corresponding first top metal interconnect structure in the first top metal interconnect structure 148. In one embodiment, the via cavities (179, 179D) may also include first pseudo-via cavities 179D, which are staggered with the first via cavities 179. The first pseudo-via cavities 179D may optionally cover a corresponding first top metal interconnect structure in the first top metal interconnect structure 148.

[0136] According to one aspect of this disclosure, the first pseudo-via cavity 179D may have a corresponding lateral range smaller than the lateral range of each via cavity 179. The lateral range of each via cavity (179, 179D) may be defined as the maximum lateral dimension of the corresponding via cavity (179, 179D), such as the lateral dimension at the top of the corresponding via cavity. In one embodiment, each first via cavity 179 may have a first lateral range, and each first pseudo-via cavity 179D may have a second lateral range, which is in the range of 10% to 65% (e.g., 20% to 50%) of the first lateral range. The first lateral range may be in the range of 400 nm to 1000 nm (e.g., 500 nm to 700 nm), but may also be smaller and larger in size. Therefore, the lateral dimension at the top of the first via cavity 179 can be in the range of 400nm to 1000nm (such as 500nm to 700nm), while the lateral dimension at the top of the first pseudo via cavity 179D can be in the range of 40nm to 650nm (such as 50nm to 450nm (e.g. 100nm to 350nm)).

[0137] In one embodiment, each sidewall of the first through-hole cavity 179 may have a first cone angle α1 relative to the vertical direction, and each sidewall of the first pseudo-through-hole cavity 179D may have a second cone angle b1 relative to the vertical direction. The first cone angle α1 may be in the range of 10 degrees to 45 degrees, but smaller and larger angles are also possible. The second cone angle b1 may be in the range of 10 degrees to 45 degrees, but smaller and larger angles are also possible. In one embodiment, the second cone angle b1 is the same as the first cone angle α1.

[0138] As mentioned above Figure 5DAs described, the etching rate of the anisotropic etching process used to form the respective via cavities (179, 179D) may be aspect ratio-dependent. In this case, the first via cavity 179 with a lower aspect ratio is etched to a greater depth than the first pseudo-via cavity 179D, which has a higher aspect ratio. Therefore, the first via cavity 179 extends to the first topmost metal interconnect structure 148, and the first via cavity 179 has a greater depth than the first pseudo-via cavity 179D. The depth of the first via cavity 179 is the same as the thickness of the first bonding level dielectric layer 180. In one embodiment, the depth of the first pseudo-via cavity 179D may be in the range of 30% to 80% (e.g., 40% to 70%) of the thickness of the first bonding level dielectric layer 180. The first via cavity 179 may have a horizontal bottom surface exposing the top surface of the first topmost metal interconnect structure 148, while the first pseudo-via cavity 179D may terminate at a point on the bottom. Therefore, the first through-hole cavity 179 may have a trapezoidal vertical cross-sectional shape, while the first pseudo through-hole cavity 179D may have a triangular vertical cross-sectional shape.

[0139] Anisotropic etching parameters are selected to form a first cone angle and a second cone angle such that the desired region of the first topmost metal interconnect structure 148 is exposed in each first via cavity 179, and the first pseudo-via cavity 179D does not extend through the entire thickness of the first bonding level dielectric layer 180. For example, if the thickness of the first bonding level dielectric layer 180 is 520 nm, and the desired exposure width of the top surface of the first topmost metal interconnect structure 148 is 140 nm, then the width of the top of the first via cavity 179 can be 600 nm, and the width of the top of the first pseudo-via cavity 179D can be less than 370 nm, and etching parameters are selected to form a first cone angle a1 and a second cone angle b1 of approximately 24 degrees. In other words, the angle between the horizontal surface and the sidewalls of the cavities (179, 179D) is approximately 66 degrees.

[0140] refer to Figure 10D , Figure 10E and Figure 10F Execute the above regarding Figure 9D The described steps are to form a first metal bonding structure 190 and a first pseudo metal bonding structure 190D in the respective first through-hole cavity 179 and first pseudo through-hole cavity 179D.

[0141] refer to Figure 10G Execute the above regarding Figure 9E The described steps are to bond a first semiconductor die 100 to a second semiconductor die 200 to form a bonding assembly.

[0142] refer to Figures 10A to 10GA bonding assembly is provided for a first semiconductor die 100 and a second semiconductor die 200. The first semiconductor die 100 includes: a first dielectric material layer 130 located on a first semiconductor device 120; a first metal interconnect structure 140 embedded in the first dielectric material layer 130 and electrically connected to the first semiconductor device 120; and a first bonding level dielectric layer 180 located on the first dielectric material layer 130 and embedded in a first metal bonding structure 190 electrically connected to a corresponding first metal interconnect structure in the first metal interconnect structure 140, and the first bonding level dielectric layer further embedding a first pseudo-metal bonding structure 190D. The first metal bonding structure 190 has a different vertical cross-sectional shape than the first pseudo-metal bonding structure 190D.

[0143] In one embodiment, the first pseudo-metallic bond structure 190 has a smaller lateral extent than the first metallic bond structure 190D. In one embodiment, the first metallic bond structure 190 has a trapezoidal vertical cross-sectional shape, and the first pseudo-metallic bond structure 190 has a triangular vertical cross-sectional shape.

[0144] In one embodiment, the sidewalls of the first metal bonding structure and the first pseudo-metal bonding structure are tapered, such that the first metal bonding structure contacts a predetermined region of the first metal interconnect structure in the first metal interconnect structure, and that the first pseudo-metal bonding structure does not extend through the entire thickness of the first bonding level dielectric layer.

[0145] In one embodiment, the first metal bonding structure 190 includes a first metal through-hole portion (or may be composed of the first metal through-hole portion); the first pseudo-metal bonding structure 190D includes a first pseudo-metal through-hole portion (or may be composed of the first pseudo-metal through-hole portion), the first pseudo-metal through-hole portion having a smaller height than the first metal through-hole portion; and all top peripheries of the first metal through-hole portion and all top peripheries of the first pseudo-metal through-hole portion are located in a horizontal plane.

[0146] In one embodiment, the first metal bonding structure 190 has the same composition as the first pseudo-metal bonding structure 190D. For example, the first metal bonding structure 190 and the first pseudo-metal bonding structure 190D each include a corresponding metal barrier pad 190B and a corresponding metal filler portion 190F.

[0147] Figures 11A to 11F Steps for forming an eleventh exemplary structure according to another embodiment of this disclosure are illustrated. (See reference...) Figure 11AThe eleventh exemplary structure includes a first semiconductor die 100, which can be obtained from... Figure 1A The illustrated first semiconductor die 100 implies that the combination of the first silicate glass layer 184 and the first dielectric bonding material layer 186 is replaced by a first dielectric bonding material layer 185. The first dielectric bonding material layer 185 may comprise any material that can be used in the first dielectric bonding material layer 186 and the first silicate glass layer 184. For example, the first dielectric bonding material layer 185 may comprise an undoped silicate glass layer (i.e., silicon oxide) or a doped silicate glass layer. The thickness of the first dielectric bonding material layer 185 may be in the range of 400 nm to 2000 nm (such as 600 nm to 2000 nm), but smaller and larger thicknesses are also possible.

[0148] An etch mask layer (not shown) may be applied over the first dielectric bonding material layer 185 and may be patterned to form a first opening covering the first topmost metal interconnect structure 148 and optionally a second opening covering the first topmost metal interconnect structure 148. According to one aspect of this disclosure, the area of ​​each first opening may be at least 1.5 times, and / or at least 2 times, and / or at least 4 times, such as 1.5 times to 10 times, larger than the area of ​​each second opening. In one embodiment, each of the first and second openings may have a corresponding horizontal cross-sectional shape of rectangle, rounded rectangle, or circle.

[0149] An anisotropic etching process can be performed to form cavities (179, 179D) in the upper portion of the first dielectric bonding material layer 185. In one embodiment, the cavities (179, 179D) may include first cavities 179 arranged in a two-dimensional array, which may be a two-dimensional periodic array. Each first cavity 179 may cover a corresponding first topmost metal interconnect structure in the first topmost metal interconnect structure 148. In one embodiment, the cavities (179, 179D) may also include first pseudo-cavities 179D, which are staggered with the first cavities 179. The first pseudo-cavities 179D may optionally cover a corresponding first topmost metal interconnect structure in the first topmost metal interconnect structure 148. Figure 11A In the embodiment shown, the first pseudo-cavity 179D does not cover the corresponding first top metal interconnect structure in the first top metal interconnect structure 148.

[0150] The first pseudo-cavity 179D may have a corresponding lateral range smaller than the lateral range of each first cavity 179. The lateral range of each cavity (179, 179D) may be defined as the maximum lateral dimension of the corresponding cavity (179, 179D). In one embodiment, each first cavity 179 may have a first lateral range, and each first pseudo-cavity 179D may have a second lateral range, which is in the range of 10% to 80% (e.g., 20% to 60%) of the first lateral range. The first lateral range may be in the range of 500 nm to 2000 nm, but smaller and larger dimensions are also possible.

[0151] In one embodiment, each sidewall of the first cavity 179 may have a first cone angle α1 relative to the vertical direction, and each sidewall of the first pseudo-cavity 179D may have a second cone angle b1 relative to the vertical direction. The first cone angle α1 may be in the range of 3 degrees to 30 degrees, but smaller and larger angles are also possible. The second cone angle b1 may be in the range of 3 degrees to 30 degrees, but smaller and larger angles are also possible. In this embodiment, the first cone angle may be equal to the second cone angle, or the first cone angle may be different from the second cone angle.

[0152] The depth of the first recess 179 is the same as or greater than the depth of the first dummy recess 179D. In one embodiment, the depths of the first recess 179 and the first dummy recess 179D may be in the range of 30% to 80% (e.g., 40% to 70%) of the thickness of the first bonding level dielectric layer 180. In one embodiment, the depths of the first recess 179 and the first dummy recess 179D may be in the range of 30% to 80% (e.g., 40% to 70%) of the thickness of the first dielectric bonding material layer 185. In one embodiment, the anisotropic etching process patterning the first recess 179 and the first dummy recess 179D may have an etching rate that depends on the aspect ratio of the etched material portion. Subsequently, the etch mask layer may be selectively removed relative to the materials of the first dielectric bonding material layer 185, the first etch stop dielectric layer 182, and the first topmost metal interconnect structure 148. In summary, the first cavity 179 and the first pseudo-cavity 179D can be formed in the first bonding stage dielectric layer 180 such that each first pseudo-cavity 179D has a smaller lateral extent than each first cavity 179 (i.e., narrower than each first cavity).

[0153] refer to Figure 11BThe insulating material may be conformally deposited in the peripheral portions of the first cavity 179 and the first pseudo-cavity 179D, and above the top surface of the first dielectric bonding material layer 185. A continuous insulating material layer 183L may be formed in the peripheral portions of the first cavity 179 and the first pseudo-cavity 179D, and above the first dielectric bonding material layer 185. The continuous insulating material layer 183L comprises an insulating material, such as silicon nitride, silicon oxynitride, silicon carbonitride, dielectric metal oxide, etc. In one embodiment, the continuous insulating material layer 183L comprises silicon carbonitride and / or is substantially composed of silicon carbonitride. The thickness of the continuous insulating material layer 183L may be selected such that the ratio of the maximum lateral dimension of the second void 179V2 located within the first pseudo-cavity 179D to the maximum lateral dimension of the first void 179V1 located within the first cavity 179 is in the range of 0.01 to 0.5 (such as 0.1 to 0.4), but smaller and larger ratios may also be used. In other words, the second gap 179V2 is narrower than the first gap 179V1.

[0154] refer to Figure 11C A first anisotropic etching process can be performed to etch the horizontally extended portion of the continuous insulating material layer 183L. Each remaining portion of the continuous insulating material layer 183L located in the peripheral portion of the corresponding first cavity 179 includes a first type of in-process insulating spacer 18A'. Each remaining portion of the continuous insulating material layer 183L located in the peripheral portion of the corresponding first pseudo-cavity 179D includes a second type of in-process insulating spacer 18B'. The first type of in-process insulating spacer 18A' and the second type of in-process insulating spacer 18AB' are collectively referred to as in-process insulating spacer 183'.

[0155] refer to Figure 11D A second anisotropic etching process can be performed to etch the materials of the first dielectric bonding material layer 185, the in-process insulating spacer 183', and the first etch-stop dielectric layer 182. According to one aspect of this disclosure, the second anisotropic etching process may include etching chemicals and / or process conditions that etch the corners of the in-process insulating spacer 183' and / or selectively etch the material of the in-process insulating spacer 183' at a higher etch rate than that of the material of the first dielectric bonding material layer 185. Each first-type in-process insulating spacer 18A' is converted to a first-type insulating spacer 18A, which has a generally tubular configuration and is located in the peripheral portion of a corresponding first cavity 179. Each second-type in-process insulating spacer 18B' is converted to a second-type insulating spacer 18B, which has a generally tubular configuration and is located in the peripheral portion of a corresponding first pseudo-cavity 179D.

[0156] Each first-type insulating spacer 18A is embedded in the first bonding-level dielectric layer 180 and vertically spaced from the first dielectric material layer 130. Each second-type insulating spacer 18B is embedded in the first bonding-level dielectric layer 180 and vertically spaced from the first dielectric material layer 130. In one embodiment, during the initial anisotropic etching step of the second anisotropic etching process, the etching rate of the material of the insulating spacer 183 is higher than the etching rate of the material of the first dielectric bonding material layer 185, and the insulating spacer 183 may be completely formed below a horizontal plane including the recessed horizontal top surface of the first dielectric bonding material layer 185. In one embodiment, the insulating spacer 183 may be completely located below a first horizontal plane and may be vertically spaced from the first horizontal plane, which includes the topmost surface of the first bonding-level dielectric layer 180 and may be the recessed horizontal top surface of the first dielectric bonding material layer 185. In one embodiment, the insulating spacer 183 may be formed entirely above the second horizontal plane and may be vertically spaced from the second horizontal plane, which includes the bottom surface of the first bonding stage dielectric layer 180.

[0157] A first stepped through-hole cavity 189S1 is formed in the space of each first gap 179V1. The first stepped through-hole cavity 189S1 is laterally surrounded by a corresponding first-type insulating spacer of the first-type insulating spacer 18A. A second stepped through-hole cavity 189S2 is formed in the space of each second gap 179V2. The second stepped through-hole cavity 189S2 is laterally surrounded by a corresponding second-type insulating spacer of the second-type insulating spacer 18B. As used herein, a stepped through-hole cavity refers to a cavity having stepped sidewalls (i.e., sidewalls comprising a plurality of vertically extending sidewall segments connected by at least one laterally extending surface segment).

[0158] Each first stepped via 189S1 extends through a corresponding first-type insulating spacer 18A and through the first bonding level dielectric layer 180 to the top surface of a corresponding first metal interconnect structure in the first metal interconnect structure 140. Each second stepped via 189S2 extends through a corresponding second-type insulating spacer 18B and has a bottom surface covering the bottom surface of the first bonding level dielectric layer 180, and does not extend to the top surface of a corresponding first metal interconnect structure in the first metal interconnect structure 140.

[0159] According to one aspect of this disclosure, the second anisotropic etching process includes a reactive ion etching (RIE) process, which includes tapered etching conditions for generating microloads. For example, the RIE process incorporates an etching chemical that generates a polymer, which produces a polymer material as an etching product. The polymer material blocks the width of the remaining, narrower second void 179V2 in the narrower second stepped via cavity 189S2, and terminates the RIE process before the bottom surface of the second stepped via cavity 189S2 reaches the bottom surface of the first bonding stage dielectric layer 180. In contrast, the polymer material does not block the entire width of the wider remaining first void 179V1 in the wider first stepped via 189S1, and the RIE process continues until the bottom surface of the first stepped via 189S1 reaches the bottom surface of the first bonding stage dielectric layer 180 and the top surface of the corresponding first metal interconnect structure in the first metal interconnect structure 140 is exposed to the bottom of the corresponding first stepped via 189S1. In one embodiment, each second stepped via 189S2 has a smaller vertical and lateral extent than any first stepped via 189S1.

[0160] The upper portion of the first stepped via cavity 189S1 includes a wider pad portion of the cavity, and the lower portion of the first stepped via cavity 189S1 includes a narrower via portion of the cavity. Therefore, a separate via photolithography step is not required in the eleventh exemplary structure.

[0161] In one embodiment, each first stepped cavity 189S1 may have a first vertical cross-sectional profile including a first contoured sidewall, the first contoured sidewall including a first upper sidewall segment having a first upper cone angle a1 relative to the vertical direction, a first lower sidewall segment having a first lower cone angle a2 relative to the vertical direction, and a first connecting surface segment having a first connecting cone angle a3 relative to the vertical direction. The first upper sidewall segment may be a physically exposed upper sidewall segment of the first dielectric bonding material layer 185. The first lower sidewall segment may include a physically exposed lower sidewall segment of the first type insulating spacer 18A and additional physically exposed lower sidewall segments of the first dielectric bonding material layer 185. The first connecting surface segment may include additional physically exposed upper sidewall segments of the first type insulating spacer 18A. The first connecting cone angle a3 is greater than the first upper cone angle a1 and the first lower cone angle a2. In one embodiment, the first upper cone angle a1 may be in the range of 3 degrees to 30 degrees, but smaller and larger angles may also be used. In one implementation, the first lower cone angle a2 may be in the range of 3 degrees to 30 degrees, but smaller and larger angles may also be used. The first connecting cone angle a3 may be in the range of 6 degrees to 60 degrees (such as from 10 degrees to 45 degrees), but smaller and larger angles may also be used.

[0162] In one embodiment, each second stepped cavity 189S2 may have a second vertical cross-sectional profile including a second profiled sidewall, the second profiled sidewall including a second upper sidewall segment having a second upper cone angle b1 relative to the vertical direction, a second lower sidewall segment having a second lower cone angle b2 relative to the vertical direction, and a second connecting surface segment having a second connecting cone angle b3 relative to the vertical direction. The second upper sidewall segment may be a physically exposed upper sidewall segment of the first dielectric bonding material layer 185. The second lower sidewall segment may include a physically exposed lower sidewall segment of the second type insulating spacer 18B and additional physically exposed lower sidewall segments of the first dielectric bonding material layer 185. The second connecting surface segment may include additional physically exposed upper sidewall segments of the second type insulating spacer 18B. The second connecting cone angle b3 is greater than the second upper cone angle b1 and the second lower cone angle b2. In one embodiment, the second upper cone angle b1 may be in the range of 3 degrees to 30 degrees, but smaller and larger angles may also be used. In one embodiment, the second lower cone angle b2 may be in the range of 3 degrees to 30 degrees, but smaller and larger angles may also be used. The second connecting cone angle b3 may be in the range of 6 degrees to 60 degrees (such as 10 degrees to 45 degrees), but smaller and larger angles may also be used. In one embodiment, the second upper cone angle b1 may be the same as the first upper cone angle a1, and the second lower cone angle b2 may be the same as the first lower cone angle a2.

[0163] refer to Figure 11E At least one conductive material may be deposited in the first stepped cavity 189S1 and the second stepped cavity 189S2. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the first dielectric bonding material layer 185 by performing a planarization process. In one embodiment, the at least one conductive material may comprise a combination of a conductive metal barrier material and a metal filler material. The conductive metal barrier material may comprise a metal nitride material, such as WN, TiN, TaN, MoN, TiC, TaC, and / or WC, and may have a thickness in the range of 5 nm to 50 nm, but smaller and larger thicknesses are also possible. The conductive metal barrier material may be deposited by physical vapor deposition or by chemical vapor deposition. The metal filler material comprises highly conductive metals, such as W, Cu, Cu-Al, Al, Mo, Co, Ru, etc. The metal filler material may be deposited by physical vapor deposition, electroplating, and / or chemical vapor deposition. The planarization process that can be used to remove excess portions of the at least one conductive material from above a horizontal plane including the top surface of the first dielectric bonding material layer 185 may employ chemical mechanical polishing.

[0164] The filling of each remaining portion of the corresponding first stepped cavity 189S1 with the at least one conductive material constitutes a first stepped bonding structure 190S, which is a type of first conductive bonding structure 190. In one embodiment, each first metal bonding structure in the first stepped bonding structure 190S includes a combination of a first metal barrier pad 190B (which is a patterned portion of conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of metal filler material). The filling of each remaining portion of the corresponding second stepped cavity 189S2 with the at least one conductive material constitutes a first pseudo-stepped bonding structure 190DS, which is a type of first pseudo-conductive bonding structure 190D. In one embodiment, each first pseudo-metal bonding structure in the first pseudo-stepped bonding structure 190DS includes a combination of a first metal barrier pad 190B (which is a patterned portion of conductive metal barrier material) and a first metal filler portion 190F (which is a patterned portion of metal filler material).

[0165] A first conductive bonding structure 190 (including a first stepped bonding structure 190S) may be formed in a first stepped via cavity 189S1. A first pseudo-conductive bonding structure 190D (including a first pseudo-stepped bonding structure 190DS) may be formed in a second stepped via cavity 189S2. At least one of the first conductive bonding structures 190 may be electrically connected to one of the first metal interconnect structures 140. Each of the first pseudo-conductive bonding structures 190D may have a smaller vertical extent than the first conductive bonding structure 190 and may be electrically isolated from the first metal interconnect structure 140. Each of the first pseudo-conductive bonding structures 190D may have a smaller vertical and lateral extent than any of the first conductive bonding structures 190.

[0166] In one embodiment, at least one of the first conductive bonding structures 190 may have a first vertical cross-sectional profile, the first vertical cross-sectional profile including a first profile-shaped sidewall, the first profile-shaped sidewall including a first upper sidewall segment having a first upper cone angle a1 relative to the vertical direction, a first lower sidewall segment having a first lower cone angle a2 relative to the vertical direction, and a first connecting surface segment having a first connecting cone angle a3 relative to the vertical direction, the first connecting cone angle a3 being greater than the first upper cone angle a1 and the first lower cone angle a2. In one embodiment, at least one of the first pseudo-conductive bonding structures 190D may have a second vertical cross-sectional profile, the second vertical cross-sectional profile including a second profile-shaped sidewall, the second profile-shaped sidewall including a second upper sidewall segment having a second upper cone angle b1 relative to the vertical direction, a second lower sidewall segment having a second lower cone angle b2 relative to the vertical direction, and a second connecting surface segment b3 having a second connecting cone angle relative to the vertical direction, the second connecting cone angle being greater than the second upper cone angle b1 and the second lower cone angle b2.

[0167] In one embodiment, the second upper cone angle b1 is the same as the first upper cone angle a1, and the second lower cone angle b2 is the same as the first lower cone angle a2. In one embodiment, the first upper sidewall section contacts the first bonding level dielectric layer 180, and the lower portion of the first lower sidewall section contacts the first bonding level dielectric layer 180. In one embodiment, the upper portion of the first lower sidewall section contacts the first type insulating spacer 18A, and the first connection surface section contacts the first type insulating spacer 18A.

[0168] refer to Figure 11F A second semiconductor die 200 may be provided. This second semiconductor die includes a second substrate 208, a second semiconductor device 220, a second dielectric material layer 230, and a second bonding level dielectric layer 280. The second semiconductor device is formed on and / or within the second substrate 208. The second dielectric material layer is formed above the second semiconductor device 220 and embedded in a second metal interconnect structure 240. The second bonding level dielectric layer is formed above the second dielectric material layer 230. The second substrate 208 may include any substrate that can be used with the first substrate 108. The second semiconductor device 220 may include any type of semiconductor device known in the art. In one embodiment, the first semiconductor device 120 may include a memory array, and the second semiconductor device 220 may include peripheral circuitry configured to control the operation of the memory array, or vice versa. The second metal interconnect structure 240 may be electrically connected to the second semiconductor device 220.

[0169] A second topmost metal interconnect structure 248 is illustrated, which is a subset of the second metal interconnect structure 240. In one embodiment, the second topmost metal interconnect structure 248 may have the same pattern as the two-dimensional array of the second conductive bonding structures 290 formed in the second bonding stage dielectric layer 280. In one embodiment, the second topmost metal interconnect structure 248 may be arranged in a rectangular array pattern or in a hexagonal array pattern.

[0170] The second bonding stage dielectric layer 280 includes a second etch-stop dielectric layer 282 and a second dielectric bonding material layer 285. The second etch-stop dielectric layer 282 includes a dielectric material that can be used as an etch-stop structure. For example, the second etch-stop dielectric layer 282 may include silicon nitride, silicon carbonitride, and / or dielectric metal oxide. The thickness of the second etch-stop dielectric layer 282 may range from 10 nm to 50 nm, but smaller and larger thicknesses are also possible. The second dielectric bonding material layer 285 may include any material that can be used in the first dielectric bonding material layer 185. The thickness of the second dielectric bonding material layer 285 may range from 400 nm to 2000 nm (such as 600 nm to 1200 nm), but smaller and larger thicknesses are also possible.

[0171] Reference can be performed on the second semiconductor die 200 Figures 11A to 11E The described processing steps are modified, with any necessary alterations, to form a second stepped bond structure 290S and a second pseudo-stepped bond structure 290DS in the second bonding stage dielectric layer 280. The second stepped bond structure 290S is a second conductive bond structure 290. The second pseudo-stepped bond structure 290DS is a second pseudo-conductive bond structure 290D. In one embodiment, each second stepped bond structure in the second stepped bond structure 290S includes a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). In one embodiment, each second pseudo-stepped bond structure in the second pseudo-stepped bond structure 290DS includes a combination of a second metal barrier pad 290B (which is a patterned portion of a conductive metal barrier material) and a second metal filler portion 290F (which is a patterned portion of a metal filler material). Generally speaking, the geometric features of the second stepped joint structure 290S can be the same as those of the first stepped joint structure 190S, and the geometric features of the second pseudo-stepped joint structure 290DS can be the same as those of the first pseudo-stepped joint structure 190DS.

[0172] In one embodiment, the second step-step bond structure 290S can be arranged as a mirror image of the first step-step bond structure 190S. In another embodiment, the second pseudo-step-step bond structure 290DS can be arranged as a mirror image of the pattern of the first pseudo-step-step bond structure 190DS without any area overlap.

[0173] The second conductive bonding structure 290 (which may include a second step-bonding structure 290S) can be bonded to the first step-bonding structure 190S via metal-to-metal bonding. In one embodiment, the entire horizontal surface of the first pseudo-step-bonding structure 190DS, which is coplanar with the horizontal surface of the first dielectric bonding material layer 185, is in contact with the horizontal surface of the second dielectric bonding material layer 285. In one embodiment, the entire horizontal surface of the second pseudo-step-bonding structure 290DS, which is coplanar with the horizontal surface of the second dielectric bonding material layer 285, is in contact with the horizontal surface of the first dielectric bonding material layer 185.

[0174] In one embodiment, in addition to metal-to-metal bonding, dielectric-to-dielectric bonding may be performed between the second dielectric bonding material layer 285 and the first dielectric bonding material layer 185. Generally, each of the second dielectric bonding material layer 285 and the first dielectric bonding material layer 185 includes and / or is substantially composed of a corresponding dielectric material that can be used for dielectric-to-dielectric bonding.

[0175] refer to Figure 11G An alternative configuration of the eleventh exemplary structure according to the embodiments of this disclosure can be obtained from the following methods: Figure 11F The eleventh exemplary structure derivation shows that the layout of the first pseudo-stepped bond structure 190DS and the second pseudo-stepped bond structure 290DS is modified such that the pattern of the second pseudo-stepped bond structure 290DS is a mirror image of the pattern of the first pseudo-stepped bond structure 190DS. Therefore, the first pseudo-stepped bond structure 190DS can be bonded to the second pseudo-stepped bond structure 290DS via metal-to-metal bonding.

[0176] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not mutually exclusive. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device can provide equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. In cases where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A method for forming a semiconductor structure, the method comprising: A first semiconductor device is formed above, on, or in the first substrate; A first dielectric material layer is formed above the first semiconductor device, wherein the first metal interconnect structure is electrically connected to the first semiconductor device. A first bonding level dielectric layer comprising a stack of layers is formed above the first dielectric material layer, the stack of layers comprising a first silicate glass layer and a first dielectric bonding material layer; A through-hole cavity is formed through the first dielectric bonding material layer and the first silicate glass layer; The via cavity is converted into an integrated pad and via cavity by performing a selective etching process, wherein the selective etching process selectively etches the material of the first dielectric bonding material layer relative to the material of the first silicate glass layer; as well as A first integrated pad and via bonding structure is formed, comprising a corresponding metal via portion and a corresponding metal pad portion. The corresponding metal via portion is laterally surrounded by a first silicate glass layer, and the corresponding metal pad portion is laterally surrounded by a first dielectric bonding material layer within the via cavity. One of the first integrated pad and via bonding structures includes a first metal barrier pad that contacts the sidewall of the first silicate glass layer, the horizontal surface of the first silicate glass layer, and the entire sidewall of the first dielectric bonding material layer.

2. The method according to claim 1, further comprising: A hard mask layer is formed over the first dielectric bonding material layer, the hard mask layer including an opening through the hard mask layer; as well as The hard mask layer is used as an etching mask to perform an anisotropic etching process to form the via cavity through the first dielectric bonding material layer and the first silicate glass layer.

3. The method according to claim 2, further comprising: The hard mask layer is removed before performing the selective etching process.

4. The method of claim 2, wherein the selective etching process laterally extends the via cavity at the level of the first dielectric bonding material layer to form the integrated pad and the pad cavity portion of the via cavity, and reduces the thickness of the first dielectric bonding material layer to the same size as the lateral etching distance of the sidewall of the first dielectric bonding material layer around the via cavity.

5. The method of claim 2, wherein the selective etching process is performed when the hard mask layer is present on the top surface of the first dielectric bonding material layer.

6. The method of claim 5, wherein the thickness of the first dielectric bonding material layer remains constant during the selective etching process.

7. The method of claim 1, wherein the selective etching process comprises an isotropic etching process.

8. The method according to claim 1, wherein: The first dielectric bonding material layer includes a first silicon carbon nitride layer; and The first metal barrier pad includes a conductive metal nitride or conductive metal carbide layer that extends from the bottom surface to the top surface of the first silicon carbide layer and surrounds a portion of the metal or metal alloy filler material.

9. The method according to claim 1, further comprising: A second semiconductor die is provided, the second semiconductor die including a second dielectric material layer located on a second semiconductor device and embedded in a second metal interconnect structure, and further including a second bonding level dielectric layer embedded in a metal bonding structure; as well as The metal bonding structure is bonded to the first integrated pad and through-hole bonding structure by metal-to-metal bonding.

10. The method according to claim 9, further comprising: The second bonding level dielectric layer is bonded to the first dielectric bonding material layer by dielectric-to-dielectric bonding.

11. A bonding assembly for a first semiconductor die and a second semiconductor die, wherein the first semiconductor die comprises: A first dielectric material layer is located on a first semiconductor device; A first metal interconnect structure is embedded in the first dielectric material layer and electrically connected to the first semiconductor device. A first bonding level dielectric layer is located on the first dielectric material layer and includes a layer stack, the layer stack including a first silicate glass layer and a first silicon carbon nitride layer; and A first integrated pad and via bonding structure includes corresponding metal via portions and corresponding metal pad portions. The corresponding metal via portions are laterally surrounded by a first silicate glass layer, and the corresponding metal pad portions are laterally surrounded by a first silicon carbon nitride layer and bonded to a corresponding second metal bonding structure of the second semiconductor die by metal-to-metal bonding. One of the first integrated pad and via bonding structures includes a first metal barrier pad that contacts the sidewall of the first silicate glass layer, the horizontal surface of the first silicate glass layer, and the entire sidewall of the first silicon carbon nitride layer.

12. The bonding assembly of claim 11, wherein the second semiconductor die includes a second bonding-level dielectric layer, the second bonding-level dielectric layer being embedded in the second metal bonding structure and bonded to the first silicon carbon nitride layer by dielectric-to-dielectric bonding.

13. The bonding assembly of claim 12, wherein the second bonding stage dielectric layer comprises a second silicon carbon nitride layer, the second silicon carbon nitride layer being bonded to the first silicon carbon nitride layer via the dielectric-to-dielectric bonding.

14. The bonding assembly of claim 12, wherein the second bonding stage dielectric layer comprises a second silicate glass layer, the second silicate glass layer being bonded to the first silicon carbonitride layer via the dielectric-to-dielectric bonding.

15. The bonding assembly of claim 11, wherein the bottom surface of the metal pad portion of the first integrated pad and via bonding structure lies within a horizontal plane including the interface between the first silicate glass layer and the first silicon carbon nitride layer.

16. The bonding assembly of claim 11, wherein the first metal barrier pad comprises a conductive metal nitride or conductive metal carbide layer extending from the bottom surface to the top surface of the first silicon carbon nitride layer and surrounding a portion of the metal or metal alloy filler material.

17. The bonding assembly of claim 16, wherein the first bonding stage dielectric layer further comprises a first etch-stop dielectric layer located below the first silicate glass layer and contacting and laterally surrounding the first metal barrier pad.

18. The bonding assembly of claim 11, wherein the second semiconductor die comprises: A second dielectric material layer is located on a second semiconductor device; A second metal interconnect structure is embedded in the second dielectric material layer and electrically connected to the second semiconductor device; and A second bonding-level dielectric layer is located on the second dielectric material layer and comprises a layer stack, the layer stack including a second silicate glass layer and a second silicon carbon nitride layer. The second metal bonding structure includes a second integrated pad and via bonding structure. The second integrated pad and via bonding structure includes a corresponding metal via portion and a corresponding metal pad portion. The corresponding metal via portion is laterally surrounded by a second silicate glass layer, and the corresponding metal pad portion is laterally surrounded by a second silicon carbon nitride layer.

19. The bonding assembly of claim 11, wherein the second semiconductor die comprises: A second dielectric material layer is located on a second semiconductor device; A second metal interconnect structure is embedded in the second dielectric material layer and electrically connected to the second semiconductor device; and A second bonding-level dielectric layer is located on the second dielectric material layer and comprises a layer stack, the layer stack including a second silicate glass layer and a second silicon carbon nitride layer. The second metal bonding structure includes a through-hole bonding structure, which includes a corresponding straight sidewall that extends through the entire second silicate glass layer and through the entire second silicon carbon nitride layer.

20. The bonding assembly of claim 11, wherein the second semiconductor die comprises: A second dielectric material layer is located on a second semiconductor device; A second metal interconnect structure is embedded in the second dielectric material layer and electrically connected to the second semiconductor device; and A second bonding-level dielectric layer, situated on the second dielectric material layer and comprising a layer stack including a second silicate glass layer and an etch-stop dielectric layer. The second metal bonding structure includes a through-hole bonding structure, which includes a corresponding straight sidewall that extends through the entire second silicate glass layer and through the entire etch-stop dielectric layer.

21. A bonding assembly for a first semiconductor die and a second semiconductor die, wherein the first semiconductor die comprises: A first dielectric material layer is located on a first semiconductor device; A first metal interconnect structure is embedded in the first dielectric material layer and electrically connected to the first semiconductor device. and A first bonding level dielectric layer is located on the first dielectric material layer and embedded with a first metal bonding structure. The first metal bonding structure is electrically connected to a corresponding first metal bonding structure in the first metal bonding structure. The first bonding level dielectric layer further embeds a first pseudo-metal bonding structure. The first pseudo-metal bonding structure has a smaller vertical range than the first metal bonding structure and is electrically isolated from the first metal interconnect structure. The first metal bonding structure has the same composition as the first pseudo-metal bonding structure.

22. The bonding component of claim 21, wherein: The first metal bonding structure includes a first metal through-hole portion; The first pseudo-metal bonding structure includes a first pseudo-metal via portion, the first pseudo-metal via portion having a smaller height than the first metal via portion; and All top peripheries of the first metal through-hole portion and all top peripheries of the first pseudo-metal through-hole portion lie in a horizontal plane.

23. The bonding assembly of claim 22, wherein the first bonding stage dielectric layer comprises a stack of a first silicate glass layer and a first dielectric bonding material layer.

24. The bonding component of claim 23, wherein: Each of the first metal bonding structures includes a corresponding first metal pad portion, the corresponding first metal pad portion being connected to a corresponding first metal via portion in the first metal via portion; and Each of the first pseudo-metal bonding structures in the first pseudo-metal bonding structure includes a corresponding first pseudo-metal pad portion, the corresponding first pseudo-metal pad portion being connected to a corresponding subset of a plurality of first pseudo-metal via portions.

25. The bonding assembly of claim 24, wherein the horizontal interface between the first silicate glass layer and the first dielectric bonding material layer is located in the horizontal plane.

26. The bonding assembly of claim 24, wherein the first metal pad portion and the first pseudo-metal pad portion have the same height as the thickness of the first dielectric bonding material layer.

27. The bonding assembly of claim 24, wherein the first dielectric bonding material layer comprises a first silicon carbon nitride layer, the first silicon carbon nitride layer being bonded to the second dielectric bonding material layer in the second semiconductor die via dielectric-to-dielectric bonding.

28. The bonding assembly of claim 24, wherein each of the first pseudo-metal via portions has a corresponding maximum lateral dimension, the corresponding maximum lateral dimension being less than 1 / 3 of the maximum lateral dimension of one of the first metal via portions.

29. The bonding assembly of claim 24, wherein the respective subset of the plurality of first pseudo-metal via portions comprises a respective two-dimensional array of first pseudo-metal via portions, each of the first pseudo-metal via portions having a maximum lateral extent smaller than any of the first metal via portions.

30. The bonding assembly of claim 24, wherein the respective subset of the plurality of first pseudo-metal via portions comprises a respective set of two or more first pseudo-metal via portions nested within each other, such that each first pseudo-metal via portion within the respective set of two or more first pseudo-metal via portions laterally surrounds or is laterally surrounded by any other first pseudo-metal via portion within the respective set of two or more first pseudo-metal via portions.

31. The bonding component according to claim 23, wherein: The first metal bonding structure is composed of the first metal through-hole portion; The first pseudo-metal bonding structure is composed of the first pseudo-metal through-hole portion.

32. The bonding assembly of claim 31, wherein the first dielectric bonding material layer includes a horizontal surface located in the horizontal plane and is bonded to the second dielectric bonding material layer within the second semiconductor die by dielectric-to-dielectric bonding.

33. The bonding component according to claim 22, wherein: The first bonding-level dielectric layer includes a first silicate glass layer, which laterally surrounds the first metal via portion and the first pseudo-metal via portion; and The top surface of the first silicate glass layer lies within the horizontal plane.

34. The bonding assembly of claim 33, wherein the first silicate glass layer is bonded to a second dielectric bonding material layer within the second semiconductor die by dielectric-to-dielectric bonding.

35. A method for forming a semiconductor structure, the method comprising: A first semiconductor device is formed above, on, or in the first substrate; A first metal interconnect structure is formed above the first semiconductor device and embedded in a first dielectric material layer; A first bonding level dielectric layer is formed above the first dielectric material layer; A via cavity and a pseudo via cavity are formed in the first bonding level dielectric layer, wherein the via cavity extends vertically from the top surface of the bonding level dielectric layer to the bottom surface of the bonding level dielectric layer, and the pseudo via cavity has a smaller vertical range than the via cavity; as well as A first metal bonding structure and a first pseudo-metal bonding structure are formed, wherein each of the first metal bonding structures is formed in a corresponding first space, the corresponding first space comprising the entire space of a corresponding via cavity, and each of the first pseudo-metal bonding structures is formed in a corresponding second space, the corresponding second space comprising the entire space of a corresponding subset of the plurality of pseudo-via cavities, wherein the first metal bonding structure has the same composition as the first pseudo-metal bonding structure.

36. The method according to claim 35, further comprising: A hard mask layer is formed over the first dielectric bonding material layer, the hard mask layer including an opening through the hard mask layer; as well as The hard mask layer is used as an etching mask to perform an anisotropic etching process to form the via cavity and the pseudo via cavity through the first bonding level dielectric layer.

37. The method of claim 36, wherein: The first bonding-level dielectric layer includes a layer stack, the layer stack including a first silicate glass layer and a first dielectric bonding material layer; and The method further includes performing a selective etching process that selectively etches the material of the first dielectric bonding material layer relative to the material of the first silicate glass layer, thereby converting each via cavity in the via cavity into a corresponding integrated pad and via cavity, and converting each pseudo via cavity in the pseudo via cavity into a corresponding integrated pad and via cavity.

38. The method according to claim 37, further comprising: The hard mask layer is removed before performing the selective etching process.

39. The method of claim 37, wherein the selective etching process is performed when the hard mask layer is present on the top surface of the first dielectric bonding material layer.

40. The method of claim 35, wherein: The corresponding first space is the same as the entire space of the corresponding through-hole cavity; and The corresponding second space is the same as the entire space of the corresponding subset of the plurality of pseudo-through-hole cavities.

41. A bonding assembly for a first semiconductor die and a second semiconductor die, wherein the first semiconductor die comprises: A first dielectric material layer is located on a first semiconductor device; A first metal interconnect structure is embedded in the first dielectric material layer and electrically connected to the first semiconductor device. A first bonding level dielectric layer is located on the first dielectric material layer and embedded with a first metal bonding structure. The first metal bonding structure is electrically connected to a first metal bonding structure within the first metal bonding structure. The first bonding level dielectric layer further embeds a first pseudo-metal bonding structure. The first pseudo-metal bonding structure has a smaller vertical range than the first metal bonding structure and is electrically isolated from the first metal interconnect structure. The first metal bonding structure has a different vertical cross-sectional shape than the first pseudo-metal bonding structure.

42. The bonding assembly of claim 41, wherein the first pseudo-metallic bonding structure has a smaller lateral extent than the first metallic bonding structure.

43. The bonding assembly of claim 41, wherein the first metal bonding structure has a trapezoidal vertical cross-sectional shape, and the first pseudo-metal bonding structure has a triangular vertical cross-sectional shape.

44. The bonding assembly of claim 43, wherein the sidewalls of the first metal bonding structure and the first pseudo-metal bonding structure are tapered, such that the first metal bonding structure contacts a predetermined region of the first metal interconnect structure in the first metal interconnect structure, and such that the first pseudo-metal bonding structure does not extend through the entire thickness of the first bonding stage dielectric layer.

45. The bonding component according to claim 41, wherein: The first metal bonding structure includes a first metal through-hole portion; The first pseudo-metal bonding structure includes a first pseudo-metal via portion, the first pseudo-metal via portion having a smaller height than the first metal via portion; and All top peripheries of the first metal through-hole portion and all top peripheries of the first pseudo-metal through-hole portion lie in a horizontal plane.

46. ​​The bonding component of claim 45, wherein: The first metal bonding structure is composed of the first metal through-hole portion; and The first pseudo-metal bonding structure is composed of the first pseudo-metal through-hole portion.

47. The bonding assembly of claim 41, wherein the second semiconductor die comprises: A second metal interconnect structure is embedded in a second dielectric material layer; and A second bonding level dielectric layer is embedded in a second metal bonding structure. The second metal bonding structure is electrically connected to a corresponding second metal interconnect structure in the second metal interconnect structure and is bonded to the first metal bonding structure by metal-to-metal bonding. The second bonding level dielectric layer further embeds a second pseudo-metal bonding structure, which is electrically isolated from the second metal interconnect structure. The first pseudo-metal bonding structure is bonded to the second pseudo-metal bonding structure by additional metal-to-metal bonding.

48. The bonding assembly of claim 47, wherein the second bonding stage dielectric layer is bonded to the first bonding stage dielectric layer by dielectric-to-dielectric bonding.

49. The bonding assembly of claim 41, wherein the first metal bonding structure has the same composition as the first pseudo-metal bonding structure.

50. The bonding assembly of claim 49, wherein the first metal bonding structure and the first pseudo-metal bonding structure each include a corresponding metal barrier pad and a corresponding metal filler portion.

51. A method for forming a semiconductor structure, the method comprising: A first semiconductor device is formed above, on, or in the first substrate; A first metal interconnect structure is formed above the first semiconductor device and embedded in a first dielectric material layer; A first bonding level dielectric layer is formed above the first dielectric material layer; A first via cavity and a first pseudo via cavity are simultaneously formed in the first bonding stage dielectric layer, wherein the first pseudo via cavity has a smaller lateral range and a smaller depth than the first via cavity. as well as Simultaneously, a first metal bonding structure is formed in the first through-hole cavity, and a first pseudo-metal bonding structure is formed in the first pseudo-through-hole cavity to form a first semiconductor die.

52. The method of claim 51, wherein the first pseudo-metallic bonding structure has a smaller lateral extent than the first metallic bonding structure.

53. The method of claim 51, wherein the first metal bonding structure has a trapezoidal vertical cross-sectional shape, and the first pseudo-metal bonding structure has a triangular vertical cross-sectional shape.

54. The method according to claim 51, wherein: The first metal bonding structure includes a first metal through-hole portion; The first pseudo-metal bonding structure includes a first pseudo-metal via portion, the first pseudo-metal via portion having a smaller height than the first metal via portion; and All top peripheries of the first metal through-hole portion and all top peripheries of the first pseudo-metal through-hole portion lie in a horizontal plane.

55. The method according to claim 54, wherein: The first metal bonding structure is composed of the first metal through-hole portion; and The first pseudo-metal bonding structure is composed of the first pseudo-metal through-hole portion.

56. The method according to claim 51, further comprising: The second semiconductor die is bonded to the first semiconductor die.

57. The method of claim 56, wherein the second semiconductor die comprises: A second metal interconnect structure is embedded in a second dielectric material layer; and A second bonding level dielectric layer is embedded in a second metal bonding structure. The second metal bonding structure is electrically connected to a corresponding second metal interconnect structure in the second metal interconnect structure and is bonded to the first metal bonding structure via metal-to-metal bonding. The second bonding level dielectric layer further embeds a second pseudo-metal bonding structure, which is electrically isolated from the second metal interconnect structure. The first pseudo-metal bonding structure is bonded to the second pseudo-metal bonding structure via additional metal-to-metal bonding, and the second bonding level dielectric layer is bonded to the first bonding level dielectric layer via dielectric-to-dielectric bonding.

58. The method of claim 51, wherein the first metal bonding structure has the same composition as the first pseudo-metal bonding structure.

59. The method of claim 58, wherein the first metal bonding structure and the first pseudo-metal bonding structure each comprise a corresponding metal barrier pad and a corresponding metal filler portion.

60. The method of claim 51, wherein the step of simultaneously forming the first through-hole cavity and the first pseudo through-hole cavity comprises: Simultaneously etch the first via cavity and the first pseudo via cavity in the first bonding level dielectric layer, such that the sidewalls of the first via cavity and the first pseudo via cavity are tapered and a predetermined area of ​​the first metal interconnect structure is exposed in the first via cavity, and such that the first pseudo via cavity does not extend through the entire thickness of the first bonding level dielectric layer.

61. A bonding component, the bonding component comprising: First Semiconductor Die; and A second semiconductor die, the second semiconductor die being bonded to the first semiconductor die: The first semiconductor die includes: A first dielectric material layer is located on a first semiconductor device; A first metal interconnect structure is embedded in the first dielectric material layer and electrically connected to the first semiconductor device. A first bonding level dielectric layer is located on the first dielectric material layer and embeds a first conductive bonding structure. The first conductive bonding structure is electrically connected to a first metal interconnect structure in the first metal interconnect structure. The first bonding level dielectric layer further embeds a first pseudo-conductive bonding structure, which has a smaller vertical extent than the first conductive bonding structure and is electrically isolated from the first metal interconnect structure. A first type of insulating spacer is embedded in the first bonding level dielectric layer and laterally surrounds the first conductive bonding structure and is vertically spaced from the second semiconductor die and the first dielectric material layer.

62. The bonding component according to claim 61, wherein: The first type of insulating spacer is located entirely below and vertically spaced from the first horizontal plane, which includes the topmost surface of the first bonding stage dielectric layer; and The first type of insulating spacer is located entirely above and vertically spaced from the second horizontal plane, which includes the bottom surface of the first bonding level dielectric layer.

63. The bonding assembly of claim 61, further comprising a second type of insulating spacer embedded in the first bonding stage dielectric layer and laterally surrounding the first pseudo-conductive bonding structure.

64. The bonding component of claim 63, wherein: The first type of insulating spacer includes silicon carbonitride; and The second type of insulating spacer includes silicon carbonitride.

65. The bonding assembly of claim 61, wherein the first pseudo-conductive bonding structure has a smaller vertical and lateral extent than the first conductive bonding structure.

66. The bonding assembly of claim 61, wherein the first conductive bonding structure has a first vertical cross-sectional profile, the first vertical cross-sectional profile including a first profile-shaped sidewall, the first profile-shaped sidewall including a first upper sidewall segment having a first upper cone angle relative to the vertical direction, a first lower sidewall segment having a first lower cone angle relative to the vertical direction, and a first connecting surface segment having a first connecting cone angle relative to the vertical direction, the first connecting cone angle being greater than the first upper cone angle and the first lower cone angle.

67. The bonding assembly of claim 66, wherein the first pseudo-conductive bonding structure has a second vertical cross-sectional profile, the second vertical cross-sectional profile including a second profile-shaped sidewall, the second profile-shaped sidewall including a second upper sidewall segment having a second upper cone angle relative to the vertical direction, a second lower sidewall segment having a second lower cone angle relative to the vertical direction, and a second connecting surface segment having a second connecting cone angle relative to the vertical direction, the second connecting cone angle being greater than the second upper cone angle and the second lower cone angle.

68. The bonding component of claim 67, wherein: The second upper cone angle is the same as the first upper cone angle; and The second lower cone angle is the same as the first lower cone angle.

69. The bonding component of claim 66, wherein: The first upper sidewall section contacts the first bonding level dielectric layer; and The lower portion of the first lower sidewall section contacts the first bonding level dielectric layer.

70. The bonding component of claim 69, wherein: The upper portion of the first lower sidewall section contacts the first type of insulating spacer; and The first connecting surface section contacts the first type of insulating spacer.

71. The bonding assembly of claim 61, wherein the second semiconductor die comprises: A second metal interconnect structure is embedded in a second dielectric material layer; and A second bonding level dielectric layer is embedded in a second conductive bonding structure. The second conductive bonding structure is electrically connected to a corresponding second metal interconnect structure in the second metal interconnect structure and is bonded to the first conductive bonding structure by metal-to-metal bonding. The second bonding level dielectric layer is further embedded in a second pseudo conductive bonding structure, which is electrically isolated from the second metal interconnect structure.

72. The bonding assembly of claim 71, wherein the entire top surface of the first pseudo-conductive bonding structure is in contact with the surface of the second bonding stage dielectric layer.

73. The bonding assembly of claim 71, wherein the first pseudo-conductive bonding structure is bonded to the second pseudo-conductive bonding structure by an additional metal-to-metal bonding.

74. The bonding assembly of claim 71, wherein the second bonding stage dielectric layer is bonded to the first bonding stage dielectric layer by dielectric-to-dielectric bonding.

75. A method for forming a semiconductor structure, the method comprising: A first semiconductor device is formed on a first substrate; A first metal interconnect structure is formed above the first semiconductor device and embedded in a first dielectric material layer; A first bonding level dielectric layer is formed above the first dielectric material layer; A first cavity and a first pseudo-cavity are formed in the first bonding stage dielectric layer, wherein the first pseudo-cavity has a smaller lateral extent than the first cavity. An insulating spacer material layer is formed in the first cavity and the first pseudo-cavity, and above the first bonding level dielectric layer. An anisotropic etching process is performed to etch the materials of the insulating spacer material layer and the first bonding level dielectric layer to form a first type of insulating spacer in the peripheral portion of the first cavity and a second type of insulating spacer in the peripheral portion of the first pseudo-cavity, such that a first stepped via extends through the first type of insulating spacer and through the first bonding level dielectric layer to reach the top surface of a first metal interconnect structure in the first metal interconnect structure, and a second stepped via extends through the second type of insulating spacer and has a bottom surface covering the bottom surface of the first bonding level dielectric layer; as well as A first conductive bonding structure is formed in the first stepped via cavity and a first pseudo-conductive bonding structure is formed in the second stepped via cavity to form a first semiconductor die.

76. The method of claim 75, wherein the anisotropic etching process comprises a reactive ion etching (RIE) process, the RIE process generating a polymer material as an etching product, the polymer material blocking the remaining voids in the second stepped via cavity, and terminating the RIE process before the bottom surface of the second stepped via cavity reaches the bottom surface of the first bonding level dielectric layer, wherein the polymer material does not block the entire remaining voids in the first stepped via cavity, and the RIE process continues until the bottom surface of the first stepped via cavity reaches the bottom surface of the first bonding level dielectric layer, and the top surface of a corresponding first metal interconnect structure in the first metal interconnect structure is exposed to the bottom of the corresponding first stepped via cavity.

77. The method of claim 75, wherein the first stepped through-hole cavity has a first vertical cross-sectional profile, the first vertical cross-sectional profile including a first profile-shaped sidewall, the first profile-shaped sidewall including a first upper sidewall section having a first upper cone angle relative to the vertical direction, a first lower sidewall section having a first lower cone angle relative to the vertical direction, and a first connecting surface section having a first connecting cone angle relative to the vertical direction, the first connecting cone angle being greater than the first upper cone angle and the first lower cone angle.

78. The method according to claim 77, wherein: The first upper sidewall section includes the first surface section of the first bonding level dielectric layer; and The lower portion of the first lower sidewall section includes the second surface section of the first bonding level dielectric layer.

79. The method according to claim 78, wherein: The upper portion of the first lower sidewall section includes the lower portion of the inner sidewall of the first type of insulating spacer; and The first connecting surface section includes the upper portion of the inner sidewall of the first type of insulating spacer.

80. The method of claim 75, further comprising: A second semiconductor die is provided, the second semiconductor die including a second bonding level dielectric layer with embedded second conductive bonding structure and second pseudo-conductive bonding structure; as well as The second semiconductor die is bonded to the first semiconductor die, such that the second conductive bonding structure is bonded to the first conductive bonding structure by metal-to-metal bonding.

Images