A graded deposition LPCVD process for N-type battery passivation layers

Abstract

This invention relates to the field of N-type crystalline silicon solar cell manufacturing technology, specifically to a graded deposition LPCVD process for N-type cell passivation layers. The main steps include depositing a silicon-oxygen tunneling layer of 1.5–2.5 nm and graded deposition of the film layers. The graded deposition steps include: a first-stage deposition to obtain a polycrystalline silicon film of 90–150 nm with a crystallinity of 80–95%; a second-stage deposition to obtain a polycrystalline silicon film of 50–100 nm with a crystallinity of 60–80%; and a third-stage deposition to obtain a polycrystalline silicon film of 30–80 nm with a crystallinity ≤50%. This invention achieves polycrystalline silicon films with crystallization gradient characteristics by changing process parameters, such as pressure, temperature, and gas flow rate ratio, within the same deposition process. The crystallinity of polycrystalline silicon significantly affects the diffusion behavior of impurity atoms subsequently doped using methods such as boron diffusion and phosphorus diffusion. This technology can optimize film performance, meet specific process application requirements, and further improve cell performance.

Description

Technical Field

[0001] This invention relates to the field of N-type crystalline silicon solar cell manufacturing technology, specifically to a graded deposition LPCVD process for N-type cell passivation layers. Background Technology

[0002] In N-type battery manufacturing processes, such as TOPCon and BC batteries, LPCVD is commonly used to prepare the tunneling oxide layer and polycrystalline silicon layer. The tunneling oxide layer and polycrystalline silicon layer together form the back passivation structure of the battery, which enhances the passivation effect, reduces the back recombination rate, and improves the carrier transport efficiency, thereby improving the battery conversion efficiency.

[0003] The current mainstream LPCVD process parameters are designed to first prepare a tunneling oxide layer under atmospheric pressure, and then deposit a polycrystalline silicon thin film under fixed process parameters. The polycrystalline silicon thin film formed under this process has a relatively simple structure, either amorphous silicon or polycrystalline silicon, and the film quality is poor, affecting the cell conversion efficiency. The impact of LPCVD process pressure on the quality of polycrystalline silicon thin films is mainly reflected in the deposition rate, surface roughness, uniformity, microstructure, and passivation performance. Optimization of film quality requires precise control of pressure parameters. For example, adjusting the pressure parameters can precisely control the surface morphology of the polycrystalline silicon thin film, helping to reduce surface defects and improve the flatness of the polycrystalline silicon thin film. Adjusting the pressure range can also control the degree of crystallinity and grain size of the polycrystalline silicon thin film, thereby improving the passivation performance of the polycrystalline silicon.

[0004] The current mainstream efficiency of the latest BC battery technology is 27.3%, which is still far from its theoretical limit of 29.3%. As the main production process of BC batteries, LPCVD process will dop the deposited polycrystalline silicon film with impurity atoms through diffusion (boron diffusion, phosphorus diffusion) after the LPCVD process is completed, forming P-type semiconductor (boron diffusion) and N-type semiconductor (phosphorus diffusion). Therefore, further optimization is needed to improve the quality of polycrystalline silicon film formation and improve the process effect. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a graded deposition LPCVD process for N-type battery passivation layers to improve the conversion efficiency of N-type batteries.

[0006] This invention is achieved through the following technical solution:

[0007] A hierarchical deposition LPCVD process for an N-type battery passivation layer specifically includes the following steps:

[0008] S1 Preparation: Place the silicon wafer to be processed into a sealed quartz furnace tube and check the pressure and temperature to ensure that the LPCVD equipment reaches the required state for the process.

[0009] S2 deposition of silicon-oxygen tunneling layer: Under normal pressure, the temperature is controlled at 550-650℃, 20000-40000 sccm of 9N pure oxygen is introduced, and the reaction time is 20-50 min to prepare a silicon-oxygen tunneling layer with a thickness of 1.5-2.5 nm.

[0010] S3 primary deposition: pressure 50-150 mTorr, temperature controlled at 610-650℃, 1000-2000 sccm of 5N pure SiH4 introduced, reaction time 20-30 min, deposited polycrystalline silicon thin film thickness 90-150 nm, crystallization rate 80-95%.

[0011] S4 secondary deposition: pressure 150-300 mTorr, temperature controlled at 580-630℃, 1000-2000 sccm of 5N pure SiH4 is introduced, reaction time 5-15 min, deposited polycrystalline silicon thin film thickness 50-100 nm, crystallinity 60-80%.

[0012] S5 three-stage deposition: pressure 300-500 mTorr, temperature controlled at 530-580℃, 1000-2000 sccm of 5N pure SiH4 introduced, reaction time 4-10 min, deposited polycrystalline silicon thin film thickness 30-50 nm, crystallinity ≤50%.

[0013] After each step S2, S3, S4, and S5 is completed, there are corresponding auxiliary steps such as vacuuming, leak detection, and purging to ensure the independence and integrity of each process step.

[0014] S6 Vacuum Break: Set the furnace tube pressure to atmospheric pressure, introduce 20,000 sccm of nitrogen into the furnace tube to quickly restore it to atmospheric pressure, and end the process.

[0015] S7 Unloading: Open the furnace door and unload the silicon wafers that have completed the process. The wafers are then transported out of the furnace tube and placed on the buffer rack for cooling, thus completing the entire process.

[0016] This process is applied in the preparation of N-type batteries, especially BC batteries, to optimize film performance and improve battery performance.

[0017] The beneficial effects of this invention are:

[0018] 1. This invention designs a graded deposition process for polycrystalline silicon within the same LPCVD process cycle. By changing process parameters such as pressure, temperature, and gas flow rate ratio, a polycrystalline silicon film with a crystallization gradient can be obtained. Furthermore, the crystallinity of the polycrystalline silicon significantly affects the diffusion behavior of impurity atoms subsequently doped using methods such as boron diffusion and phosphorus diffusion. When the process of this invention is matched with subsequent doping processes, the conversion efficiency of N-type solar cells can be improved by 0.05% to 0.1%.

[0019] 2. Taking N-type polycrystalline silicon as an example, this invention mainly focuses on pressure grading design, optimizing film performance, and precisely controlling the uniformity, concentration, and depth of phosphorus doping atoms diffusion in polycrystalline silicon, thereby improving the back passivation contact performance and enhancing battery quality.

[0020] 3. The primary deposition process of this invention reduces gas-phase collisions, allowing the precursor SiH4 to directly reach the silicon-based surface. Furthermore, the low pressure extends the mean free path of silicon atoms, promoting surface migration, facilitating lattice alignment, reducing nucleation density, and promoting grain growth. Under low pressure, the gas-phase reaction is controlled by the surface reaction, resulting in higher mobility of adsorbed atoms, which is beneficial for improving crystallinity, achieving a crystallinity of 80-95%. The high internal crystallinity can promote the uniform distribution of phosphorus impurities in the phosphorus diffusion process during BC battery fabrication.

[0021] 4. In the two-stage deposition process of this invention, the gas phase reaction (thermal decomposition of silane) and the surface reaction (adsorption and growth of silicon atoms on the silicon wafer surface) compete to form a mixed control mechanism, resulting in a wider grain size distribution and a crystallization rate of 60-80%, which can improve the uniformity of the film and sacrifice some crystallization rate in exchange for better step coverage. This step can appropriately increase the deposition rate and balance the overall process time so as not to be too long.

[0022] 5. The three-stage deposition process of this invention promotes gas-phase nucleation, with gas-phase reactions dominating, leading to the formation of small grains or amorphous phases and the formation of more amorphous silicon with a crystallinity of less than 50%. At this point, the film deposition rate is too fast, limiting surface migration and increasing the nucleation density, resulting in a small grain structure. This layer can suppress the diffusion depth of phosphorus atoms and increase their doping concentration on the surface, achieving better passivation contact. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the step-by-step deposition process of the present invention;

[0024] Figure 2 This is a schematic diagram of the key steps in the deposition process of an existing production line. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] For those skilled in the art, the deposition step time, flow rate, pressure and other parameters in this invention can be adjusted according to the specific circumstances, and the process structure can be broken down. At the same time, the adjustment of the process time, process temperature and process structure in this process are all within the scope of protection of this invention.

[0027] Explanation of crystallinity: Crystallinity is the proportion of crystalline components in a material, describing the relative ratio of ordered crystalline to disordered amorphous regions within the material, usually expressed as a percentage. In this invention, the crystallinity of the polycrystalline silicon layer refers to the proportion of amorphous silicon transformed into polycrystalline silicon (p-Si) during heat treatment or other crystallization processes. The crystallinity of polycrystalline silicon is typically measured using X-ray diffraction and Raman spectroscopy. In the following examples, the crystallinity refers to the proportion of crystalline components in the polycrystalline silicon layer.

[0028] This invention provides a graded deposition LPCVD process for N-type battery passivation layers, specifically including the following steps:

[0029] S1 Preparation: Place the silicon wafer to be processed into a sealed quartz furnace tube, evacuate the vacuum, and heat up to facilitate control of the equipment to achieve the required process conditions.

[0030] S2 deposition of silicon-oxygen tunneling layer: Under normal pressure, the temperature is controlled at 550-650℃, 20000-40000 sccm of 9N pure oxygen is introduced, and the reaction time is 20-50 min to prepare a silicon-oxygen tunneling layer with a thickness of 1.5-2.5 nm.

[0031] This step corresponds to Figure 1 The deposition of an ultrathin silicon-oxygen tunneling layer is mainly used to passivate interface defects and enhance the unidirectional selectivity of charge carriers.

[0032] S3 primary deposition: pressure 50-150 mTorr, temperature controlled at 610-650℃, 1000-2000 sccm of 5N pure SiH4 introduced, reaction time 20-30 min, deposited polycrystalline silicon thin film thickness 90-150 nm.

[0033] This step corresponds to Figure 1 Low-pressure deposition in silicon-based solar cells reduces gas-phase collisions, allowing the precursor SiH4 to directly reach the silicon surface. Furthermore, the low pressure extends the mean free path of silicon atoms, promoting surface migration, facilitating lattice alignment, reducing nucleation density, and promoting grain growth. Under low pressure, gas-phase reactions are controlled by surface reactions, resulting in higher mobility of adsorbed atoms, which is beneficial for improving crystallinity, achieving 80–95%. This high internal crystallinity promotes the uniform distribution of phosphorus impurities in the phosphorus diffusion process during BC battery fabrication.

[0034] S4 secondary deposition: pressure 150-300 mTorr, temperature controlled at 580-630℃, 1000-2000 sccm of 5N pure SiH4 is introduced, reaction time 5-15 min, and a polycrystalline silicon thin film thickness of 50-100 nm is deposited.

[0035] This step corresponds to Figure 1In medium-pressure deposition, the gas-phase reaction (thermal decomposition of silane) competes with the surface reaction (adsorption and growth of silicon atoms on the silicon wafer surface), forming a mixed control mechanism. This results in a wider grain size distribution and a crystallinity typically between 60% and 80%, which improves film uniformity by sacrificing some crystallinity for better step coverage. This step allows for a suitable increase in the deposition rate, balancing and controlling the overall process time to prevent it from becoming excessively long.

[0036] S5 three-stage deposition: pressure 300-500 mTorr, temperature controlled at 530-580℃, 1000-2000 sccm of 5N pure SiH4 is introduced, reaction time 4-10 min, and a polycrystalline silicon thin film thickness of 30-50 nm is deposited.

[0037] This step corresponds to Figure 1 High-pressure deposition promotes gas-phase nucleation, with gas-phase reactions dominating, leading to the formation of small grains or amorphous phases and the formation of more amorphous silicon with a crystallinity below 50%. At this point, the film deposition rate is too fast, limiting surface migration and increasing nucleation density, resulting in a small grain structure. This layer can suppress the diffusion depth of phosphorus atoms and increase their doping concentration on the surface, achieving better passivation contacts.

[0038] After each step S2, S3, S4, and S5 is completed, there are corresponding auxiliary steps such as vacuuming, leak detection, and purging to ensure the independence and integrity of each process step and better reflect the process effect.

[0039] S6 Vacuum Break: Set the furnace tube pressure to atmospheric pressure, introduce 20,000 sccm of nitrogen into the furnace tube to quickly restore it to atmospheric pressure, and end the process.

[0040] S7 Unloading: The furnace door is opened and the silicon wafers that have completed the process are unloaded from the furnace tube by a paddle and placed on a buffer rack for cooling. The entire process is now complete.

[0041] Example 1

[0042] A graded deposition LPCVD process for N-type battery passivation layers, using existing Laplace LPCVD equipment, with 2640 wafers per tube, and specific process parameters are as follows:

[0043] S1 Preparation: Place the silicon wafer to be processed into a sealed quartz furnace tube, evacuate the vacuum, and heat it to reach the required state for the process.

[0044] S2 deposition of silicon-oxygen tunneling layer: Under normal pressure and temperature of 620℃, 30000 sccm of 9N pure oxygen is introduced and the reaction time is 30 min to prepare a silicon-oxygen tunneling layer with a thickness of 1.7 nm.

[0045] S3 primary deposition: pressure 80 mTorr, temperature 630℃, 1500 sccm of silane introduced, reaction time 25 min, depositing a polycrystalline silicon layer with a thickness of 120 nm and a crystallinity of 95%.

[0046] S4 secondary deposition: pressure 200 mTorr, temperature 600℃, silane 1500 sccm introduced, reaction time 10 min, depositing a polycrystalline silicon layer with a thickness of 60 nm and a crystallinity of 80%.

[0047] S5 three-stage deposition: pressure 400 mTorr, temperature 550℃, 1500 sccm of silane introduced, reaction time 7 min, deposition of a 40 nm thick amorphous silicon-based thin film.

[0048] After steps S2, S3, S4, and S5 are completed, the corresponding auxiliary steps are vacuuming, leak detection, and purging.

[0049] S6 Vacuum Break: Set the furnace tube pressure to atmospheric pressure and introduce 20,000 sccm of nitrogen into the furnace tube to quickly restore it to atmospheric pressure.

[0050] S7 Unloading: The furnace door is opened and the silicon wafers that have completed the process are unloaded from the furnace tube by the paddle and placed on the buffer rack for cooling. The entire process is now complete.

[0051] Example 2

[0052] A hierarchical deposition LPCVD process for N-type battery passivation layers differs from Example 1 in that:

[0053] S3 primary deposition: pressure 150 mTorr, temperature 630℃, 1500 sccm of silane introduced, reaction time 20 min, depositing a polycrystalline silicon layer with a thickness of 120 nm and a crystallinity of 95%.

[0054] S4 secondary deposition: pressure 300 mTorr, temperature 600℃, 1500 sccm of silane introduced, reaction time 5 min, depositing a polycrystalline silicon layer with a thickness of 60 nm and a crystallinity of 80%.

[0055] S5 three-stage deposition: pressure 500 mTorr, temperature 550℃, 1500 sccm of silane introduced, reaction time 4 min, deposition of a 40 nm thick amorphous silicon-based thin film.

[0056] Example 3

[0057] A hierarchical deposition LPCVD process for N-type battery passivation layers differs from Example 1 in that:

[0058] S3 primary deposition: pressure 50 mTorr, temperature 630℃, 1500 sccm of silane introduced, reaction time 30 min, depositing a polycrystalline silicon layer with a thickness of 120 nm and a crystallinity of 95%.

[0059] S4 secondary deposition: pressure 150 mTorr, temperature 600℃, 1500 sccm of silane introduced, reaction time 15 min, depositing a polycrystalline silicon layer with a thickness of 60 nm and a crystallinity of 80%.

[0060] S5 three-stage deposition: pressure 300 mTorr, temperature 550℃, 1500 sccm of silane introduced, reaction time 10 min, deposition of a 50 nm thick amorphous silicon-based thin film.

[0061] Example 4

[0062] A hierarchical deposition LPCVD process for N-type battery passivation layers differs from Example 1 in that:

[0063] S3 primary deposition: pressure 80 mTorr, temperature 650℃, silane 1500 sccm introduced, reaction time 24 min, depositing a polycrystalline silicon layer with a thickness of 120 nm and a crystallinity of 95%.

[0064] S4 secondary deposition: pressure 200 mTorr, temperature 630℃, 1500 sccm of silane introduced, reaction time 6 min, depositing a polycrystalline silicon layer with a thickness of 60 nm and a crystallinity of 80%.

[0065] S5 three-stage deposition: pressure 400 mTorr, temperature 580℃, 1500 sccm of silane introduced, reaction time 5 min, deposition of a 40 nm thick amorphous silicon-based thin film.

[0066] Example 5

[0067] A hierarchical deposition LPCVD process for N-type battery passivation layers differs from Example 1 in that:

[0068] S3 primary deposition: pressure 80 mTorr, temperature 610℃, silane 1500 sccm introduced, reaction time 28 min, depositing a polycrystalline silicon layer with a thickness of 120 nm and a crystallinity of 95%.

[0069] S4 secondary deposition: pressure 200 mTorr, temperature 580℃, 1500 sccm of silane introduced, reaction time 15 min, depositing a polycrystalline silicon layer with a thickness of 60 nm and a crystallinity of 80%.

[0070] S5 three-stage deposition: pressure 400 mTorr, temperature 530℃, 1500 sccm of silane introduced, reaction time 10 min, deposition of a 40 nm thick amorphous silicon-based thin film.

[0071] Example 6

[0072] A hierarchical deposition LPCVD process for N-type battery passivation layers differs from Example 1 in that:

[0073] S2 deposition of silicon-oxygen tunneling layer: Under normal pressure and temperature of 580℃, 30000 sccm of 9N pure oxygen is introduced and the reaction time is 50 min to prepare a silicon-oxygen tunneling layer with a thickness of 2.5 nm.

[0074] S3 primary deposition: pressure 80 mTorr, temperature 650℃, silane 1500 sccm introduced, reaction time 26 min, depositing a polycrystalline silicon layer with a thickness of 150 nm and a crystallinity of 95%.

[0075] S4 secondary deposition: pressure 200 mTorr, temperature 630℃, 1500 sccm of silane introduced, reaction time 6 min, depositing a polycrystalline silicon layer with a thickness of 50 nm and a crystallinity of 80%.

[0076] S5 three-stage deposition: pressure 400 mTorr, temperature 580℃, 1500 sccm of silane introduced, reaction time 6 min, deposition of a 30 nm thick amorphous silicon-based thin film.

[0077] Example 7

[0078] A hierarchical deposition LPCVD process for N-type battery passivation layers differs from Example 1 in that:

[0079] S2 deposition of silicon-oxygen tunneling layer: Under normal pressure and temperature of 550℃, 30000 sccm of 9N pure oxygen is introduced and the reaction time is 25 min to prepare a silicon-oxygen tunneling layer with a thickness of 1.5 nm.

[0080] S3 primary deposition: pressure 80 mTorr, temperature 610℃, 1500 sccm of silane introduced, reaction time 25 min, depositing a polycrystalline silicon layer with a thickness of 90 nm and a crystallinity of 95%.

[0081] S4 secondary deposition: pressure 200 mTorr, temperature 580℃, 1500 sccm of silane introduced, reaction time 15 min, depositing a polycrystalline silicon layer with a thickness of 100 nm and a crystallinity of 80%.

[0082] S5 three-stage deposition: pressure 400 mTorr, temperature 530℃, 1500 sccm of silane introduced, reaction time 10 min, deposition of a 30 nm thick amorphous silicon-based thin film.

[0083] Comparative Example 1

[0084] like Figure 2 As shown, process experiments were conducted using existing Laplace LPCVD equipment, with 2640 wafers per tube. The specific process parameters are as follows:

[0085] S1 places the silicon wafer to be processed into a sealed quartz furnace tube, evacuates the vacuum, and heats it to reach the required state for the process.

[0086] S2 deposition of silicon-oxygen tunneling layer: process temperature 580℃, pressure atmospheric pressure, 30000 sccm of pure 9N oxygen is introduced to prepare a silicon-oxygen tunneling layer with a thickness of 1.5nm.

[0087] S3 polycrystalline silicon thin film: deposition pressure 100mTorr, temperature 600℃, deposition thickness 210nm.

[0088] After steps S2 and S3 are completed, the corresponding auxiliary steps are vacuuming, leak detection, and purging to ensure the independence and integrity of each process step, resulting in differences in the microstructure of polycrystalline silicon and better reflecting the process effect.

[0089] S4 Vacuum Break: The furnace tube pressure is set to atmospheric pressure, and a large amount of nitrogen is introduced into the furnace tube to quickly restore the furnace tube to atmospheric pressure.

[0090] S5 Open the furnace door and unload the boat: The silicon wafers that have completed the process are transported out of the furnace tube by the paddle and placed on the buffer rack for cooling, thus ending the entire process.

[0091] Comparative Example 2

[0092] like Figure 2 As shown, process experiments were conducted using existing Laplace LPCVD equipment, with 2640 wafers per tube. Specific conditions and parameters are as follows:

[0093] S1 places the silicon wafer to be processed into a sealed quartz furnace tube, evacuates the vacuum, and heats it to reach the required state for the process.

[0094] S2 deposition of silicon-oxygen tunneling layer: process temperature 580℃, pressure atmospheric pressure, 30000 sccm of pure 9N oxygen is introduced to prepare a silicon-oxygen tunneling layer with a thickness of 1.5nm.

[0095] S3 polycrystalline silicon thin film: deposition pressure 150mTorr, temperature 620℃, deposition thickness 220nm.

[0096] After steps S2 and S3 are completed, the corresponding auxiliary steps are vacuuming, leak detection, and purging to ensure the independence and integrity of each process step, resulting in differences in the microstructure of polycrystalline silicon and better reflecting the process effect.

[0097] S4 Vacuum Break: The furnace tube pressure is set to atmospheric pressure, and a large amount of nitrogen is introduced into the furnace tube to quickly restore the furnace tube to atmospheric pressure.

[0098] S5 Open the furnace door and unload the boat: The silicon wafers that have completed the process are transported out of the furnace tube by the paddle and placed on the buffer rack for cooling, thus ending the entire process.

[0099] The above Examples 1-7 and Comparative Examples 1 and 2 were used to conduct verification experiments on battery conversion efficiency and electrical performance. The experimental design is as follows:

[0100] The entire battery manufacturing process follows the BC battery preparation method: First, a 140μm thick silicon wafer with a resistivity of 6-18Ω·cm is polished using an alkaline solution to remove line marks and impurities, forming a smooth surface with a reflectivity of over 40%. Then, cross-distributed P-type regions (LPCVD + boron diffusion doping) and N-type regions (LPCVD + phosphorus diffusion doping) are prepared on the back of the silicon wafer. A single P-type region is 400-500μm wide, and a single N-type region is 300-400μm wide, with a 100-200μm physical isolation area between the two regions. Next, the silicon wafer undergoes double-sided alumina passivation and silicon nitride passivation. Finally, positive and negative grid lines are printed on the back to form electrodes.

[0101] During normal production on the production line, 24,000 wafers are randomly selected before and after the LPCVD process and precisely divided into 9 groups using the AB slicing method for later use.

[0102] In the LPCVD process, the experimental groups were named Examples 1-7; the other two control groups were Comparative Examples 1-2, named Comparative Example 1 and Comparative Example 2. All nine experimental groups were completed using the same machine, and subsequent processes were also completed using the same equipment to prepare finished batteries. These batteries were then tested using a Senbain IV testing machine according to international standards IEC 61215 and IEC 61730. Detailed results from the nine experimental groups are summarized below:

[0103] Table 1 shows a comparison of the battery conversion efficiency and electrical performance of each process group:

[0104] Example 1 2451 27.659％ 0.7475 8.3375 84.87 0.00305 549 94.22％ Example 2 2501 27.648％ 0.747 8.3331 84.93 0.0028 517 94.96％ Example 3 2538 27.634％ 0.7482 8.3318 84.75 0.0029 554 93.75％ Example 4 2432 27.65％ 0.7477 8.3382 84.79 0.00307 548 93.29％ Example 5 2411 27.62％ 0.7466 8.3338 84.87 0.00302 552 94.64％ Example 6 2467 27.618％ 0.746 8.3362 84.97 0.0031 553 93.18％ Example 7 2513 27.601％ 0.745 8.3376 84.95 0.00313 557 93.93％ Comparative Example 1 2348 27.58％ 0.7467 8.3252 84.86 0.0027 551 93.92％ Comparative Example 2 2491 27.55％ 0.7465 8.3259 84.79 0.0028 559 93.68％

[0105] Based on the average electrical performance data from the nine experimental groups in Table 1, it can be seen that the embodiments of the present invention have an advantage of 0.05% to 0.1% in battery conversion efficiency, mainly reflected in the gains in open-circuit voltage Voc and current Isc. This indicates that the graded deposition process in LPCVD, with low, medium, and high pressures in the LPCVD process, improves the film structure, crystallinity, passivation performance, and subsequent uniformity of impurity atom diffusion, enhances passivation contact, and increases carrier collection efficiency, thus contributing to improved battery conversion efficiency.

[0106] Photoluminescence (PL) testing systems are commonly used to inspect the quality of various processes in the manufacturing of solar cells. The system utilizes a laser as the excitation source, providing photons with a certain energy. Electrons in the ground state of the semiconductor material (silicon-based) absorb these photons and enter an excited state. These excited electrons are unstable and quickly return to the ground state, emitting fluorescence with an infrared peak. The high-voltage lens of the instrument captures this fluorescence, creating the PL image. The intensity of the fluorescence is proportional to the density of non-equilibrium minority carriers at that location. Defect locations become recombination centers for minority carriers; the more defects there are, the lower the minority carrier density in that region, resulting in a weaker fluorescence effect. This appears as dark dots, lines, or areas on the image. Conversely, areas with fewer defects and less minority carrier recombination appear as brighter areas. Therefore, PL testing can determine whether defects exist in the solar cell or at a particular stage of its manufacturing process, indirectly characterizing the photoelectric conversion efficiency of the battery.

[0107] ECV (Effective Chemical Vapor Detection) is primarily used to test the diffusion impurity distribution on silicon wafers, specifically the surface doping concentration and diffusion depth of impurity atoms. The combined performance of these two factors determines the sheet resistance after impurity atom diffusion. Surface concentration and diffusion depth both affect cell conversion efficiency. Therefore, ECV testing of surface concentration and diffusion depth is used to evaluate process effectiveness and assess cell conversion efficiency.

[0108] PL testing employed the LIS-R3 PL imaging inspection system (photoluminescence imaging inspection system) from BTImaging, Australia, to test the PL of batteries for each process group. ECV testing used the ECV (model CVP21) from WEP, Germany.

[0109] The PL results and ECV test data are shown in Table 2:

[0110]

[0111] The test results in Table 2 show that the embodiments of the present invention have a certain effect on improving battery quality. The PL brightness of the embodiments is greater than that of the comparative examples. Specifically, the PL brightness of Examples 1 and 2 is above 17000, which is about 1000 higher than that of the comparative examples. This indicates that these two embodiments can achieve better passivation effects, reduce battery defects, reduce carrier recombination centers, and improve carrier lifetime and diffusion length, thereby improving the overall quality of the battery and resulting in higher conversion efficiency. Furthermore, the data on phosphorus atom diffusion depth and surface doping concentration of the embodiments show that the surface doping concentration of the embodiments, especially Example 1, is the highest, indicating improved contact and a suitable diffusion depth, which promotes carrier tunneling. Both of these factors contribute to improving battery conversion efficiency.

[0112] LPCVD graded deposition pressure can utilize polycrystalline silicon with different structures. By taking advantage of the different crystal states of polycrystalline silicon to affect diffusion depth and uniformity, graded deposition processes can be designed and optimized to more precisely control the surface concentration and diffusion depth of the required impurities, thereby improving the passivation quality of the battery, improving contact performance, and increasing the battery conversion efficiency.

[0113] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A graded deposition LPCVD process for an N-type battery passivation layer, characterized in that, The main process steps include depositing a silicon-oxygen tunneling layer and a graded deposition film layer. The graded deposition film layer steps include primary deposition, secondary deposition, and tertiary deposition in sequence to obtain a polycrystalline silicon thin film. The specific process parameters for the first-stage deposition are: pressure 50~150 mTorr, temperature controlled at 610~650℃, 1000~2000 sccm of 5N pure SiH4 introduced, and reaction time 20~30 min. The specific process parameters for the secondary deposition are: pressure 150~300 mTorr, temperature controlled at 580~630℃, 1000~2000 sccm of 5N pure SiH4 introduced, and reaction time 5~15 min. The specific process parameters for the three-stage deposition are: pressure 300~500 mTorr, temperature controlled at 530~580℃, 1000~2000 sccm of 5N pure SiH4 introduced, and reaction time 4~10 min. The specific parameters of the polycrystalline silicon thin film are as follows: The thickness of the primary deposited polycrystalline silicon thin film is 90~150nm, and the crystallinity is 80~95%. The thickness of the secondary deposited polycrystalline silicon thin film is 50~100nm, and the crystallinity is 60~80%. The thickness of the tertiary deposited polycrystalline silicon thin film is 30~50nm, and the crystallinity is ≤50%.

2. The hierarchical deposition LPCVD process for an N-type battery passivation layer according to claim 1, characterized in that, The thickness of the deposited silicon-oxygen tunneling layer is 1.5~2.5 nm.

3. The hierarchical deposition LPCVD process for an N-type battery passivation layer according to claim 2, characterized in that, The specific process parameters for depositing the silicon-oxygen tunneling layer are as follows: under normal pressure, the temperature is controlled at 550~650℃, oxygen with a purity of 9N is introduced at 20000~40000 sccm, and the reaction time is 20~50 min.

4. The hierarchical deposition LPCVD process for an N-type battery passivation layer according to claim 3, characterized in that, After each step is completed, there are corresponding auxiliary steps such as vacuuming, leak detection, and purging.

5. The hierarchical deposition LPCVD process for an N-type battery passivation layer according to claim 3, characterized in that, It is used in the preparation of BC batteries.

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