Chip aging automatic test method, system and medium

Abstract

This application provides an automated chip aging test method, system, and medium, relating to the field of semiconductor technology. The method includes: identifying the type identifier of the chip under test (DUT), calling its corresponding aging test parameter set, performing aging tests on the DUT using the aging test parameter set, collecting key electrical parameters of the DUT during the aging test process, comparing them, obtaining comparison results, and automatically recording anomalies and terminating the current aging test stage of the DUT when the comparison results exceed a preset threshold range. By automatically recording anomaly information and terminating the aging process, a fully automated closed-loop processing from data acquisition and analysis to decision-making and control is achieved. This not only improves testing efficiency but also effectively protects testing equipment and samples, reduces resource waste and the risk of misjudgment, and overcomes the problems of low accuracy and slow response speed in aging trend identification.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an automatic chip aging test method, system and medium. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, chips are increasingly widely used in consumer electronics, communication equipment, automotive electronics, and industrial control. During long-term use, chips are affected by various factors such as temperature stress, electrical stress, and environmental humidity, which can lead to performance degradation or even failure. To ensure product reliability and lifespan, aging tests are typically introduced into chip production and quality control processes to simulate long-term operating conditions and expose potential failure risks in advance.

[0003] Among related technical methods, one approach involves continuously pressurizing, heating, or applying electrical signals to batches of chips under constant temperature, constant pressure, or programmable stress conditions. Electrical parameters (such as operating voltage, current, and output signal amplitude) are periodically sampled, and then statistical analysis is used to determine whether the chips meet aging performance requirements. This method can efficiently complete the aging verification of batches of chips and, by setting detection thresholds, filter out products that fail to meet performance standards, thereby improving product reliability before shipment.

[0004] Regarding the above technical solutions, although the chip aging status can be basically judged by using fixed sampling intervals and conventional statistical analysis methods, problems such as inaccurate identification of aging trends and delayed detection of performance drift are prone to occur when the chip performance changes slowly or the change pattern is complex. This results in potential defective chips not being screened out in time during testing. Summary of the Invention

[0005] To overcome the problems of low accuracy and slow response speed in aging trend identification, this application provides an automatic chip aging test method, system and medium.

[0006] On one hand, the present invention provides an automatic chip aging test method, comprising: identifying the type identifier of the chip under test, and calling the corresponding aging test parameter group from a preset parameter library based on the type identifier; performing aging test on the chip under test using the aging test parameter group, and collecting key electrical parameters of the chip under test in real time during the aging test process; analyzing the aging trend based on the key electrical parameters, calculating the performance drift value based on the aging trend, comparing the performance drift value with a corresponding threshold range to obtain a comparison result; when the comparison result exceeds the preset threshold range, automatically performing an anomaly recording operation and terminating the current aging test stage of the chip under test.

[0007] Optionally, the step of identifying the type identifier of the chip under test and calling the corresponding aging test parameter group from a preset parameter library based on the type identifier includes: electrically connecting the test device to the pins of the chip under test through the pin contact module, applying a preset identification voltage and identification current to the chip under test to measure the response characteristic parameters of the chip under test under the action of the identification voltage and identification current; matching and comparing the response characteristic parameters with standard response characteristic parameters pre-stored in the parameter library, and determining the type identifier of the chip under test when the matching similarity reaches a preset threshold; and calling the corresponding aging test parameter group from the preset parameter library according to the type identifier, wherein the aging test parameter group includes aging voltage value, aging current value, aging temperature value, and sampling interval time.

[0008] Optionally, the step of electrically connecting the pins of the chip under test (DUT) via the pin contact module of the test equipment and applying a preset identification voltage and identification current to the DUT to measure the response characteristic parameters of the DUT under the identification voltage and identification current includes: placing the DUT on the chip carrier stage of the test fixture, ensuring that the pins of the DUT are aligned with the contact pads on the test fixture using positioning pins and a clamping mechanism; activating an electric drive mechanism to control the elastic probe array in the pin contact module to establish an electrical connection with the pins of the DUT; measuring the contact resistance value of each connection point between the elastic probe array and the DUT, and determining the contact resistance value when the contact resistance value is lower than a preset threshold. Upon confirming successful electrical connection, a preset identification voltage and identification current are sequentially applied to the power supply pins of the chip under test (DUT). Simultaneously, the voltage values ​​of each output pin of the DUT are measured using a voltmeter; the current flowing through each pin of the DUT is measured using an ammeter; the impedance characteristics between the input and output terminals of the DUT are measured using an impedance analyzer; the frequency response characteristics of the DUT under AC excitation are measured using a spectrum analyzer; and the total power consumption of the chip under the identification voltage and identification current is measured using a power meter. The voltage values, current values, impedance characteristics, frequency response characteristics, and total power consumption are then used as response characteristic parameters.

[0009] Optionally, the step of performing an aging test on the chip under test using the aging test parameter set and acquiring key electrical parameters of the chip under test in real time during the aging test includes: applying the aging voltage value from the aging test parameter set to the power supply pin of the chip under test; applying the aging current value from the aging test parameter set to the chip under test; adjusting the test environment temperature to the aging temperature value from the aging test parameter set and keeping it constant; setting the trigger period of a preset timer as the sampling period according to the sampling interval time in the aging test parameter set; when the preset timer reaches the preset trigger time, the test system sequentially switches to each test stage of the chip under test through a multiplexer matrix and applies a preset test signal to the chip under test in each test stage; measuring the electrical response of the chip under test under the excitation of the test signal in real time and calculating the key electrical parameters.

[0010] Optionally, the step of analyzing the aging trend based on the key electrical parameters, calculating the performance drift value based on the aging trend, and comparing the performance drift value with the corresponding threshold range to obtain a comparison result includes: performing time-series analysis on the key electrical parameters to calculate the rate of change of key parameters between two adjacent sampling time points, fitting an aging trend curve based on the rate of change of key parameters within multiple consecutive sampling periods; performing numerical analysis on the aging trend curve to obtain the performance drift value, and numerically comparing the performance drift value with the threshold range of the corresponding chip type stored in the parameter library to obtain a comparison result.

[0011] Optionally, the step of performing time-series analysis on the key electrical parameters to calculate the rate of change of key parameters between two adjacent sampling time points, and fitting an aging trend curve based on the rate of change of key parameters within multiple consecutive sampling periods, includes: extracting the key electrical parameters of the chip under test at multiple consecutive sampling time points, forming a time-series array of the key electrical parameters according to the timestamp order, calculating the absolute change of each key electrical parameter between two adjacent sampling time points, and calculating the parameter change rate based on the absolute change; obtaining the parameter change rate of the same key electrical parameter within N consecutive sampling periods to form a change rate sequence, filtering the change rate sequence according to a moving average filter to obtain a filtered change rate sequence; and performing curve fitting on the change rate sequence using the least squares method to obtain an aging trend curve.

[0012] Optionally, the step of triggering an anomaly recording operation and terminating the current aging test stage of the chip under test when the comparison result exceeds a preset threshold range includes: recording the current timestamp, chip identifier, anomaly parameter type, anomaly parameter value, and test stage number to the anomaly log database when the comparison result exceeds the preset threshold range; sending a stop command to the current test stage of the chip under test to cut off the aging voltage and aging current supply to the test stage, thereby terminating the current aging test stage of the chip under test.

[0013] On the other hand, this application also provides an automatic chip aging test system, comprising: a chip identification module, used to identify the type identifier of the chip under test, and call the corresponding aging test parameter group from a preset parameter library based on the type identifier; an aging test module, used to perform aging tests on the chip under test using the aging test parameter group, and collect key electrical parameters of the chip under test in real time during the aging test process; a trend analysis module, used to analyze the aging trend based on the key electrical parameters, calculate the performance drift value based on the aging trend, compare the performance drift value with a corresponding threshold range, and obtain a comparison result; and an aging termination module, used to automatically perform an anomaly recording operation and terminate the current aging test stage of the chip under test when the comparison result exceeds the preset threshold range.

[0014] On the other hand, this application also provides a computer-readable storage medium storing at least one instruction or at least one program, which is loaded and executed by a processor to implement the automatic chip aging test method as described in any one of the above.

[0015] This application provides an automated chip aging test method, system, and medium with the following technical advantages: high identification accuracy and fast response speed. By combining chip type identifiers with a preset parameter library, automated matching of test conditions for different types of chips is achieved, avoiding the inefficiency and errors of manual parameter configuration. During the aging test, key electrical parameters are collected in real time and time-series analysis and polynomial fitting based on the rate of change are performed, accurately depicting the dynamic trend of chip aging. The comparison of performance drift values ​​with threshold ranges provides a clear judgment standard for the anomaly detection process. Furthermore, by automatically recording anomaly information and terminating the aging process, a fully automated closed-loop processing from data acquisition and analysis to decision-making and control is achieved. This not only improves testing efficiency but also effectively protects test equipment and samples, reduces resource waste and the risk of misjudgment, and overcomes the problems of low aging trend identification accuracy and slow response speed. Attached Figure Description

[0016] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating an automatic chip aging test method provided in an embodiment of the present invention;

[0018] Figure 2 This is a schematic block diagram of the structure of an automatic chip aging test system provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or sub-modules is not necessarily limited to those steps or sub-modules explicitly listed, but may include other steps or sub-modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1 As shown, this invention provides an automated chip aging test method that accurately monitors and dynamically determines the performance drift of different types of chips during the aging test process, and takes timely measures to address performance anomalies, thereby improving test efficiency and accuracy and reducing unnecessary test resource consumption. The automated chip aging test method specifically includes the following steps:

[0023] Step S1: Identify the type identifier of the chip under test, and call the corresponding aging test parameter group from the preset parameter library based on the type identifier.

[0024] The chip identification module configured in the testing system reads the type identifier of the chip under test. This type identifier is a unique identification information embedded within the chip and can be directly obtained through read commands from the external pins of the chip package, I²C bus commands, or SPI bus commands. After receiving the type identifier, the testing system accesses a preset parameter library stored in a database server and retrieves an aging test parameter set that perfectly matches the type identifier. This aging test parameter set includes all parameters required for the aging test, such as the voltage stress value, operating frequency, test duration, temperature setpoint, and sampling period of key electrical parameters.

[0025] When the type identifier of the chip under test is a 32-bit binary code, a specific read command 0xAB is sent after the device is powered on via the I²C bus. The chip returns a unique code 0x12345678. The system retrieves the aging test parameter group that matches the code in the parameter library. The voltage stress value is set to 1.2V, the operating frequency is 800MHz, the temperature is set to 125℃, the sampling period is 500ms, and the test duration is 72 hours.

[0026] Step S2: Use the aging test parameter group to perform aging test on the chip under test, and collect the key electrical parameters of the chip under test in real time during the aging test process.

[0027] The testing system configures the temperature control device, power supply module, and clock generation module of the test chamber according to the settings in the aging test parameter group, so that the chip under test operates under specified voltage, frequency, and temperature conditions. During the aging test, the data acquisition module synchronously reads key electrical parameters, including operating current, output signal amplitude, signal delay time, and power consumption, according to the sampling period, and stores the acquisition results with timestamps in the test data storage unit.

[0028] For test conditions of 125℃ temperature, 1.2V voltage, and 800MHz frequency, the data acquisition module uses a four-channel high-precision ADC to collect the chip's operating current (mA), output signal amplitude (V), signal delay time (ns), and power consumption (mW) at 500ms intervals, and stores each sampled data as a quintuple of {timestamp, current, amplitude, delay, power consumption}.

[0029] Step S3: Analyze the aging trend based on the key electrical parameters, calculate the performance drift value based on the aging trend, compare the performance drift value with the corresponding threshold range, and obtain the comparison result.

[0030] The testing system first performs time-series analysis on the continuously acquired key electrical parameters, calculates the rate of change between two adjacent sampling time points, and fits the rate of change using a polynomial fitting algorithm within at least one sampling period window (e.g., a 10-minute window) to obtain an aging trend curve. Subsequently, the change in the target index is extracted from the aging trend curve as the performance drift value, and the performance drift value is numerically compared with a preset threshold range to generate a comparison result.

[0031] A third-order polynomial fitting algorithm (least square fitting algorithm) is used to fit the rate of change sequence of signal delay time, and the slope k of the fitting curve is used as the performance drift value. When the performance drift value is +0.005ns / min, it is compared with the preset threshold range [-0.003ns / min, +0.003ns / min], and it is found that the drift value has exceeded the upper limit.

[0032] Step S4: When the comparison result exceeds the preset threshold range, an abnormality recording operation is automatically performed, and the current aging test of the chip under test is terminated.

[0033] The current performance drift value, the corresponding historical data of key electrical parameters, test environment parameters and time information are written as anomaly records into the anomaly database. The control module then sends a termination signal to the test control system to shut down the power supply and heating device for the chip under test, thereby stopping the aging process.

[0034] In one example, when the performance drift value of the signal delay time exceeds the threshold, the abnormal record is recorded in the format of {chip ID, timestamp, test temperature, test voltage, test frequency, historical data of key electrical parameters, performance drift value}. After the record is completed, the power supply to the test chamber is immediately cut off via a relay, and a buzzer alarm signal is issued.

[0035] It should be noted that when the comparison results do not exceed the preset threshold range, the testing system will continue to execute the test according to the aging test parameter group until the test duration ends or manual intervention is required.

[0036] In this embodiment, the type identifier of the chip under test is identified, and the corresponding aging test parameter group is retrieved from a preset parameter library based on the type identifier. Subsequently, the chip under test is subjected to aging test using the aging test parameter group, and key electrical parameters of the chip under test are collected in real time during the aging process. After obtaining the key electrical parameters, the aging trend is analyzed based on the key electrical parameters, and the performance drift value is calculated according to the aging trend. The performance drift value is compared with the corresponding threshold range to obtain the comparison result. When the comparison result exceeds the preset threshold range, an anomaly recording operation is automatically performed, and the current aging test stage of the chip under test is terminated, thereby realizing dynamic monitoring and automated processing of the chip aging state.

[0037] This technical solution can automatically call matching aging test parameter groups for different types of chips under test, realizing adaptive configuration of the testing process; during the aging test, key electrical parameters are collected in real time and trend analysis is performed, which can capture the changing characteristics of chip performance in a timely manner; by comparing the performance drift value with the threshold range and automatically recording the abnormality and terminating the aging process when the threshold is exceeded, it can not only improve the screening efficiency of defective chips, but also avoid invalid or excessive aging tests, improve the utilization rate of test resources and the accuracy of overall detection.

[0038] As a preferred option, step S1 can also be implemented using the following example:

[0039] The test equipment is electrically connected to the pins of the chip under test by a pin contact module. A preset identification voltage and identification current are applied to the chip under test to measure the response characteristic parameters of the chip under test under the action of the identification voltage and identification current.

[0040] The pin contact module of the test equipment includes multiple elastic probe pins, each corresponding to a pin of the chip under test (DUT). The pin surfaces are coated with a highly conductive metal layer (such as gold plating) to ensure a contact resistance of less than 0.05Ω during contact, guaranteeing signal transmission stability. Before connection, the pin contact module uses an automatic positioning mechanism to precisely align the pin positions with the DUT pin positions, with a positional deviation not exceeding ±0.02mm, ensuring no loose connections or short circuit risks. After electrical connection is completed, a recognition voltage and recognition current are applied to the DUT through the test equipment's built-in constant voltage and constant current source. The recognition voltage ranges from 0.5V to 1.5V, and the recognition current ranges from 1mA to 5mA, with accuracy errors for both voltage and current not exceeding ±0.1%. Under this voltage and current, the response characteristic parameters of the DUT during the recognition period are acquired. These response characteristic parameters include quiescent current, quiescent voltage, pin-to-pin resistance, and transient response waveform data after internal circuit excitation.

[0041] In one example, a microcontroller chip under test (MCU) with 48 pins is used. The MCU is aligned with these pins using 48 probes from a pin contact module. The contact pressure is set to 20g ± 2g per probe to ensure reliable electrical contact without damaging the pins. After connection, a 1.0V identification voltage and a 2mA identification current are applied to the chip. The identification period is set to 200ms. Within this period, the static current and static voltage values ​​of each pin, as well as the transient response waveform under the input signal pulse, are acquired at a sampling frequency of 1MHz. The obtained transient response waveforms are converted into digital signals and stored in the test equipment buffer for subsequent feature comparison.

[0042] The response feature parameters are matched and compared with the standard response feature parameters pre-stored in the parameter library. When the matching similarity reaches a preset threshold, the type identifier of the chip under test is determined.

[0043] In this step, the test equipment processes the collected response feature parameters using a feature extraction algorithm. The feature extraction process includes normalizing the transient response waveform, extracting parameters such as peak voltage, peak current, rise time, and fall time, and combining these feature parameters into a feature vector. Then, using a similarity calculation method based on Euclidean distance, this feature vector is compared one by one with the standard response feature parameter vectors in the parameter library. The formula for calculating the matching similarity is:

[0044] ;

[0045] in, To match similarity (values ​​range from 0 to 1) Let i be the i-th characteristic parameter of the chip under test. Let be the i-th value of the standard response feature parameter, and n be the number of feature parameters. When the matching similarity S is greater than or equal to 0.95, it is considered a successful match, thus determining the type identifier of the chip under test.

[0046] In one example, the characteristic parameters of the chip under test collected are:

[0047] The peak voltage is 1.02V, peak current is 2.05mA, rise time is 18ns, and fall time is 20ns. The Euclidean distance is calculated with the standard characteristic parameters (peak voltage 1.01V, peak current 2.04mA, rise time 18ns, fall time 21ns) of the chip with model number "MCU-1234" in the parameter library. The similarity is 0.976, which is greater than the preset threshold of 0.95. Therefore, the chip type is identified as "MCU-1234".

[0048] Based on the type identifier, the aging test parameter group corresponding to the type of chip under test is called from the preset parameter library. The aging test parameter group includes aging voltage value, aging current value, aging temperature value and sampling interval time.

[0049] After confirming the type identifier, the testing equipment retrieves the aging test parameter set that perfectly corresponds to that type identifier from the parameter library of local storage or a remote server. The aging voltage value in the parameter set ranges from 100% to 130% of the chip's rated operating voltage, the aging current value is set according to 90% to 110% of the chip's rated operating current, the aging temperature value is set between 90% and 110% of the chip's rated maximum operating temperature, and the sampling interval is set between 1 and 60 seconds depending on the chip type and aging sensitivity. This parameter set is directly used in the control logic of subsequent aging tests, including the settings for the constant voltage source, constant current source, and temperature control system, ensuring the accuracy and consistency of the aging test.

[0050] For the previously identified "MCU-1234" chip, its rated operating voltage is 3.3V, rated operating current is 50mA, and rated maximum operating temperature is 85℃. The corresponding aging test parameter set in the parameter library is: aging voltage 4.0V, aging current 52mA, aging temperature 90℃, and sampling interval 10 seconds. After calling this parameter set, the power output module of the test equipment sets the output voltage to 4.0V, the current limit to 52mA, the temperature control system heats to 90℃ and maintains a stable temperature, and the data acquisition module records the chip's key electrical parameters every 10 seconds for subsequent aging trend analysis.

[0051] The step of electrically connecting the test equipment to the pins of the chip under test (DUT) via the pin contact module, and applying a preset identification voltage and identification current to the DUT to measure the response characteristic parameters of the DUT under the identification voltage and identification current, can be preferably further described as follows:

[0052] The chip under test is placed on the chip carrier stage of the test fixture, and the pins of the chip under test are aligned with the contact pads on the test fixture by the positioning pins and clamping mechanism.

[0053] In this step, the geometric accuracy of the chip carrier stage and the positioning pin is ensured by a test fixture with a machining accuracy of not less than ±0.01mm; the positioning pin is made of wear-resistant stainless steel and is used in conjunction with a clamping mechanism (such as a spiral pressure block or pneumatic pressure plate) to ensure that the chip will not shift when contact pressure is applied; the surface of the chip carrier stage is coated with an anti-static coating, and the surface of the contact pad is electroplated with a gold layer thickness of 1-3μm to reduce contact resistance and avoid oxidation.

[0054] In one example, a QFP-64 packaged chip under test is placed on the chip carrier stage of the test fixture. The positioning holes of the chip are aligned by two positioning pins with a diameter of 3mm, and a clamping force of about 0.5MPa is applied by a pneumatic clamping mechanism to ensure accurate alignment of the chip pins with the contact pads.

[0055] The start-up electric drive mechanism controls the establishment of an electrical connection between the elastic probe array in the control pin contact module and the pins of the chip under test. The elastic probes are made of gold-plated material and have a preset contact pressure range.

[0056] In this step, the electric drive mechanism uses a stepper motor and a lead screw transmission system, with a position control accuracy better than 0.05mm; the needle bar of the elastic probe array is made of beryllium copper, with a gold plating layer thickness of 1μm, a needle tip diameter of 0.3mm, and the contact pressure is controlled in the range of 15gf-30gf to ensure that the oxide layer on the pin surface can be removed without causing pin deformation.

[0057] In one example, a stepper motor drives the probe array to move downwards, eventually applying a contact pressure of 20 gf to each pin, and the contact establishment process is monitored by the springback stroke of the probe array.

[0058] The contact resistance value between the elastic probe array and each connection point in the chip under test is measured by the contact resistance detection circuit. When the contact resistance value is lower than the preset threshold, the electrical connection is confirmed to be established successfully. The preset identification voltage and identification current are applied to the power supply pin of the chip under test in sequence. The identification voltage is a number of voltage levels within the range of 50%-80% of the chip's rated operating voltage. At the same time, the preset amplitude identification current is injected into the input pin of the chip under test through the current source module. The identification current is a DC current in the milliampere level or an AC current with a frequency range between 1kHz and 1MHz.

[0059] In this step, the contact resistance detection circuit adopts a four-terminal measurement method with a measurement accuracy better than 0.1mΩ and a threshold of 50mΩ; the identification voltage is output by a multi-channel programmable DC power supply with a voltage resolution of 0.01V; the amplitude of the identification current is set by a high-precision constant current source with a DC accuracy of ±0.5% and the AC current is generated by a function signal generator and driven by a power amplifier with a frequency resolution of 1Hz.

[0060] In one example, for a chip with a rated operating voltage of 3.3V, four identification voltage levels of 1.65V, 2.31V, 2.64V and 2.97V are applied sequentially, while a DC identification current of 10mA and an AC identification current of 100kHz and 5mA are injected into the input pin.

[0061] While applying the identification voltage and identification current, the voltage values ​​of each output pin of the chip under test are measured using a voltmeter.

[0062] In this step, a 16-bit resolution digital multimeter is used, with a measurement accuracy better than ±0.01% and a sampling frequency of 1kHz to ensure that short-term voltage fluctuations can be captured.

[0063] In one example, the voltage values ​​of each output pin were measured in the range of 0V to 2.9V and recorded in the data acquisition system.

[0064] The current flowing through each pin of the chip under test is measured using an ammeter.

[0065] In this step, the ammeter is implemented using a shunt resistor + differential amplifier structure. The shunt resistor has an accuracy of 0.1% and a temperature drift of 5ppm / ℃, and the measurement range is from 1μA to 500mA.

[0066] In one example, the quiescent current of the output pin was measured to be between 50 μA and 200 μA, and the current of the input pin was between 8 mA and 12 mA.

[0067] The impedance characteristics between the input and output terminals of the chip under test are measured using an impedance analyzer.

[0068] In this step, the impedance analyzer measures frequencies from 10 Hz to 10 MHz, with an impedance measurement accuracy better than ±1%, and uses at least 100 sweep points to obtain complete amplitude and phase frequency response curves.

[0069] In one example, a frequency sweep measured the impedance from the input to the output to be approximately 5kΩ at the low-frequency end and dropped to 500Ω at the high-frequency end.

[0070] The frequency response characteristics of the chip under test under AC excitation were measured using a spectrum analyzer.

[0071] In this step, the spectrum analyzer measures a bandwidth range from 1 Hz to 1 GHz, and the resolution bandwidth (RBW) can be set from 1 Hz to 1 MHz to ensure accurate analysis of different frequency components.

[0072] For example, under 100kHz AC current excitation, the output terminal shows a main peak at 100kHz with an amplitude of 0.8V, while the amplitude at higher harmonics is less than -40dB.

[0073] The total power consumption of the chip under the action of the identification voltage and identification current is measured by a power meter.

[0074] The power meter should have DC and AC power measurement capabilities with an accuracy of 0.1% and a sampling rate of 1kHz. The measured total power consumption is 85mW.

[0075] Voltage, current, impedance characteristics, frequency response characteristics, and total power consumption are used as response characteristic parameters.

[0076] The response characteristic parameters are stored in the data management module of the test equipment. The data format is CSV or binary data packet, which facilitates subsequent matching and comparison with the standard response characteristic parameters in the parameter library.

[0077] For example, the voltage value, current value, impedance characteristics, frequency response characteristics, and total power consumption are packaged into a parameter vector, such as 2.97, 0.0002, 500, -40, 0.085, and stored in a database for comparison.

[0078] As a preferred option, step S2 can also be implemented using the following example:

[0079] The programmable power module of the test equipment applies the aging voltage value from the aging test parameter set to the power pin of the chip under test.

[0080] In this step, the output of the programmable power module is directly connected to the power pin of the chip under test (DUT) via the power supply bus within the test equipment. The aging voltage value is set with an accuracy of ±0.1%FSR (Full Scale Range), and the programmable power module supports a voltage resolution of 0.1mV to ensure that the voltage applied to the DUT is accurate and stable. The aging voltage value is directly taken from a preset range in the aging test parameter set, such as 10%-30% higher than the chip's rated operating voltage, to accelerate the aging effect. During the voltage application process, the built-in voltage monitoring circuit detects the output voltage in real time and automatically adjusts the output through a closed-loop control algorithm (such as a PID control algorithm) to ensure that the voltage fluctuation does not exceed ±0.5mV throughout the entire aging cycle.

[0081] In one example, when the aging voltage set in the aging test parameter group is 3.6V, the programmable power supply module increases to 3.6V in 0.1mV steps and maintains a stable output. At the same time, the high-precision ADC module collects the actual output voltage once per second and records it to the test database so that the relationship between the actual applied voltage and the degree of chip aging can be retrospectively analyzed in subsequent aging trend analysis.

[0082] The current control module applies the aging current value from the aging test parameter group to the chip under test.

[0083] In this step, the current control module achieves constant current output through a precision current source circuit connected in series with the load terminal of the chip under test, with a current accuracy of ±0.05%FSR and a resolution of 1µA. The aging current value is provided by the aging test parameter set and is taken as 120%-150% of the chip's rated operating current, used to accelerate the formation of internal migration, electrothermal stress, and interface defects in the device. To ensure the stability of the aging current, the current control module also adopts a closed-loop control algorithm, which monitors the output current in real time and automatically adjusts to compensate for deviations. At the same time, it is combined with an overcurrent protection circuit, which immediately cuts off the output when the current exceeds the set value by more than 5%.

[0084] In one example, when the aging test parameter set is 150mA, the current control module will perform a circuit self-test before applying the current to confirm that the load impedance is within a safe range (e.g., 2Ω to 50Ω). Then, it will gradually increase the current to 150mA at a slope of 1mA / ms and maintain this current throughout the aging process, with a fluctuation range of less than ±0.1mA.

[0085] The temperature control system is activated to adjust the test environment temperature to the aging temperature value in the aging test parameter group and keep it constant.

[0086] In this step, the temperature control system consists of a high-precision heating / cooling unit, a temperature sensor array, and a PID closed-loop temperature controller. It can adjust the ambient temperature within the range of -40°C to +200°C with an adjustment accuracy of ±0.1°C. The aging temperature value is taken from the aging test parameter set and set at a level 10%-30% higher than the chip's rated operating temperature range to accelerate the material aging and stress accumulation process. At least four temperature sensors are arranged in the test chamber to monitor the temperature distribution in the four cardinal directions (top, bottom, left, and right) of the chip. Temperature uniformity is calculated through multi-point sampling, and the heating / cooling power is automatically adjusted when the temperature difference exceeds ±0.5°C.

[0087] In one example, when the aging temperature set in the aging test parameter group is 125°C, the temperature control system first heats up to the target temperature under no-load after startup, and then introduces hot air evenly into the test chamber through the preheating air duct, so that the chip under test reaches the target temperature within 5 minutes, and uses a real-time monitoring system to control the temperature fluctuation within ±0.2°C.

[0088] The sampling period is set as the trigger period of the preset timer according to the sampling interval time in the aging test parameter group. When the preset timer reaches the preset trigger time, the test system switches to each test stage of the chip under test in sequence through the multiplexer matrix, and applies a preset test signal to the chip under test in each test stage. The test signal includes at least one of DC bias voltage, AC small signal and step pulse signal.

[0089] In this step, the time reference for the preset timer is provided by a high-stability temperature-compensated crystal oscillator (TCXO), with a time accuracy better than ±1ppm, ensuring a stable and consistent sampling time interval. The multiplexer matrix adopts a combination of relays and solid-state switches to achieve nanosecond-level switching speeds and ensure low crosstalk (<-80dB). A DC bias voltage is used for static electrical characteristic measurements, an AC small signal is used for frequency response analysis, and a step pulse signal is used for transient response testing. Each test signal is output from the signal source module and fed into the input terminal of the chip under test through an impedance matching network.

[0090] In one example, when the sampling interval set in the aging test parameter group is 10 minutes, the timer is triggered once every 600 seconds, and the test system sequentially switches to the DC bias test (applying a 2.5V DC voltage), the AC small signal test (applying a 100mV amplitude, 1MHz frequency sine wave signal), and the step pulse test (applying a 1ns rise time, 3.3V amplitude square wave pulse).

[0091] The electrical response of the chip under test under test is measured in real time by a high-precision data acquisition module under test signal excitation, and key electrical parameters are calculated. The key electrical parameters include at least one of the following: on-resistance calculated by measuring the voltage drop and current ratio of the chip in the on state; leakage current obtained by measuring the reverse current of the chip in the off state; gate threshold voltage obtained by applying an incremental gate voltage and detecting the gate voltage value corresponding to the start of a significant increase in drain current; saturation current obtained by measuring the maximum output current of the chip under rated operating voltage; and turn-on voltage obtained by applying an incremental voltage and detecting the voltage value corresponding to the start of conduction of the chip. The measured and calculated key electrical parameter values, together with the current timestamp and chip identifier, are stored in the test database.

[0092] In this step, the high-precision data acquisition module employs a 24-bit resolution ADC with a sampling rate of up to 1 MSPS (millions of samples per second), and uses a four-wire measurement method to reduce the impact of contact resistance. On-resistance is calculated using the formula R=V / I, with voltage and current measurement accuracies of ±0.05%FSR and ±0.1%FSR, respectively; leakage current measurement resolution reaches 1 nA; the gate threshold voltage uses a step-scan method (0.1mV increments) combined with real-time data analysis to determine the critical point where the drain current increase exceeds 10 times; saturation current and turn-on voltage measurements also use an incremental scan method combined with a linear regression algorithm to calculate the inflection point position. All measured key electrical parameters, along with the current timestamp (accurate to milliseconds) and the chip's unique identifier, are stored in a structured data format in the test database to support subsequent aging trend modeling and analysis.

[0093] In one example, when measuring the on-resistance of a MOSFET chip, the system measured a current of 1.65A with a DC voltage of 3.3V applied. The on-resistance was then calculated to be 2.0Ω, and the measured time and chip serial number were stored in the database for subsequent trend fitting analysis with data from other time points.

[0094] As a preferred option, step S3 can also be implemented using the following example:

[0095] Time series analysis was performed on key electrical parameters to calculate the rate of change of key parameters between two adjacent sampling time points, and the aging trend curve was fitted based on the rate of change of key parameters within multiple consecutive sampling periods.

[0096] The testing system first reads all key electrical parameter values ​​of the target chip under test during the aging test process from the test database in timestamp order. Key electrical parameters include, but are not limited to: on-resistance, leakage current, gate threshold voltage, saturation current, and turn-on voltage. The read data is stored in a two-dimensional array, where the row index represents the sampling time point and the column index represents each type of key electrical parameter. The system sequentially retrieves two adjacent sampling time points Ti and Ti+1, and calculates the absolute change ΔP = parameter value (Ti+1) - parameter value (Ti) for each key electrical parameter. Then, it calculates the rate of change R = ΔP / (Ti+1-Ti), where Ti+1-Ti is in seconds, and the unit of the rate of change depends on the physical quantity of the corresponding parameter, such as mΩ / s, nA / s, mV / s, etc. All calculations are performed by the data processing module (built into the test equipment or an external server) using double-precision floating-point numbers to avoid trend fitting errors caused by insufficient floating-point precision.

[0097] In one example, if the on-resistance of a MOSFET chip is 15.23 mΩ at T1 = 3600 s and 15.57 mΩ at T2 = 7200 s, then the absolute change ΔP = 15.57 - 15.23 = 0.34 mΩ. With a sampling interval T2 - T1 = 3600 s, the rate of change R = 0.34 / 3600 ≈ 9.44 × 10⁻⁵ mΩ / s. The system records this rate of change in the corresponding rate of change array for subsequent trend curve fitting.

[0098] Numerical analysis is performed on the aging trend curve to obtain the performance drift value. The performance drift value is the percentage deviation of the current measurement value from the initial reference value. The performance drift value is then compared with the threshold range of the corresponding chip type stored in the parameter library to obtain the comparison result.

[0099] In this step, after generating the aging trend curve y=f(t), the system calculates the difference between the parameter value P(t) at the current test time point and the baseline value P(t_0) at the initial test time point. The performance drift value D = [P(t) - P(t_0)] / P(t_0) × 100%, where P(t_0) is the parameter value sampled for the first time. The system reads the performance drift threshold range corresponding to the chip type from the parameter library (e.g., on-resistance drift threshold ±5%, leakage current drift threshold ±20%), and strictly compares the calculated D with the threshold range to determine whether the limit is exceeded. If the limit is exceeded, an alarm is triggered.

[0100] In one example, if the initial gate threshold voltage of a chip is P(t_0) = 3.00V and the current value is P(t) = 3.15V, then D = (3.15 - 3.00) / 3.00 × 100% = 5.0%. If the gate threshold voltage drift range for this chip type is set to ±4%, then the result is out of range. The system will log "Gate threshold voltage drift exceeds limit, exceedance 1%" and issue a test termination signal.

[0101] The step of performing time-series analysis on key electrical parameters to calculate the rate of change of key parameters between two adjacent sampling time points, and fitting an aging trend curve based on the rate of change of key parameters over multiple consecutive sampling periods, can be preferably further described as follows:

[0102] Key electrical parameters of the chip under test are extracted at multiple consecutive sampling time points. These parameters are then arranged into a time series array according to their timestamps. The time point T between two adjacent sampling times is then calculated. i and T i+1 The absolute change of each key electrical parameter between values ​​is calculated, and the rate of change of the parameter is calculated based on the absolute change. The formula for calculating the rate of change of the key electrical parameter is: Rate of change = (Parameter value T) / (T * ...) * () * (T * (T * ( i+1 -Parameter value T i ) / (T i+1 -T i ).

[0103] During the data extraction phase, the system calls the database query interface, specifying the chip ID, parameter type, and sampling time sorting conditions in the form of SQL queries to ensure the temporal order of the data. The system uses NumPy array structures in Python for efficient batch rate of change calculation, reducing loop operation overhead, and normalizes the units of all sampling intervals to ensure that the rates of change under different sampling periods can be directly compared.

[0104] In one example, if the on-resistance sampling values ​​of the chip during a 10-hour aging test are [15.23, 15.35, 15.41, 15.57] mΩ, corresponding to sampling time points [0, 3600, 7200, 10800] seconds, then the rate of change array is calculated as follows:

[0105] First segment: R1 = (15.35 - 15.23) / (3600 - 0) ≈ 3.33 × 10 -5 mΩ / s;

[0106] Second section: R² = (15.41 - 15.35) / (7200 - 3600) ≈ 1.67 × 10 -5 mΩ / s;

[0107] Third segment: R3 = (15.57 - 15.41) / (10800 - 7200) ≈ 4.44 × 10 -5 mΩ / s;

[0108] The system stores the obtained R1, R2, and R3 into a rate of change sequence for subsequent filtering and fitting.

[0109] The rate of change of the same key electrical parameter within N consecutive sampling periods is obtained to form a rate of change sequence. The rate of change sequence is then filtered using a moving average filter to obtain a filtered rate of change sequence, where N is a positive integer greater than or equal to 10.

[0110] The moving average filtering employs the existing "Simple Moving Average" (SMA) method. Specifically, the window size is set to N, the arithmetic mean of all rates of change within the window is calculated, and the result is used as the filtered value for the current window. The window slides for one sampling period at a time until the entire rate of change sequence has been traversed. In the hardware implementation, the DSP module in the FPGA can be used to perform addition, accumulation, shifting, and division to reduce the CPU's computational load.

[0111] In one example, if N=10 and the rate of change sequence is [0.12, 0.15, 0.18, 0.17, 0.16, 0.14, 0.13, 0.12, 0.11, 0.10, 0.09, 0.08] mΩ / s, then the first filter value is (0.12+0.15+…+0.10) / 10=0.138mΩ / s, the second filter value is (0.15+0.18+…+0.09) / 10=0.133mΩ / s, and so on, to obtain a smooth rate of change sequence for trend fitting.

[0112] By fitting the rate of change sequence with the least squares method, an aging trend curve describing the change of key electrical parameters over time is obtained. The mathematical expression of the aging trend curve is a function of y=f(t), where y represents the value of the key electrical parameter, t represents the aging time, and f(t) is the fitted trend function.

[0113] The least squares method employs existing mathematical calculation methods such as linear regression or polynomial regression. It establishes an error sum of squares function S = Σ(y_i - f(t_i))² based on the parameter change rate sequence and the corresponding time series. The optimal fitting parameters are obtained by taking the partial derivative of the coefficients of f(t) and setting it to zero. The system can call the Python function NumPy.polyfit or the MATLAB function polyfit to perform the fitting. The order k is determined based on the goodness of fit R², with a value of 1 ≤ k ≤ 3.

[0114] In one example, if the filtered rate of change sequence corresponds to time points [0, 1h, 2h, 3h, 4h], and the on-resistance values ​​are [15.23, 15.30, 15.37, 15.49, 15.57] mΩ respectively, the system selects second-order polynomial regression, and the fitting result is f(t) = 0.02t² + 0.04t + 15.23, R² = 0.998. This trend curve can be used to predict subsequent aging states; for example, the on-resistance at 6 hours is expected to be 15.83 mΩ.

[0115] As a preferred option, step S4 can also be implemented using the following example:

[0116] When the comparison result exceeds the preset threshold range, the current timestamp, chip identifier, abnormal parameter type, abnormal parameter value, and test stage number are recorded in the abnormal log database.

[0117] In this step, the comparison result is output by step S3, including the comparison result of the performance drift value and the threshold range. When the result exceeds the threshold range, the system calls the exception logging module (which can be an independent process running on the test control server) to automatically collect the current timestamp (accurate to milliseconds, in YYYY-MM-DDHH:MM:SS.SSS format), chip identifier (Chip_ID, which can be a 32-bit unique serial number), exception parameter type (e.g., "on-resistance" or "gate threshold voltage"), exception parameter value (a real value with 6 decimal places), and the corresponding test stage number (Test_Stage_ID, which can be an integer from 1 to N, where N is the total number of test stages). The collected data is formatted as a JSON object and sent to the log database write interface via TCP / IP protocol. The database uses MySQL version 8.0, and the abnormal log table Abnormal_Log has predefined fields including: Log_ID (auto-incrementing primary key), Timestamp, Chip_ID, Param_Type, Param_Value, Stage_ID, and Operator_ID (record operator number). The process employs a transaction control mechanism to ensure the consistency and integrity of log data during writing. Any write failure will trigger a retry mechanism, with a maximum of 3 retries, each with an interval of 200ms.

[0118] For example, in an aging test, the system detected that the initial on-resistance (Rds_on) of a certain MOSFET chip was 0.003820Ω, and the measured value after 120 hours of aging was 0.005120Ω. The corresponding performance drift value was (0.005120-0.003820) / 0.003820×100%=34.02%, while the preset threshold range for this chip in the parameter library was ±25%. Because the drift value exceeded 25%, the system generated an anomaly record at 14:32:15.124 on 2025-08-15.

[0119] {

[0120] "Timestamp":"2025-08-1514:32:15.124",

[0121] "Chip_ID":"MCU202508150001",

[0122] "Param_Type":"Rds_on",

[0123] "Param_Value": 0.005120,

[0124] "Stage_ID":3,

[0125] "Operator_ID":"OP_015"

[0126] }

[0127] The system immediately writes the JSON data to the Abnormal_Log table via TCP port 3306, and only ends the recording process after returning the INSERTSUCCESS status code.

[0128] A stop command is sent to the test stage where the chip under test is located, cutting off the aging voltage and aging current supply to the test stage to terminate the current aging test stage of the chip under test.

[0129] After the exception log is completed, the system calls the Test_Control_Module to determine the specific test stage where the chip is located based on the Stage_ID in the exception log. Then, it sends a stop command to the corresponding Burn-in PowerControlUnit via the control bus (e.g., RS-485 or Industrial Ethernet). The data frame format of the stop command is as follows:

[0130] [Header:0xAA55][Stage_ID:1byte][Command:0x02][CRC16:2bytes], where Command:0x02 indicates "stop power supply". Upon receiving the stop command, the aging power control unit will execute the following actions:

[0131] Turn off the output relay (response time not exceeding 5ms);

[0132] The output voltage drop slope is controlled within the range of 0.1V / ms to prevent the chip from being damaged by instantaneous reverse voltage surges.

[0133] Simultaneously, the aging current path is cut off (achieved using a MOSFET switching array, with a turn-off time of less than 2ms).

[0134] The status of this step is marked as "STOPPED", and the execution result is fed back to the test control module.

[0135] After receiving feedback and confirming successful shutdown, the test control module records the status to the Test_Status table in the test database and triggers the alarm module to display a prompt to the operator's workstation.

[0136] For example, in the case of the MOSFET chip with abnormal on-resistance mentioned above, the chip's Stage_ID is 3, corresponding to the "high-temperature 125°C aging test". When the system detects a performance drift of 34.02% and writes it to the anomaly log, the test control module immediately generates a stop command data frame:

[0137] AA5503021F2B (where 1F2B is a CRC16 checksum) is sent to the aging power supply control unit ID=3 via RS-485 bus. Upon receiving the command, this unit shuts off the output relay within 3ms, smoothly reducing the voltage from 5.000V to 0V (taking 50ms) and the current from 2.000A to 0A (taking 1ms). After shutdown, the control unit returns an execution status frame AA5503009C3E indicating "successfully stopped." The system writes this status to the Test_Status table and displays "Chip MC202508150001 stopped aging at 2025-08-15 14:32:15.189" on the operator terminal.

[0138] like Figure 2 As shown, the present invention also provides an automatic chip aging test system 10, which specifically comprises the following modules:

[0139] The chip identification module 11 is used to identify the type identifier of the chip under test and call the corresponding aging test parameter group from the preset parameter library based on the type identifier.

[0140] The aging test module 12 is used to perform aging tests on the chip under test using the aging test parameter group, and to collect key electrical parameters of the chip under test in real time during the aging test process.

[0141] The trend analysis module 13 is used to analyze the aging trend based on key electrical parameters, calculate the performance drift value based on the aging trend, compare the performance drift value with the corresponding threshold range, and obtain the comparison result.

[0142] The aging termination module 14 is used to automatically perform an error recording operation and terminate the current aging test phase of the chip under test when the comparison result exceeds the preset threshold range.

[0143] In this embodiment, the chip identification module 11, aging test module 12, trend analysis module 13, and aging termination module 14 are connected via wired communication under a system bus architecture (preferably based on Gigabit Ethernet TCP / IP protocol, transmission delay ≤1 ms), achieving high-speed data synchronization and real-time command delivery. The chip identification module 11 uses a high-resolution two-dimensional code scanner (resolution accuracy not less than 300 dpi) or an RFID reader (operating frequency 13.56 MHz, reading distance ≤5 cm) to obtain the type identifier, and calls the corresponding aging test parameter group through an HTTPS encrypted connection (TLS1.3, key length 256 bit) with the parameter library server. The aging test module 12 has a built-in programmable power supply module (output voltage range 0~20V, resolution 0.1mV; output current range 0~5 A, resolution 0.1mA) and a high-speed sampling unit (sampling frequency ≥100 kHz, quantization accuracy 16). The system ensures real-time acquisition of key electrical parameters during the aging process. The trend analysis module 13 runs on an industrial control computer (CPU frequency ≥ 3.0 GHz, memory capacity ≥ 16 GB), employing a sliding window averaging algorithm and a least-squares linear regression algorithm (IEEE 754 double-precision floating-point arithmetic) to calculate the aging trend and performance drift value. When the performance drift value exceeds the threshold range, the aging termination module 14 cuts off the aging voltage and current supply via a relay drive unit (contact capacity ≥ 5 A, response time ≤ 5 ms) and a MOSFET array (on-resistance ≤ 10 mΩ). Simultaneously, it writes the abnormal record to the abnormal log database (MySQL 8.0, transaction mode ACID, character encoding UTF-8) and triggers an audible and visual alarm (sound pressure level ≥ 90 dB, flashing frequency 1 Hz). This system achieves a fully automated closed loop from chip identification, testing, data analysis to abnormal handling, avoiding delays caused by manual operation and improving the accuracy and safety of testing.

[0144] The present invention also provides a computer-readable storage medium storing at least one instruction or at least one program, wherein the at least one instruction or at least one program is loaded and executed by a processor to implement the automatic chip aging test method described above.

[0145] In this embodiment, a test control program written in a mixture of C++ and Python is pre-stored in a computer-readable storage medium (preferably a solid-state drive with a capacity of not less than 256GB and an interface type of NVMe PCIe 3.0×4). When this program runs on an industrial control computer, it calls the interface functions of the chip identification driver module, the aging test control module, the trend analysis algorithm module, and the aging termination control module to implement all the steps of the above-mentioned automatic chip aging test method. The program adopts a modular design structure. The chip identification driver module is responsible for parsing the type identifier and calling the parameter library API interface (RESTful style, JSON return format). The aging test control module controls the programmable power supply output and collects key electrical parameters through serial communication (RS-485, baud rate 115200 bps). The trend analysis algorithm module uses the NumPy library to perform matrix operations to calculate the performance drift value and compare it with the threshold. The aging termination control module drives the relay and MOSFET array through the digital output port to cut off the voltage and current and calls the database to write abnormal records. The introduction of this computer-readable storage medium enables the method of the present invention to be deployed across hardware platforms, achieving rapid upgrades and remote maintenance, while ensuring the consistency and reproducibility of the test logic.

[0146] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are also possible or may be advantageous.

[0147] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device, equipment, and storage medium embodiments are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0148] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing the relevant hardware to implement them. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0149] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An automated chip aging test method, characterized in that, include: Identify the type identifier of the chip under test, and call the corresponding aging test parameter group from the preset parameter library based on the type identifier; Apply the aging voltage value from the aging test parameter group to the power supply pin of the chip under test; Apply the aging current value from the aging test parameter group to the chip under test; The ambient temperature is adjusted to the aging temperature value in the aging test parameter group and kept constant. A preset timer trigger period is set as the sampling period according to the sampling interval in the aging test parameter group. When the preset timer reaches the preset trigger time, the test system sequentially switches to each test stage of the chip under test via a multiplexer matrix, and applies a preset test signal to the chip under test in each test stage. The electrical response of the chip under test under the test signal excitation is measured in real time, and key electrical parameters are calculated. Key electrical parameters of the chip under test are extracted at multiple consecutive sampling time points. These parameters are then arranged into a time series array according to their timestamps. The absolute change of each key electrical parameter between two adjacent sampling time points is calculated, and the parameter change rate is calculated based on this absolute change. The parameter change rate of the same key electrical parameter within N consecutive sampling periods is obtained to form a change rate sequence. This change rate sequence is then filtered using a moving average filter to obtain a filtered change rate sequence. The change rate sequence is then curve-fitted using the least squares method to obtain an aging trend curve. Numerical analysis is performed on the aging trend curve to obtain a performance drift value. This performance drift value is then numerically compared with the threshold range for the corresponding chip type stored in the parameter library to obtain a comparison result. When the comparison result exceeds the preset threshold range, an abnormality recording operation is automatically performed, and the current aging test phase of the chip under test is terminated.

2. The automatic chip aging test method according to claim 1, characterized in that, The step of identifying the type identifier of the chip under test and calling the corresponding aging test parameter group from a preset parameter library based on the type identifier includes: The test equipment is electrically connected to the pins of the chip under test through the pin contact module, and a preset identification voltage and identification current are applied to the chip under test to measure the response characteristic parameters of the chip under test under the action of the identification voltage and identification current. The response feature parameters are matched and compared with the standard response feature parameters pre-stored in the parameter library. When the matching similarity reaches a preset threshold, the type identifier of the chip under test is determined. The corresponding aging test parameter group is retrieved from the preset parameter library according to the type identifier. The aging test parameter group includes aging voltage value, aging current value, aging temperature value and sampling interval time.

3. The automatic chip aging test method according to claim 2, characterized in that, The step of electrically connecting the chip under test (DUT) to the pins via the pin contact module of the testing equipment, applying a preset identification voltage and identification current to the DUT, and measuring the response characteristic parameters of the DUT under the influence of the identification voltage and identification current includes: The chip under test is placed on the chip carrier stage of the test fixture, and the pins of the chip under test are aligned with the contact pads on the test fixture by the positioning pins and clamping mechanism. The electric drive mechanism controls the elastic probe array in the pin contact module to establish an electrical connection with the pins of the chip under test. The contact resistance value between the elastic probe array and each connection point in the chip under test is measured. When the contact resistance value is lower than a preset threshold, the electrical connection is confirmed to be successfully established. A preset identification voltage and identification current are then applied to the power supply pin of the chip under test in sequence. While applying the identification voltage and the identification current, the voltage values ​​of each output pin of the chip under test are measured using a voltmeter; The current flowing through each pin of the chip under test is measured using an ammeter. The impedance characteristics between the input and output terminals of the chip under test were measured using an impedance analyzer. The frequency response characteristics of the chip under test under AC excitation were measured using a spectrum analyzer. The total power consumption of the chip under the action of the identification voltage and identification current is measured by a power meter; The voltage value, the current value, the impedance characteristic, the frequency response characteristic, and the total power consumption are used as response characteristic parameters.

4. The automatic chip aging test method according to claim 1, characterized in that, The step of triggering an anomaly recording operation and terminating the current aging test phase of the chip under test when the comparison result exceeds a preset threshold range includes: When the comparison result exceeds the preset threshold range, the current timestamp, chip identifier, abnormal parameter type, abnormal parameter value and test stage number are recorded in the abnormal log database. A stop command is sent to the test stage where the chip under test is currently located, cutting off the aging voltage and aging current supply to the test stage to terminate the aging test stage where the chip under test is currently located.

5. An automated chip aging test system, characterized in that, include: The chip identification module is used to identify the type identifier of the chip under test and, based on the type identifier, call the corresponding aging test parameter group from the preset parameter library; An aging test module is used to apply the aging voltage value from the aging test parameter group to the power supply pin of the chip under test; Apply the aging current value from the aging test parameter group to the chip under test; The ambient temperature is adjusted to the aging temperature value in the aging test parameter group and kept constant. A preset timer trigger period is set as the sampling period according to the sampling interval in the aging test parameter group. When the preset timer reaches the preset trigger time, the test system sequentially switches to each test stage of the chip under test via a multiplexer matrix, and applies a preset test signal to the chip under test in each test stage. The electrical response of the chip under test under the test signal excitation is measured in real time, and key electrical parameters are calculated. The trend analysis module is used to extract key electrical parameters of the chip under test at multiple consecutive sampling time points, arrange the key electrical parameters into a time series array according to the timestamp order, calculate the absolute change of each key electrical parameter between two adjacent sampling time points, and calculate the parameter change rate based on the absolute change; obtain the parameter change rate of the same key electrical parameter within N consecutive sampling periods to form a change rate sequence, filter the change rate sequence according to the moving average filter to obtain a filtered change rate sequence; perform curve fitting on the change rate sequence using the least squares method to obtain an aging trend curve; perform numerical analysis on the aging trend curve to obtain a performance drift value, and compare the performance drift value with the threshold range of the corresponding chip type stored in the parameter library to obtain a comparison result; The aging termination module is used to automatically record an anomaly and terminate the current aging test phase of the chip under test when the comparison result exceeds a preset threshold range.

6. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction or at least one program segment, which is loaded and executed by a processor to implement claim 1. The automatic chip aging test method described in any one of the following 4.

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