Voltage source circuit, power supply voltage generation method and chip

Abstract

The embodiment of the invention relates to the field of integrated circuits, and discloses a voltage source circuit, a power voltage generation method and a chip. The voltage source circuit comprises a first voltage source. The first voltage source is configured to provide an adjustable voltage and is used for receiving a target control signal and providing a target output voltage of a corresponding size to the high-speed interface from a range of the adjustable voltage in response to the target control signal; wherein the target control signal is determined by taking the eye pattern width of the signal transmitted by the high-speed interface as the target width.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, specifically to a voltage source circuit, a power supply voltage generation method, and a chip. Background Technology

[0002] In modern computer architectures, high-speed interface technology plays a crucial role. High-speed interface technology supports a wide range of applications, from simple external storage devices to high-performance graphics processing cards, such as data transfer standards like PCI Express (PCIe), Serial ATA (SATA), and Universal Serial Bus 3.0 (USB 3.0).

[0003] The PHY (Port Physical Layer) chip in a high-speed interface provides support and protocols for data transmission. PHY chips typically operate at high data transfer rates; for example, the PHY of LPDDR5X memory can achieve data transfer rates of 9600 Mbps / pin or 8533 Mbps / pin.

[0004] At high data transmission rates, chip power supply noise can have a greater negative impact on data transmission. Therefore, a stable voltage source is needed for high-speed interfaces. Related technologies add a large number of on-die decoupling capacitors to control chip power supply noise; however, this occupies a significant amount of chip area. Summary of the Invention

[0005] In view of this, embodiments of this application provide a voltage source circuit and chip.

[0006] The technical solution of this application embodiment is implemented as follows:

[0007] This application provides a voltage source circuit for a high-speed interface, comprising: a first voltage source configured to provide an adjustable voltage for receiving a target control signal and, in response to the target control signal, providing a target output voltage of a corresponding magnitude to the high-speed interface from within the range of the adjustable voltage; wherein the target control signal is determined based on the eye diagram width of the signal transmitted by the high-speed interface being a target width.

[0008] In some embodiments, the voltage source circuit further includes: a second voltage source configured to provide a fixed voltage; wherein the fixed voltage is within the range of the adjustable voltage; and a power switching module electrically connected to the first voltage source and the second voltage source respectively, configured to receive and switch the first voltage source or the second voltage source to provide power to the high-speed interface according to a voltage selection signal; wherein the voltage selection signal corresponds to the operating mode of the high-speed interface.

[0009] In some embodiments, the target output voltage includes a clock voltage and input / output voltages; the first voltage source includes a control module, a first output module, and a second output module; wherein the control module is electrically connected to the control terminals of the first output module and the second output module respectively, and is configured to output a voltage control signal to the first output module and the second output module in response to the target control signal; the first output module is configured to provide the clock voltage in response to the voltage control signal; wherein the clock voltage is provided to the clock circuit of the high-speed interface; the second output module is configured to provide a plurality of the input / output voltages in response to the voltage control signal; wherein each input / output voltage is provided to at least one signal input / output path of the high-speed interface.

[0010] In some embodiments, the first voltage source further includes an isolation module electrically connected between the first output module and the second output module, used to isolate signal noise between the first output module and the second output module.

[0011] In some embodiments, the control module is further configured to receive a switch signal and a wake-up signal; the switch signal is an enable control signal for the control module, used to control the enable state of the control module; the wake-up signal is used to control the increase of the operating current of the control module in the initial enable stage, so as to improve the speed at which the control module is woken up from the power-down state.

[0012] In some embodiments, the control module includes: an operational amplifier; a non-inverting input of the operational amplifier receiving a reference voltage; the value of the reference voltage being determined based on the target control signal; an inverting input of the operational amplifier receiving feedback voltages from the first output module and the second output module; and an output of the operational amplifier connected to the control terminals of the first output module and the second output module for outputting the control voltage to the first output module and the second output module.

[0013] In some embodiments, both the first output module and the second output module include: a voltage output unit; the voltage output unit includes: a first transistor and a first resistor; the source of the first transistor is electrically connected to a power supply terminal; the gate of the first transistor is connected to the output terminal of the control module to receive the voltage control signal; the drain of the first transistor serves as a voltage output terminal to output a target voltage; the first resistor is connected between the drain of the first transistor and the inverting input terminal of the operational amplifier; the first output module includes one voltage output unit, and the second output module includes multiple voltage output units corresponding to the number of output signal paths.

[0014] In some embodiments, the second output module further includes a pre-voltage providing unit electrically connected to the output terminal of the second output module and configured to be turned on in response to an activation signal, so that the second output module provides a pre-stabilized voltage to the signal input / output channel in advance when the signal input / output channel performs input and output operations.

[0015] This application also provides a power supply voltage generation method for a high-speed interface, applied to a voltage source circuit of a high-speed interface, comprising: responding to a target control signal, providing a target output voltage of a corresponding magnitude to the high-speed interface circuit from within an adjustable voltage range, wherein the target control signal is determined based on the target width of the eye diagram of the signal transmitted by the high-speed interface.

[0016] In some embodiments, the target control signal is obtained through training, including: controlling the voltage source circuit to supply power to the high-speed interface through the control signal, and using the high-speed interface for signal transmission; if the width of the eye diagram of the signal transmitted by the high-speed interface is greater than the target width, then adjusting the control signal to reduce the output voltage of the voltage source circuit; or, if the width of the eye diagram of the signal transmitted by the high-speed interface is less than the target width, then adjusting the control signal to increase the output voltage of the voltage source circuit; until the control signal is adjusted to the point where the eye diagram width corresponding to the output voltage provided by the voltage source circuit is the target width, and the control signal at this point is taken as the target control signal.

[0017] In some embodiments, the voltage source circuit is further configured to provide a fixed voltage, and the power supply voltage generation method further includes: selecting a matching voltage from the fixed voltage and the target voltage as the power supply voltage of the high-speed interface based on the operating mode of the high-speed interface.

[0018] This application embodiment also provides a chip, including: the voltage source circuit and high-speed interface described in the above solution; the voltage source circuit is connected to the high-speed interface to provide power supply voltage to the high-speed interface.

[0019] Therefore, the first voltage source can provide a suitable target output voltage within an adjustable voltage range, enabling the eye diagram width of the signal transmitted through the high-speed interface to reach the target width. This reduces power supply noise to the target range, effectively controlling power supply noise. Attached Figure Description

[0020] Figure 1 A schematic diagram of the voltage source circuit provided in the embodiments of this application. Figure 1 ;

[0021] Figure 2 A schematic diagram of the voltage source circuit provided in the embodiments of this application. Figure 2 ;

[0022] Figure 3 A schematic diagram of the structure of the first voltage source provided in the embodiments of this application. Figure 1 ;

[0023] Figure 4 A schematic diagram of the structure of the first voltage source provided in the embodiments of this application. Figure 2 ;

[0024] Figure 5 A schematic diagram of the structure of the first voltage source provided in the embodiments of this application. Figure 3 ;

[0025] Figure 6 This is a schematic diagram of the structure of the digital-to-analog converter provided in the embodiments of this application;

[0026] Figure 7 This is a schematic diagram of the power switching module provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the signal waveform provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of the high-speed interface provided in the embodiments of this application;

[0029] Figure 10 A schematic diagram illustrating the implementation flow of the power supply voltage generation method provided in the embodiments of this application;

[0030] Figure 11 The illustration provided for the embodiments of this application Figure 1 ;

[0031] Figure 12 The illustration provided for the embodiments of this application Figure 2 ;

[0032] Figure 13 The illustration provided for the embodiments of this application Figure 3 ;

[0033] Figure 14 This is a schematic diagram of the chip structure provided in an embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0037] Figure 1 This is a schematic diagram of an optional structure of the voltage source circuit for the high-speed interface provided in an embodiment of this application. (Reference) Figure 1 The voltage source circuit 810 includes: a first voltage source 10.

[0038] In this embodiment, the first voltage source 10 is configured to provide an adjustable voltage Vreg. The first voltage source 10 can receive a target control signal Ctrl<7:0>_tar and, in response to the target control signal Ctrl<7:0>_tar, provide a target output voltage Vreg_tar of a corresponding magnitude to the high-speed interface from within the range of the adjustable voltage Vreg.

[0039] In this embodiment, the target control signal Ctrl<7:0>_tar is determined based on the eye diagram width of the signal transmitted through the high-speed interface as the target width. That is, the first voltage source 10 can be controlled by the control signal Ctrl<7:0> to supply power to the high-speed interface, and the high-speed interface can be used for signal transmission. Furthermore, the eye diagram width of the signal transmitted through the high-speed interface is compared with the target width. If the eye diagram width is inconsistent with the target width, the control signal Ctrl<7:0> is adjusted until the widths are consistent. At this point, the control signal Ctrl<7:0> is the target control signal Ctrl<7:0>_tar.

[0040] In this embodiment, read / write training can be performed before each startup initialization of the high-speed interface DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and the entire evaluation and adjustment process can be completed by an algorithm. The training results can be evaluated based on the parameters of the eye diagram, thereby determining the target control signal Ctrl<7:0>_tar and providing a target output voltage Vreg_tar of the corresponding magnitude.

[0041] In this embodiment of the application, during the read / write training process, the target output voltage Vreg_tar can be reduced as much as possible to save power consumption; however, the target output voltage Vreg_tar cannot be adjusted too low to ensure that the circuits in the high-speed interface are provided with effective power.

[0042] It should be noted that an eye diagram is a graph displayed on an oscilloscope by accumulating a series of digital signals. The eye diagram can reflect the effects of intersymbol interference and noise.

[0043] Understandably, the first voltage source 10 can provide a suitable target output voltage Vreg_tar within the adjustable voltage Vreg range, so that the eye diagram width of the signal transmitted through the high-speed interface reaches the target width. This reduces power supply noise to the target range, effectively controlling power supply noise.

[0044] Meanwhile, the target width of the eye diagram can be configured according to different scenarios. Therefore, providing the target output voltage Vreg_tar based on the target width of the eye diagram can ensure that the circuit's operating state meets the requirements of the scenario.

[0045] In some embodiments of this application, such as Figure 2 As shown, the voltage source circuit 810 also includes a second voltage source 20 and a power switching module 30.

[0046] In this embodiment, the second voltage source 20 is configured to provide a fixed voltage VDD. The fixed voltage is within the range of an adjustable voltage; for example, the adjustable voltage Vreg ranges from 0.4V to 0.85V, and the fixed voltage VDD is 0.75V.

[0047] In this embodiment, the power switching module 30 is electrically connected to the first voltage source 10 and the second voltage source 20, respectively. The power switching module 30 is configured to receive and switch between the first voltage source 10 and the second voltage source 20 to provide power to the high-speed interface according to the voltage selection signal Vreg_sel. The voltage selection signal Vreg_sel corresponds to the operating mode of the high-speed interface.

[0048] In this embodiment of the application, the operating modes of the high-speed interface may include: high performance mode, normal performance mode, and ultra-low power mode, etc.

[0049] In high-performance mode, such as when the computer is running a large game, the voltage source circuit 810 can provide a higher power supply voltage, such as the maximum voltage within the adjustable voltage Vreg range, to ensure the power requirements of high-performance mode.

[0050] In normal performance mode, such as when the computer is running office software, the voltage source circuit 810 can provide a fixed voltage VDD instead of using the first voltage source 10.

[0051] In ultra-low power modes, such as the standby state of a computer, the voltage source circuit 810 can provide a lower supply voltage, such as the lowest voltage in the adjustable voltage Vreg range, thereby saving power consumption.

[0052] Understandably, using the first voltage source 10, which provides an adjustable voltage Vreg, allows for adjustment of the voltage level as needed; however, this incurs additional power consumption. Conversely, using the second voltage source 20, which provides a fixed voltage VDD, does not incur additional power consumption but cannot adjust the voltage level. Therefore, by switching between the first voltage source 10 and the second voltage source 20 to provide either an adjustable or fixed voltage source to the high-speed interface according to its different operating modes, flexibility is increased, allowing for better matching of the requirements under different operating modes.

[0053] In some embodiments of this application, such as Figure 3 As shown, the first voltage source 10 also receives a switching signal Ldo_on. The switching signal Ldo_on can control the enable state of the first voltage source 10, so that the first voltage source 10 can be turned on when it is needed, and correspondingly, the first voltage source 10 can be turned off when it is not needed, thereby reducing power consumption.

[0054] In some embodiments of this application, such as Figure 3 As shown, the first voltage source 10 also receives a wake-up signal Ldo_fast. During the initial enabling phase of turning on the first voltage source 10, the wake-up signal Ldo_fast can accelerate the wake-up process.

[0055] In some embodiments of this application, such as Figure 3 As shown, the target output voltage Vreg_tar provided by the first voltage source 10 includes: a clock voltage Vreg_ck and an input / output voltage Vreg_io. The clock voltage Vreg_ck is provided to the clock circuit of the high-speed interface; the input / output voltage Vreg_io is provided to at least one signal input / output path of the high-speed interface.

[0056] The following explanation uses LPDDR5 (5th generation low-power double-rate synchronous dynamic random access memory) as an example.

[0057] On the one hand, LPDDR5 commands and addresses are sampled through the differential clock CK. That is to say, both addresses and commands are placed on the CA bus and sampled on both the rising and falling edges of the differential clock CK, while the chip select signal CS is only sampled on a single edge of the differential clock CK.

[0058] On the other hand, in LPDDR5, the data bus is sampled using a differential clock WCK, which is synchronized with the data DQ. The data DQ is sampled on both sides of the differential clock WCK. Specifically, writing data is done by the DRAM using the differential clock WCK to sample the data DQ, while reading data is done by the PHY using a selectable read clock RDQS to sample the DQ. The selectable read clock RDQS and the differential clock WCK are different clocks.

[0059] refer to Figure 9 When the interface circuit is a DDR interface circuit, the clock circuit is a clock transmission circuit (the transmission path of the clock signal pclk), which is powered by the clock voltage Vreg_ck; while the signal input path is a data write / read path (the transmission path of differential clock WCK, data DQ and optional read clock RDQS), which is powered by the input / output voltage Vreg_io.

[0060] In some embodiments of this application, such as Figure 3 As shown, the first voltage source 10 also receives an activation signal Active.

[0061] It should be noted that during circuit switching (such as the read / write operation switching of DDR), current fluctuations will cause voltage drop (IR drop). IR drop occurs at the trigger edge of the clock signal. The transition of the clock signal not only changes the switching state of a large number of transistors, but also causes the combinational logic circuit to transition. This generates a large current across the entire chip in a short period of time, and this instantaneous large current will cause IR drop.

[0062] In this embodiment, the activation signal Active can control the adjustment of the change edge of the target output voltage Vreg_tar, avoiding IR drop during circuit switching, so that the circuit in the high-speed interface is connected to the first voltage source 10 after the target output voltage Vreg_tar has stabilized, thereby improving the stability of the power supply.

[0063] In some embodiments of this application, such as Figure 4 As shown, the first voltage source 10 includes: a control module 103, a first output module 101, and a second output module 102.

[0064] In this embodiment, the control module 103 is electrically connected to the control terminals of the first output module 101 and the second output module 102, respectively, and is configured to output a voltage control signal Vgate to the first output module 101 and the second output module 102 in response to the target control signal Ctrl<7:0>_tar.

[0065] In this embodiment of the application, the first output module 101 is configured to provide a clock voltage Vreg_ck in response to the voltage control signal Vgate; wherein the clock voltage Vreg_ck is provided to the clock circuit of the high-speed interface.

[0066] In this embodiment of the application, the second output module 102 is configured to provide a plurality of input and output voltages Vreg_io in response to the voltage control signal Vgate; wherein each input and output voltage Vreg_io is provided to at least one signal input and output path of the high-speed interface.

[0067] In this embodiment of the application, reference is made to Figure 4 The first output module 101 and the second output module 102 also provide feedback voltages Vregck_fb and Vregio_fb to the control module 103, respectively. The control module 103 adjusts the voltage control signal Vgate based on the feedback voltages Vregck_fb and Vregio_fb, so that the voltages output by the first output module 101 and the second output module 102 reach the target values.

[0068] In some embodiments of this application, reference is made to Figure 4 The second output module 102 includes a plurality of second voltage output units 1021. Each second voltage output unit 1021, in response to a voltage control signal Vgate, provides an input / output voltage Vreg_io to power a corresponding signal input / output path in the high-speed interface. For example, the plurality of second voltage output units 1021 correspond to a plurality of data read / write paths of DDR.

[0069] Understandably, on the one hand, the first output module 101 provides the clock voltage Vreg_ck, and the second output module 102 provides the input / output voltage Vreg_io; thus, the clock voltage Vreg_ck for the clock circuit and the input / output voltage Vreg_io for the signal input / output path are provided by two independent modules, thereby avoiding mutual interference between the clock voltage Vreg_ck and the input / output voltage Vreg_io and ensuring the stability of the power supply.

[0070] On the other hand, both the first output module 101 and the second output module 102 are controlled by the voltage control signal Vgate output by the control module 103; thus, by multiplexing one control module 103 for the first output module 101 and the second output module 102, the number of control modules is reduced, thereby saving chip area.

[0071] In some embodiments of this application, such as Figure 4 As shown, the first voltage source 10 also includes an isolation module 104. The isolation module 104 is electrically connected between the first output module 101 and the second output module 102, and is used to isolate signal noise between the first output module 101 and the second output module 102; thereby, it can further avoid mutual interference between the clock voltage Vreg_ck and the input / output voltage Vreg_io, and ensure the stability of the power supply.

[0072] In this embodiment, the isolation module 104 can be disposed between the feedback terminal of the first output module 101 and the feedback terminal of the second output module 102 to isolate AC noise between the first output module 101 and the second output module 102. In some embodiments, the isolation module 104 may include a resistor; in other embodiments, the isolation module 104 may also employ other noise circuit structures, such as circuit structures composed of inductors, resistors, and other devices.

[0073] In some embodiments of this application, Figure 4 The control module 103 in the middle is also used to receive Figure 3 The control module 103 is configured with a switch signal Ldo_on and a wake-up signal Ldo_fast. The switch signal Ldo_on is the enable control signal for the control module 103, used to control the enable state of the control module 103, thereby controlling the enable state of the first voltage source 10; for example, the switch signal Ldo_on can be a power switch signal. The wake-up signal Ldo_fast is used to increase the operating current of the control module 103 during the initial enable phase, thereby improving the speed at which the control module 103 is woken up from a power-down state.

[0074] refer to Figure 8 When the switch signal Ldo_on is high, the control module 103 is enabled, and thus the first voltage source 10 is enabled and provides an adjustable voltage Vreg.

[0075] Continue to refer to Figure 8During the initial enable phase of the control module 103, that is, for a short period of time after the switch signal Ldo_on transitions to a high level, the wake-up signal Ldo_fast is at a high level. This increases the operating current of the control module 103 and speeds up the wake-up process. In some embodiments of this application, the high-level duration of the wake-up signal Ldo_fast is approximately 300 ns.

[0076] Continue to refer to Figure 8 After the control module 103 is fully awakened, when the first voltage source 10 is in a stable operating state, the voltage selection signal Vreg_sel is at a high level. At this time, the circuit in the high-speed interface switches to using the voltage source provided by the first voltage source 10, that is, it is in Vreg mode.

[0077] In some embodiments of this application, such as Figure 5 As shown, the control module 103 includes an operational amplifier Amp. The non-inverting input of operational amplifier Amp receives a reference voltage Vref. The inverting input of operational amplifier Amp receives a feedback voltage Vregck_fb from the first output module 101 and a feedback voltage Vregio_fb from the second output module 102. The output of operational amplifier Amp is connected to the control terminals of the first output module 101 and the second output module 102, for outputting a control voltage Vgate to both modules.

[0078] In this embodiment, the value of the reference voltage Vref is determined based on the target control signal Ctrl<7:0>_tar. Figure 6 The target control signal Ctrl<7:0>_tar can be converted into a reference voltage Vref of the corresponding size via a digital-to-analog converter (DAC). For example, the larger the binary value represented by the target control signal Ctrl<7:0>_tar, the larger the value of the converted reference voltage Vref.

[0079] In the embodiments of this application, Figure 3 The on / off signal Ldo_on and the wake-up signal Ldo_fast can be applied to Figure 5 The operational amplifier Amp is located in the module. Therefore, the switching signal Ldo_on can control the enable state of the operational amplifier Amp; the wake-up signal Ldo_fast can control the increase of the operating current of the operational amplifier Amp in the initial enable stage, so as to improve the speed at which the control module 103 is woken up from the power-down state.

[0080] In some embodiments of this application, reference is made to Figure 5The operational amplifier Amp can be powered by a charge pump CP. The switching signal Ldo_on and the wake-up signal Ldo_fast can control the enable and current of the operational amplifier Amp by controlling the charge pump CP, that is, by controlling the power supply of the operational amplifier Amp.

[0081] In some embodiments of this application, such as Figure 5 As shown, both the first output module 101 and the second output module 102 include voltage output units (first voltage output unit 1011 and second voltage output unit 1021). Both the first voltage output unit 1011 and the second voltage output unit 1021 include a first transistor M1 and a first resistor R1.

[0082] In this embodiment, the source of the first transistor M1 is electrically connected to the power supply terminal VDD1; the gate of the first transistor M1 is connected to the output terminal of the control module 103 to receive the voltage control signal Vgate; the drain of the first transistor M1 serves as the voltage output terminal, outputting the target voltage (clock voltage Vreg_ck or input / output voltage Vreg_io). A first resistor R1 is connected between the drain of the first transistor M1 and the inverting input terminal of the operational amplifier Amp.

[0083] It should be noted that, Figure 5 In the diagram, Clk rptx2 represents the equivalent load current of the circuit connected to the first voltage output unit 1011, that is, the equivalent load current of the clock circuit of the high-speed interface; DQ[0] and DQ[7] represent the equivalent schematic diagram of the circuit connected to the second voltage output unit 1021, that is, the input and output paths of the high-speed interface.

[0084] It should be noted that, Figure 5 The DQ[0-7] shown is an example of an interface circuit for DDR. Since DDR uses an 8-bit register, it is DQ[0-7], that is, 8 data paths. If the embodiment of this application is used for other data transmission interfaces, other numbers may be used, and there is no limitation here.

[0085] In this embodiment of the application, the first output module 101 includes a first voltage output unit 1011. The first voltage output unit 1011, in response to the voltage control signal Vgate, provides a clock voltage Vreg_ck to power the clock circuit Clk rptx2 of the high-speed interface.

[0086] In this embodiment of the application, the second output module 102 includes a plurality of voltage output units 1021 corresponding to the number of output signal paths. Each second voltage output unit 1021 provides an input-output voltage Vreg_io in response to the voltage control signal Vgate, providing power to a corresponding signal input-output path (i.e., one of DQ[0] to DQ[7]) in the high-speed interface.

[0087] In some embodiments of this application, such as Figure 5 As shown, the second output module 102 further includes a pre-voltage providing unit Ireg_io. The pre-voltage providing unit Ireg_io is electrically connected to the output terminal of the second output module 102 and is configured to be turned on in response to the activation signal Active, so that the second output module 102 provides a pre-stabilized voltage to the signal input and output channels in advance when the signal input and output channels are performing input and output operations.

[0088] refer to Figure 8 When performing read / write operations (i.e., input and output operations), the activation signal Active is high, thereby enabling the pre-voltage supply unit Ireg_io, which can provide a pre-stabilized voltage to the signal input and output channels in advance.

[0089] It should be noted that during circuit switching (such as the read / write operation switching of DDR), current fluctuations will cause voltage drop (IR drop). IR drop occurs at the trigger edge of the clock signal. The transition of the clock signal not only changes the switching state of a large number of transistors, but also causes the combinational logic circuit to transition. This generates a large current across the entire chip in a short period of time, and this instantaneous large current will cause IR drop.

[0090] In this embodiment, the pre-voltage supply unit Ireg_io, controlled by the activation signal Active, first provides a compensation voltage at the output port of the second voltage output unit 1021 to compensate for the generated IR drop. Then, after the voltage stabilizes, the pre-voltage supply unit Ireg_io is turned off. In this way, the output voltage fluctuation due to IR drop can be avoided, thus improving the stability of the power supply.

[0091] In some embodiments of this application, such as Figure 7As shown, the power switching module 30 includes two second transistors M2. The first second transistor M2 has its source connected to a first voltage source 10, receiving an adjustable voltage Vreg; its gate receives an inverted voltage selection signal Vreg_selb. The second second transistor M2 has its source connected to a second voltage source 20, receiving a fixed voltage VDD; its gate receives a voltage selection signal Vreg_sel. The drains of both second transistors M2 are connected to the output terminal of the power switching module 30.

[0092] refer to Figure 7 When the voltage selection signal Vreg_sel is 1 (high level) and the inverted voltage selection signal Vreg_selb is 0 (low level), the first second transistor M2 is turned on, and the power switching module 30 outputs an adjustable voltage Vreg, meaning that power is supplied by the first voltage source 10. Conversely, when the voltage selection signal Vreg_sel is 0 (low level) and the inverted voltage selection signal Vreg_selb is 1 (high level), the second second transistor M2 is turned on, and the power switching module 30 outputs a fixed voltage VDD, meaning that power is supplied by the second voltage source 20.

[0093] Figure 9 A partial circuit diagram of the high-speed interface 820 is shown. (Reference) Figure 9 This is an external clock circuit used to transmit the clock signal pclk. Depending on the scenario requirements, it can switch between the clock voltage Vreg_ck and the fixed voltage VDD as the voltage source. Correspondingly, each of the multiple signal input / output paths is configured with a corresponding switchable voltage source, which can switch between the input / output voltage Vreg_io and the fixed voltage VDD as the voltage source. Here, DDL represents the delay chain on the input / output path.

[0094] refer to Figure 9 In the case of an interface circuit with DDR interface circuitry, the input and output paths of differential clock WCK, data DQ, and optional read clock RDQS are powered by separate voltage sources. In this way, the voltage sources are distributed to avoid mutual interference between the various input and output paths and improve the stability of the power supply.

[0095] This application embodiment also provides a power supply voltage generation method for a high-speed interface, which is applied to the voltage source circuit of a high-speed interface, including step S101.

[0096] S101, in response to the target control signal, provides a target output voltage of a corresponding magnitude to the high-speed interface circuit within the adjustable voltage range. The target control signal is determined based on the target width of the eye diagram of the signal transmitted through the high-speed interface.

[0097] In this embodiment, the chip can be trained by reading / writing using a software program, and the training results can be evaluated by observing the eye diagram. In this way, the target control signal can be determined, and a target output voltage of the corresponding size can be provided.

[0098] In this embodiment of the application, the target output voltage can be reduced as much as possible during the read / write training process to save power consumption; however, the target output voltage cannot be adjusted too low to ensure that the circuits in the high-speed interface are provided with effective power.

[0099] In some embodiments of this application, it can be achieved through Figure 10 The steps S201 to S204 shown are used to train and obtain the target control signal, and each step will be explained in detail.

[0100] S201: The voltage source circuit is controlled by the control signal to supply power to the high-speed interface, and the high-speed interface is used for signal transmission.

[0101] S202. If the width of the eye diagram of the signal transmitted by the high-speed interface is greater than the target width, adjust the control signal to reduce the output voltage of the voltage source circuit.

[0102] S203. If the width of the eye diagram of the signal transmitted by the high-speed interface is less than the target width, adjust the control signal to increase the output voltage of the voltage source circuit.

[0103] S204. Adjust the control signal until the eye diagram width corresponding to the output voltage provided by the voltage source circuit is the target width, and use the control signal at this time as the target control signal.

[0104] In this embodiment, the eye diagram width of the signal transmitted via the high-speed interface can be compared with the target width. If the eye diagram width is inconsistent with the target width, the control signal is adjusted until the widths are consistent, thus obtaining the target control signal. For example, if the target width is X ps, when the eye diagram width > X ps, the control signal is adjusted to reduce the output voltage (clock voltage Vreg_ck and input / output voltage Vreg_io) of the voltage source circuit; correspondingly, when the eye diagram width < X ps, the control signal is adjusted to increase the output voltage (clock voltage Vreg_ck and input / output voltage Vreg_io) of the voltage source circuit.

[0105] Understandably, since eye diagrams can reflect the effects of inter-symbol interference and noise, determining the target control signal based on the target width of the eye diagram can effectively control the noise of the target output voltage.

[0106] In some embodiments of this application, the voltage source circuit is also used to provide a fixed voltage, and the power supply voltage generation method further includes step S301.

[0107] S301, based on the high-speed interface operating mode, selects a matching voltage from the fixed voltage and the target voltage as the power supply voltage for the high-speed interface.

[0108] Understandably, a voltage source circuit provides an adjustable voltage, allowing the voltage level to be adjusted as needed, but this incurs additional power consumption. Conversely, a voltage source circuit provides a fixed voltage, which does not incur additional power consumption, but the voltage level cannot be adjusted. Therefore, based on the high-speed interface's operating mode, the voltage source circuit selects a matching voltage from the fixed voltage and the target voltage as the power supply voltage for the high-speed interface. This increases flexibility and allows for better matching of the needs of different operating modes.

[0109] Figures 11 to 13 This is a schematic diagram illustrating the effect of an embodiment of this application.

[0110] like Figure 11 As shown, after using the wake-up signal Ldo_fast, the speed at which the control module in the first voltage source is woken up from the power-down state is improved, thereby the adjustable voltage Vreg output by the first voltage source can quickly rise to a stable value.

[0111] like Figure 12 As shown, eye Figure 1 and eyes Figure 2 All are powered by a fixed voltage VDD; among them, the eye Figure 1 VDD noise is ±0%, eye Figure 2 The VDD noise is ±4%. Correspondingly, the eye... Figure 1 and eyes Figure 2 All are powered by an adjustable voltage Vreg; among them, the eye Figure 3 Corresponding eye Figure 1 VDD noise is ±0%; eye Figure 4 Corresponding eye Figure 2 VDD noise is ±4%.

[0112] refer to Figure 12 When VDD noise is very low, i.e., VDD noise is ±0%, a fixed voltage VDD is used for the eye. Figure 1 and an eye using adjustable voltage Vreg Figure 3 Since the difference is not significant, it is appropriate to switch to a fixed voltage VDD for power supply, that is, to use the second voltage source 20 for power supply, in order to reduce additional power consumption.

[0113] Accordingly, continue to refer to Figure 12 When VDD noise is relatively high, i.e., VDD noise is ±4%, a fixed voltage VDD is used for the eye. Figure 2 and an eye using adjustable voltage Vreg Figure 4 The difference is quite large, eyes Figure 4 Significantly superior to eye Figure 2 At this point, it is appropriate to switch to using adjustable voltage Vreg for power supply, that is, to use the first voltage source 10 for power supply, in order to control power supply noise.

[0114] like Figure 13 As shown, with VDD noise of ±4% (frequency 99MHz), without the use of adjustable voltage Vreg for power supply, the signal in the eye diagram is significantly more divergent, with a divergence width of up to 2.63ps; correspondingly, with the use of adjustable voltage Vreg for power supply, the signal in the eye diagram is significantly more convergent, with a divergence width of only 0.27ps.

[0115] Figure 14 This is a schematic diagram of the structure of a chip provided in an embodiment of this application, such as... Figure 14 As shown, chip 800 includes a voltage source circuit 810 and a high-speed interface 820. The voltage source circuit 810 is connected to the high-speed interface 820 and provides a power supply voltage to the high-speed interface 820. The voltage source circuit 810 includes the structure described in the previous embodiment.

[0116] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0117] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0119] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0120] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0121] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium, including instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0122] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A voltage source circuit for a high-speed interface, comprising: A first voltage source is configured to provide an adjustable voltage for receiving a target control signal and, in response to the target control signal, providing a target output voltage of a corresponding magnitude to the high-speed interface from within the range of the adjustable voltage; wherein the target control signal is determined based on the eye diagram width of the signal transmitted through the high-speed interface as the target width.

2. The voltage source circuit according to claim 1, further comprising: A second voltage source is configured to provide a fixed voltage; wherein the fixed voltage is within the range of the adjustable voltage. The power switching module is electrically connected to the first voltage source and the second voltage source respectively, and is configured to receive and switch the first voltage source or the second voltage source to provide power to the high-speed interface according to the voltage selection signal; the voltage selection signal corresponds to the operating mode of the high-speed interface.

3. The voltage source circuit according to claim 1, wherein the target output voltage includes: Clock voltage and input / output voltage; The first voltage source includes: a control module, a first output module, and a second output module; wherein, The control module is electrically connected to the control terminals of the first output module and the second output module respectively, and is configured to output voltage control signals to the first output module and the second output module in response to the target control signal. The first output module is configured to provide the clock voltage in response to the voltage control signal; wherein the clock voltage is provided to the clock circuit of the high-speed interface; The second output module is configured to provide a plurality of the input and output voltages in response to the voltage control signal; wherein each of the input and output voltages is provided to at least one signal input / output path of the high-speed interface.

4. The voltage source circuit according to claim 3, wherein the first voltage source further comprises: An isolation module is electrically connected between the first output module and the second output module to isolate signal noise between the first output module and the second output module.

5. The voltage source circuit according to claim 1, The control module is also used to receive switch signals and wake-up signals; The switch signal is the enable control signal of the control module, used to control the enable state of the control module; The wake-up signal is used to control the increase of the operating current during the initial stage of enabling the control module, so as to improve the speed at which the control module is woken up from the power-down state.

6. The voltage source circuit according to claim 3, wherein the control module comprises: Operational amplifier; The non-inverting input of the operational amplifier receives a reference voltage; The value of the reference voltage is determined based on the target control signal; The inverting input terminal of the operational amplifier receives the feedback voltages from the first output module and the second output module. The output terminal of the operational amplifier is connected to the control terminals of the first output module and the second output module, and is used to output the control voltage to the first output module and the second output module.

7. The voltage source circuit according to claim 3, wherein both the first output module and the second output module comprise: Voltage output unit; The voltage output unit includes: a first transistor and a first resistor; The source of the first transistor is electrically connected to the power supply terminal; the gate of the first transistor is connected to the output terminal of the control module to receive the voltage control signal; the drain of the first transistor serves as the voltage output terminal to output the target voltage. The first resistor is connected between the drain of the first transistor and the inverting input of the operational amplifier; The first output module includes one voltage output unit, and the second output module includes multiple voltage output units corresponding to the number of output signal paths.

8. The voltage source circuit according to claim 4, wherein the second output module further comprises: The pre-voltage providing unit, electrically connected to the output terminal of the second output module, is configured to be turned on in response to an activation signal, so that the second output module provides a pre-stabilized voltage to the signal input / output channel in advance when the signal input / output channel is performing input and output operations.

9. A method for generating power supply voltage for a high-speed interface, applied to a voltage source circuit of a high-speed interface, comprising: In response to a target control signal, a target output voltage of a corresponding magnitude is provided to the high-speed interface circuit from within the adjustable voltage range, the target control signal being determined based on the target width of the eye diagram of the signal transmitted through the high-speed interface.

10. The power supply voltage generation method according to claim 9, wherein the target control signal is obtained through training, comprising: The voltage source circuit is controlled by a control signal to supply power to the high-speed interface, and the high-speed interface is used for signal transmission. If the width of the eye diagram of the signal transmitted by the high-speed interface is greater than the target width, the control signal is adjusted to reduce the output voltage of the voltage source circuit; or, if the width of the eye diagram of the signal transmitted by the high-speed interface is less than the target width, the control signal is adjusted to increase the output voltage of the voltage source circuit. The control signal is adjusted until the eye diagram width corresponding to the output voltage provided by the voltage source circuit is the target width, and the control signal at this time is taken as the target control signal.

11. The power supply voltage generation method according to claim 9, wherein the voltage source circuit is further configured to provide a fixed voltage, and the power supply voltage generation method further comprises: Based on the operating mode of the high-speed interface, a matching voltage is selected from the fixed voltage and the target voltage as the power supply voltage of the high-speed interface.

12. A chip, comprising: The voltage source circuit and high-speed interface according to any one of claims 1 to 8; The voltage source circuit is connected to the high-speed interface to provide power voltage to the high-speed interface.

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