Output-capacitor-free low dropout linear regulator adopting Class-AB output structure

Abstract

The embodiment of the invention provides a low dropout regulator without an output capacitor, which adopts a Class-AB output structure. The output-capacitor-free low dropout linear regulator adopting the Class-AB output structure is applied to the field of CMOS analog integrated circuit design and comprises a differential regeneration input stage, a folding stage, a push-pull driving buffer stage and a power output stage. The differential regeneration input stage improves the gain and common-mode rejection capability, the folding stage mirror image structure realizes low-voltage domain driving and double-path symmetrical amplification and enhances the dynamic performance of the circuit, and the Class-AB push-pull output stage provides strong driving capability and ensures quick response during large-range load change. Multi-stage zero adjustment and internal frequency compensation are embedded in a full-current path, closed-loop stability under the condition that no external output capacitor exists is effectively achieved, and the gain, the response speed, the stability and the integration degree are optimized through the overall structure of the linear voltage regulator.

Description

Technical Field

[0001] This invention relates to the field of CMOS analog integrated circuit design, and more particularly to a capacitorless low-dropout linear regulator employing a Class-AB output structure. Background Technology

[0002] Low dropout regulators (LDOs) are important modules for power management in analog integrated circuits and are widely used in applications with high requirements for power supply noise and response speed, such as system-on-chip (SoC) and radio frequency front-ends.

[0003] Traditional LDOs primarily use Class-A operational amplifiers. While Class-A LDOs are simple in structure and easy to compensate for, their output capability is limited, making them ill-suited for handling large load variations. Current LDO designs generally rely on large external output capacitors to improve system stability and transient response. However, for highly integrated chips and miniaturized designs, large external capacitors not only occupy PCB area and increase system cost but also limit chip-level integration. Capacitor-free designs of Class-A LDOs typically require sacrificing bandwidth or increasing on-chip compensation capacitors, leading to poorer transient response. While Class-AB LDOs offer stronger output capability, their push-pull structure introduces problems such as complex driving and insufficient gate drive capability. Especially without external output capacitors, the system is prone to loop instability and output voltage overshoot. Furthermore, traditional LDOs are mostly unidirectional, making it difficult to meet the demands of modern SoCs for bidirectional high-current dynamic loads.

[0004] Therefore, how to achieve low quiescent current, fast response speed, wide load range pull-down current output, and ensure system stability and low noise in a Class-AB type LDO without external output capacitors is a key technical problem that urgently needs to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a capacitorless low-dropout linear regulator employing a Class-AB output structure. The capacitorless low-dropout linear regulator with a Class-AB output structure provided by this invention includes: a differential input stage, a folding stage, a push-pull drive buffer stage, and a power output stage.

[0006] The differential input stage is connected to the folded stage, the folded stage is connected to the push-pull drive buffer stage, and the push-pull drive buffer stage is connected to the power output stage.

[0007] The differential input stage includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

[0008] The folding stage includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0009] The push-pull drive buffer stage includes: a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

[0010] The power output stage includes: a tenth PMOS transistor, an eleventh PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, and a third resistor.

[0011] Optionally, the gates of the first PMOS transistor and the second PMOS transistor are connected to the negative feedback node, the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the reference voltage, the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to the drain of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply voltage, and the gate of the fifth PMOS transistor is connected to the first bias voltage.

[0012] Optionally, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor, the source of the third NMOS transistor is grounded, the source of the second NMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is grounded, the gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0013] Optionally, the sources of the sixth and seventh PMOS transistors are connected to a power supply voltage; the gates of the sixth and seventh PMOS transistors are connected; the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor; the drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor; the drain of the eighth PMOS transistor is connected to the drain of the seventh NMOS transistor; the drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor; the gate of the eighth PMOS transistor is connected to a third bias voltage; the gate of the ninth PMOS transistor is connected to a third bias voltage; the gate of the seventh NMOS transistor is connected to a second bias voltage; the source of the seventh NMOS transistor is connected to the drains of the first and third PMOS transistors; the gate of the eighth NMOS transistor is connected to the second bias voltage; and the source of the eighth NMOS transistor is connected to the drains of the fourth and sixth NMOS transistors.

[0014] Optionally, the source of the tenth PMOS transistor is connected to the power supply voltage, the gate of the tenth PMOS transistor is connected to the first bias voltage, the drain of the tenth PMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor, the source of the ninth NMOS transistor is grounded, the source of the eleventh PMOS transistor is connected to the power supply voltage, the gate of the eleventh PMOS transistor is connected to the drain of the ninth PMOS transistor, the drain of the eleventh PMOS transistor is connected to the drain of the tenth NMOS transistor, the first end of the first resistor is connected to the gate of the tenth NMOS transistor, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the drain of the tenth NMOS transistor, the first end of the second resistor is connected to the drain of the tenth NMOS transistor, the second end of the second resistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the source of the tenth NMOS transistor, the first end of the second capacitor is connected to the drain of the tenth NMOS transistor, and the second end of the second capacitor is connected to the source of the tenth NMOS transistor.

[0015] Optionally, the capacitorless low-dropout linear regulator with Class-AB output structure further includes: a volume modulation circuit and a transient overshoot improvement circuit;

[0016] The bulk modulation error amplifier includes: a twelfth PMOS transistor, a thirteenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor;

[0017] The transient overshoot improvement circuit includes: a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a third capacitor, and a fourth capacitor.

[0018] Optionally, the source of the twelfth PMOS transistor is connected to the power supply voltage, the gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor is connected to the power supply voltage, the gate of the thirteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor, the drain of the thirteenth PMOS transistor is connected to the drain of the twelfth NMOS transistor, the drain of the twelfth PMOS transistor is connected to the drain of the eleventh NMOS transistor, the source of the eleventh NMOS transistor is connected to the drain of the thirteenth NMOS transistor, the source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, and the source of the thirteenth NMOS transistor is grounded.

[0019] Optionally, the source of the fourteenth PMOS transistor is connected to the power supply voltage; the gate of the fourteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor and the drain of the fifteenth PMOS transistor; the drain of the fourteenth PMOS transistor is connected to the source of the sixteenth NMOS transistor, the gate of the sixteenth NMOS transistor, and the gate of the fourteenth NMOS transistor; the drains of the sixteenth NMOS transistor and the fourteenth NMOS transistor are grounded; the source of the fifteenth PMOS transistor is connected to the power supply voltage; the gate of the fifteenth PMOS transistor is connected to the gate of the fifteenth NMOS transistor and the gate of the sixteenth PMOS transistor; the drain of the fifteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor; the source of the fifteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor; the source of the seventeenth NMOS transistor is grounded; and the first terminal of the third capacitor is connected to the source of the fifteenth NMOS transistor and the seventeenth NMOS transistor. The drain of the transistor is connected. The second terminal of the third capacitor is connected to the first terminal of the fourth capacitor. The second terminal of the fourth capacitor is connected to the drain of the sixteenth PMOS transistor and the source of the nineteenth PMOS transistor. The source of the sixteenth PMOS transistor is connected to the power supply voltage. The drain of the sixteenth PMOS transistor is connected to the source of the nineteenth PMOS transistor. The drain of the nineteenth PMOS transistor is connected to the drain of the eighteenth NMOS transistor and the gate of the nineteenth NMOS transistor. The source of the eighteenth NMOS transistor is grounded. The gate of the eighteenth NMOS transistor is connected to the gate of the seventeenth NMOS transistor and the gate of the nineteenth PMOS transistor. The source of the nineteenth NMOS transistor is grounded. The drain of the nineteenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor. The source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor are connected to the power supply voltage. The gate of the seventeenth PMOS transistor and the gate of the eighteenth PMOS transistor are connected.

[0020] This invention provides a capacitorless low-dropout linear regulator (LDO) with a Class-AB output structure. It employs a regenerative folded common-source error amplifier and body-terminal modulation technology, and introduces a symmetrical push-pull Class-AB buffer driver stage. This enables high power supply rejection ratio (PSRR), low quiescent power consumption, and excellent loop stability without the need for a large external capacitor. This structure not only improves input stage gain and common-mode rejection capability but also dynamically optimizes the threshold voltage of the power transistor through body-terminal modulation, giving the LDO faster response and stronger output capability during load surges. The push-pull output stage ensures driving capability under high-current loads, while the internal multi-stage compensation network further optimizes frequency response and system stability. The overall solution is highly integrated, simplifying peripheral design and suitable for on-chip system power management scenarios with high requirements for power quality and transient performance. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0022] Figure 1 A circuit diagram of a capacitorless low-dropout linear regulator with a Class-AB output structure is provided for an embodiment of the present invention.

[0023] Figure 2 A schematic diagram of the bulk modulation error amplifier and transient overshoot improvement circuit provided in an embodiment of the present invention;

[0024] Figure 3 This is a small-signal equivalent block diagram provided in an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of the load transient response provided in an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram illustrating the response of the output voltage when the input voltage undergoes a step change under different load currents, as provided in an embodiment of the present invention.

[0027] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0030] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0031] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0032] Figure 1 A circuit diagram of a capacitorless low-dropout linear regulator with a Class-AB output structure is provided for an embodiment of the present invention, as shown below. Figure 1 As shown, the capacitorless low-dropout linear regulator with a Class-AB output structure includes: a differential input stage, a folding stage, a push-pull drive buffer stage, and a power output stage; the differential input stage is connected to the folding stage, the folding stage is connected to the push-pull drive buffer stage, and the push-pull drive buffer stage is connected to the power output stage.

[0033] Specifically, the differential input stage includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4;

[0034] The folding stage includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6;

[0035] The push-pull drive buffer stage includes: the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8;

[0036] The power output stage includes: tenth PMOS transistor MP10, eleventh PMOS transistor MP11, ninth NMOS transistor MN9, tenth NMOS transistor MN10, first capacitor C1, second capacitor C2, first resistor R1, second resistor R2 and third resistor R3.

[0037] Understandably, the differential input stage is built on a four-transistor crossover structure, consisting of two pairs of PMOS transistors. One pair senses the feedback voltage Vfb, and the other senses the reference voltage Vref. By connecting the sources together and introducing a constant current source, error-sensitive amplification of the reference voltage Vref and feedback voltage Vfb under differential input can be achieved. The input stage adopts a cross-connected regenerative structure, that is, the transistors sensing the reference voltage Vref are the third PMOS transistor MP3 and the fourth PMOS transistor MP4, and the transistors sensing the feedback voltage Vfb are the first PMOS transistor MP1 and the second PMOS transistor MP2. The drains of the second PMOS transistor MP2 and the third PMOS transistor MP3 are cross-connected to the folded stage, thereby introducing regenerative positive feedback in the current path, effectively improving the input transconductance and suppressing input mismatch, and enhancing the sensitivity of the differential pair.

[0038] Specifically, the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the feedback voltage Vfb, the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the reference voltage Vref, the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the drain of the fifth PMOS transistor MP5, the source of the fifth PMOS transistor MP5 is connected to the power supply voltage VIN, and the gate of the fifth PMOS transistor MP5 is connected to the first bias voltage VB1.

[0039] Understandably, the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded through the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5, while the third NMOS transistor MN3 and the sixth NMOS transistor MN6 form a dynamic current replication path. Through feedback regulation, the current distribution between the main branch and the auxiliary branch is ensured to be symmetrical, so that the output current of the folding stage has an approximately mirror-image characteristic, possessing current reproduction capability, and improving the linearity and common-mode rejection ratio of the circuit.

[0040] Specifically, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2; the drain of the third PMOS transistor MP3 is connected to the drain of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is connected to the drain of the fourth NMOS transistor MN4; the source of the fourth NMOS transistor MN4 is grounded; the gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3; the drain of the third NMOS transistor MN3 is connected to the drain of the first PMOS transistor MP1; the source of the third NMOS transistor MN3 is grounded; the source of the second NMOS transistor MN2 is connected to the drain of the fifth NMOS transistor MN5; the source of the fifth NMOS transistor MN5 is grounded; the gate of the fifth NMOS transistor MN5 is connected to the gate of the sixth NMOS transistor MN6; the drain of the sixth NMOS transistor MN6 is connected to the drain of the fourth PMOS transistor MP4; and the source of the sixth NMOS transistor MN6 is grounded.

[0041] Understandably, the push-pull drive buffer stage is composed of PMOS and NMOS transistors, forming a Class-AB operating mode. The active pull-up is provided by the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7. The pull-down is completed by the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, with their sources connected to the output nodes of the preceding folded path. The conduction levels of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are controlled by the second bias voltage VB2, responsible for adjusting the preceding error signal (i.e., the current information after folding and mirroring) into two differential voltages, which are applied to the gate control terminals of the power output PMOS / NMOS transistors respectively. The eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 serve as the current output path of the pull-up driver, providing level transmission for the push-pull structure.

[0042] Specifically, the sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the power supply voltage VIN; the gates of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected; the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8; the drain of the seventh PMOS transistor MP7 is connected to the source of the ninth PMOS transistor MP9; the drain of the eighth PMOS transistor MP8 is connected to the drain of the seventh NMOS transistor MN7; and the drain of the ninth PMOS transistor MP9 is connected to the drain of the eighth NMOS transistor MN8. The gates of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are connected to the third bias voltage VB3. The gate of the seventh NMOS transistor MN7 is connected to the second bias voltage VB2. The source of the seventh NMOS transistor MN7 is connected to the drain of the first PMOS transistor MP1 and the third NMOS transistor MP3. The gate of the eighth NMOS transistor MN8 is connected to the second bias voltage VB2. The source of the eighth NMOS transistor MN8 is connected to the drain of the fourth PMOS transistor MP4 and the sixth NMOS transistor MN6.

[0043] The power output stage receives control signals from the push-pull buffer stage and adjusts the high-current output capability through two parallel reverse drive paths. The ninth NMOS transistor MN9 and the tenth PMOS transistor MP10, and the tenth NMOS transistor MN10 and the eleventh PMOS transistor MP11, respectively receive drain control signals from the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9, controlling the output node VOUT voltage through main loop feedback. To achieve system stability, the VOUT node is connected to the gate of the control transistor through a series RC compensation network, thereby introducing main pole compensation and avoiding loop oscillations caused by the lack of an external output capacitor. Fast voltage drive response is achieved through coupling with the drive path via the first capacitor C1 and the second capacitor C2, respectively, for positive and negative current abrupt changes.

[0044] Specifically, the source of the tenth PMOS transistor MP10 is connected to the power supply voltage, the gate of the tenth PMOS transistor MP10 is connected to the first bias voltage, the drain of the tenth PMOS transistor MP10 is connected to the drain of the ninth NMOS transistor MN9, the gate of the ninth NMOS transistor MN9 is connected to the drain of the eighth PMOS transistor MP8, the source of the ninth NMOS transistor MN9 is grounded, the source of the eleventh PMOS transistor MP11 is connected to the power supply voltage, the gate of the eleventh PMOS transistor MP11 is connected to the drain of the ninth PMOS transistor MP9, and the drain of the eleventh PMOS transistor MP11 is connected to the drain of the tenth NMOS transistor MN10. The first resistor R1 is connected to the gate of the tenth NMOS transistor MN10. The second resistor R1 is connected to the first capacitor C1. The second capacitor C1 is connected to the drain of the tenth NMOS transistor MN10. The first resistor R2 is connected to the drain of the tenth NMOS transistor MN10. The second resistor R2 is connected to the first resistor R3. The second resistor R3 is connected to the source of the tenth NMOS transistor MN10. The first capacitor C2 is connected to the drain of the tenth NMOS transistor MN10. The second capacitor C2 is connected to the source of the tenth NMOS transistor MN10.

[0045] Figure 2 The bulk modulation error amplifier and transient overshoot improvement circuit provided in the embodiments of the present invention, such as Figure 2 As shown, the bulk modulation error amplifier includes: the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, and the thirteenth NMOS transistor MN13; the transient overshoot improvement circuit includes: the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the seventeenth PMOS transistor MP17, the eighteenth PMOS transistor MP18, the nineteenth PMOS transistor MP19, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the third capacitor C3, and the fourth capacitor C4.

[0046] Specifically, the source of the twelfth PMOS transistor MP12 is connected to the power supply voltage VIN, the gate of the twelfth PMOS transistor MP12 is connected to the drain of the twelfth PMOS transistor MP12, the source of the thirteenth PMOS transistor MP13 is connected to the power supply voltage VIN, the gate of the thirteenth PMOS transistor MP13 is connected to the gate of the twelfth PMOS transistor MP12, the drain of the thirteenth PMOS transistor MP13 is connected to the drain of the twelfth NMOS transistor MN12, the drain of the twelfth PMOS transistor MP12 is connected to the drain of the eleventh NMOS transistor MN11, the source of the eleventh NMOS transistor MN11 is connected to the drain of the thirteenth NMOS transistor MN13, the source of the twelfth NMOS transistor MN12 is connected to the drain of the thirteenth NMOS transistor MN13, and the source of the thirteenth NMOS transistor MN13 is grounded.

[0047] The source of the fourteenth PMOS transistor MP14 is connected to the power supply voltage VIN. The gate of the fourteenth PMOS transistor MP14 is connected to the drain of the fifteenth NMOS transistor MN15 and the drain of the fifteenth PMOS transistor MP15. The drain of the fourteenth PMOS transistor MP14 is connected to the source of the sixteenth NMOS transistor MN16, the gate of the sixteenth NMOS transistor MN16, and the gate of the fourteenth NMOS transistor MN14. The drains of the sixteenth NMOS transistor MN16 and the drain of the fourteenth NMOS transistor MN14 are grounded. The fifteenth PMOS transistor MP14... The source of transistor 15 is connected to the power supply voltage VIN. The gate of the fifteenth PMOS transistor MP15 is connected to the gate of the fifteenth NMOS transistor MP5 and the gate of the sixteenth PMOS transistor MP16. The drain of the fifteenth PMOS transistor MP15 is connected to the drain of the fifteenth NMOS transistor MN15. The source of the fifteenth NMOS transistor MN15 is connected to the drain of the seventeenth NMOS transistor MN17. The source of the seventeenth NMOS transistor MN17 is grounded. The first terminal of the third capacitor C3 is connected to the source of the fifteenth NMOS transistor MN15 and the seventeenth NMOS transistor MN17. The drain of the first capacitor is connected to the drain of the second capacitor C3. The second terminal of the third capacitor C3 is connected to the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 is connected to the drain of the sixteenth PMOS transistor MP16 and the source of the nineteenth PMOS transistor MP19. The source of the sixteenth PMOS transistor MP16 is connected to the power supply voltage VIN. The drain of the sixteenth PMOS transistor MP16 is connected to the source of the nineteenth PMOS transistor MP19. The drain of the nineteenth PMOS transistor MP19 is connected to the drain of the eighteenth NMOS transistor MN18 and the gate of the nineteenth NMOS transistor MN19. The eighteenth NMOS transistor... The source of transistor MN18 is grounded. The gate of the eighteenth NMOS transistor MN18 is connected to the gate of the seventeenth NMOS transistor MN17 and the gate of the nineteenth PMOS transistor MP19. The source of the nineteenth NMOS transistor MN19 is grounded. The drain of the nineteenth NMOS transistor MN19 is connected to the drain of the seventeenth PMOS transistor MP17. The source of the seventeenth PMOS transistor MP17 and the source of the eighteenth PMOS transistor MP18 are connected to the power supply voltage VIN. The gate of the seventeenth PMOS transistor MP17 and the gate of the eighteenth PMOS transistor MP18 are connected.

[0048] Understandably, when the load current suddenly changes from zero to negative or from a small current absorption to a large current absorption, the gate of the n-type power transistor cannot immediately sense this change. Therefore, the current is primarily supplied by charging the load capacitor. When the output voltage rises slightly, the current in MP19 increases, thereby raising the gate voltage of MN19, allowing more current to flow through MN19. As a result, the large current in MN19 charges the gate of the n-type power transistor, enabling it to carry an even larger current. Simultaneously, the error amplifier shuts down the p-type power transistor.

[0049] When the load current suddenly changes from a positive (negative) value to zero, the current first charges (discharges) the load capacitor, causing the output voltage to drop (rise) slightly. Therefore, the error amplifier immediately pulls down (raises) the gate voltage of the n-type power transistor. This process is fast enough that no transient overshoot correction circuitry is needed.

[0050] When the load current suddenly changes from zero to a positive value or suddenly increases, the gate of the p-type power transistor cannot immediately sense this change. Therefore, the current is still supplied by charging the load capacitor. When the output voltage drops slightly, the current in MP14 and MN15 increases, allowing more current to flow through MN14. As a result, the large current through MN14 discharges the gate of the p-type power transistor, enabling it to output a larger current.

[0051] Furthermore, the bulk modulation error amplifier lowers the threshold voltage of the p-type power transistor, thereby further increasing the current flowing through it. Simultaneously, the main error amplifier shuts down the n-type power transistor.

[0052] The effect of the difference between the threshold voltage Vth of a MOSFET and the source voltage is called the bulk effect.

[0053]

[0054] in, It is the voltage difference between the source and the body. It is the body effect coefficient. for Threshold voltage at that time This represents the Fermi level potential.

[0055] The body modulation error amplifier (BMA) improves the transient response and output capability of an LDO by adjusting the body voltage of the power transistor, which in turn adjusts the threshold voltage (Vth) of the power transistor. By adjusting the bulk voltage, the threshold voltage of the MOSFET can be dynamically lowered or raised, thereby increasing or decreasing its conduction capability. Under normal steady-state conditions, the BMA operates in conventional error amplifier mode, adjusting the P-bulk voltage to maintain a suitable threshold voltage for the main power transistor, ensuring stable output voltage. During sudden load changes (such as a sudden increase in load current), the BMA circuit rapidly lowers the P-bulk voltage, reducing the threshold voltage of the main power transistor, making it easier to conduct and outputting a larger current, thus improving the LDO's transient response speed. When the load decreases, the P-bulk voltage recovers, the threshold voltage increases, the conduction capability of the main power transistor weakens, and the output current decreases. Traditional LDO error amplifiers only adjust the gate, limited by the inherent threshold voltage of the MOSFET, resulting in limited response speed and output capability. The BMA circuit works in conjunction with the transient enhancement circuit, simultaneously adjusting both the gate and body, dynamically optimizing MOSFET characteristics and improving LDO performance.

[0056] Figure 4 This is a schematic diagram of the load transient response provided in an embodiment of the present invention, illustrating the transient response of the output voltage of a class-AB LDO when the load current changes abruptly (from 0mA to ±100mA, and then back to 0mA). It is divided into two cases: (a) current supply mode (+100 mA) and (b) current sinking mode (-100mA).

[0057] (a) In current supply mode, when the load current abruptly changes from 0mA to +100mA, the output voltage Vout drops, with a maximum voltage drop of 220mV, and the recovery time to steady state is 3.6μs. When the load current returns from +100mA to 0mA, the output voltage rises, with a maximum voltage rise of 150mV, and the recovery time is 3.5μs.

[0058] (b) Current absorption mode: When the load current changes abruptly from 0mA to -100mA, the output voltage will rise, with a maximum voltage rise of 170mV and a recovery time of 3μs. When the load current returns from -100mA to 0mA, the output voltage will drop, with a maximum voltage drop of 70mV and a recovery time of 2μs.

[0059] Data shows that the LDO can recover to a steady state in a short time when the load current changes rapidly, and the voltage fluctuation is small, indicating that it has excellent transient response performance and is suitable for application scenarios with high power supply stability requirements.

[0060] Figure 5This is a schematic diagram illustrating the response of the output voltage when the input voltage undergoes a step change under different load currents, as provided in an embodiment of the present invention. The loads are categorized as (a) -100mA and (b) +100mA.

[0061] (a) -100mA load:

[0062] When the input voltage jumps from 1.2V to 1.8V, the output voltage rises by a maximum of 300mV, with a recovery time of 6.7μs. When the input voltage jumps from 1.8V to 1.2V, the output voltage drops by a maximum of 66mV, with a recovery time of 2.5μs.

[0063] (b) +100mA load:

[0064] When the input voltage jumps from 1.2V to 1.8V, the output voltage rises by a maximum of 390mV, with a recovery time of 7.3μs. When the input voltage jumps from 1.8V to 1.2V, the output voltage drops by a maximum of 66mV, with a recovery time of 3μs.

[0065] Data shows that when the input voltage changes abruptly, the output voltage of this LDO can recover quickly, and the voltage fluctuation is controlled within a reasonable range, demonstrating good linear transient response capability.

[0066] Figure 3 The small-signal equivalent block diagram provided in this embodiment of the invention. Through theoretical analysis, the system comprises four left-half-plane poles, three left-half-plane zeros, and two right-half-plane zeros, with the specific distribution and calculation formulas as follows:

[0067]

[0068]

[0069]

[0070]

[0071] Among them, R eq1 R eq2 R eq3 These are the equivalent resistances seen at the outputs of the main error amplifier, the interstage level shifter, and the body-end modulation error amplifier, respectively. , , These are the equivalent capacitances seen at the outputs of the main error amplifier, the interstage level shifter, and the body-terminal modulation error amplifier, respectively. dn With r dp These are the output resistances of the NMOS and PMOS power transistors, respectively. out R is the equivalent resistance at the LDO output.out =R1∥(R2+R3)∥r dp ∥r dn ). These correspond to the poles formed by the equivalent resistance and capacitance seen at the main error amplifier, level shifting stage, and body-terminal modulation output, respectively. These are the principal poles, and they determine the rate at which the loop gain decays at different frequencies. The fourth pole... The output pole is defined by the equivalent resistance R at the LDO output terminal. out With the on-chip load capacitor C L These factors, working together, reflect the high-frequency response characteristics of the output. The system also includes three left-half-plane zeros and two right-half-plane zeros, specifically:

[0072]

[0073]

[0074]

[0075]

[0076] in, These are the transconductances of the main error amplifier and the body-terminal modulation error amplifier, respectively. For the gate-drain capacitance of p-type and n-type power transistors, This is the equivalent resistance at the LDO output terminal. For compensation capacitors.

[0077] Miller capacitors Mainly used to generate The secondary pole of the compensation level conversion path is offset. In a Class-AB LDO, the poles of the bulk modulation error amplifier This is not caused by a single physical node, but rather by the interaction of multiple sub-paths. Specifically, the output impedance and parasitic capacitance of the bulk modulation error amplifier itself form the fundamental pole, and the bulk modulation signal is coupled to the main loop through the bulk effect of the PMOS power transistor, introducing an additional phase delay. Therefore, a zero is used. Compensator Modulation Error Amplifier Pole Zero point of the right half-plane Derived from the gate-drain capacitance C of the power transistor gdp / C gdn and transconductance g mp / g mn Zeros in the right half-plane cannot be canceled out by zeros in the left half-plane; it is necessary to ensure that they are outside the gain-bandwidth product. Therefore, this can be achieved by increasing Cgd (e.g., optimizing the power transistor size) to push it to ultra-high frequencies. Output poles By adjusting CL Size and optimized power transistor dimensions push it to high frequencies.

[0078] Through the reasonable distribution and design of the above-mentioned multiple poles and zeros, the LDO regulator of the present invention can achieve stable operation across the entire load range, making it easy to adjust the stability margin of the system under different load currents and improve the robustness and reliability of the system.

[0079] For example, the input voltage range is 1.2V to 2.5V, the output voltage is 1V, the maximum sink / pump load current is ±100mA, and the quiescent current is only 5μA. Key capacitor parameters are: C2=10pF, C1=1pF, C3=0.5pF, C4=1pF. Key resistor parameters are: R1=2kΩ, R2=200kΩ, R3=800kΩ.

[0080] Simulations show that the load regulation is 25 μV / mA and 20 μV / mA at input voltages of 1.2V and 1.8V, respectively. The line regulation is 1.15 mV / V, 0.69 mV / V, and 2.23 mV / V at different load currents (0 and ±100mA), respectively. Regarding load transient response, with a current step of ±100mA, the maximum overshoot / undershoot is 220 mV, the maximum recovery time is 3.6 μs, the minimum overshoot / undershoot is 70 mV, the minimum recovery time is 2 μs, and the phase margin is between 35° and 85°, indicating good stability across the entire load range. The power supply rejection ratio varies from -50 dB to -70 dB under different load currents.

[0081] The differential input stage of the architecture described in this invention employs a regenerative structure, significantly improving gain and common-mode rejection. The folded mirror structure enables low-voltage domain driving and dual-path symmetrical amplification, enhancing the circuit's dynamic performance. The Class-AB push-pull output stage provides powerful driving capability, ensuring rapid response under high-current loads. Multi-stage zero-point adjustment and internal frequency compensation are embedded throughout the entire current path, effectively achieving closed-loop stability without external output capacitors. Furthermore, the bulk modulation error amplifier further optimizes the threshold characteristics of the MOSFET by dynamically adjusting the body voltage of the power transistor, improving the transient response speed and output capability of the LDO during load changes. The transient enhancement circuit provides dedicated current paths and compensation mechanisms for different load variations, significantly improving output voltage overshoot / undershoot and recovery time. The overall solution synergistically optimizes gain, response speed, stability, and integration, making it suitable for on-chip system power management scenarios with extremely high requirements for power quality and transient performance.

[0082] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0083] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A capacitorless low-dropout linear regulator employing a Class-AB output structure, characterized in that, include: Differential input stage, folding stage, push-pull drive buffer stage, and power output stage; The differential input stage is connected to the folded stage, the folded stage is connected to the push-pull drive buffer stage, and the push-pull drive buffer stage is connected to the power output stage. The differential input stage includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; The folding stage includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The push-pull drive buffer stage includes: a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The power output stage includes: a tenth PMOS transistor, an eleventh PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, and a third resistor.

2. The capacitorless low-dropout linear regulator with a Class-AB output structure according to claim 1, characterized in that, The gates of the first PMOS transistor and the second PMOS transistor are connected to the negative feedback node. The gates of the third PMOS transistor and the fourth PMOS transistor are connected to the reference voltage. The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to the drain of the fifth PMOS transistor. The source of the fifth PMOS transistor is connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the first bias voltage.

3. The capacitorless low-dropout linear regulator with a Class-AB output structure according to claim 1, characterized in that, The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor, the source of the third NMOS transistor is grounded, the source of the second NMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is grounded, the gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the sixth NMOS transistor is grounded.

4. The capacitorless low-dropout linear regulator with Class-AB output structure according to claim 1, characterized in that, The sources of the sixth and seventh PMOS transistors are connected to the power supply voltage. The gates of the sixth and seventh PMOS transistors are connected. The drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the seventh NMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the eighth PMOS transistor is connected to the third bias voltage. The gate of the ninth PMOS transistor is connected to the third bias voltage. The gate of the seventh NMOS transistor is connected to the second bias voltage. The source of the seventh NMOS transistor is connected to the drains of the first and third PMOS transistors. The gate of the eighth NMOS transistor is connected to the second bias voltage. The source of the eighth NMOS transistor is connected to the drains of the fourth and sixth NMOS transistors.

5. The capacitorless low-dropout linear regulator with a Class-AB output structure according to claim 1, characterized in that, The source of the tenth PMOS transistor is connected to the power supply voltage, the gate of the tenth PMOS transistor is connected to the first bias voltage, the drain of the tenth PMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the ninth NMOS transistor is grounded. The source of the eleventh PMOS transistor is connected to the power supply voltage, the gate of the eleventh PMOS transistor is connected to the drain of the ninth PMOS transistor, and the drain of the eleventh PMOS transistor is connected to the drain of the tenth NMOS transistor. The first terminal of the first resistor is connected to the gate of the tenth NMOS transistor, the second terminal of the first resistor is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the drain of the tenth NMOS transistor, the first terminal of the second resistor is connected to the drain of the tenth NMOS transistor, the second terminal of the second resistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the source of the tenth NMOS transistor, the first terminal of the second capacitor is connected to the drain of the tenth NMOS transistor, and the second terminal of the second capacitor is connected to the source of the tenth NMOS transistor.

6. The capacitorless low-dropout linear regulator with a Class-AB output structure according to claim 1, characterized in that, The capacitorless low-dropout linear regulator with Class-AB output structure also includes: a bulk modulation error amplifier and a transient overshoot improvement circuit; The bulk modulation error amplifier includes: a twelfth PMOS transistor, a thirteenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; The transient overshoot improvement circuit includes: a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a third capacitor, and a fourth capacitor.

7. The capacitorless low-dropout linear regulator with a Class-AB output structure according to claim 6, characterized in that, The source of the twelfth PMOS transistor is connected to the power supply voltage, and the gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor. The source of the thirteenth PMOS transistor is connected to the power supply voltage, and the gate of the thirteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor. The drain of the thirteenth PMOS transistor is connected to the drain of the twelfth NMOS transistor. The drain of the twelfth PMOS transistor is connected to the drain of the eleventh NMOS transistor. The source of the eleventh NMOS transistor is connected to the drain of the thirteenth NMOS transistor. The source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor. The source of the thirteenth NMOS transistor is grounded.

8. The capacitorless low-dropout linear regulator with a Class-AB output structure according to claim 6, characterized in that, The source of the fourteenth PMOS transistor is connected to the power supply voltage. The gate of the fourteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor and the drain of the fifteenth PMOS transistor. The drain of the fourteenth PMOS transistor is connected to the source, gate, and gate of the sixteenth NMOS transistor. The drains of the sixteenth NMOS transistor and the fourteenth NMOS transistor are grounded. The source of the fifteenth PMOS transistor is connected to the power supply voltage. The gate of the fifteenth PMOS transistor is connected to the gate of the fifteenth NMOS transistor and the gate of the sixteenth PMOS transistor. The drain of the fifteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor. The source of the fifteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor. The source of the seventeenth NMOS transistor is grounded. The first terminal of the third capacitor is connected to the source of the fifteenth NMOS transistor and the drain of the seventeenth NMOS transistor. The drain is connected, the second terminal of the third capacitor is connected to the first terminal of the fourth capacitor, the second terminal of the fourth capacitor is connected to the drain of the sixteenth PMOS transistor and the source of the nineteenth PMOS transistor, the source of the sixteenth PMOS transistor is connected to the power supply voltage, the drain of the sixteenth PMOS transistor is connected to the source of the nineteenth PMOS transistor, the drain of the nineteenth PMOS transistor is connected to the drain of the eighteenth NMOS transistor and the gate of the nineteenth NMOS transistor, the source of the eighteenth NMOS transistor is grounded, the gate of the eighteenth NMOS transistor is connected to the gate of the seventeenth NMOS transistor and the gate of the nineteenth PMOS transistor, the source of the nineteenth NMOS transistor is grounded, the drain of the nineteenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor, the source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor are connected to the power supply voltage, and the gate of the seventeenth PMOS transistor and the gate of the eighteenth PMOS transistor are connected.

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