Clock control method of DAC time division multiplexing multichannel driving system in optical computing system

Abstract

The invention discloses a clock control method of a multi-channel driving system for DAC time division multiplexing in an optical computing system, which comprises the following steps: S101, acquiring a time interval from an edge moment when a control signal of a sampling control circuit jumps from an effective state to an invalid state to a stable holding state at an initial temperature; s102, acquiring the time interval of the DAC from the updating of the input data to the stabilization of the analog output voltage of the DAC; s103, target compensation delay needed by DAC input data is obtained, and the target compensation delay meets the requirement that after the control signal enters the invalid state, analog output of the DAC is kept stable and unchanged within the establishment keeping time; and S104, performing delay processing of target compensation delay on the input data of the DAC by using a delay circuit arranged at the input end of the DAC, and inputting the data into the DAC. According to the invention, DAC data updating and the working time sequence of the sampling hold circuit can be coordinated, and sampling errors caused by time sequence conflicts are avoided.

Description

Technical Field

[0001] This invention relates to the field of photonic computing technology, and in particular to a clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system. Background Technology

[0002] In AI computing, electronic chips play a crucial role in data transmission and computation. The entire process of artificial neural network algorithms involves a large number of matrix multiplication operations, which traditional computer architectures like CPUs struggle to handle, resulting in low computational efficiency. Therefore, academia and industry have turned their attention to new hardware architectures specifically designed for artificial neural networks and deep learning, such as GPUs, ASICs, and FPGAs. However, regardless of the architecture, all these technologies utilize traditional microelectronics techniques for design and manufacturing. Improving AI chip performance is inseparable from increasing microelectronic integration. However, in the early 21st century, microelectronics processes have struggled to keep pace with Moore's Law predictions, making it increasingly difficult to increase chip integration.

[0003] Compared to electrons, photons possess many unique properties: photons have no rest mass, there is no interaction force between photons, and there is almost no interference; different wavelengths of light can be used for simultaneous multi-channel communication, and photons can still achieve stable modulation and information transmission at modulation frequencies of tens of hertz, while electrical signals face radiation loss problems at high frequencies; furthermore, optical signals are not affected by electromagnetic fields, offering strong confidentiality. Even more uniquely, using certain optical structures, photons can perform mathematical operations with zero energy consumption. Therefore, photons can be used to achieve ultra-high-speed, low-energy, or even zero-energy computing, thereby breaking through the performance and cost bottlenecks of traditional microelectronic chips.

[0004] As the semiconductor industry gradually enters the post-Moore's Law era, the development of integrated circuits continues to evolve in different directions. On the one hand, new semiconductor materials are being developed, especially carbon nanotubes and two-dimensional semiconductor materials, to continue the essence of Moore's Law and further shrink the size of devices or chips, i.e., "More Moore"; on the other hand, new architectures and heterogeneous integrated chips are being developed for specific application areas, such as neuromorphic chips, optoelectronic chips, and quantum chips, to achieve "More than Moore".

[0005] Photonic chips based on silicon-based optoelectronic technology integrate micron- and nano-scale photonic, electronic, and optoelectronic devices onto a single silicon substrate using materials and processes compatible with integrated circuits. This achieves functional integration and complementary advantages between microelectronic and optoelectronic devices, resulting in high-performance optoelectronic chips. This is an effective way to address the performance bottlenecks and information congestion faced by traditional integrated circuits. Benefiting from the mature application of fiber optic communication, photons, as information carriers, have more multiplexing dimensions compared to electrons, such as amplitude, phase, wavelength, and mode, thus possessing greater bandwidth, faster speed, and lower energy consumption. Early silicon-based optoelectronic chips were developed to replace copper interconnect technology and solve the communication bottleneck between the processor core and memory of microelectronic chips. The microprocessor and memory units were implemented by microelectronic devices, while photonic devices mainly performed signal transmission and reception. With the increasing maturity of silicon photonics technology and the significant advantages of optical communication, attention to silicon photonic computing chips has gradually shifted from information transmission to information processing, including cutting-edge application areas such as analog computing, quantum computing, and neuromorphic computing.

[0006] In optical computing systems, to reduce the size and power consumption of photonic computing chips, it is necessary to simplify the components as much as possible. To this end, the applicant provides a method and system (CN202410825015.5) for sharing control of photonic computing chips and multi-photonic computing unit DACs in a hybrid optoelectronic computing system. This includes a photonic computing array composed of several photonic computing units; each photonic computing unit in the array is connected to the same DAC and shares the DAC to form a subarray, and the subarrays can operate in parallel; each photonic computing unit in the subarray can be switched on and off with its shared DAC, and the DAC can only form a path with one photonic computing unit at a time; each photonic computing unit in the same subarray is connected in series with the DAC, and the number of photonic computing units in the subarrays is inconsistent, resulting in subarrays containing different numbers of photonic computing units having different computing power.

[0007] The driving system of the time-division multiplexed DAC circuit is a key component for realizing multi-channel signal processing. In this system, the sample-and-hold circuit samples the analog voltage output by the DAC in a time-division manner, temporarily stores the voltage signal on a capacitor, and then drives an external load via the driving circuit, thereby realizing the orderly processing and transmission of multi-channel signals.

[0008] However, in actual circuit operation, due to inherent circuit delay characteristics and amplifier response time, timing mismatches may occur during the sampling process of the sample-and-hold circuit. Specifically, the sample-and-hold circuit is driven by the control signal `en_sh`. When `en_sh` is active (usually high), the corresponding channel is selected, and the circuit samples accordingly. When `en_sh` transitions from high to low (i.e., the active state ends), the circuit enters the hold phase, locking the sampled voltage onto the capacitor. If the DAC's input data has been updated before `en_sh` ends its active state (i.e., before the high-to-low transition is complete), meaning the DAC's output voltage `dac_out` has changed, and the currently selected channel is still active, the corresponding sample-and-hold circuit will incorrectly acquire the updated voltage signal instead of the expected stable voltage.

[0009] like Figure 1 As shown, in the incorrect timing scenario, when the control signal en_sh [3] changes from high level to low level, the output voltage dac_out of the DAC has changed due to data update, causing the sample-and-hold circuit of the corresponding channel to collect the wrong voltage, which seriously affects the accuracy of subsequent signal processing and thus restricts the overall performance of the optical computing system, such as the calculation accuracy. Summary of the Invention

[0010] The purpose of this invention is to provide a clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system, which partially solves or alleviates the above-mentioned deficiencies in the prior art, can coordinate the working timing of DAC data update and sample-and-hold circuit, avoid sampling errors caused by timing conflicts or reduce the probability of sampling errors to a certain extent.

[0011] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide a clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system, comprising: S101 acquires the time interval from the moment the control signal of the sampling control circuit transitions from the active state to the inactive state at the initial temperature (e.g., room temperature) to when it enters the stable holding state, denoted as the holding setup time T. _SH_hold ; S102 obtains the time interval from the DAC updating its input data to the stabilization of its analog output voltage, denoted as the DAC delay time T. _DAC_latency ; S103 is based on maintaining setup time T _SH_hold and DAC delay time T _DAC_latencyThe target compensation delay T required to acquire DAC input data delay The target compensation delay satisfies the condition that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold-up time. S104 uses a delay circuit located at the DAC input terminal to perform target compensation delay T on the DAC input data. delay The input to the DAC is after the delay processing.

[0012] Furthermore, based on the establishment time T _SH_hold and DAC delay time T _DAC_latency The target compensation delay T required to acquire DAC input data delay The steps include using the formula: T delay = T _DAC_latency -T _SH_hold +T margin , Calculate the target compensation delay; where T delay To compensate for the delay in the target, T _DAC_latency T is the DAC delay time. _SH_hold To maintain setup time, T margin For safety margin.

[0013] Furthermore, the safety margin T margin To maintain the setup time T _SH_hold 10% to 20%.

[0014] Furthermore, it also includes: S201 uses the delay circuit to perform target compensation delay T on the test data. delay The input to the DAC is processed with a delay; S202 acquires the transition edge of the control signal and the analog output waveform of the DAC; After S203 determines that the control signal has entered an invalid state, the analog output of the DAC during the hold-up time T _SH_hold Does it contain any jumps? S204 uses the target compensation delay as the initial compensation delay in the absence of a jump.

[0015] Furthermore, it also includes: S205 acquires the time interval Δt between the moment when the control signal enters an invalid state and the moment when the DAC analog output jumps in the case of a transition; S206 uses the time interval Δt to adjust the safety margin T margin The correction is made so that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold setup time.

[0016] Furthermore, the safety margin T is calculated using the time interval Δt. margin The steps for making the correction include using the formula: T margin '=k*(T margin +Δt), Adjust the safety margin; where T margin 'T is the corrected safety margin.' margin For safety margin, Δt is the time interval, k is the correction coefficient, and k∈(1,1.1]; Using the formula: T delay = T _DAC_latency -T _SH_hold +T margin ' , Calculate the target compensation delay; where T delay To compensate for the delay in the target, T _DAC_latency T is the DAC delay time. _SH_hold To maintain setup time, T margin 'This is the corrected safety margin.'

[0017] Furthermore, it also includes: S301 acquires the time interval between the edge of the control signal of the sampling control circuit transitioning from the active state to the inactive state at N different temperatures, and the time interval between that transition and the entry into the stable holding state, denoted as the i-th holding setup time T. _SH_hold（i） where i = 1 ~ N; S302 obtains the time interval from the update of the input data to the stabilization of its analog output voltage of the DAC, denoted as the i-th DAC delay time T. _DAC_latency（i） where i = 1 ~ N; The S303 acquires the target compensation delay T required to obtain N DAC input data based on N hold-up times and N delay times. delay（i） Where i = 1 to N; and N targets are used to compensate for the delay T. delay（i） Construct a delay-temperature change curve and calculate the temperature compensation coefficient α using linear regression. S304 When the temperature change is detected to exceed the preset threshold, temperature compensation is performed on the target compensation delay based on the temperature compensation coefficient α.

[0018] Furthermore, the temperature interval between the N different temperatures is 0.5℃-1℃.

[0019] Furthermore, the step of performing temperature compensation on the target compensation delay based on the temperature compensation coefficient α includes using the formula: T delay=[1+α*(T-T0)]*T delay , Temperature compensation is applied to the target compensation delay; where T delay ' represents the target compensation delay after temperature compensation, T is the current temperature monitored in real time, T0 is the initial temperature, and α is the delay temperature compensation coefficient.' delay To compensate for the delay in achieving the goal.

[0020] Furthermore, the optical computing system includes multiple DACs, with each channel using a sample-and-hold circuit to time-multiplex one DAC; the clock control method further includes: S401 clusters the DACs, resulting in several groups; S402 takes the maximum target compensation delay among the groups as the baseline compensation delay for that group, and optimizes the baseline compensation delay using the maximum temperature compensation coefficient among them to obtain the common target compensation delay for the group: T delay-group =[1+α max *(T -T0)]*T delay_max ; Among them, T delay-group To compensate for the delay of the shared target for the group, α max T is the maximum temperature compensation coefficient within this group. delay_max The maximum target compensation delay within this group is T, where T is the current temperature as monitored in real time, and T0 is the initial temperature.

[0021] Furthermore, the k-means clustering algorithm is used to cluster the DAC based on the target compensation delay and the temperature compensation coefficient.

[0022] Beneficial effects: This invention maintains the setup time T by defining key parameters. _SH_hold DAC delay time T _DAC_latency And based on formula T delay = T _DAC_latency - T _SH_hold + T margin Calculating the target compensation delay transforms the abstract requirement of avoiding sampling errors into measurable and calculable engineering parameters. This eliminates the ambiguity of traditional empirical timing adjustments, ensuring precise timing matching between the DAC output and the sample-and-hold circuit from the design stage, laying the foundation for fundamental system reliability.

[0023] Through a verification-correction mechanism, the theoretically calculated T is first verified using test data. delay If a jump in the DAC output is detected during the hold-up time, the quantization deviation is adjusted by Δt, and the safety margin is corrected, forming a closed loop of calculation-verification-correction-re-verification. This effectively compensates for the difference between theoretical calculations and the characteristics of the actual circuit, ensuring T...delay It is truly effective at the hardware level, significantly improving the method's adaptability to hardware characteristics.

[0024] To address the temperature drift issue in optical computing systems, this invention constructs a "delay-temperature change curve" and obtains a temperature compensation coefficient α based on linear regression, enabling dynamic delay adjustment in response to temperature changes. This ensures that the timing relationship between the DAC output and the sample-and-hold circuit always meets constraints over a wide temperature range, avoiding timing misalignments caused by temperature.

[0025] For multi-DAC time-division multiplexing scenarios, this invention employs the k-means clustering algorithm to group DACs with similar target compensation delays and temperature coefficients together, calculating the shared delay of the group based on the maximum delay and maximum temperature coefficient. This principle ensures the timing safety of all DACs within a group while reducing the number of parameters to be managed from one per DAC to one per group, significantly reducing system control complexity and real-time computational pressure (especially when the temperature interval is set small to ensure accuracy, greatly reducing testing pressure), thus balancing reliability and efficiency in multi-channel scenarios.

[0026] Safety margin T in this invention margin The value of and the range of the correction coefficient k achieve a balance between covering uncertainty and avoiding excessive delay. This approach addresses potential risks such as measurement errors and circuit noise with a margin, while avoiding excessive delays in DAC output updates due to an excessively large margin, thus ensuring the system's response speed and meeting the dual requirements of high speed and high reliability for optical computing systems. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0028] Figure 1 This is a diagram illustrating the disordered timing sequence. Figure 2 This is a flowchart of Embodiment 3 of the present invention; Figure 3 A schematic diagram of the correct timing; Figure 4 This is a schematic diagram of the structure of Embodiment 1; Figure 5 This is a schematic diagram of the structure of Example 2; Detailed Implementation To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0029] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0030] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0033] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0034] Example 1: like Figure 4 As shown, this embodiment provides a multi-channel driving system for time-division multiplexing of DACs in an optical computing system, including: A clock control circuit (not shown in the figure) is used to generate a clock signal ck, which includes alternating high and low levels. As the system timing reference source, the clock control circuit generates a periodically alternating high and low level clock signal ck, providing a unified timing rhythm for the entire drive system. All circuit modules, such as data circuit registers, selection circuit registers, decoders, DACs, etc., operate synchronously based on this clock, ensuring timing consistency for multi-module collaborative operation.

[0035] A data circuit is connected to the output of the clock control circuit. The data circuit includes a DAC (Digital Converter), and the output of the DAC is connected to multiple data channels via a switch matrix. Each data channel includes a sample-and-hold circuit and a driver circuit (Drv).

[0036] Data circuit registers (such as) Figure 4 The D flip-flop on the data circuit latches 8-bit data signals bin[7:0] (the specific number of bits can be adjusted according to actual needs), and updates the output synchronously on the rising edge of the clock signal ck, providing a stable and synchronous digital input for the DAC and avoiding asynchronous data transitions from interfering with DAC conversion.

[0037] The DAC receives digital data output from the register output Q of the data receiving circuit and converts it into an analog voltage dac_out. It is the core module of the system's digital-to-analog signal conversion. Its conversion accuracy is determined by the bit width of the data signal bin, and the conversion speed directly affects the quality of the output analog signal, requiring precise timing matching with the sample-and-hold circuit.

[0038] The DAC output is connected to multiple data channels via a switch matrix. Each channel includes a sample-and-hold circuit (not shown in the diagram) to control analog signal acquisition and holding, and a driver circuit (Drv) to enhance signal driving capability. The switch matrix enables time-division multiplexing, allowing a single DAC to provide analog signals to multiple channels, achieving resource multiplexing.

[0039] The selection circuit is connected to the output of the clock control circuit. The selection circuit is equipped with a decoder, and the output of the decoder is connected to the control terminal of each switch in the switch matrix.

[0040] Select circuit register (e.g.) Figure 4 The D flip-flop on the selection circuit latches the 4-bit selection signal sel_sh[3:0], which is synchronized with the data circuit register and triggered by the clock signal ck to ensure that the data update is aligned with the channel selection timing.

[0041] The decoder receives the selection signal sel_sh[3:0] and decodes it to generate a 16-bit enable signal (or control signal) en_sh[15:0] corresponding to 16 data channels (it can be understood that the number of channels can be set according to actual needs, and there is no limit in this embodiment), realizing the mapping of one selection signal controlling one channel enable, and determining which channel's switch is turned on to turn on the DAC output.

[0042] Example 2: like Figure 5 As shown, this application also provides another multi-channel driving system for time-division multiplexing of DAC in an optical computing system, which includes the components described in Embodiment 1 above. However, unlike Embodiment 1, this embodiment has a delay circuit connected to the data circuit. The delay circuit can delay the input data bin of the DAC before inputting it to the data circuit register and the DAC, so that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold-up time.

[0043] Example 3: like Figure 2 As shown, this embodiment provides a clock control method applied to a multi-channel drive system with time-division multiplexing of DAC in the optical computing system of Embodiment 2. The specific steps include: S101 acquires the time interval from the moment the control signal of the sampling control circuit transitions from the active state to the inactive state at the initial temperature (e.g., room temperature) to when it enters the stable holding state, denoted as the holding setup time T. _SH_hold .

[0044] The sampling control circuit controls the sampling process. Its valid state, such as `en_sh` high level, selects a channel to connect to the DAC output, allowing that channel to acquire the latest analog voltage. Its invalid state, such as `en_sh` low level, disconnects the channel from the DAC output, entering hold mode. This requires the latched voltage to remain stable; otherwise, voltage fluctuations will cause input errors to the subsequent optical computing module.

[0045] Ideally, the transition from an active state to an inactive state should be instantaneous, meaning a rapid shift from a high level to a low level. However, due to factors such as link delay, such as... Figure 1 The transition between the high and low levels of the enable signal en_sh[3] has a gradual slope, and the time taken for this slope is called the "time interval from the edge moment when the control signal transitions from the effective state to the ineffective state to when it enters the stable holding state".

[0046] Optical computing systems are generally quite sensitive to temperature, therefore maintaining a settling time T is important. _SH_holdIt is not static; it will drift with temperature. Additionally, maintain the setup time T. _SH_hold It cannot be measured in practice and can only be obtained through simulation.

[0047] S102 obtains the time interval from the DAC updating its input data to the stabilization of its analog output voltage, denoted as the DAC delay time T. _DAC_latency .

[0048] The core function of a DAC is to convert the digital input bin[7:0] into an analog output dac_out. However, this process is not instantaneous; there is a timing delay. The delay begins at the moment the DAC input data is updated, such as the ck edge of the register that latches the new data; the delay ends when the DAC output voltage reaches a stable value. The DAC delay time T is... _DAC_latency That is, the time interval between the two moments mentioned above, which is the total delay for the DAC to complete one digital-to-analog conversion and output stably.

[0049] Simply put, T _DAC_latency This describes the complete response time of the DAC from receiving a new digital instruction to outputting a valid analog voltage.

[0050] Similarly, the DAC delay time cannot be actually measured in the circuit and can only be obtained through simulation.

[0051] S103 is based on maintaining setup time T _SH_hold and DAC delay time T _DAC_latency The target compensation delay T required to acquire DAC input data delay The target compensation delay satisfies the condition that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold setup time.

[0052] In the DAC time-division multiplexing multi-channel drive system provided in Example 1, there may be a timing conflict: the control signal en_sh enters an invalid state, such as a high-to-low transition, before entering a hold state, that is, it needs to go through T... _SH_hold It takes time for the voltage to stabilize. If the DAC output changes abruptly during this period, it will lead to sampling errors.

[0053] In this step, by delaying the update time of the DAC input data, the DAC output stabilization time is allowed to cover the hold-up setup phase of the sample-and-hold circuit. See [link / reference]. Figure 3 This ensures that the DAC does not update its data before sampling.

[0054] More specifically, based on the establishment time T _SH_hold and DAC delay time T _DAC_latency The target compensation delay T required to acquire DAC input data delayThe steps include using the formula: T delay = T _DAC_latency -T _SH_hold +T margin , Calculate the target compensation delay; where T delay To compensate for the delay in the target, T _DAC_latency T is the DAC delay time. _SH_hold To maintain setup time, T margin For safety margin.

[0055] Safety margin T margin Used to cover uncertainties such as process deviations and temperature drift. Its value range is generally the hold-up time T. _SH_hold The percentage is 10% to 20%, which is set by the engineer based on the actual situation.

[0056] Through T _DAC_latency and T _SH_hold The quantization circuit has an inherent delay; use T margin Covering engineering uncertainties; ultimately calculating T delay This ensures that the timing of the DAC output is precisely matched with that of the sample-and-hold circuit.

[0057] S104 uses a delay circuit located at the DAC input terminal to perform target compensation delay T on the DAC input data. delay The input to the DAC is after the delay processing.

[0058] The delay circuit is located at the input of the DAC and directly affects the DAC's input data bin[7:0]. After receiving the raw input data, the circuit design delays the data transmission by T. delay The data is then fed into the DAC for digital-to-analog conversion. By delaying the data input time, the update time of the DAC output voltage is indirectly delayed. The update of the DAC output dac_out depends on the input data, and the input delay is synchronously transmitted to the output.

[0059] DAC input data via T delay After the delay, ensure that the value only changes after the en_sh signal ends and the sampling and holding circuit stabilizes to avoid sampling errors. Figure 3 As shown.

[0060] Target compensation delay T delay While theoretically it can cover the delay and achieve accurate sampling, due to uncertainties in practice, some embodiments still require adjustment of T. delay Further verification and adjustments will be made, including: S201 uses the delay circuit to perform target compensation delay T on the test data. delayThe input to the DAC is after the delay processing.

[0061] The preset test data is input into the delay circuit at the input of the DAC, and the target compensation delay T calculated in step S103 is applied to the test data through this circuit. delay The delayed test data is then sent to the DAC. By applying a Tf to the test data... delay This simulates the delay scenario of DAC input data in a real system, providing a basis for subsequent verification of T. delay The effectiveness provides an observable source of signal.

[0062] S202 acquires the transition edge of the control signal and the analog output waveform of the DAC.

[0063] The transition edge of the control signal is the moment when the control signal en_sh of the sample-and-hold circuit transitions from an active state (e.g., high level) to an inactive state (e.g., low level). Record the change of the DAC output voltage over time, especially the complete process of dac_out transitioning from the old value to the new value after the test data is input.

[0064] After S203 determines that the control signal has entered an invalid state, the analog output of the DAC during the hold-up time T _SH_hold Does it have any jumps?

[0065] Starting from the moment when the control signal en_sh enters the invalid state, a time interval of T is extracted. _SH_hold The key window; observe whether the DAC output waveform dac_out shows any jumps within this window.

[0066] S204 uses the target compensation delay as the initial compensation delay in the absence of a jump.

[0067] If it is determined that there is no jump, it indicates that the target compensation delay T delay It can effectively coordinate the timing of the DAC output and the sample-and-hold circuit, ensuring that the sample-and-hold circuit does not sample incorrect voltages. Therefore, this T... delay The initial compensation delay was officially determined and used as the benchmark parameter for actual system operation. Real-world scenarios were simulated using test data, real-time timing was captured through waveform acquisition, and the delay effect was verified through timing analysis. Ultimately, T was confirmed. delay The effectiveness; S205 acquires the time interval Δt between the moment when the control signal enters an invalid state and the moment when the DAC analog output changes during a transition.

[0068] When a transition is detected, it is necessary to accurately capture two key timing nodes: First, the moment t when the control signal en_sh transitions from an active state to an inactive state. _dac_jumpThe second DAC analog output, dac_out, begins to transition from the old voltage value to the new voltage value at time t. _en_sh_end The time interval between the two is defined as Δt = t _en_sh_end -t _dac_jump .

[0069] A positive Δt indicates that the DAC output transition occurs before the control signal enters an invalid state, representing a more severe timing misalignment, essentially a target compensation delay T. delay If the value is too small, the DAC output will update too early. This indicates that the current T... delay If the set timing constraints are not met, the degree of deviation needs to be quantified using Δt.

[0070] S206 uses the time interval Δt to adjust the safety margin T margin The correction is made so that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold setup time.

[0071] More specifically, using the formula: T margin '=k*(T margin +Δt), Adjust the safety margin; where T margin 'T is the corrected safety margin.' margin For safety margin, Δt is the time interval, k is the correction coefficient, and k∈(1,1.1]; When the DAC output changes within the setup time, it essentially represents the original safety margin T. margin The timing deviations of actual circuits, such as manufacturing process errors and amplifier response delays that are larger than theoretical values, are not fully covered. (Through T...) margin +Δt adds the original safety margin to the actual measurement deviation Δt to form the basic correction amount, which directly compensates for the detected timing misalignment, so that the clock signal and DAC signal are aligned, that is, the data update occurs exactly when sampling, so further compensation is still needed.

[0072] In this step, a correction coefficient k is set to further delay the DAC signal, ensuring that the corrected safety margin is sufficient to cover the actual scenario, and allowing the DAC signal to be updated after sampling.

[0073] Using the formula: T delay = T _DAC_latency -T _SH_hold +T margin ' , Calculate the target compensation delay; where T delay To compensate for the delay in the target, T _DAC_latency T is the DAC delay time. _SH_holdTo maintain setup time, T margin 'This is the corrected safety margin.'

[0074] Corrected safety margin T margin Substituting into the target compensation delay formula, the final update T is obtained. delay By extending the delay time of the DAC input data, the update time of the DAC output is indirectly delayed.

[0075] Since temperature changes can cause timing characteristics of circuits to drift, some embodiments can also perform dynamic temperature compensation. This involves collecting key parameters at different temperatures, establishing a temperature-delay relationship model, and ultimately achieving real-time timing calibration during temperature fluctuations to ensure that the sample-and-hold circuit always acquires the correct voltage. The specific steps include: S301 acquires the time interval between the edge of the control signal of the sampling control circuit transitioning from the active state to the inactive state at N different temperatures, and the time interval between that transition and the entry into the stable holding state, denoted as the i-th holding setup time T. _SH_hold（i） , where i = 1 - N.

[0076] At N preset temperature points, such as 5℃, 10℃, 15℃, 20℃, 25℃...60℃, covering the system's operating temperature range, the hold-up time of the sampling control circuit is collected for each temperature point.

[0077] In other embodiments, to improve accuracy, the temperature interval between N different temperature points is 0.5℃-1℃. Compared to setting the temperature interval to 5℃, the testing pressure and computational load will be further increased. Therefore, to further reduce the pressure, this application subsequently groups the data and clusters those with the same or similar temperature response characteristics and the same or similar timing characteristics (i.e., similar delays). This clustering can transform these similarities into uniformly manageable groups, laying the foundation for simplified control in the future.

[0078] The characteristics of core components in a sample-and-hold circuit, such as capacitors and operational amplifiers, are significantly affected by temperature. As temperature rises, capacitor leakage increases, amplifier bandwidth decreases, and this may lead to temperature fluctuations (T0). _SH_hold Extended; as temperature decreases, the device response speed slows down, which may also change T. _SH_hold This step captures T by measuring at multiple temperature points. _SH_hold The pattern of temperature variation provides basic data for subsequent compensation.

[0079] S302 obtains the time interval from the update of the input data to the stabilization of its analog output voltage of the DAC, denoted as the i-th DAC delay time T. _DAC_latency（i） , where i = 1 ~ N.

[0080] At the same N temperature points as in step S301, the delay time of the DAC is collected respectively.

[0081] The digital-to-analog conversion process of a DAC is also affected by temperature. Increased temperature leads to a decrease in carrier mobility in semiconductor devices, slowing down switching speed and potentially causing T... _DAC_latency The temperature fluctuations also affect the accuracy of resistors and capacitors, indirectly altering the conversion delay. This step corresponds to S301, synchronously acquiring data on the relationship between temperature and DAC delay time to ensure that the target compensation delay calculated subsequently can cover the timing characteristics across the entire temperature range.

[0082] The S303 acquires the target compensation delay T required to obtain N DAC input data based on N hold-up times and N delay times. delay（i） Where i = 1 to N; and N targets are used to compensate for the delay T. delay（i） Construct a delay-temperature change curve and calculate the temperature compensation coefficient α using linear regression.

[0083] Based on the data collected in steps S301 and S302, the following formula is used: T delay（i） = T _DAC_latency（i） -T _SH_hold（i） + T margin , Calculate the target compensation delay for each temperature point; where T delay（i） For the delay compensation of the i-th target.

[0084] With temperature as the horizontal axis, T delay（i） Plot the delay-temperature change curve with the vertical axis as the ordinate, and then fit the curve using a linear regression algorithm to obtain the description of T. delay Linear relationship with temperature: T delay（T） = α*T + b, where α is the temperature compensation coefficient, reflecting the temperature change caused by a unit temperature change in T. delay The change is T, where T is the current temperature as monitored in real time, and b is the drift. delay（T） The temperature function is used for target delay compensation.

[0085] Temperature changes will simultaneously alter T _SH_hold and T _DAC_latency This leads to a delay of T in the target compensation process. delay It fluctuates with temperature. α is obtained through linear regression, which correlates temperature change with T. delay Adjusting the quantities establishes a quantitative relationship, providing a mathematical model for subsequent real-time compensation; that is, "knowing how much the temperature changes, we can calculate T." delay How much adjustment is needed?

[0086] S304 When a temperature change exceeding a preset threshold is detected, temperature compensation is performed on the target compensation delay based on the temperature compensation coefficient α. Specifically, the formula is: T delay =[1+α*(T-T0)]*T delay , Temperature compensation is applied to the target compensation delay; where T delay ' represents the target compensation delay after temperature compensation, T is the current temperature monitored in real time, T0 is the initial temperature, and α is the delay temperature compensation coefficient.' delay To compensate for the delay in achieving the goal.

[0087] The system monitors the current temperature T in real time; when the difference between the current temperature and the initial temperature exceeds a preset threshold, such as ±5℃, the target compensation delay is updated. The updated T... delay A delay circuit applied to the input of a DAC to adjust the delay time of the DAC input data.

[0088] Since the optical computing system includes multiple DACs, each channel uses a sample-and-hold circuit to time-multiplex one DAC. If a separate delay circuit were set up for each DAC for compensation, the entire system would be very bloated. Therefore, this invention uses a grouped delay method to simplify the system. Specifically, the clock control method further includes: S401 clusters the DACs, resulting in several groups.

[0089] In a multi-DAC system, due to process variations, layout differences, and varying degrees of device aging, the TV of each DAC will differ. delay（i） and α （i） There are inherent differences. However, DACs with similar characteristics often have similar timing requirements and temperature response patterns. Clustering can transform these similarities into uniformly manageable groups, laying the foundation for subsequent simplified control.

[0090] This embodiment employs the k-means clustering algorithm, using the key characteristic parameters of each DAC as the clustering basis to divide the multiple DACs in the system into several groups. Key parameters include the target compensation delay T. delay（i） and temperature compensation coefficient α （i） During the clustering process, the algorithm will group T... delay（i） Similar and α （i） Similar DACs are grouped together, resulting in multiple groups with homogeneous characteristics.

[0091] Of course, in other embodiments, T may also be used. delay（i） The difference is less than the preset difference threshold, and α （i） Multiple DACs with a difference less than a preset difference threshold are grouped together.

[0092] S402 takes the maximum target compensation delay among the groups as the baseline compensation delay for that group, and optimizes the baseline compensation delay using the maximum temperature compensation coefficient among them to obtain the common target compensation delay for the group: T delay-group =[1+α max *(T -T0)]*T delay_max ; Among them, T delay-group To compensate for the delay of the shared target for the group, α max T is the maximum temperature compensation coefficient within this group. delay_max The maximum target compensation delay within this group is T, where T is the current temperature as monitored in real time, and T0 is the initial temperature (e.g., room temperature).

[0093] In this step, the baseline compensation delay is first determined: the maximum value T among the target compensation delays of all DACs in the group is selected. delay_max As a baseline, ensure coverage of the DAC with the longest latency requirement within the group. Then, combine this with temperature compensation factor optimization, selecting the largest temperature compensation factor α within the group. max The formula is used to calculate the shared target compensation delay for the group.

[0094] Some DACs within the group may require shorter delays, but the maximum delay ensures that even the most delay-sensitive DACs, requiring the longest possible delay to meet timing requirements, can still update their outputs after the sample-and-hold circuit stabilizes, avoiding sampling errors caused by insufficient delays in individual DACs. Some DACs within the group are less sensitive to temperature (α is small), but the maximum α covers the most temperature-sensitive DACs, ensuring that even the most temperature-affected DACs have their compensation delays adequately adjusted to avoid timing misalignments due to temperature drift.

[0095] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0097] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system, characterized in that... include: S101 acquires the time interval from the edge of the control signal of the sampling control circuit transitioning from the active state to the inactive state at the initial temperature, to the time it enters the stable holding state, denoted as the holding setup time T. _SH_hold ; In the S102 data acquisition circuit, the time interval between the DAC updating its input data and the stabilization of its analog output voltage is denoted as the DAC delay time T. _DAC_latency ; S103 is based on maintaining the setup time T _SH_hold and DAC delay time T _DAC_latency The target compensation delay T required to acquire DAC input data delay The target compensation delay satisfies the condition that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold-up time. S104 uses a delay circuit located at the DAC input terminal to perform target compensation delay T on the DAC input data. delay The input to the DAC is after the delay processing.

2. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 1, characterized in that... Based on the establishment time T _SH_hold and DAC delay time T _DAC_latency The target compensation delay T required to acquire DAC input data delay The steps include using the formula: T delay = T _DAC_latency -T _SH_hold +T margin , Calculate the target compensation delay; where T delay To compensate for the delay in the target, T _DAC_latency T is the DAC delay time. _SH_hold To maintain setup time, T margin For safety margin.

3. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 2, characterized in that... Also includes: S201 uses the delay circuit to perform target compensation delay T on the test data. delay The input to the DAC is processed with a delay; S202 acquires the transition edge of the control signal and the analog output waveform of the DAC; After S203 determines that the control signal has entered an invalid state, the analog output of the DAC during the hold-up time T _SH_hold Does it contain any jumps? S204 uses the target compensation delay as the initial compensation delay in the absence of a jump.

4. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 3, characterized in that... Also includes: S205 acquires the time interval Δt between the moment when the control signal enters an invalid state and the moment when the DAC analog output jumps in the case of a transition; S206 uses the time interval Δt to adjust the safety margin T margin The correction is made so that when the control signal enters an invalid state, the analog output of the DAC remains stable during the hold setup time.

5. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 4, characterized in that... Using the time interval Δt to measure the safety margin T margin The steps for making the correction include using the formula: T margin ’=k*(T margin +Δt) , Adjust the safety margin; where T margin 'T is the corrected safety margin.' margin For safety margin, Δt is the time interval, k is the correction coefficient, and k∈(1,1.1]; Using the formula: T delay = T _DAC_latency -T _SH_hold +T margin ’ , Calculate the target compensation delay; where T delay To compensate for the delay in the target, T _DAC_latency T is the DAC delay time. _SH_hold To maintain setup time, T margin 'This is the corrected safety margin.' 6. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 2, characterized in that... Also includes: S301 acquires the time interval between the edge of the control signal of the sampling control circuit transitioning from the active state to the inactive state at N different temperatures, and the time interval between that transition and the entry into the stable holding state, denoted as the i-th holding setup time T. _SH_hold（i） where i = 1 ~ N; S302 obtains the time interval from the update of the input data to the stabilization of its analog output voltage of the DAC, denoted as the i-th DAC delay time T. _DAC_latency（i） where i = 1 ~ N; The S303 acquires the target compensation delay T required to obtain N DAC input data based on N hold-up times and N delay times. delay（i） Where i = 1 to N; and N targets are used to compensate for the delay T. delay（i） Construct a delay-temperature change curve and calculate the temperature compensation coefficient α using linear regression. S304 When the temperature change is detected to exceed the preset threshold, temperature compensation is performed on the target compensation delay based on the temperature compensation coefficient α.

7. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 6, characterized in that... The temperature interval between N different temperatures is 0.5℃-1℃.

8. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 6, characterized in that... The step of performing temperature compensation on the target compensation delay based on the temperature compensation coefficient α includes using the formula: T delay ’=[1+α*(T-T0)]*T delay , Temperature compensation is applied to the target compensation delay; where T delay ' represents the target compensation delay after temperature compensation, T is the current temperature monitored in real time, T0 is the initial temperature, and α is the delay temperature compensation coefficient.' delay To compensate for the delay in achieving the goal.

9. A clock control method for a multi-channel drive system with time-division multiplexing of a DAC in an optical computing system according to any one of claims 6 to 8, characterized in that... The optical computing system includes multiple DACs, and each group of channels uses one DAC in a time-division multiplexing manner through a set of sample-and-hold circuits; The clock control method further includes: S401 clusters the DACs, resulting in several groups; S402 takes the maximum target compensation delay among the groups as the baseline compensation delay for that group, and optimizes the baseline compensation delay using the maximum temperature compensation coefficient among them to obtain the common target compensation delay for the group: T delay-group =[1+α max *(T -T0)]*T delay_max ; Among them, T delay-group To compensate for the delay of the shared target for the group, α max T is the maximum temperature compensation coefficient within this group. delay_max The maximum target compensation delay within this group is T, where T is the current temperature as monitored in real time, and T0 is the initial temperature.

10. The clock control method for a multi-channel drive system with time-division multiplexing of DAC in an optical computing system according to claim 9, characterized in that: The k-means clustering algorithm is used to cluster the DAC based on the target compensation delay and the temperature compensation coefficient.

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