Method for analyzing worst-case execution time of tasks in multi-core real-time system sharing cache

Abstract

The application discloses a multi-core real-time system task worst execution time analysis method considering shared cache, and relates to the technical field of computer systems, and the method comprises the following steps: generating memory references of each memory block; wherein the memory references comprise the addresses, access times and ages of the corresponding memory blocks; modeling the ordered contention regions based on the memory references; determining the cache miss numbers generated by the system task accessing the contention regions; and analyzing the worst case execution time of the system task according to the cache miss numbers. The application proposes a fine cross-core cache interference analysis scheme by constructing a contention region sequence, combining the access times of the memory references and the age information of the cache blocks, and utilizing dynamic programming to construct a worst path analysis process under the partial order constraint of the program regions, so that the structural property and the accuracy of the analysis are significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer systems, and particularly to a worst-case execution time analysis method for multi-core real-time system tasks considering shared cache. BACKGROUND

[0002] In a multi-core real-time system, multiple tasks are usually assigned to different processing cores for parallel execution, and these cores often use shared cache. Although shared cache can improve resource utilization to a certain extent, it also introduces serious inter-core cache contention problem, that is, when multiple tasks are executed in parallel, the data accessed by each other may be mapped to the same cache set, causing cache block eviction, thus generating cache miss and increasing the worst-case execution time (WCET).

[0003] Traditional WCET analysis mainly focuses on cache behavior modeling in single-core systems, and analysis methods include Must / May analysis, persistence analysis, etc. These methods can accurately capture cache hits and misses of tasks on their own execution paths and provide accurate execution time upper bound for single-core scenarios. However, when tasks are deployed in a multi-core system, the traditional method cannot accurately capture the cache state changes caused by the cache access of other tasks, and thus cannot effectively evaluate the worst-case delay under shared cache. SUMMARY

[0004] Therefore, embodiments of the present application provide a worst-case execution time analysis method for multi-core real-time system tasks considering shared cache and related devices to improve the accuracy of worst-case execution time analysis.

[0005] An aspect of an embodiment of the present application provides a worst-case execution time analysis method for multi-core real-time system tasks considering shared cache, which includes the following steps:

[0006] generating memory references of each memory block; wherein the memory references include addresses, access times and ages corresponding to the memory blocks;

[0007] modeling to obtain ordered contention regions based on each memory reference;

[0008] determining the number of cache misses generated by system task access to the contention regions;

[0009] analyzing the worst-case execution time of the system task according to the number of cache misses.

[0010] In some embodiments, the generating memory references of each memory block includes the following steps:

[0011] record the address of each memory block in the same out-of-order program area; define the access times of each memory block as 1; define the value of the age of each memory block as the number of different addresses accessed in the cache since the last access of the memory block; if the memory block has never appeared, define the corresponding age as infinite;

[0012] define the address, the access times and the age as the memory reference of the memory block;

[0013] if the memory block is in multiple out-of-order program areas, calculate the cumulative access times for each out-of-order program area where the memory block is located;

[0014] the cumulative access times are:

[0015] ;

[0016] wherein, is the cumulative access times;

[0017] if , generate a new memory reference according to the cumulative access times.

[0018] In some embodiments, modeling an ordered contention area based on each memory reference comprises the following steps:

[0019] Let and represent the index of the first and the last of the out-of-order program area sequence accessed by the remote task that affects the memory reference ;

[0020] construct a range according to the partition expression;

[0021] the partition expression is:

[0022] ;

[0023] wherein, the function returns the index of the UR containing the memory reference after the address of the last access of the memory block ;

[0024] for , the age of the block in and is less than the cache correlation degree organize into a contention area;

[0025] for each out-of-order program area of the execution path of the local task ​The above analysis ultimately forms a complete sequence of contested areas.

[0026] In some embodiments, determining the number of cache misses generated when a system task accesses the contention region includes the following steps:

[0027] Determine the first number of cache misses resulting from a remote task accessing the contentious region;

[0028] Determine the number of second cache misses resulting from local tasks accessing the contentious region;

[0029] The step of analyzing the worst-case execution time of the system task based on the number of cache misses includes the following steps:

[0030] Analyze the first worst-case execution time of the remote task based on the first cache miss count;

[0031] The second worst-case execution time of the local task is analyzed based on the number of cache misses.

[0032] In some embodiments, determining the first number of cache misses resulting from a remote task accessing the contention region includes the following steps:

[0033] Set eviction threshold ,in The age of the memory block, used to indicate if the remote task access hits. If each address is distinct, a local block is evicted once; for an unordered sequence of interfering tasks, remote task access within a single unordered program region is modeled as a queue. ,queue The elements within represent the number of times different addresses were accessed, and are sorted in descending order of the number of accesses;

[0034] The procedure for performing block evicting is as follows: when a single out-of-order program region in the interfering task... Use queues when remotely accessing contested regions. The front of the middle A non-zero element causes one eviction from the block; each eviction results in the queue being evicted. Decrement the value of the element used in the middle by one;

[0035] Repeat the block evicting operation steps to obtain an upper bound on the number of cache misses caused by a single unordered program region to the contention region;

[0036] When a contested region is accessed by a sequence of consecutive, unordered remote program regions, each queue Element-wise accumulation yields a queue of unordered program region sequences. Then, the block evicting operation steps are executed again to obtain the upper bound of the number of cache misses caused by the unordered program region sequence to the contention region.

[0037] In some embodiments, the method further includes the following steps:

[0038] when While it may not be sufficient to evict a local block on its own, increasing the age of the local block makes it easier for the next interfering task's out-of-order program region to evict the local block. The minimum of the sum of the number of cache misses and the number of disordered program regions minus one is taken as the upper bound for additional cache misses.

[0039] In some embodiments, determining the number of second cache misses generated when a local task accesses the contention region includes the following steps:

[0040] Assignment to the first contested area arrive ,in The values ​​are enumerated from 1 to the total number of disordered program regions, and a fine-grained cache contention analysis method is used to obtain them. ,Will As generated during the enumeration process The set, and record ;

[0041] Starting from the second contention region, in each previous row state In, enumeration The value ranges from x to the total number of disordered regions, and removes evicted elements from the currently contested region. Then, a fine-grained cache contention analysis method was used to calculate the number of cache misses and compare it with the cache miss count. Add, update For this value and the current The maximum value among the values; As generated during the enumeration process The set, and record ;

[0042] After dynamic programming, all The maximum value in the value is determined to be the number of cache misses caused by cache contention in the worst case.

[0043] Another aspect of this application embodiment provides a worst-case execution time analysis apparatus for multi-real real-time system tasks considering shared cache, the apparatus comprising:

[0044] A memory reference generation unit is used to generate memory references for each memory block; wherein, the memory reference includes the address, access count, and age of the corresponding memory block;

[0045] contention region modeling unit, configured to model contention regions in order based on the memory references;

[0046] cache contention analysis unit, configured to determine cache miss numbers generated by system task accessing the contention regions;

[0047] worst-case cache contention estimation unit, configured to analyze worst-case execution time of the system task according to the cache miss numbers.

[0048] Another aspect of the embodiments of the present application further provides an electronic device, comprising a processor and a memory;

[0049] The memory is configured to store a program;

[0050] The processor executes the program to implement the method according to any one of the preceding aspects.

[0051] Another aspect of the embodiments of the present application further provides a computer readable storage medium, which stores a program, and the program is executed by a processor to implement the method according to any one of the preceding aspects.

[0052] The present application has at least the following beneficial effects:

[0053] The present application can generate memory references of each memory block, wherein the memory reference comprises an address, an access number and an age of the corresponding memory block; model contention regions in order based on the memory references; determine cache miss numbers generated by system task accessing the contention regions; and analyze worst-case execution time of the system task according to the cache miss numbers. The present application proposes a fine cross-core cache interference analysis scheme by constructing a contention region sequence, combining the access number of the memory reference and the age information of the cache block, and using dynamic programming to construct a worst-path analysis process under the partial order constraint of the program region, which significantly improves the structural and precision of the analysis. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0055] Figure 1 A flowchart of a method for analyzing worst-case execution time of multi-core real-time system task considering shared cache provided by the embodiments of the present application;

[0056] Figure 2 A schematic diagram of different memory references of the same memory block provided by the embodiments of the present application;

[0057] Figure 3 A schematic diagram of a fine-grained cache contention analysis process example provided for an embodiment of the present application;

[0058] Figure 4 A structural block diagram of a multi-core real-time system task worst-case execution time analysis device considering shared cache provided for an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the purposes, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0060] Before the detailed description of the embodiments of the present application, first, some related technologies involved in the embodiments of the present application are described as follows:

[0061] Worst-Case Execution Time (WCET): The longest time a task in a real-time system takes to execute without being interrupted (blocked, preempted, etc.), i.e., the time of instruction execution.

[0062] Shared Cache: A cache level in a multi-core system that is accessed by multiple cores, usually L2 or L3 cache. The use of shared cache improves data reuse efficiency, but also brings cache contention problems across cores.

[0063] Cache Associativity: A key parameter in cache, describing the number of blocks that can be accommodated in each cache set.

[0064] Cache Contention: Refers to the access behavior of a single or multiple core tasks to the shared cache affecting each other, causing cache blocks to be replaced in advance, resulting in cache miss behavior of some local access, which increases the delay of task execution.

[0065] Ages of Blocks: In a block access sequence of a task, the number of other cache blocks with unique addresses that have been accessed in the cache since the last access of a cache block. Since a program point can be reached by multiple access sequences, the age of a block at this program point is defined as the maximum value of the age in all possible trajectories.

[0066] Memory Reference: A triple (address, access count, age) representing an access to a specific address in a region and its cache state information, used to refine the cache hit analysis.

[0067] Unordered Program Region (UR): A program segment in the task control flow graph, divided according to the structure, used to organize complex program structures. The access behavior within a UR is considered unordered, but the original partial order relationship in the control flow graph is still maintained between URs.

[0068] Contention Region (CR): An analysis unit evolved from the unordered program region, used to identify the set of all memory references in the local task that may be affected when a remote access occurs. There is one or more memory references in a contention region that will be contended.

[0069] Current research attempts to capture possible cross-core interference by analyzing the partial order relationship between the concurrent structure, life cycle or execution path of the task, and estimates the number of cache misses accordingly. However, these methods generally have the problem of excessive pessimism, and do not consider the specific cache state and actual access behavior, thus greatly overestimating the worst-case execution time of the task.

[0070] Some related technical solutions are as follows:

[0071] Timing analysis method for estimating the life cycle of tasks concurrently executed on multiple cores: Based on single-core analysis, determine the initial life cycle of each task, and then expand its life cycle by estimating the delay caused by cache contention. In each iteration, if the number of blocks accessed by the interfering task exceeds the difference between the age of the analyzed block and the cache association, the access is determined to be likely to cause cache miss.

[0072] Precise estimation method considering the worst-case additional execution time of shared cache contention: The concept of "unordered program region" is introduced to express the internal and external nested structure in the task in a modular way, and the partial order relationship between program paths is used to identify which program segments may exist in time. Mutual exclusion. Dynamic programming is introduced to calculate the maximum number of cache misses to obtain the cache interference estimate.

[0073] In multi-core real-time systems, shared cache contention among tasks is a key factor leading to WCET estimation bias. Existing methods mostly identify potential cross-core interference at the granularity of program regions or task lifetimes, but still have significant deficiencies in handling shared cache contention. Timing analysis methods assume that interfering tasks can interfere with the analyzed task throughout their entire execution period, failing to reasonably model the interference scenarios that may occur within the program structure, resulting in severe over-pessimistic estimates. Existing estimation methods that consider cache contention consider that as long as interfering tasks exist with block addresses mapped to the same group as the analyzed task, corresponding memory accesses are uniformly considered as cache misses, without considering the actual state and access behavior of the cache block. Especially when the cache association degree is high or the number of repeated executions is large, this analysis method that ignores the actual cache state will produce significant errors,

[0074] Therefore, the present application proposes a fine-grained cross-core cache contention analysis scheme, which can significantly improve the accuracy of shared cache interference analysis while maintaining scalability. The embodiments of the present application take program regions as the basic analysis unit, and for each program segment that may be interfered, a "contention region" sequence containing the actual cache access behavior is constructed, which explicitly identifies the set of memory references that may be interfered under a specific concurrent situation. On this basis, combined with the access frequency and age of the cache block, a cache miss number calculation method based on dynamic programming is proposed, and the continuous interference influence across unordered program regions that is not considered by traditional methods is effectively compensated, solving the shortcomings of the prior art.

[0075] Reference Figure 1 The embodiments of the present application provide a multi-core real-time system task worst-case execution time analysis method considering shared cache, specifically comprising the following steps S100-S130:

[0076] S100: generating memory references of each memory block; wherein the memory references include addresses, access frequencies and ages corresponding to the memory blocks;

[0077] S110: modeling to obtain ordered contention regions based on each memory reference;

[0078] S120: determining the number of cache misses generated by system task accessing the contention regions;

[0079] S130: analyzing the worst-case execution time of the system task according to the number of cache misses.

[0080] Optionally, the generating memory references of each memory block comprises the following steps:

[0081] Record the addresses of each memory block within the same unordered program region; define the access count of each memory block as 1; define the age of each memory block as the number of different cached addresses since the last access of the memory block; if the memory block has never appeared, define the corresponding age as infinity;

[0082] Define the address, the number of accesses, and the age as memory references to memory blocks;

[0083] If the memory block is located in multiple unordered program regions, then the cumulative access count is calculated for each unordered program region where the memory block is located;

[0084] The cumulative number of visits is:

[0085] ;

[0086] in, The total number of visits;

[0087] like Then, a new memory reference is generated based on the cumulative number of accesses.

[0088] Optionally, obtaining an ordered contention region based on the modeling of each memory reference includes the following steps:

[0089] set up and These respectively indicate that remote task access affects the memory references. Unordered program region The indices of the first and last elements of the sequence;

[0090] The construction range is divided according to the partitioning expression;

[0091] The partitioning expression is:

[0092] ;

[0093] Among them, the function Returns the address containing the last accessed memory block. The subsequent memory reference to the UR index;

[0094] for , will satisfy and The age of the middle block is less than the cache associativity. Organize into a contention zone;

[0095] The execution path of each unordered program region for local tasks The above analysis ultimately forms a complete sequence of contested areas.

[0096] Optionally, determining the number of cache misses generated when a system task accesses the contention region includes the following steps:

[0097] Determine the first number of cache misses resulting from a remote task accessing the contentious region;

[0098] Determine the number of second cache misses resulting from local tasks accessing the contentious region;

[0099] The step of analyzing the worst-case execution time of the system task based on the number of cache misses includes the following steps:

[0100] Analyze the first worst-case execution time of the remote task based on the first cache miss count;

[0101] The second worst-case execution time of the local task is analyzed based on the number of cache misses.

[0102] Optionally, determining the first number of cache misses generated when a remote task accesses the contention region includes the following steps:

[0103] Set eviction threshold ,in The age of the memory block, used to indicate if the remote task access hits. If each address is distinct, a local block is evicted once; for an unordered sequence of interfering tasks, remote task access within a single unordered program region is modeled as a queue. ,queue The elements within represent the number of times different addresses were accessed, and are sorted in descending order of the number of accesses;

[0104] The procedure for performing block evicting is as follows: when a single out-of-order program region in the interfering task... Use queues when remotely accessing contested regions. The front of the middle A non-zero element causes one eviction from the block; each eviction results in the queue being evicted. Decrement the value of the element used in the middle by one;

[0105] Repeat the block evicting operation steps to obtain an upper bound on the number of cache misses caused by a single unordered program region to the contention region;

[0106] When a contested region is accessed by a sequence of consecutive, unordered remote program regions, each queue Element-wise accumulation yields a queue of unordered program region sequences. Then, the block evicting operation steps are executed again to obtain the upper bound of the number of cache misses caused by the unordered program region sequence to the contention region.

[0107] Optionally, the method further includes the following steps:

[0108] when While it may not be sufficient to evict a local block on its own, increasing the age of the local block makes it easier for the next interfering task's out-of-order program region to evict the local block. The minimum of the sum of the number of cache misses and the number of disordered program regions minus one is taken as the upper bound for additional cache misses.

[0109] Optionally, determining the number of second cache misses generated when a local task accesses the contention region includes the following steps:

[0110] Assignment to the first contested area arrive ,in The values ​​are enumerated from 1 to the total number of disordered program regions, and a fine-grained cache contention analysis method is used to obtain them. ,Will As generated during the enumeration process The set, and record ;

[0111] Starting from the second contention region, in each previous row state In, enumeration The value ranges from x to the total number of disordered regions, and removes evicted elements from the currently contested region. Then, a fine-grained cache contention analysis method was used to calculate the number of cache misses and compare it with the cache miss count. Add, update For this value and the current The maximum value among the values; As generated during the enumeration process The set, and record ;

[0112] After dynamic programming, all The maximum value in the value is determined to be the number of cache misses caused by cache contention in the worst case.

[0113] The following section will provide a detailed introduction and explanation of the solutions in the embodiments of this application, using specific application examples.

[0114] System model description in this embodiment:

[0115] To simplify the presentation of the analysis, this embodiment focuses on a dual-core real-time system with two cores sharing a single-level fully associative cache with a number of cache lines denoted by , i.e., the cache associativity. Each cache line can store a memory block loaded from the main memory, and the cache replacement policy uses the least recently used (LRU) algorithm. This hardware setup can be naturally extended to a multi-level, set-associative cache hierarchy, and does not limit the applicability of the subsequent analysis procedure. The system concurrently executes local tasks and interfering tasks , both of which are described by control-flow graphs (CFGs), where each edge is associated with a set of accessed memory blocks. A single memory block accessed at a certain program point is denoted by , and its block address is denoted by . An access to may result in a cache hit or a cache miss. Different are allowed to have the same address because a task can access the same data block at two different program points. The age of a block is defined as the number of unique blocks with different addresses that have been accessed since the last access to the same address in a block access sequence (also referred to as a trace) of a task. Since a program point can be reached by multiple paths (traces), the age of a block at a program point is defined as the maximum age of the block in all possible traces. This age information is assumed to be obtained in advance by existing single-core cache analysis methods and is input as a known parameter in the analysis.

[0116] To avoid the complexity of fully unrolling loops, the system of this embodiment uses the concept of unordered program regions (URs) to structure the CFG. Blocks within the same loop form a UR, which is denoted by , and the number of loop executions is denoted by . If a block is not within any loop, it forms a UR with a loop execution number of 1. In particular, if there are nested loop structures, blocks within inner loops also form URs. An execution path of the CFG is denoted by , where the URs are arranged in the order of outermost execution (URs without an outer layer are referred to as outermost URs). In the context of a unique path, it can be simply denoted by . For UR structures formed by nested loops, the function anc(Ux) returns the set of outer URs that directly or indirectly contain , which is used to derive the number of executions and interference relationships.

[0117] Based on the above model, this embodiment further constructs a contention region, establishes a cache miss quantification criterion, and calculates the worst-case cross-core cache contention situation through dynamic programming, providing a refined and scalable upper bound estimate for the worst-case execution time of multi-core systems.

[0118] The specific operation steps and overall workflow of this embodiment are as follows:

[0119] The specific operation steps of this embodiment are divided into four steps: (1) generation of memory reference triples; (2) modeling of contention regions; (3) fine-grained cache contention analysis; and (4) worst-case cache contention estimation based on dynamic programming.

[0120] The specific explanation is as follows:

[0121] 1. Generation of memory reference triples.

[0122] like Figure 2 As shown, Figure 2 For the same memory block Different memory references. In shared cache analysis, the compiler focuses on control flow, while the cache is concerned with address, access count, and replacement order. To ensure all subsequent analyses use the same granularity, this embodiment first abstracts each memory access into a triple. Memory references The triplet form is (address, access count, age). For the same memory block... Its memory reference may be different. For example Figure 2 As shown, when When located in different program regions, its access frequency and age differ, leading to different memory references. The specific partitioning method is as follows:

[0123] 1.1 Record the first visit. Each memory block within Record its address Set the number of visits The value of the block's age is 1, and the value of the block's age is: from The number of different cached addresses accessed since the last access; if an address has never appeared before, its age is set to infinity. These are then combined into triples. Add to collection .

[0124] 1.2 Consider the different memory references caused by the loop. If If it is located in a multi-level loop, then... Each UR (represented as) All counts are based on cumulative visits:

[0125] ;

[0126] If , a new memory reference triplet is generated. This guarantees that the phenomenon of "the same address is repeatedly accessed in the loop body" can be accurately captured, thus obtaining the complete memory reference set.

[0127] 2. Contention region modeling.

[0128] The memory reference set alone is not enough to depict the code execution order and the remote access of interference tasks. Therefore, the embodiment reorganizes the memory references into ordered contention regions CR. A CR can be understood as "which memory blocks in this contention region can be evicted if the remote core writes to the same group of addresses during this period". This segmentation allows the subsequent analysis to "segment by segment" add interference, rather than overestimate the entire program at once. The construction process is as follows:

[0129] 2.1 Divide the construction range. Let and denote the first and last UR indices of the UR sequence that can be affected by remote access , then and can constitute a range, which facilitates the modeling of contention regions. The division principle is shown in the formula, where the function returns the index of the UR containing the memory reference after the last access .

[0130] ;

[0131] 2.2 For , the blocks in and whose ages are less than the cache affinity of are organized into a CR. The above analysis is performed for each of the execution path, and finally a complete CR sequence is constructed.

[0132] After the analysis is completed, the originally flat memory reference set is divided into a time-ordered, controllable-granularity CR sequence, which facilitates subsequent fine-grained cache contention calculation.

[0133] 3. Fine-grained cache contention analysis.

[0134] On a shared cache, the access of a remote core can evict the cache blocks of a local task, causing a cache miss. The embodiment first performs fine-grained modeling on the local task path , obtaining the contention region CR. Then the number of cache misses that can be caused at the CR level when performing remote access needs to be considered.

[0135] Exemplarily, Figure 3 For fine-grained cache contention analysis process example ( ).

[0136] 3.1 First set eviction threshold , where is the age of the block, i.e. if remote accesses hit different addresses, then the local block can be evicted once. For the UR sequence of the interference task (as shown in (a) of Figure 3 , this embodiment models the remote accesses in a single UR as a queue , and the elements in the queue are the number of accesses to different addresses, and are sorted in descending order according to the number.

[0137] 3.2 When a single UR (denoted as ) in the interference task performs remote access on the CR, the first non-zero elements in the queue can cause the eviction of a block. Each time the eviction occurs, the value of the used element in the queue is reduced by one. Repeating this step can obtain an upper bound of the number of cache misses caused by the single UR on the CR (as shown in (b) of Figure 3 ).

[0138] 3.3 When the CR is affected by a continuous remote UR sequence instead of a single UR, the queue elements of each are accumulated to obtain the queue of the UR sequence, and then the operation steps in 3.2 are performed, which can obtain an upper bound of the number of cache misses caused by the UR sequence on the CR (as shown in (c) of Figure 3 ).

[0139] In particular, consider the following continuous contention case: It is not enough to evict the local block itself, but it can increase the age of the block, so that the UR of the next interference task can evict the local block. This situation can occur between the URs of two adjacent interference tasks, and can increase the number of cache misses. In this embodiment, the queue is still possible to occur the sum of the number of cache misses and the value of the number of interference task URs minus one (i.e. the number of regions that can occur continuous contention), and the minimum value of the two is taken as the upper bound of the additional cache misses.

[0140] 4. Worst-case cache contention estimation based on dynamic programming.

[0141] The above scheme provides a contention analysis of a continuous remote UR sequence interfering with CR. However, for the contention between the contention region sequence formed by local task paths and the unordered program region sequence formed by interfering task paths, an algorithm is needed to find the "optimal allocation" between the two, that is, to determine which UR sequence contends for which CR sequence when the cumulative cache miss count reaches its maximum value, i.e., the worst-case cross-core cache contention. To find the optimal allocation, this embodiment introduces state symbols. ,in, This indicates that the s-th CR has been processed. This indicates that the interfering UR sequence used the first... Each UR, h, represents a sub-scenario number within the current CR, derived from a binary sequence of hit states of memory references within the CR. Each state symbol records the cumulative number of misses and has a set. References that have been completely evicted in previous CRs are recorded to avoid duplicate calculations. The specific calculation process is as follows:

[0142] 4.1 First, initialize the module state and allocate power to the first CR. arrive ,in The values ​​are enumerated from 1 to the total number of interfering URs, and a fine-grained cache contention analysis method is used to obtain the values. ,Will As generated during the enumeration process The set, and record .

[0143] 4.2 Starting from the second CR, in each "Previous Row Status" In, enumeration The value ranges from x to the total number of interfering URs, removing the elements that have been expelled from the current CR. Then, a fine-grained cache contention analysis method was used to calculate the number of cache misses and compare it with the cache miss count. Add, update For this value and the current The maximum value among the values. As generated during the enumeration process The set, and record .

[0144] After dynamic programming, all The maximum value in the range represents the number of cache misses caused by cache contention in the worst-case scenario.

[0145] In summary, this embodiment includes the following key points:

[0146] 1. A contention region modeling mechanism is proposed: according to the partial order structure of the out-of-order program region in the program execution path, a contention region sequence is constructed, and each contention region explicitly contains those memory references that may be disturbed by remote tasks during the current program segment execution.

[0147] 2. A fine-grained cache contention analysis method based on access behavior and cache state is proposed: combining the address, access frequency and block age information of each memory reference, a quantifiable cache miss determination criterion is established, and the number of cache misses is accurately calculated under specific interference sequences.

[0148] 3. A complete cross-core cache contention analysis process based on dynamic programming is constructed: under the premise of maintaining the partial order constraints between contention regions, a state transition strategy is adopted to optimize the search of the worst-case cache interference path under different interference task paths, effectively avoiding repeated calculation and improving analysis accuracy.

[0149] The embodiment can implement the following technical solutions:

[0150] 1. A contention region construction method: based on the partial order relationship of the out-of-order region in the program structure, the memory references that may be disturbed on the target task execution path are identified, a contention region sequence with temporal constraints is constructed, and it is used for subsequent cache interference analysis.

[0151] 2. A cache miss quantification method considering access frequency and cache state: for different age and access frequency memory references in each contention region, the maximum possible cache miss number is calculated in combination with the access address distribution of the remote task.

[0152] 3. A worst-case cache contention estimation method based on dynamic programming: according to the partial order relationship between contention regions, the state space of all feasible interference paths is traversed, the maximum cache interference number of the target task is calculated, and it is used to support multi-core WCET estimation.

[0153] The beneficial effects of the embodiment include:

[0154] The embodiment constructs a contention region sequence, combines the access frequency of memory references and the age information of cache blocks, and proposes a fine-grained cross-core cache interference analysis method. The dynamic programming is used to construct the worst-case path analysis process under the partial order constraints of program regions, which significantly improves the structural and accuracy of the analysis. Compared with existing methods, the embodiment realizes cache contention analysis considering cache state and parallel task access behavior, effectively alleviating the problem of excessive pessimism. While keeping the computational complexity controllable, the embodiment realizes fine-grained modeling and analysis of the influence of shared cache interference in multi-core systems, and has good generality and scalability.

[0155] Reference Figure 4The embodiment of the application provides a worst-case execution time analysis device of a multi-core real-time system task considering a shared cache, which comprises the following steps:

[0156] a memory reference generation unit configured to generate memory references of each memory block, wherein the memory references comprise addresses, access times and ages of the memory blocks;

[0157] a contention region modeling unit configured to model ordered contention regions based on the memory references;

[0158] a cache contention analysis unit configured to determine cache miss numbers generated by system task accesses to the contention regions;

[0159] a worst-case cache contention estimation unit configured to analyze worst-case execution times of the system task according to the cache miss numbers.

[0160] It can be understood that the content in the method embodiment is applicable to the device embodiment, the device embodiment specifically implements the functions of the method embodiment, and the device embodiment achieves the same beneficial effects as the method embodiment.

[0161] In some alternative embodiments, the functions / operations mentioned in the block diagram can not occur in the order mentioned in the operation diagram. For example, depending on the functions / operations involved, two blocks shown in succession can actually be executed substantially simultaneously or the blocks can sometimes be executed in reverse order. In addition, the embodiments presented and described in the flowcharts of the present application are provided by way of example, and the purpose is to provide a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are independently executed.

[0162] Furthermore, although the present application is described in the context of functional modules, it is understood that one or more of the functions and / or features described can be integrated in a single physical device and / or software module, or one or more functions and / or features can be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary to an understanding of the present application. Rather, the actual implementation is within the routine of an engineer in the art, given the property, function and internal relationships of the various functional modules disclosed herein. Accordingly, the present application is not limited to the specific details of the functional modules described herein. It is also understood that the particular concepts disclosed are illustrative only and not intended to limit the scope of the present application, which is defined in the appended claims and their equivalents.

[0163] If the functions are implemented in software, the functions can be stored in or implemented as one or more computer program products, which can be incorporated into a computer-readable medium for use by or in connection with an apparatus, method, or system as described herein. The computer-readable medium can be a computer- only medium, a partially software and partially hardware medium, or a medium that contains both software and hardware. The computer-readable medium can be any medium that can contain, store, or transport the program for use by or in connection with the computer. The computer-readable medium can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium. The computer-readable medium can be a computer program product. The computer program product can be packaged on an apparatus-based medium or transmitted by a device programmed to perform the process steps of the computer program product. The computer program product can contain computer program code.

[0164] Logic and / or steps represented in flow diagrams or otherwise described herein, for example, can be embodied in computer-readable instructions, orders, or a sequence of instructions, which can be executed by, for example, an instruction execution system, apparatus, or device, such as a computer-based system, processor- based system, or other system that can fetch the instructions from a instruction execution system, apparatus, or device and execute the instructions. In this context, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium.

[0165] More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can also be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

[0166] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, or combinations thereof, can be used: a discrete logic circuit having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0167] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples.

[0168] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and alterations can be made hereto without departing from the principles and spirit of the application, and the scope of the present application is defined by the claims and their equivalents.

[0169] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the described embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A method for worst-case execution time analysis of tasks in a multi-core real-time system sharing a cache, characterized in that, The method comprises the following steps: generating memory references of each memory block; wherein the memory references comprise addresses, access times and ages of the memory blocks; modeling ordered contention regions based on the memory references; determining cache miss numbers generated by system tasks accessing the contention regions; analyzing worst-case execution times of the system tasks according to the cache miss numbers; The determining of the cache miss numbers generated by system tasks accessing the contention regions comprises the following steps: determining first cache miss numbers generated by remote tasks accessing the contention regions; determining second cache miss numbers generated by local tasks accessing the contention regions; The analyzing of the worst-case execution times of the system tasks according to the cache miss numbers comprises the following steps: analyzing first worst-case execution times of the remote tasks according to the first cache miss numbers; analyzing second worst-case execution times of the local tasks according to the second cache miss numbers; The determining of the first cache miss numbers generated by remote tasks accessing the contention regions comprises the following steps: Setting eviction threshold wherein, is the number of cache lines, is the age of the memory block, indicating that if the remote task access hits different addresses, then evict a local block; for the out-of-order program region sequence of the interference task, model the remote task access in a single out-of-order program region as a queue , the elements in the queue are the access times to different addresses, and are sorted in descending order of the number of times. The operation step of performing the eviction block: when a single out-of-order program region in the interference task uses the queue to remotely access the contention region , the first non-zero element in the queue causes an eviction of a block; the value of the element used in the queue is decremented by one each time an eviction is caused. repeating the evicting of the blocks to obtain an upper bound of cache miss numbers caused by a single unordered program region to the contention regions; When the contention region is accessed by a sequence of consecutive remote unordered program region, the number of cache misses caused by the sequence of unordered program region to the contention region is obtained by queueing element-level accumulation, obtaining the queue of the sequence of unordered program region repeating the operation steps of the eviction block to obtain the upper bound of the number of cache misses caused by the sequence of unordered program region to the contention region; The determining of the second cache miss numbers generated by local tasks accessing the contention regions comprises the following steps: allocating to where values enumerate from 1 to the total number of interference out-of-order program regions, and is obtained using a fine-grained cache contention analysis method , and record ;​ From the second contention region, in each of the last line state , the value of enumeration from x to the total number of interference unordered program regions, remove the elements that have been expelled in the current contention region , calculate its miss number using the fine-grained cache contention analysis method and add , update to the maximum value of the value of the current ; take as the set of generated in the enumeration process, and record ; After dynamic programming, the maximum value in is determined as the number of cache misses due to cache contention in the worst case.

2. The method of claim 1, wherein, The generating of the memory references of each memory block comprises the following steps: recording addresses of each memory block in the same unordered program region; defining an access time of each memory block as 1; defining an age of each memory block as a number of different addresses accessed in the cache from the last time the memory block was accessed to the present; if the memory block has never appeared, defining the corresponding age as infinity; defining the addresses, the access times and the ages as the memory references of the memory blocks; if the memory block is located in multiple unordered program regions, calculating a cumulative access time for each unordered program region in which the memory block is located; The cumulative access time is: ； wherein, is the cumulative number of accesses; If then generating a new said memory reference from said cumulative access count.

3. The method for worst-case execution time analysis of tasks of a multi-core real-time system taking shared caches into account according to claim 2, characterized in that, The modeling of ordered contention regions based on the memory references comprises the following steps: Let and denote the first and last index of the sequence of out-of-order program regions whose remote task access affects the memory reference respectively; constructing ranges according to partition expressions; The partition expression is: ； where the function returns the address of the memory block containing the last access to said memory block the index of the UR of the memory reference following; UR is an unordered program region; For will satisfy and the age of the block in organize into one said contention area; is an execution path of a control flow graph; Execution path for local task per out-of-order program region Upon the above analysis, a complete sequence of contention regions is finally constructed.

4. The method for worst-case execution-time analysis of tasks of a multi-core real-time system taking shared caches into account according to claim 1, characterized in that, The method further comprises the following steps: When It is not sufficient to evict the local chunk by itself, but increasing the age of the local chunk makes it possible for the next interfering task's out-of-order program region to evict the local chunk when the local chunk is in each The minimum of the sum of the number of cache misses that still occur and the value of the number of interfering out-of-order program regions minus one is taken as an upper bound on the additional cache misses that occur.

5. An apparatus for worst-case execution-time analysis of tasks of a multi-core real-time system considering shared caches, characterized in that, The device is applied to the worst-case execution time analysis method of multi-core real-time system tasks considering shared caches, and the device comprises: a memory reference generating unit configured to generate memory references of each memory block; wherein the memory references comprise addresses, access times and ages of the memory blocks; a contention region modeling unit configured to model ordered contention regions based on the memory references; a cache contention analysis unit configured to determine cache miss numbers generated by system tasks accessing the contention regions; a worst-case cache contention estimation unit configured to analyze worst-case execution times of the system tasks according to the cache miss numbers.

6. An electronic device, comprising: The electronic device comprises a processor and a memory; The memory is configured to store a program; The processor is configured to execute the program to implement the method according to any one of claims 1 to 4.

7. A computer readable storage medium characterized in that, The storage medium stores a program, and the program is executed by the processor to implement the method in any one of claims 1 to 4.

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