A logic synthesis cut delay prediction method based on a graph neural network

Abstract

The application provides a logic synthesis cut delay prediction method based on a graph neural network, first constructs a cut delay prediction data set of a logic synthesis circuit, then extracts structural and functional features of nodes in a cut subgraph, constructs a heterogeneous cut-level graph with the cut super node as the center, and encapsulates the graph into a graph neural network input format. Then a delay prediction model is constructed, including a graph neural network module and a multilayer perceptron module, wherein the graph neural network module extracts circuit structural features through SAGE convolution, dynamically correlates standard cell library features through a pointer attention mechanism, and forms an enhanced cut representation. Finally, the trained model is used to predict the delay of the cut in the new circuit. The application effectively improves the cut structure modeling capability and delay prediction accuracy, and can be used for optimizing the cut selection strategy in the synthesizer and improving the logic synthesis quality.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronic design automation, and particularly relates to a logic synthesis cut delay prediction method based on a graph neural network. BACKGROUND

[0002] In logic synthesis, a Boolean network is a network composed of logic gates (such as AND gates, OR gates, NOT gates, etc.) and signal lines, which represents the logic function of a circuit. In order to generate a high-quality synthesis result, it is necessary to select appropriate substructures from the Boolean network for mapping, and these substructures are "cuts". Each cut represents a possible logic partitioning. In the synthesis process, each cut needs to be mapped to one or more standard cells to realize its logic function, and therefore the standard cell library provides key implementation resources and timing references for the performance evaluation of the cut. Logic synthesis plays a crucial role in the electronic design automation (EDA) flow, and its goal is to generate a gate-level netlist that performs well in terms of area, delay, etc. under the premise of meeting functional constraints, through a series of logic transformations and optimization operations. In order to achieve a high-quality synthesis result, modern synthesizers usually adopt a "cut-based mapping" strategy, that is, multiple optional cuts are extracted from the Boolean network as candidate structures, and their performance under the target cost function (such as area, timing, power consumption) is evaluated, so as to select the best mapping structure and generate a gate-level netlist that meets the design requirements. In the cut selection process, predicting the timing performance of the mapped cut is a key factor affecting the quality of synthesis. However, current industrial synthesis tools usually use simple heuristic indicators such as logic levels, node numbers, and reverse fan-out to approximate the delay performance of the cut. This method cannot accurately model the dependency between logic structures, is prone to evaluation bias, and thus leads to unsatisfactory synthesis results and even increases the timing repair cost in the backend placement and routing.

[0003] With the development of graph neural network (GNN) technology, its expression ability in processing graph structure data has gradually attracted attention in the field of hardware design. Existing research has attempted to apply graph neural networks to the quality evaluation task of circuit graphs, and has achieved certain results. However, most of these methods are based on full graph modeling and cannot accurately depict the structural details at the cut level, making it difficult to meet the demand for rapid evaluation of large-scale cut candidate structures in the synthesis stage. SUMMARY

[0004] The present application aims to solve the problems of traditional logic synthesis process, such as relying on simple proxy indicators for cut delay estimation, insufficient prediction accuracy, and inability to effectively guide optimization strategy selection, by providing a logic synthesis cut delay prediction method based on a graph neural network.

[0005] To solve the above problems, the application adopts the following technical solutions:

[0006] In a first aspect, the application provides a logic synthesis cutting delay prediction method based on a graph neural network, comprising:

[0007] Step S1: constructing a logic synthesis circuit cutting delay prediction dataset, and dividing the dataset into a training set and a test set;

[0008] The dataset contains input data and label data; the input data contains an RTL Verilog described circuit and a standard cell library for mapping, and the label data is the path maximum delay value of each cutting root node in the circuit after mapping is completed, which is obtained by a static timing analysis tool.

[0009] Step S2: preprocessing the input data and label data;

[0010] Step S3: constructing a cutting delay prediction model based on a graph neural network, and training and testing using the preprocessed dataset;

[0011] The cutting delay prediction model based on the graph neural network includes a pointer attention-graph neural network (GNN-Attn) module and a multilayer perceptron module.

[0012] The pointer attention-graph neural network module is used for preprocessed input data, and separately processes circuit graph node feature embedding and standard cell library feature embedding, and splices the processed features to obtain cutting node feature embedding.

[0013] The multilayer perceptron module is used to receive the cutting node feature embedding generated by the pointer attention-graph neural network module, and regressively output the corresponding delay prediction value.

[0014] Step S4: using the trained graph neural network cutting delay prediction model to predict the delay of each cutting in the circuit to be synthesized.

[0015] Preferably, the pointer attention-graph neural network module includes a circuit node feature processing submodule, a standard cell library feature processing submodule, and a feature enhancement submodule.

[0016] The circuit node feature processing submodule is configured to receive initial node feature embeddings of each node in the heterogeneous cut-level graph, sequentially pass through two graph convolution blocks and a pooling layer to extract local neighborhood information of the nodes and generate cut preliminary feature embeddings. The graph convolution block is composed of a graph convolution operation (SAGEConv) and an activation function operation (SiLU). The input of the first graph convolution block is the initial node feature embedding, and the input of the second graph convolution block is the activation result output by the first graph convolution block. The pooling layer is configured to perform a convergence operation on feature embeddings of all nodes in a Cone (logical cone) region corresponding to each cut node to obtain a preliminary feature embedding representation of the cut node. The Cone region is defined as a subnetwork region centered on a certain cut node and containing all downstream (or upstream) logical gates and signal paths of the node.

[0017] The node feature updating process in the graph convolution block sequentially consists of a graph convolution operation (SAGEConv) and an activation function operation (SiLU), and the overall calculation process can be described by the following formula:

[0018]

[0019] wherein, represents the embedding representation of the ith node in the lth layer, represents a set of neighbor nodes of the node i, AGG(·) represents an aggregation operation using a mean function, W represents a learnable linear transformation weight matrix, and σ(·) represents a SiLU activation function.

[0020] The standard cell library feature processing submodule is configured to receive a standard cell library feature embedding, sequentially pass through a first RMSNorm (Root Mean Square Normalization) layer, a first linear transformation layer, a second RMSNorm layer, and a second linear transformation layer, and output a standardized standard cell library feature embedding.

[0021] The first RMSNorm layer and the second RMSNorm layer have the same structure and adopt root mean square normalization. The mathematical expression is as follows:

[0022]

[0023] The linear transformation is a fully connected linear mapping, and the mathematical expression is as follows:

[0024]

[0025] wherein h represents an input feature vector, represents the ith component of the vector h, where h is the dimension of the vector h, h' is the output feature vector after linear transformation, W is a learnable weight matrix, b is a learnable bias vector, and γ is a learnable scaling factor for normalization, A small constant to prevent division by zero errors.

[0026] The feature enhancer module is configured to receive the cut preliminary feature embedding and the standardized standard cell library feature embedding, dynamically establish a feature association relationship between the cut node and the standard cell library by using a Pointer Attention (PA) mechanism, output a PA enhanced feature, and then splice the cut preliminary feature embedding and the PA enhanced feature to form a final cut node feature embedding for subsequent delay regression prediction by a multilayer perceptron (MLP) module. The mathematical description of the PA mechanism is as follows:

[0027]

[0028] wherein represents the cut preliminary feature embedding, Lib represents the standardized standard cell library feature embedding, are learnable linear transformation matrices for queries, keys, and values, respectively, is a feature dimension scaling factor, and a softmax operation normalizes the weight distribution on the standard cell library feature set.

[0029] Preferably, the MLP module comprises a first linear layer, a first activation function layer (SiLU), a first dropout layer, a second linear layer, a second activation function layer (SiLU), a second dropout layer, a third linear layer, and a third activation function layer (PReLU) cascaded in sequence, and is configured to output a delay prediction value of the cut.

[0030] Preferably, the step S2 comprises the following sub-steps:

[0031] S201: converting a circuit described in RTL verilog into an And-Inverter Graph (AIG) format circuit; and constructing a directed acyclic graph from the AIG format circuit wherein V is a node set comprising logical AND gate nodes and logical NOT gate nodes, and E is an edge set representing a connection relationship between the nodes.

[0032] S202: Extract a logical Cone region formed by a reverse transmission closure of each logical node in the directed acyclic graph as a root node, and construct a plurality of cut subgraphs; create a cut supernode for each cut subgraph; wherein the cut subgraph refers to a directed acyclic subgraph formed by tracing back to all predecessor nodes of a target node (i.e. cut root node) in the Boolean network as a starting point. The input boundary of the subgraph is composed of a set of predecessor nodes, referred to as the input nodes or leaf nodes of the cut; the cut subgraph internally contains all logic gates and signal paths from these input nodes to the root node. Each cut subgraph represents a local functional structure, which can be used for the construction and delay prediction of candidate mapping units.

[0033] As a preferred, the cut supernode is a high-level abstract representation of the cut subgraph, and the initial feature embedding of the cut supernode is mapped by splicing the feature embedding mean of the nodes contained in the cut subgraph and the fan-out number embedding of the root node, and the cut supernode is connected to the cut internal node through a heterogeneous edge, forming a heterogeneous graph structure centered on the cut.

[0034] S203: The newly created cut supernode is taken as a new node of the directed acyclic graph to form a heterogeneous cut-level graph; construct a structural feature embedding and a functional feature embedding for each node in the heterogeneous cut-level graph, and splice them to form an initial node feature embedding.

[0035] As a preferred, the functional feature embedding includes controllability indicators, observability indicators, and type identification of the node in the circuit logic, which is used to assist the model in understanding the signal propagation difficulty and the node logic behavior; the structural feature embedding includes node type, topology level, and fan-out number, which is used to describe the topological properties of the node in the graph structure.

[0036] As a preferred, the node type is 0 or 1, 0 represents an AND node, and 1 represents a NOT node; the topology level of the node refers to the number of nodes on the longest path from any main input to the node; and the fan-out number refers to the number of outputs of the node.

[0037] S204: Encapsulate the initial node embedding and the corresponding label of each node in the heterogeneous cut-level graph into a graph neural network input data format to construct a standardized graph sample.

[0038] In a second aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores machine executable instructions capable of being executed by the processor, and the processor executes the machine executable instructions to implement the method.

[0039] In a third aspect, the present application provides a machine readable storage medium, characterized in that the machine readable storage medium stores machine executable instructions, and when the machine executable instructions are invoked and executed by a processor, the machine executable instructions cause the processor to implement the method.

[0040] Compared with the prior art, the present application has the beneficial effects that:

[0041] The graph neural network module of the present application parses the AIG graph structure of the logic synthesis circuit through the graph neural network convolution layer, extracts the node local neighborhood features, combines the pointer attention mechanism to dynamically aggregate the standard cell library features, forms the enhanced cut (Cut) node feature representation, and improves the modeling ability of the model for the delay characteristics of different cut structures; the multi-layer perceptron module uses the enhanced cut features for regression prediction, accurately estimates the path delay after cut mapping, and through continuous training and accumulation of sample experience, can quickly and accurately predict the cut delay when facing circuits of different sizes and structures, improve the decision quality of cut selection and mapping in the logic synthesis optimization stage, significantly speed up the synthesis convergence and improve the result quality. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is the flow chart of the logic synthesis cut delay prediction method based on the graph neural network provided by the present application.

[0043] Figure 2 is the complete model framework diagram provided by the present application.

[0044] Figure 3 is the GNN-Attn module diagram provided by the present application.

[0045] Figure 4 is the multi-layer perceptron module diagram provided by the present application. DETAILED DESCRIPTION

[0046] The principles and features of the logic synthesis cut delay prediction method based on the graph neural network provided by the present application are further described in detail below in combination with the drawings, and the examples are only used to explain the present application, but not to limit the scope of the present application. It should be noted that the drawings are simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures, and the emphasis of each drawing is different, sometimes using different proportions.

[0047] The present application provides a logic synthesis cut delay prediction method based on a graph neural network, and the scheme flow chart is as follows Figure 1As shown. First, the Cut delay prediction dataset of the logic synthesis circuit is constructed, and the circuit is divided into two groups of training set and test set in advance, the dataset contains input data and label data, the input data contains the circuit described by RTL Verilog and the standard cell library used for mapping, and the label data is the maximum delay of the path corresponding to the Cut root node; the input data is preprocessed to generate a circuit graph in AIG format, the node structure and functional features are extracted, and a heterogeneous graph structure centered on the Cut super node is constructed; a Cut delay prediction model based on graph neural network is constructed, the model includes a GNN-Attn module and a multilayer perceptron module, and is trained on the preprocessed training set; the test set is input into the trained model, the delay of each Cut in the circuit is predicted, and the prediction performance is evaluated using the error index.

[0048] Therefore, a logic synthesis Cut delay prediction method based on a graph neural network, specifically includes:

[0049] S1: Construct a logic synthesis circuit Cut delay prediction dataset, which is divided into a training set and a test set according to a predetermined proportion, for subsequent model training and verification. The dataset contains input data and label data; the input data contains a circuit described by RTL Verilog and a standard cell library used for mapping, and the label data is the path maximum delay value of each Cut root node in the circuit after mapping, which is obtained by a static timing analysis tool (STA). In this embodiment, the standard cell library uses the ASAP7 standard cell library.

[0050] S2: Preprocess the input data and label data. For each circuit instance in the dataset, first convert it to And-Inverter Graph (AIG) format, extract the logical Cone region of each node and form a Cut subgraph. For each node, extract structural features (such as node type, topology level, fan-out number) and functional features (such as controllability, observability indicators), and concatenate these features to form an initial node feature embedding. At the same time, introduce the cell features in the standard cell library to form a standardized standard cell library feature embedding.

[0051] S3: Construct a Cut delay prediction model based on a graph neural network, the overall model structure is as shown in Figure 2 , including a pointer attention-graph neural network (GNN-Attn) module, a feature enhancement module, and a multilayer perceptron (MLP) prediction module.

[0052] The structure of GNN-Attn is as shown in Figure 3As shown, the circuit node feature processing submodule, the standard cell library feature processing submodule, and the feature enhancement submodule are included. In the circuit node feature processing submodule, the initial feature embedding of each node in the heterogeneous cut-level graph is sequentially subjected to two graph convolution blocks to extract the local neighborhood information of the node. The features of all nodes in the Cone region corresponding to each Cut node are aggregated by a pooling layer to generate the Cut preliminary feature embedding. In the standard cell library feature processing submodule, the standard cell library features are subjected to two times of RMSNorm normalization and linear transformation processing to generate the standardized standard cell library feature embedding. In the feature enhancement submodule, the Cut preliminary features and the standard cell library features are dynamically associated through the Pointer Attention mechanism to further enhance the Cut node features. Finally, the Cut preliminary features and the Pointer Attention enhanced features are spliced to form the final Cut node feature embedding.

[0053] The node feature updating process in the graph convolution block is sequentially composed of a graph convolution operation (SAGEConv) and an activation function operation (SiLU), and the overall calculation process can be described by the following formula:

[0054]

[0055] wherein, represents the embedding of the ith node in the lth layer, represents the neighbor node set of node i, AGG(·) represents an aggregation operation using a mean function, W represents a learnable linear transformation weight matrix, and σ(·) represents a SiLU activation function.

[0056] RMSNorm adopts root mean square normalization, and its mathematical expression is:

[0057]

[0058] The linear transformation is a fully connected linear mapping, and its mathematical expression is:

[0059]

[0060] wherein h represents an input feature vector, represents the ith component of the vector h, represents the dimension of the vector h, h' represents an output feature vector after linear transformation, W is a learnable weight matrix, b is a learnable bias vector, γ is a learnable scaling factor for normalization, is a small constant to prevent division by zero errors.

[0061] The mathematical description of the Pointer Attention mechanism is as follows:

[0062]

[0063] wherein denotes the Cut node preliminary feature embedding, Lib denotes the normalized standard cell library feature matrix, are the learnable linear transformation matrices for query, key and value respectively, is the feature dimension scaling factor, and the softmax operation normalizes the weight distribution on the standard cell library feature set.

[0064] The multi-layer perceptron module structure is shown in Figure 4 , which includes three layers of linear transformation structure, each layer is connected with SiLU activation and Dropout regularization processing in turn, and finally outputs the predicted Cut node delay value through PReLU activation function.

[0065] wherein the first linear layer is used to receive the final Cut node feature embedding output by the graph neural network module, and map it to the hidden feature space, and the mathematical expression is as follows:

[0066]

[0067] wherein is the input Cut node final feature embedding vector, is the hidden feature vector after the first linear mapping, is the first linear mapping weight matrix, is the corresponding bias term;

[0068] The second linear layer is used to map the activated and regularized feature vector input, and the mathematical expression is as follows:

[0069]

[0070] wherein denotes the feature vector after SiLU and Dropout layer processing, is the hidden feature vector after the second linear mapping is the second linear mapping weight matrix, is the corresponding bias term;

[0071] The PReLU layer is used to apply a parameter-learnable nonlinear transformation to the feature vector output by the third linear transformation, in order to introduce nonlinear expression capability and optimize the fitting effect of small negative value area in the regression task. The mathematical expression of the PReLU activation function is:

[0072]

[0073] wherein is the i-th component of the input vector, corresponding learnable slope parameter.

[0074] S4: model training and prediction, for the graph samples in the training set, input to the graph neural network model, using a stochastic gradient descent (SGD) optimizer, based on the mean square error (MSE) loss function for iterative training until the training converges. During the training process, the model continuously updates the parameters according to the difference between the true delay label and the predicted value.

[0075] After training, the test set is input into the model for prediction, and the error index between the predicted delay and the true delay is calculated to evaluate the model performance.

[0076] The test process includes the following steps:

[0077] S501: input the data in the test set into the trained model.

[0078] S502: output the final area prediction result of each circuit, and evaluate it using MAPE, which is mathematically described as follows:

[0079]

[0080] where n is the number of samples, is the actual value of the i-th sample, is the predicted value of the i-th sample.

[0081] The experimental environment parameters of the logic synthesis Cut delay prediction method based on the graph neural network proposed in the application are as shown in Table 1:

[0082] Table 1

[0083] Category Configuration Operating System Linux CPU Intel(R) Xeon(R) Gold 6348 CPU @ 2.60GHz GPU NVIDIA GeForce RTX 4090 RAM 500GB Pytorch 2.1.0 PyTorch Geometric 2.5.2

[0084] The logic synthesis Cut delay prediction results of the trained model and the DeepGate2 method on the test set of 9 circuits are shown in Table 2, and it can be seen that the error of the method of the application is smaller.

[0085] Table 2

[0086] Test Circuit DeepGate2 Invention Method dft 30.3% 10.4% aes secworks 43.2% 18.2% dynamic node 36.8% 15.5% des3 area 62.2% 16.1% wb conmax 29.7% 10.4% idft 29.1% 11.1% multiplier 21.5% 10.9% ethernet 23.1% 8.1% sqrt 59.4% 29.4% MEAN 37.2% 14.4%

[0087] The electronic device provided in the embodiments of the application, specifically, includes a memory and a processor, the memory stores executable code, and the processor executes the executable code to implement the method of any one of the embodiments.

[0088] The memory can include a high-speed random access memory (RAM), and can also include a non-volatile memory such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface (which can be wired or wireless), and the Internet, a wide area network, a local area network, a metropolitan area network, etc. can be used.

[0089] The bus can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0090] The memory is used to store programs, and the processor executes the programs after receiving execution instructions. The method executed by the device defined by the flow process disclosed in any of the embodiments of the present application can be applied to the processor or implemented by the processor.

[0091] The processor can be an integrated circuit chip having a processing capability of signals. In the implementation process, each step of the above method can be completed by integrated logic circuits or instructions in the form of software in the processor. The processor mentioned above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a ready programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Each method, step and logic block disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0092] The computer program product of the readable storage medium provided by the embodiment of the present application comprises a computer readable storage medium storing program codes, and the program codes comprise instructions for executing the method described in the foregoing method embodiments.

[0093] The functions, if realized in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of software products, which are stored in a storage medium and include instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0094] Finally, it should be noted that: the above-described embodiments are merely specific implementations of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same, the protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art within the technical range disclosed by the present application can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for predicting delay in logical synthesis segmentation based on graph neural networks, characterized in that, The method includes the following steps: Construct a logic synthesis circuit segmentation delay prediction dataset and divide the dataset into training and test sets; The dataset contains input data and label data; the input data contains circuits described by RTL Verilog and a standard cell library for mapping, and the label data is the maximum path delay value of each cut root node in the mapped circuit; Preprocess the input data and label data; Build a delay prediction model and train and test it using the preprocessed dataset; The delay prediction model includes a pointer attention-graph neural network module and a multilayer perceptron module. The pointer attention-graph neural network module is used to preprocess the input data, independently process the circuit diagram node features and standard cell library feature embeddings, and concatenate the processed features to obtain the segmented node feature embeddings. The multilayer perceptron module is used to receive the segmented node feature embeddings generated by the pointer attention-graph neural network module and regress the corresponding delay prediction value. The trained delay prediction model is used to predict the delay of each segment in the circuit to be synthesized.

2. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 1, characterized in that, The preprocessing includes the following steps: Convert the circuit described by RTL Verilog into an AIG format circuit; construct a directed acyclic graph G=(V,E) based on the AIG format circuit, where V is the set of nodes, including AND gate nodes and NOT gate nodes, and E is the set of edges, representing the connection relationship between nodes; Using each logical node in the directed acyclic graph as the root node, extract the logical cone region formed by its backpropagation closure, construct multiple cutting subgraphs, and create a cutting supernode for each cutting subgraph. The newly created cutting supernodes are used as new nodes in the directed acyclic graph to form a heterogeneous cut-level graph; structural feature embeddings and functional feature embeddings are constructed for each node in the heterogeneous cut-level graph and spliced ​​together to form the initial node feature embedding. The initial node embedding and corresponding label of each node in the heterogeneous cut-level graph are encapsulated into a graph neural network input data format.

3. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 2, characterized in that, The pointer attention-graph neural network module includes a circuit node feature processing submodule, a standard unit library feature processing submodule, and a feature enhancement submodule; The circuit node feature processing submodule is used to receive the initial node feature embedding of each node in the heterogeneous cutting level graph, and sequentially pass it through two graph convolutional blocks and one pooling layer to extract the local neighborhood information of the node and generate the initial cutting feature embedding. The standard unit library feature processing submodule is used to receive standard unit library feature embeddings, which are then passed through a first RMSNorm layer, a first linear transformation layer, a second RMSNorm layer, and a second linear transformation layer in sequence, and output standardized standard unit library feature embeddings. The feature enhancement submodule receives the initial feature embedding of the cut node and the standardized standard unit library feature embedding. It uses a pointer attention mechanism to dynamically establish the feature association between the cut node and the standard unit library, outputs the pointer attention enhanced feature, and then concatenates the initial feature embedding of the cut node and the pointer attention enhanced feature to form the final cut node feature embedding, which is used for delayed regression prediction of the subsequent multilayer perceptron module.

4. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 3, characterized in that, The graph convolutional block consists of one layer of graph convolution operation and one layer of activation function operation. The input of the first graph convolutional block is the initial node feature embedding, and the input of the second graph convolutional block is the activation result output by the first graph convolutional block. The pooling layer is used to perform a pooling operation on the feature embeddings of all nodes in the logical cone region corresponding to each cut node to obtain the preliminary feature embedding representation of the cut node.

5. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 3, characterized in that, The first and second RMSNorm layers have the same structure and both use root mean square normalization; both the first and second linear transformation layers use fully connected linear mapping.

6. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 2, characterized in that, The structural feature embedding includes node type, topology level, and fan-out number; the functional feature embedding includes the node's controllability index, observability index, and its type identifier in the circuit logic.

7. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 6, characterized in that, The node type is 0 or 1, where 0 represents an AND node and 1 represents a NOT node; the topology level refers to the number of nodes on the longest path from any main input to the node; the fan-out number refers to the number of outputs of the node.

8. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 1, characterized in that, The multilayer perceptron module includes a first linear layer, a first activation function layer, a first random deactivation layer, a second linear layer, a second activation function layer, a second random deactivation layer, a third linear layer, and a third activation function layer, which are cascaded together to output the predicted delay value of the cut.

9. An electronic device comprising a processor and a memory, characterized in that, The memory stores machine-executable instructions that can be executed by the processor to implement the method as described in any one of claims 1-8.

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