Multi-strategy-based time delay driving layer distribution method considering through hole column technology

Abstract

The invention relates to a multi-strategy-based time delay driving layer distribution method considering a through hole column technology, and the method comprises the steps: determining the initial wiring priority of a line network based on a multi-index initial sorting strategy, and constructing an initial layer distribution scheme for each line network; checking illegal line nets in the initial layer distribution scheme, and performing line clearing and redistribution after descending sorting according to time delay; allowing the violation line network with the time delay size in the top to use a through hole column and a non-default rule line, and updating the congestion cost of the grid edge by dynamically adjusting the historical cost strategy of the edge; the method comprises the following steps: screening a time sequence key line network, adjusting a layer allocation scheme of the time sequence key line network without considering congestion constraints, preferentially releasing low-delay wiring resources occupied by a non-time sequence key line network, allowing the time sequence key line network to use through hole columns and non-default rule lines, and performing line clearing and redistribution on illegal line networks after the congestion constraints are considered. And selecting an optimized layer allocation scheme. According to the method, indexes such as time delay in the design process can be effectively optimized, and a high-quality layer allocation result is obtained.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided design technology for integrated circuits, and specifically relates to a multi-strategy delay driving layer allocation method that considers through-hole pillar technology. Background Technology

[0002] With the development of advanced technologies, the scale of integrated circuits is constantly expanding, and the latency of nets is increasing, which has a significant impact on chip performance. Layer allocation algorithms, based on 2D routing schemes, rationally allocate the conductor segments of each net to various routing layers, connecting the conductors of adjacent routing layers through vias, thus obtaining a 3D routing scheme. Nets connect their pins through vias and conductors; therefore, their latency mainly consists of via latency and conductor latency. In advanced processes, non-default regular lines reduce resistance by increasing conductor width, thereby optimizing conductor latency. Through-hole pillar technology can further reduce via latency by lowering via resistance. Combining these two techniques can significantly reduce the overall net latency, thereby improving circuit performance; however, it consumes more routing resources, and excessive use may lead to congestion problems and deterioration of other performance indicators. How to balance the use of these two techniques with the rational allocation of routing resources, achieving good results while ensuring circuit performance, is a crucial issue in the layer allocation process. Summary of the Invention

[0003] The purpose of this invention is to provide a multi-strategy-based time-delay-driven layer allocation method that considers through-hole pillar technology. This method can effectively optimize indicators such as time delay in the design process and obtain high-quality layer allocation results.

[0004] To achieve the above objectives, the technical solution adopted by this invention is: a multi-strategy-based delay driving layer allocation method considering through-hole pillar technology, comprising the following steps:

[0005] (1) Delay-driven initial allocation phase: The initial routing priority of the network is determined based on a multi-index initial sorting strategy, and an initial layer allocation scheme is constructed for each network; the multi-index initial sorting strategy integrates the total path length of the network, the number of receivers and the number of turns, and calculates the network priority through preset weights;

[0006] (2) Consider the dismantling and redistribution stage of via pillars and non-default rule lines: check the illegal wire meshes in the initial layer allocation scheme, sort them in descending order of time delay, and then dismantle and redistribute them; allow the illegal wire meshes with the highest time delay to use via pillars and non-default rule lines, and update the congestion cost of the mesh edges by dynamically adjusting the historical cost strategy of the edges, iterating until the number of illegal wire meshes is less than the set number.

[0007] (3) Delay Refinement Stage of Time-Critical Nets: Screen time-critical nets, adjust their layer allocation scheme without considering congestion constraints, prioritize the release of low-latency cabling resources occupied by non-time-critical nets, allow time-critical nets to use via posts and non-default regular lines, and dismantle and reroute non-compliant nets after considering congestion constraints, and select the optimized layer allocation scheme.

[0008] Further, in step (1), the multi-index initial sorting strategy calculates the priority index of the network routing using the following formula, thereby determining the initial routing priority of the network:

[0009] order(n) = α × tpl n +β×sink n +γ×bend n

[0010] Where order(n) represents the priority index of the network cabling; the larger the order(n), the higher the cabling priority; tpl n The sink represents the total path length of net n. n Indicates the number of receivers, bend n This indicates the number of trace bends; α, β, and γ are set weight parameters.

[0011] The rule for calculating the number of turns is as follows: starting from the wire segment connected to the transmitter, if the direction of the current wire segment is not the same as the direction of the next wire segment connected to it, it is counted as 1 turn; if the direction of the current wire segment is the same as the direction of the next wire segment connected to it, the number of turns is counted as 0.

[0012] Furthermore, in step (2), the network delay is calculated using the Elmore delay model, which is implemented as follows:

[0013] A path is defined as the set of wire segments connecting the transmitter to the receiver.

[0014] Calculate the time delay d(s) for each segment s in the wire network:

[0015]

[0016] Where R(s) represents the resistance of segment s, C(s) represents the capacitance of segment s, and C down (s) represents the downstream capacitance of segment s;

[0017] For each path from the receiver to the transmitter, its delay d(si) is the sum of the delays of all line segments along that path; the calculation formula is as follows:

[0018] d(si)=∑ s∈path(si) d(s)

[0019] Where path(si) represents the path from receiver si to transmitter;

[0020] The time delay d(N) of network N is the weighted sum of the time delays of all paths, and its calculation formula is as follows:

[0021] d(N)=∑ si∈S(N) a si ×d(si)

[0022] Where S(N) represents the set of receivers for the wire network N, a si This indicates the weight of the path where receiver si is located;

[0023] To ensure that the delay of each receiver is equally important, the corresponding weight of each receiver is set to the reciprocal of the number of receivers in the net N.

[0024] Further, in step (2), the dynamic adjustment strategy for the historical cost of an edge sets the historical cost of the edge to:

[0025]

[0026] Among them, h i e h represents the value after the i-th iteration. e The value of ρ is a user-defined parameter, tu(e i,j ) represents e i,j The number of tracks already used for wiring, ta(e) i,j ) represents e i,j The number of tracks available for wiring, e i,j This represents a specific edge in the wiring mesh, where i and j are the coordinate indices of the edge, used to identify the position of the edge in the mesh.

[0027] Further, in step (2), the through-hole post includes the following types: 2×1 type connecting parallel lines and default rule lines, 2×2 type connecting two pairs of parallel lines, 3×1 type connecting wide lines and default rule lines, 3×2 type connecting wide lines and parallel lines, and 3×3 type connecting two pairs of wide lines.

[0028] Further, in step (2), the non-default rule line includes:

[0029] Parallel lines: consist of two parallel default rule lines, occupying 2 wiring tracks;

[0030] Wide lines: Width and spacing are greater than the default regular lines, occupying 3 wiring tracks.

[0031] Furthermore, the following congestion constraints are followed during layer allocation to prevent excessive congestion in cabling areas:

[0032] TWO(S k )≤TWO(S)

[0033]

[0034] Where S represents the 2D global routing result, S k S represents the 3D global routing result obtained through layer allocation, k represents the number of layers in the routing space; TWO represents the total wire overflow, and MWO represents the maximum wire overflow; the above two formulas require that: the total wire overflow of the 3D global routing result does not exceed the total wire overflow of the 2D global routing result; the maximum wire overflow of the routing layer on any layer does not exceed the maximum wire overflow of the 2D global routing result.

[0035] Furthermore, the routing directions of adjacent wiring layers are orthogonal, meaning that in a multi-layer wiring space, k / 2 layers are used for horizontal conductors, and another k / 2 layers are used for vertical conductors.

[0036] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0037] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the steps of the above method.

[0038] Compared with existing technologies, this invention has the following advantages: This invention proposes a multi-strategy-based delay-driven layer allocation method considering via-pillar technology. This method proposes a multi-index initial sorting strategy, which standardizes the net sorting in the initial stage of routing through various factors, thereby ensuring a more reasonable net routing order. Simultaneously, it proposes a method for dismantling and rerouting non-default rule lines, considering via-pillars and non-default rule lines, thereby increasing routing flexibility and optimizing the use of via-pillars. Furthermore, considering the potential overflow of non-overflowing edges and their impact on subsequent layer allocation and routing, a dynamic adjustment strategy for the historical cost of edges is proposed. Finally, to further optimize the timing characteristics of the circuit, a timing-critical net delay optimization strategy is proposed, which optimizes the delay of timing-critical nets by adjusting the layer allocation scheme of timing-critical nets. This invention can ensure good circuit performance while rationally utilizing via-pillars and allocating routing resources, effectively optimizing indicators such as delay and via count in the design process, obtaining a high-quality layer allocation scheme, and improving circuit performance. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of a multi-layer wiring model in an embodiment of the present invention; where (a) is a 3D wiring area and (b) is a 3D wiring model;

[0040] Figure 2This is a schematic diagram illustrating the use of default and non-default rule lines to connect two pins in an embodiment of the present invention;

[0041] Figure 3 These are schematic diagrams illustrating different through-hole column structure types in embodiments of the present invention;

[0042] Figure 4 The implementation flowchart of the multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology in this embodiment of the invention is shown in the figure. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0044] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0045] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0046] This embodiment provides a multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology, including the following steps:

[0047] (1) Delay-driven initial allocation phase: The initial routing priority of the network is determined based on the multi-index initial sorting strategy, and an initial layer allocation scheme is constructed for each network; the multi-index initial sorting strategy integrates the total path length of the network, the number of receivers and the number of turns, and calculates the network priority through preset weights.

[0048] The multi-index initial sorting strategy calculates the priority index of the network routing using the following formula, thereby determining the initial routing priority of the network:

[0049] order(n) = α × tpl n +β×sink n +γ×bend n

[0050] Where order(n) represents the priority index of the network cabling; the larger the order(n), the higher the cabling priority; tpl n The sink represents the total path length of net n. nIndicates the number of receivers, bend n This indicates the number of trace bends; α, β, and γ are set weight parameters.

[0051] The rule for calculating the number of turns is as follows: starting from the wire segment connected to the transmitter, if the direction of the current wire segment is not the same as the direction of the next wire segment connected to it, it is counted as 1 turn; if the direction of the current wire segment is the same as the direction of the next wire segment connected to it, the number of turns is counted as 0.

[0052] (2) Consider the dismantling and redistribution stage of via posts and non-default rule lines: check the non-violation nets in the initial layer allocation scheme, sort them in descending order of latency, and then dismantle and redistribute them; allow the non-violation nets with the largest latency to use via posts and non-default rule lines, and update the congestion cost of the mesh edges by dynamically adjusting the historical cost strategy of the edges, iterating until the number of non-violation nets is less than the set number (0.5% of the number of bus nets).

[0053] Specifically, the network delay is calculated using the Elmore delay model, which is implemented as follows:

[0054] Define the set of wire network segments connecting the transmitter to the receiver as a path. Calculate the time delay d(s) for each segment s in the wire network:

[0055]

[0056] Where R(s) represents the resistance of segment s, C(s) represents the capacitance of segment s, and C down (s) represents the downstream capacitance of segment s.

[0057] For each path from the receiver to the transmitter, its delay d(si) is the sum of the delays of all line segments along that path; the calculation formula is as follows:

[0058] d(si)=∑ s∈path(si) d(s)

[0059] Where path(si) represents the path from receiver si to transmitter.

[0060] The time delay d(N) of network N is the weighted sum of the time delays of all paths, and its calculation formula is as follows:

[0061] d(N)=∑ si∈S(N) a si ×d(si)

[0062] Where S(N) represents the set of receivers for the wire network N, a si This represents the weight of the path where receiver si is located.

[0063] To ensure that the delay of each receiver is equally important, the corresponding weight of each receiver is set to the reciprocal of the number of receivers in the net N.

[0064] The strategy for dynamically adjusting the historical cost of edges sets the historical cost of edges to:

[0065]

[0066] Among them, h i e h represents the value after the i-th iteration. e The value of ρ is a user-defined parameter, tu(e i,j ) represents e i,j The number of tracks already used for wiring, ta(e) i,j ) represents e i,j The number of tracks available for wiring, e i,j This represents a specific edge in the wiring mesh, where i and j are the coordinate indices of the edge, used to identify the position of the edge in the mesh.

[0067] The through-hole posts include the following types: 2×1 type connecting parallel lines and default rule lines, 2×2 type connecting two pairs of parallel lines, 3×1 type connecting wide lines and default rule lines, 3×2 type connecting wide lines and parallel lines, and 3×3 type connecting two pairs of wide lines. The non-default rule lines include: parallel lines: composed of two parallel default rule lines, occupying 2 wiring tracks; wide lines: wider and with a greater spacing than default rule lines, occupying 3 wiring tracks.

[0068] (3) Delay Refinement Stage of Time-Critical Nets: Screen time-critical nets, adjust their layer allocation scheme without considering congestion constraints, prioritize the release of low-latency cabling resources occupied by non-time-critical nets, allow time-critical nets to use via posts and non-default regular lines, and dismantle and reroute non-compliant nets after considering congestion constraints, and select the optimized layer allocation scheme.

[0069] In this embodiment, the following congestion constraints are followed during layer allocation to prevent excessive congestion in the cabling area:

[0070] TWO(S k )≤TWO(S)

[0071]

[0072] Where S represents the 2D global routing result, S kS represents the 3D global routing result obtained through layer allocation, k represents the number of layers in the routing space; TWO represents the total wire overflow, and MWO represents the maximum wire overflow. The above two formulas require that: the total wire overflow of the 3D global routing result does not exceed the total wire overflow of the 2D global routing result; the routing directions of adjacent routing layers are orthogonal, that is, in a multi-layer routing space, k / 2 layers place horizontal wires, and another k / 2 layers place vertical wires; the maximum wire overflow of any routing layer does not exceed the maximum wire overflow of the 2D global routing result.

[0073] The relevant content of this method will be further explained below with reference to the accompanying drawings and specific embodiments.

[0074] 1. Multilayer routing model

[0075] Figure 1 This is a schematic diagram of the multi-layer wiring model in this embodiment. For example... Figure 1 As shown in (a), multi-layer routing regions are typically divided into uniformly sized global cells (g-cells). The gray areas represent obstacles on the routing layer that occupy routing resources. The routing directions of adjacent routing layers are orthogonal. Figure 1 In (b), adjacent mesh cells are connected by edges, and mesh cells from different layers are connected by vias. Typically, a g-cell is abstracted as a point during layer allocation, causing via congestion to be ignored. Therefore, it is necessary to restore the size of the g-cell to more comprehensively consider congestion and reduce overflow.

[0076] 2. Congestion constraints

[0077] To improve the matching degree between detailed routing and overall routing, and to ensure the routing feasibility of the layer allocation scheme, the layer allocation process should avoid placing more wires than its capacity on any single routing edge to prevent overflow. Therefore, the layer allocation method proposed in this invention prevents excessive congestion in the routing area by following the constraints, the congestion constraint formulas are as follows:

[0078] TWO(S k )≤TWO(S) (1)

[0079]

[0080] Where S represents the 2D global routing result, S kS represents the 3D global routing result obtained through layer allocation, k represents the number of layers in the routing space; TWO represents the total wire overflow, and MWO represents the maximum wire overflow. Formula (1) requires that the total wire overflow of the 3D global routing result does not exceed the total wire overflow of the 2D global routing result. At the same time, the routing directions of adjacent routing layers are orthogonal, that is, in the multi-layer routing space, k / 2 layers place horizontal wires, and another k / 2 layers place vertical wires. Therefore, Formula (2) requires that the maximum wire overflow of any layer does not exceed the maximum wire overflow of the 2D routing result, ensuring that the maximum wire overflow of the edge in the 2D global routing area can be evenly distributed to its corresponding edge in the 3D global routing area.

[0081] 3. Elmore Delay Model

[0082] This invention utilizes the high-fidelity delay assessment capability of the Elmore delay model to accurately calculate the delay of a wire network. Typically, a wire network consists of a transmitter and multiple receivers, where the transmitter has a drive resistor, and each receiver has its own specific load capacitance. The set of wire network segments connecting a transmitter to a receiver is defined as a path. The delay d(s) of each segment s in the wire network is calculated according to the Elmore delay model:

[0083]

[0084] Where R(s) represents the resistance of segment s, C(s) represents the capacitance of segment s, and C down (s) represents the downstream capacitance of segment s.

[0085] For each path from the receiver to the transmitter, its delay d(si) is the sum of the delays of all line segments along that path; the calculation formula is as follows:

[0086] d(si)=∑ s∈path(si) d(s) (4)

[0087] Where path(si) represents the path from receiver si to transmitter.

[0088] The time delay d(N) of network N is the weighted sum of the time delays of all paths, and its calculation formula is as follows:

[0089] d(N)=v si∈S(N) a si ×d(si) (5)

[0090] Where S(N) represents the set of receivers for the wire network N, a si This represents the weight of the path where receiver si is located.

[0091] To ensure that the delay of each receiver is equally important, the corresponding weight of each receiver is set to the reciprocal of the number of receivers in the net N.

[0092] 4. Non-default rule line technology

[0093] Figure 2 This is a schematic diagram illustrating the connection of two pins using default and non-default rule lines in this embodiment, as shown below. Figure 2 As shown in (a), when two pins are connected using the default rule line, the wire width is the width of the wiring track, occupying one wiring track. Figure 2 In diagram (b), a parallel line is used to connect two pins. A parallel line consists of two parallel lines following a default rule, thus requiring two routing tracks. For example... Figure 2 As shown in (c), when using a wide line to connect two pins, the width and spacing of the wide line are greater than the width and spacing of the default regular line, causing the two adjacent wiring tracks to be unable to accommodate other wires. Therefore, using a wide line requires occupying three wiring tracks.

[0094] 5. Through-hole column technology

[0095] Through-hole pillars are a key technology in advanced manufacturing processes, playing a crucial role in optimizing circuit timing characteristics. By reducing via resistance, through-hole pillars can decrease via delay, thereby optimizing circuit performance. However, increasing the number of conventional vias in a through-hole pillar consumes more routing resources. Therefore, when using through-hole pillars, a balance between timing optimization and routing feasibility must be considered. In this invention, through-hole pillars are permitted to be used in the top 5% of nets arranged in descending order of delay magnitude.

[0096] To ensure wiring accuracy, it is necessary to confirm the type of through-hole posts and conductors before using them or non-default regular lines. Through-hole posts typically come in five types, such as... Figure 3 As shown: Figure 3 In the middle (a), there is a 2×1 type through-hole column connecting the parallel lines and the default rule lines. Figure 3 (b) is a 2×2 type through-hole column connecting two pairs of parallel lines. Figure 3 (c) is a 3×1 type through-hole post connecting the wide line and the default rule line. Figure 3 (d) represents a 3×2 type through-hole column connecting the wide line and the parallel line, and Figure 3 (e) is a 3×3 type through-hole post connecting two pairs of wide lines. Through-hole post structures can be used in multi-layer wiring areas, such as... Figure 3 As shown in (f), 3×2 type via pins were used to connect wide lines and parallel lines when connecting high-level routing layers, and 2×1 type via pins were used to connect parallel lines and default regular lines when connecting low-level routing layers.

[0097] 6. A multi-strategy-based time-delay driving layer allocation method considering through-hole pillar technology.

[0098] (1) Overall process

[0099] like Figure 4 As shown, the multi-strategy-based delay-driven layer allocation method based on via post technology proposed in this invention is mainly divided into three stages: the initial allocation stage dominated by delay, the dismantling and rewiring stage considering via posts and non-default rule lines, and the delay refinement stage of time-critical wire mesh.

[0100] In the initial allocation phase, which is dominated by latency, an initial layer allocation scheme is constructed for each net based on the given 2D routing scheme. Since the net order in the standard test circuit is uncertain, routing in this order during layer allocation may adversely affect the routing results. Therefore, while prioritizing the use of routing resources for nets with higher latency, the number of bends in the 2D routing scheme is considered to determine a priority for the initial allocation of each net, thereby finding a layer allocation scheme with better overall performance in the initial stage.

[0101] The rewiring and redistribution phase, considering via posts and non-default regular lines, adjusts the initial layer allocation scheme by rewiring and redistributing all non-compliant nets to achieve a layer allocation scheme with less overflow. This phase first checks if the initial layer allocation scheme meets the congestion constraints of the conductors, thus identifying all non-compliant nets. All non-compliant nets are sorted in descending order of latency, and each non-compliant net is rewired and redistributed in this order. During the iteration process, the congestion of each mesh edge is reasonably evaluated to update its historical cost. Simultaneously, because via posts and NDR conductors can further reduce net latency, the top 5% of non-compliant nets with the lowest latency are allowed to use via posts and non-default regular lines during the rewiring and redistribution process. Since via posts and non-default regular lines require more routing resources and may cause routing congestion, the iteration termination condition is set to the number of non-compliant nets being less than 0.5% of the total number of nets. If the rewiring and redistribution layer allocation scheme does not meet the iteration termination condition, a new round of iterations is performed until the condition is met, at which point the next phase begins.

[0102] The delay refinement stage for timing-critical nets first selects the timing-critical nets from the layer allocation scheme. Without considering conductor congestion constraints, the layer allocation scheme for these timing-critical nets is adjusted to find a better scheme. Simultaneously, since timing-critical nets have a significant impact on circuit performance, non-default regular lines and via pins are used to further optimize delay. Next, considering conductor congestion constraints, non-compliant nets are dismantled and redone one by one, and the two layer allocation schemes are compared to select the better scheme.

[0103] (2) Initial ranking strategy for multiple indicators

[0104] During routing, prioritized nets have greater flexibility in selecting routing resources, thus offering a greater chance of achieving better layer allocation results. Especially in the initial stages of layer allocation, simply following the net order in a standard test circuit can not only increase the uncertainty of the initial routing results but also negatively impact subsequent optimization processes. To improve routing accuracy and flexibility and reduce net latency, nets with higher latency are typically prioritized for routing resources. However, the latency of each net is unknown before determining the 3D routing scheme. According to the Elmore latency model, latency calculation is closely related to the total path length of the net.

[0105] In multi-layer cabling, each cabling layer has a specific routing direction, and the routing directions of adjacent layers are usually orthogonal. Each bend in the net may require the use of vias to connect conductors from different cabling layers. Therefore, in addition to considering the total net path length, the number of bends and receivers in the net must be taken into account. The specific formula is as follows:

[0106] order(n) = α × tpl n +β×sink n +γ×bend n (6)

[0107] Where order(n) represents the priority index of the network cabling; the larger the order(n), the higher the cabling priority; tpl n The sink represents the total path length of net n. n Indicates the number of receivers, bend n This indicates the number of bends in the trace; α, β, and γ are set weight parameters, which are set to 5, 3, and 3 respectively in this embodiment.

[0108] The calculation of turns follows these rules: Given that the direction of the conductor segment is either horizontal or vertical. Starting from the conductor segment connected to the transmitter, if the direction of the current conductor segment is not the same as the direction of the next connected conductor segment, it is counted as 1 turn. If the current conductor segment and the next connected conductor segment have the same direction, the turn count is 0.

[0109] (3) Consider the method of re-lined through-hole columns and non-default rule lines.

[0110] Because the initial routing scheme may contain non-compliant nets, these nets need to be removed and redone to eliminate them. Via pins play a crucial role in optimizing net delay by reducing via resistance. Using via pins early in the process may provide more opportunities to explore different routing schemes and find better timing performance. Therefore, consider using via pins and non-default regular lines during the removal and redone phase.

[0111] (4) Dynamically adjust the historical cost strategy of the edge

[0112] Previous work has largely updated the historical cost of overflowing edges only when overflow occurs; that is, a larger historical cost is assigned only when an edge overflows, while the historical cost is set to zero when no overflow occurs. While this approach effectively controls the use of overflowing edges in subsequent iterations, it ignores the possibility that other edges that have not overflowed may overflow later. Furthermore, even if two routing schemes do not overflow, their impact on subsequent layer allocation and routing differs. Therefore, the historical cost of the edge is set to:

[0113]

[0114] Among them, h i e h represents the value after the i-th iteration. e The value of ; ρ is a user-defined parameter, set to 0.05; tu(e i,j ) represents e i,j The number of tracks already used for wiring, ta(e) i,j ) represents e i,j The number of tracks available for wiring, e i,j This represents a specific edge in the wiring mesh, where i and j are the coordinate indices of the edge, used to identify the position of the edge in the mesh.

[0115] (5) Delay optimization strategy for time-critical lines

[0116] The goal of the optimization phase is to further optimize the latency of time-critical networks by adjusting the layer allocation scheme. Therefore, this invention proposes a latency optimization strategy for time-critical networks. The basic idea of ​​this strategy is: when non-time-critical networks compete with time-critical networks for routing resources, priority is given to releasing low-latency routing resources occupied by non-time-critical networks, providing space for time-critical networks to be stripped and rerouted. Simultaneously, time-critical networks are allowed to use vias and NDR conductors, thereby reducing the overall latency.

[0117] This embodiment also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0118] This embodiment also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the steps of the above method.

[0119] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0120] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0121] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0122] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0123] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology, characterized in that, Includes the following steps: (1) Delay-driven initial allocation phase: Determine the initial routing priority of the network based on the multi-index initial sorting strategy, and construct an initial layer allocation scheme for each network. The multi-index initial sorting strategy integrates the total path length of the network, the number of receivers, and the number of turns, and calculates the network priority through preset weights. (2) Consider the dismantling and redistribution stage of via pillars and non-default rule lines: check the illegal wire meshes in the initial layer allocation scheme, sort them in descending order of time delay, and then dismantle and redistribute them; allow the illegal wire meshes with the highest time delay to use via pillars and non-default rule lines, and update the congestion cost of the mesh edges by dynamically adjusting the historical cost strategy of the edges, iterating until the number of illegal wire meshes is less than the set number. (3) Delay Refinement Stage of Time-Critical Nets: Screen time-critical nets, adjust their layer allocation scheme without considering congestion constraints, prioritize the release of low-latency cabling resources occupied by non-time-critical nets, allow time-critical nets to use via posts and non-default regular lines, and dismantle and reroute non-compliant nets after considering congestion constraints, and select the optimized layer allocation scheme.

2. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 1, characterized in that, In step (1), the multi-index initial sorting strategy calculates the priority index of the network routing using the following formula, thereby determining the initial routing priority of the network: order(n)=α×tpl n +β×sink n +γ×bend n Where order(n) represents the priority index of the network cabling; the larger the order(n), the higher the cabling priority; tpl n The sink represents the total path length of net n. n Indicates the number of receivers, bend n This indicates the number of trace bends; α, β, and γ are set weight parameters. The rule for calculating the number of turns is as follows: starting from the wire segment connected to the transmitter, if the direction of the current wire segment is not the same as the direction of the next wire segment connected to it, it is counted as 1 turn; if the direction of the current wire segment is the same as the direction of the next wire segment connected to it, the number of turns is counted as 0.

3. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 1, characterized in that, In step (2), the network delay is calculated using the Elmore delay model, which is implemented as follows: A path is defined as the set of wire segments connecting the transmitter to the receiver. Calculate the time delay d(s) for each segment s in the wire network: Where R(s) represents the resistance of segment s, C(s) represents the capacitance of segment s, and C down (s) represents the downstream capacitance of segment s; For each path from the receiver to the transmitter, its delay d(si) is the sum of the delays of all line segments along that path; the calculation formula is as follows: d(si)=∑ s∈path(si) d(s) Where path(si) represents the path from receiver si to transmitter; The time delay d(N) of network N is the weighted sum of the time delays of all paths, and its calculation formula is as follows: d(N)=∑ si∈S(N) and si ×d(si) Where S(N) represents the set of receivers for the wire network N, a si This indicates the weight of the path where receiver si is located; To ensure that the delay of each receiver is equally important, the corresponding weight of each receiver is set to the reciprocal of the number of receivers in the net N.

4. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 1, characterized in that, In step (2), the dynamic adjustment strategy for the historical cost of an edge sets the historical cost of the edge to: Among them, h i e h represents the value after the i-th iteration. e The value of ρ is a user-defined parameter, tu(e i,j ) represents e i,j The number of tracks already used for wiring, ta(e) i,j ) represents e i,j The number of tracks available for wiring, e i,j This represents a specific edge in the wiring mesh, where i and j are the coordinate indices of the edge, used to identify the position of the edge in the mesh.

5. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 1, characterized in that, In step (2), the through-hole post includes the following types: 2×1 type connecting parallel lines and default rule lines, 2×2 type connecting two pairs of parallel lines, 3×1 type connecting wide lines and default rule lines, 3×2 type connecting wide lines and parallel lines, and 3×3 type connecting two pairs of wide lines.

6. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 1, characterized in that, In step (2), the non-default rule lines include: Parallel lines: consist of two parallel default rule lines, occupying 2 wiring tracks; Wide lines: Width and spacing are greater than the default regular lines, occupying 3 wiring tracks.

7. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 1, characterized in that, The following congestion constraints are followed during layer allocation to prevent excessive congestion in cabling areas: TWO(S k )≤TWO(S) Where S represents the 2D global routing result, S k S represents the 3D global routing result obtained through layer allocation, k represents the number of layers in the routing space; TWO represents the total wire overflow, and MWO represents the maximum wire overflow; the above two formulas require that: the total wire overflow of the 3D global routing result does not exceed the total wire overflow of the 2D global routing result; the maximum wire overflow of the routing layer on any layer does not exceed the maximum wire overflow of the 2D global routing result.

8. The multi-strategy-based delay-driven layer allocation method considering through-hole pillar technology according to claim 7, characterized in that, The routing directions of adjacent wiring layers are orthogonal, that is, in a multi-layer wiring space, k / 2 layers are placed with horizontal conductors and another k / 2 layers are placed with vertical conductors.

9. A computer-readable storage medium storing a computer program, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1-8.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and when the processor executes the program, it implements the steps of the method according to any one of claims 1-8.

Images