Nonlinear analog network and real-time edge-preserving filtering image processing method

Abstract

The invention relates to a nonlinear analog network and a real-time edge-preserving filtering image processing method. The non-linear analog network comprises a plurality of non-linear resistor units arranged in a grid; and the plurality of fixed resistance resistors are connected with the vertexes of the grids. The real-time edge-preserving filtering image processing method based on the nonlinear analog network comprises the following steps: acquiring a first analog signal of an input image; setting the resistance value of a fixed resistance value resistor, and writing the optimized edge-preserving filtering parameter into the fixed resistance value resistor; and inputting the first analog signal into a signal input end of a non-linear analog network, performing edge-preserving filtering image processing on the first analog signal through the non-linear analog network, and obtaining a second analog signal after edge-preserving filtering processing at a signal output end of the non-linear analog network. The nonlinear analog network provided by the invention can realize nanosecond processing speed of million-pixel-level images, and the millisecond processing speed is greatly improved compared with the millisecond processing speed of the existing architecture.

Description

Technical Field

[0001] This invention relates to the field of machine vision technology, and in particular to a nonlinear analog network and a real-time edge-preserving filtering image processing method, which is applicable to tasks such as noise reduction, high dynamic range imaging, and detail enhancement, and is especially suitable for edge computing scenarios such as autonomous driving, real-time video processing, and AR / VR devices. Background Technology

[0002] Image filtering is a crucial technique in image preprocessing, used to improve image quality. Its effectiveness directly impacts the efficiency and reliability of subsequent image processing and analysis. Image filtering techniques can achieve various objectives, such as reducing image noise, sharpening images, and detecting image edges.

[0003] Edge-preserving filtering is widely used for tasks such as edge-preserving denoising, high dynamic range imaging, and detail enhancement. However, edge-preserving filtering algorithms (such as bilateral filtering) are computationally complex, making real-time processing of megapixel-level images difficult. Dimensional optimization of edge-preserving filtering algorithms is very challenging, involving a trade-off between accuracy and speed. Traditional GPU / FPGA architectures, limited by irregular memory access and nonlinear computation, can only process megapixel images in milliseconds. Neural network-based image processing algorithms rely on substantial computational resources, making it even more difficult to accelerate edge-preserving filtering. Existing patents (such as CN102509266B and CN111986116B) have accelerated the process through digital algorithm optimization, but are still limited by the physical bottlenecks of electronic devices.

[0004] Therefore, there is an urgent need for an image processing method to solve the problems of slow edge-preserving filtering speed and high computational resource consumption. Summary of the Invention

[0005] To address some or all of the problems in the prior art, this invention provides a nonlinear simulation network, which includes:

[0006] Multiple nonlinear resistive elements arranged in a grid; and

[0007] Multiple fixed-value resistors are connected to the vertices of the grid.

[0008] Furthermore, the grid comprises a plurality of polygonal grid cells, each of the plurality of nonlinear resistive cells forming one of the edges of the grid cell, and the plurality of fixed-value resistors being connected to one of the vertices of the grid cell.

[0009] Furthermore, the grid cell is an N-sided polygon, where N is an integer greater than 3.

[0010] Furthermore, the number of sides of the grid cells may be the same or different.

[0011] Furthermore, the nonlinear simulation network also includes:

[0012] The signal input terminal is connected to the floating end of the fixed-value resistor; and

[0013] The signal output terminal is connected to the other end of the fixed-value resistor.

[0014] Furthermore, the nonlinear resistor unit is composed of two MOS field-effect transistors in a back-to-back common-source structure, and the gate voltage of the MOS field-effect transistor is higher than its threshold voltage.

[0015] Furthermore, the IV characteristic of the nonlinear resistor unit causes the resistance value of the nonlinear resistor unit to increase as the input voltage increases.

[0016] Furthermore, each of the nonlinear resistor units includes at least one nonlinear resistor.

[0017] Furthermore, each of the fixed-value resistors has the same resistance value, and the resistance value of the fixed-value resistor is adjusted according to the processing task.

[0018] This invention also provides a real-time edge-preserving filtering image processing method based on a nonlinear analog network, the method comprising the following steps:

[0019] Acquire the first analog signal of the input image;

[0020] Set the resistance value of the fixed resistor, and write the optimized edge-preserving filter parameters into the fixed resistor; and

[0021] The first analog signal is input to the signal input terminal of the nonlinear analog network, and the first analog signal is subjected to edge-preserving filtering image processing through the nonlinear analog network. The second analog signal after edge-preserving filtering is obtained at the signal output terminal of the nonlinear analog network.

[0022] Furthermore, acquiring the first analog signal of the input image includes:

[0023] Obtain the initial digital signal of the input image;

[0024] The initial digital signal is converted into an analog signal using a digital-to-analog converter; and

[0025] The first analog signal is obtained by multiplying the analog signal by the amplification factor n.

[0026] Furthermore, after acquiring the second analog signal after edge-preserving filtering, the process further includes:

[0027] Divide the second analog signal by the amplification factor n to obtain the processed second analog signal;

[0028] The processed second analog signal is converted into an output digital signal using an analog-to-digital converter.

[0029] Furthermore, the number of signal input terminals and the number of signal output terminals are equal to the number of pixels in the input image.

[0030] Furthermore, the first analog signal is an analog voltage signal; and / or

[0031] The second analog signal is an analog voltage signal.

[0032] Furthermore, when the input image is in RGB format, the edge-preserving filtering image processing is performed on the R, G, and B channels respectively.

[0033] Furthermore, when the input image is an irregular resolution image:

[0034] The input image is segmented into multiple sub-images, each sub-image having a size smaller than or equal to the size of the nonlinear simulation network.

[0035] The edge-preserving filtering image processing is performed independently on each sub-image to obtain the processed sub-image; and

[0036] The processed sub-images are combined into the final output image.

[0037] The present invention also provides a computer-readable storage medium storing machine-readable instructions thereon, which, when executed by a processor, perform the steps of a real-time edge-preserving filtering image processing method based on a nonlinear analog network.

[0038] The technical solution provided by this invention has the following advantages:

[0039] 1. The nonlinear simulation network proposed in this invention can achieve nanosecond-level processing speed for megapixel-level images, which is six orders of magnitude faster than the millisecond-level processing speed of existing architectures, resulting in a significant improvement in processing speed.

[0040] 2. The nonlinear simulation network proposed in this invention has significantly reduced energy consumption compared to existing architectures.

[0041] 3. The real-time edge-preserving filtering image processing method based on nonlinear analog networks proposed in this invention outperforms traditional bilateral filtering algorithms in terms of peak signal-to-noise ratio (PSNR) and structural similarity index (SSIM), and the improvement is more significant as the noise level increases.

[0042] 4. The real-time edge-preserving filtering image processing method based on nonlinear analog networks proposed in this invention can achieve efficient parallel computing without external programming by using the adaptive convolution kernel of the nonlinear analog network, thus adapting to different image processing tasks.

[0043] 5. The real-time edge-preserving filtering image processing method based on nonlinear analog networks proposed in this invention supports the processing of regular and irregular images (such as non-square resolution). For images larger than the size of the nonlinear analog network, the original image can be divided into multiple sub-images for processing and then combined into the final output image. Attached Figure Description

[0044] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0045] Figure 1 A schematic diagram of the structure of a nonlinear simulation network according to an embodiment of the present invention is shown;

[0046] Figure 2 A schematic diagram of a nonlinear resistor unit according to an embodiment of the present invention is shown;

[0047] Figures 3A-3C A schematic diagram showing different IV characteristic curves of the nonlinear resistive unit of the present invention is provided.

[0048] Figures 4A-4D The diagram shows structural schematics of different arrangements of the nonlinear resistor unit of the present invention;

[0049] Figure 5 A flowchart illustrating a real-time edge-preserving filtering image processing method based on a nonlinear analog network according to an embodiment of the present invention is shown.

[0050] Figure 6 A flowchart illustrating another embodiment of the present invention is shown for a real-time edge-preserving filtering image processing method based on a nonlinear analog network.

[0051] Figure 7 A flowchart illustrating another embodiment of the present invention, a real-time edge-preserving filtering image processing method based on a nonlinear analog network, is shown; and

[0052] Figure 8 A flowchart illustrating a real-time edge-preserving filtering image processing method based on a nonlinear analog network, according to another embodiment of the present invention, is shown. Detailed Implementation

[0053] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0054] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0055] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0056] In this invention, the term "grid or vertex of grid cell" refers to the connection point of the terminals of nonlinear resistive cells that are connected to each other.

[0057] In this invention, the term "mesh" includes a plurality of polygonal mesh cells, each of a plurality of nonlinear resistive cells forming one of the edges of the mesh cell, and a plurality of fixed-value resistors connected to one of the vertices of the mesh cell.

[0058] In this invention, the term "N-gon" simply refers to a circuit formed by connecting N nonlinear resistor units together (N being an integer greater than 3), and does not necessarily conform to the strict definition of an N-gon. For example, when the nonlinear resistor units are curved, they may form circular, elliptical, or other curved shapes when connected together. Therefore, the N-gon grid cell covers all shapes of circuits formed by N nonlinear resistor units.

[0059] In one embodiment of the present invention, the mesh comprises a plurality of polygonal mesh cells, and the number of sides of different mesh cells may be the same or different. For example, some mesh cells have 3 sides, some mesh cells have 4 sides, or other numbers.

[0060] Figure 1 A schematic diagram of the structure of a nonlinear simulation network according to an embodiment of the present invention is shown. Figure 1 As shown, the nonlinear analog network includes: a nonlinear resistor unit 101, a fixed-value resistor 102, a signal input terminal 103, and a signal output terminal 104. For example... Figure 1 As shown, multiple nonlinear resistor elements 101 are arranged in a grid; multiple fixed-value resistors 102 are connected to the vertices of the grid, i.e., each vertex in the grid is connected to a fixed-value resistor 102; a signal input terminal 103 is connected to the floating terminal of the fixed-value resistors 102 (i.e., Figure 1 The square vertex in the diagram is connected; and the signal output terminal 104 is connected to the other end of the fixed resistance resistor 102 (i.e., Figure 1 Connect the circular vertices in the graph.

[0061] Figure 2 A schematic diagram of a nonlinear resistive unit according to an embodiment of the present invention is shown. Figure 2 As shown, two N-channel enhancement-mode MOS (metal oxide semiconductor) field-effect transistors form a nonlinear resistive unit, arranged in a back-to-back common-source configuration. Each pair of MOS field-effect transistors is activated by a single, applied, identical gate voltage. The MOS field-effect transistors operate in either the linear or saturation region, i.e., when the gate voltage is above the threshold voltage, and the channel width can be, for example, set to 1 μm. It should be noted that this arrangement ensures that regardless of which side of the MOS field-effect transistor pair is at a higher voltage, if one MOS field-effect transistor enters the saturation region, the other MOS field-effect transistor remains in the linear region. The IV characteristics of this MOS field-effect transistor pair are primarily controlled by the MOS field-effect transistor in the saturation region, exhibiting bidirectional pinch-off behavior.

[0062] Figures 3A-3C A schematic diagram of different IV characteristic curves of the nonlinear resistor unit of the present invention is shown, where I and V represent the current and voltage of the nonlinear resistor unit, respectively. Figure 3A The first type of IV characteristic curve for a nonlinear resistor unit is given. I and V satisfy the function I = a × tanh(V / b), where a represents 0.15 μA and b represents 0.02 V. Figure 3A The IV characteristic curve shown exhibits bidirectional pinch-off behavior, meaning that the resistance increases with increasing voltage. Figure 3B This is the second type of IV characteristic curve for a nonlinear resistive element, where I and V satisfy the function I = a × (V / b). 0.5 Where a represents 0.15μA and b represents 0.02V. Figure 3B The IV characteristic curve shown also shows that the resistance increases with increasing voltage. Figure 3C This is the third type of IV characteristic curve for a nonlinear resistive element, where I and V satisfy the functional equation. Where a represents 0.5A / V, b represents 0.167A / V, c represents 0.1A, and m represents 0.2V. Figure 3C The IV characteristic curve shown also shows that the resistance increases with increasing voltage.

[0063] In one embodiment of the present invention, the transistor used can be a thin-film transistor, a field-effect transistor (e.g., a MOS field-effect transistor), or other switching devices with similar characteristics. In one embodiment of the present invention, the nonlinear resistor unit can be composed of any device whose IV characteristic curve satisfies that the resistance value monotonically increases with increasing input voltage. It is worth noting that using two MOS transistors in a series is one way to achieve a monotonically increasing resistance value with increasing input voltage; other devices or combinations of devices can also be used to achieve this. In one embodiment of the present invention, each nonlinear resistor unit includes at least one nonlinear resistor.

[0064] Figures 4A-4D The diagram shows structural schematics of different arrangements of the nonlinear resistor unit of the present invention. Figure 4A The nonlinear resistor units shown are arranged in a square grid. Figure 4B and Figure 4C The nonlinear resistor unit shown is arranged in a triangular grid. Figure 4D The nonlinear resistor units shown are arranged in a hexagonal grid. In one embodiment of the invention, the nonlinear resistor units can be arranged in a grid of any regular shape, and the signal output terminals can be symmetrically arranged square grids.

[0065] In one embodiment of the present invention, each fixed-value resistor has the same resistance value, and the resistance value of the fixed-value resistor can be adjusted according to the processing task. It should be noted that, according to calculations and verification, even if different fixed-value resistors have different resistance values, it will not affect the performance of the nonlinear simulation network.

[0066] The conductivity of the nonlinear analog network provided by this invention can be dynamically adjusted according to the input voltage, enabling adaptive convolution operations without external programming. Unlike traditional static convolution architectures, the nonlinear analog network proposed in this invention can achieve parallel computation through physical input-output conversion, with each output pixel calculated using its unique adaptive convolution kernel. Leveraging the inherent parallel computing characteristics of the physical system, nanosecond-level processing speeds for megapixel-level images are achieved, which is six orders of magnitude faster than the most advanced existing architectures (processing speeds in milliseconds) and two orders of magnitude lower in energy consumption. Furthermore, its image processing performance metrics, Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM), are superior to traditional bilateral filtering algorithms. Experiments show that the nonlinear analog network provided by this invention improves the PSNR by more than 0.5 dB and the SSIM by more than 0.05 dB compared to traditional bilateral filtering. Moreover, the improvement becomes more significant with increasing noise. These effects are achieved through the greater degree of freedom in the convolution kernel of the nonlinear analog network compared to bilateral filtering.

[0067] The nonlinear simulation network provided by this invention has an architecture equivalent to an adaptive convolution operation. The signal input and output terminals can be derived using Kirchhoff's laws as follows:

[0068]

[0069] Among them, V O Indicates the output signal, V I Indicates the input signal. Let C0 represent the identity matrix, C0 represent the conductance of the fixed-value resistor, and L represent the anisotropic Laplace matrix containing nonlinear resistive elements. This equation can be viewed as a convolution. Each row in the diagram represents the convolution kernel corresponding to each data point. The convolution kernel adaptively changes due to the influence of nonlinear resistive units. Under dynamic lighting conditions, the adaptive convolution kernel can quickly respond to sudden changes in brightness because the circuit response time is on the order of nanoseconds.

[0070] This invention also provides a real-time edge-preserving filtering image processing method based on a nonlinear analog network. Figure 5 A flowchart illustrating a real-time edge-preserving filtering image processing method based on a nonlinear analog network according to an embodiment of the present invention is shown. Figure 5 As shown, the real-time edge-preserving filtering image processing method based on nonlinear simulation networks includes the following steps:

[0071] Step 510: Acquire the first analog signal of the input image. Acquiring the first analog signal of the input image includes: acquiring the initial digital signal of the input image; converting the initial digital signal into an analog signal using a digital-to-analog converter; and multiplying the analog signal by a magnification factor n to obtain the first analog signal. It should be noted that the magnification factor n is determined by the voltage range applied by the circuit. For example, when the voltage range applied by the circuit is 0-3V, the floating-point pixel values ​​of the image, which are in the range of 0-1, are multiplied by a magnification factor of 3. It is important to note that a larger magnification factor results in higher energy consumption and better processing performance; therefore, a trade-off must be made between processing performance and energy consumption.

[0072] The initial digital signal of the input image is usually the signal directly measured by the sensor, which contains noise that needs to be processed. Even in noisy environments, the real-time edge-preserving filtering image processing method provided in this invention still outperforms traditional bilateral filtering. As noise increases, bilateral filtering typically only modifies the parameter σ. r / σ n , where σ r σ represents the Gaussian kernel standard deviation of the range. n The standard deviation of the Gaussian kernel represents the convolution kernel size, which is fixed and has relatively low degrees of freedom. In contrast, the convolution kernel of a nonlinear simulation network has higher degrees of freedom, meaning its size changes with noise levels, resulting in better denoising performance in high-noise environments. Image processing performance evaluation metrics include Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM). Table 1 below shows the PSNR and SSIM values ​​after processing images with nonlinear simulation networks at different noise levels.

[0073] Table 1. PSNR and SSIM values ​​after bilateral filtering and nonlinear analog network processing.

[0074]

[0075] As shown in Table 1, for different noise levels in different images, the PSNR and SSIM values ​​after processing by the nonlinear simulation network are higher than those after processing by the existing bilateral filtering, indicating that the image processed by the nonlinear simulation network has better image quality than the existing bilateral filtering.

[0076] Step 520: Set the resistance value of the fixed resistor and write the optimized edge-preserving filter parameters into the fixed resistor. In one embodiment of the present invention, if the processing task is a noise reduction task, the resistance value of the fixed resistor is configured to 2MΩ; if the processing task is a high dynamic range imaging task, the resistance value of the fixed resistor is configured to 4MΩ. The fixed resistor here, like the spatial and temporal parameters of the bilateral filter, needs to be optimized through different tasks and different nonlinear resistor devices. The optimal parameters can be found through gradual debugging in practice; these optimal parameters are the optimized edge-preserving filter parameters. Typically, the resistance value range can be... Among them I s This represents the saturation current of the nonlinear resistive element. It should be noted that, according to calculations and verification, even differences in the resistance values ​​of different fixed-value resistors will not affect the performance of the nonlinear simulation network. In one embodiment of the invention, the resistance values ​​of different fixed-value resistors can typically vary within ±70% of the optimal value without affecting the performance of the nonlinear simulation network.

[0077] Step 530: Input the first analog signal into the signal input terminal of the nonlinear analog network, perform edge-preserving filtering image processing on the first analog signal through the nonlinear analog network, and obtain the second analog signal after edge-preserving filtering at the signal output terminal of the nonlinear analog network.

[0078] In one embodiment of the present invention, a plurality of first analog signals are input signals to be subjected to edge-preserving filtering, and a plurality of second analog signals are output signals after edge-preserving filtering is performed on the input signals; the first analog signals are analog voltage signals, and the second analog signals are analog voltage signals.

[0079] In one embodiment of the present invention, when the signal to be subjected to edge-preserving filtering is a digital signal, it is necessary to convert the digital signal into an analog signal through a digital-to-analog converter, and then perform calculations through a nonlinear analog network. For example, the multiple initial digital signals can be pre-stored digital signals or digital signals acquired in real time. The multiple initial digital signals are subjected to digital-to-analog conversion to obtain multiple first analog signals.

[0080] In one embodiment of the present invention, the number of signal input terminals and signal output terminals is equal to the number of pixels in the input image, that is, each pixel value corresponds one-to-one with the vertex of the nonlinear analog network, and the neighbor relationships in front, behind, left, and right remain the same.

[0081] In one embodiment of the present invention, after obtaining the second analog signal after edge-preserving filtering, the method further includes: dividing the second analog signal by the amplification factor n to obtain the processed second analog signal; and converting the processed second analog signal into an output digital signal using an analog-to-digital converter.

[0082] The real-time edge-preserving filtering image processing method based on nonlinear analog networks provided by this invention can obtain all the results of the edge-preserving filtering operation in a single calculation, which greatly reduces the number of analog-to-digital conversions and the time required in the process of acquiring the first analog signal, thereby reducing power consumption and improving calculation speed.

[0083] The real-time edge-preserving filtering image processing method based on nonlinear analog networks provided by this invention can be used for sensor data processing, for example, for camera system design, to directly process the acquired image signals, such as denoising, detail enhancement, image rendering, HDR tone mapping, etc., without the need for digital-to-analog conversion, further reducing the power consumption of the image processing process, improving the computing speed, and meeting the strict power consumption and area requirements of edge device design.

[0084] Figure 6 A flowchart illustrating another embodiment of the present invention, a real-time edge-preserving filtering image processing method based on a nonlinear analog network, is shown. Figure 6 As shown, steps 610 to 630 are the same as steps 510 to 530; in step 640, the difference between the first analog signal and the second analog signal is multiplied by a factor greater than 1, and then added to the second analog signal to obtain the target image, thereby achieving the effect of detail enhancement.

[0085] Figure 7 A flowchart illustrating another embodiment of the present invention, a real-time edge-preserving filtering image processing method based on a nonlinear analog network, is shown. Figure 7 As shown, steps 710 to 730 are the same as steps 510 to 530; in step 740, an edge extraction operation is performed on the difference between the first analog signal and the second analog signal, for example, using the Sobel operator, and then subtracted by the second analog signal to obtain the target image, thereby achieving the image rendering effect.

[0086] In one embodiment of the present invention, when the input image is in RGB format, edge-preserving filtering image processing is performed on the R, G, and B channels respectively. Figure 8This diagram illustrates a flowchart of a real-time edge-preserving filtering image processing method based on a nonlinear analog network according to another embodiment of the present invention. In step 810, a first analog signal of the input image is acquired, and the luminance channel value is extracted from the first analog signal. The luminance channel value is L = 0.299 × R + 0.587 × G + 0.114 × B, where R, G, and B are the values ​​of the three RGB channels in the input image, respectively. The input image is in RGB format; the luminance is initially calculated numerically using a weighted sum, and the R, G, and B channels are processed separately afterward. In step 820, a fixed-value resistor is set, and the optimized edge-preserving filtering parameters are written into the fixed-value resistor. For example, the fixed-value resistor can be set to R = 4 MΩ. In step 830, the L signal in the first analog signal is logarithmically processed and then input into the signal input terminal of the nonlinear analog network. The nonlinear analog network performs edge-preserving filtering image processing on the logarithmically processed first analog signal, and the edge-preserving filtered second analog signal is acquired at the signal output terminal of the nonlinear analog network. In step 840, the second analog signal V... O The signal is compressed and combined with the input signal L, resulting in: Where CF is defined as V I This represents the first analog signal after logarithmic processing. This result is then divided by L and multiplied by the original RGB image to obtain the target image, thereby achieving the HDR tone mapping effect.

[0087] In one embodiment of the present invention, when the input image is an irregular resolution image: the input image is divided into multiple sub-images, each sub-image having a size less than or equal to the size of the nonlinear simulation network; the edge-preserving filtering image processing is performed independently on each sub-image to obtain a processed sub-image; and the processed sub-images are combined into a final output image.

[0088] The nonlinear simulation network proposed in this invention can achieve nanosecond-level processing speeds for megapixel-level images, improving upon the millisecond-level processing speeds of existing architectures by six orders of magnitude, resulting in a significant speed increase and a substantial reduction in energy consumption. The real-time edge-preserving filtering image processing method based on the nonlinear simulation network proposed in this invention outperforms traditional bilateral filtering algorithms in both Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM) evaluation metrics, with the improvement becoming more pronounced as noise levels increase. Through the adaptive convolution kernel of the nonlinear simulation network, efficient parallel computation can be achieved without external programming, adapting to different image processing tasks. It supports the processing of both regular and irregular images (such as non-square resolution images). For images larger than the size of the nonlinear simulation network, the original image can be divided into multiple sub-images for processing and then combined into the final output image.

[0089] In one embodiment of the present invention, a computer-readable storage medium is also provided, on which machine-readable instructions are stored. When executed by a processor, the machine-readable instructions perform the following processing steps: acquiring a first analog signal of an input image; setting the resistance value of a fixed-value resistor and writing the optimized edge-preserving filtering parameters into the fixed-value resistor; inputting the first analog signal into the signal input terminal of a nonlinear analog network, performing edge-preserving filtering image processing on the first analog signal through the nonlinear analog network, and acquiring a second analog signal after edge-preserving filtering at the signal output terminal of the nonlinear analog network.

[0090] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined according to the technical solutions of the invention and their equivalents.

Claims

1. A nonlinear analog network configured to perform edge-preserving filtering operations, characterized in that, include: Multiple nonlinear resistive elements are arranged in a grid; as well as Multiple fixed-value resistors are connected to the vertices of the grid.

2. The nonlinear simulation network according to claim 1, characterized in that, The grid comprises a plurality of polygonal grid cells, each of the plurality of nonlinear resistive cells forming one of the edges of the grid cell, and the plurality of fixed-value resistors being connected to one of the vertices of the grid cell.

3. The nonlinear simulation network according to claim 2, characterized in that, The grid cell is an N-sided polygon, where N is an integer greater than 3.

4. The nonlinear simulation network according to claim 2, characterized in that, The number of sides of the grid cells may be the same or different.

5. The nonlinear simulation network according to claim 1, characterized in that, Also includes: The signal input terminal is connected to the floating end of the fixed resistance resistor; as well as The signal output terminal is connected to the other end of the fixed-value resistor.

6. The nonlinear simulation network according to claim 1, characterized in that, The nonlinear resistor unit is composed of two MOS field-effect transistors in a back-to-back common-source structure, and the gate voltage of the MOS field-effect transistor is higher than its threshold voltage.

7. The nonlinear simulation network according to claim 1, characterized in that, The IV characteristic of the nonlinear resistor unit causes its resistance value to increase as the input voltage increases.

8. The nonlinear simulation network according to claim 1, characterized in that, Each of the nonlinear resistor units includes at least one nonlinear resistor.

9. The nonlinear simulation network according to claim 1, characterized in that, Each of the fixed-value resistors has the same resistance value, and the resistance value of the fixed-value resistor is adjusted according to the processing task.

10. A real-time edge-preserving filtering image processing method based on the nonlinear analog network according to any one of claims 1-9, characterized in that, Includes the following steps: Acquire the first analog signal of the input image; Set the resistance value of the fixed resistor, and write the optimized edge-preserving filter parameters into the fixed resistor; and The first analog signal is input to the signal input terminal of the nonlinear analog network, and the first analog signal is subjected to edge-preserving filtering image processing through the nonlinear analog network. The second analog signal after edge-preserving filtering is obtained at the signal output terminal of the nonlinear analog network.

11. The real-time edge-preserving filtering image processing method based on a nonlinear analog network according to claim 10, characterized in that, The first analog signal for acquiring the input image includes: Obtain the initial digital signal of the input image; The initial digital signal is converted into an analog signal using a digital-to-analog converter; and The first analog signal is obtained by multiplying the analog signal by the amplification factor n.

12. The real-time edge-preserving filtering image processing method based on a nonlinear analog network according to claim 10, characterized in that, After acquiring the second analog signal after edge-preserving filtering, the process further includes: Divide the second analog signal by the amplification factor n to obtain the processed second analog signal; The processed second analog signal is converted into an output digital signal using an analog-to-digital converter.

13. The real-time edge-preserving filtering image processing method based on a nonlinear analog network according to claim 10, characterized in that, The number of signal input terminals and the number of signal output terminals are equal to the number of pixels in the input image.

14. The real-time edge-preserving filtering image processing method based on a nonlinear analog network according to claim 10, characterized in that, The first analog signal is an analog voltage signal; and / or The second analog signal is an analog voltage signal.

15. The real-time edge-preserving filtering image processing method based on a nonlinear analog network according to claim 10, characterized in that, When the input image is in RGB format, the edge-preserving filtering image processing is performed on the R, G, and B channels respectively.

16. The real-time edge-preserving filtering image processing method based on a nonlinear analog network according to claim 10, characterized in that, When the input image is an irregular resolution image: The input image is segmented into multiple sub-images, each sub-image having a size smaller than or equal to the size of the nonlinear simulation network. The edge-preserving filtering image processing is performed independently on each sub-image to obtain the processed sub-image; as well as The processed sub-images are combined into the final output image.

17. A computer-readable storage medium, characterized in that, It stores machine-readable instructions that, when executed by a processor, perform the steps of the method according to any one of claims 10-16.

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