Display driving circuit, chip and equipment

Abstract

The invention discloses a display driving circuit, a chip and equipment, and belongs to the technical field of electronics. The circuit comprises a power supply switching module used for adjusting the power supply voltage of an internal logic module, and the power supply voltage is used for supplying power to a unit connected with a bidirectional interface in the internal logic module; the internal logic module is used for receiving a first synchronous signal sent by the bidirectional interface, converting the voltage of the first synchronous signal from a first voltage to a second voltage to obtain a second synchronous signal and sending the second synchronous signal to the first unit, and the first voltage is determined based on the adjusted power supply voltage; or the internal logic module is used for receiving the third synchronizing signal sent by the first unit, converting the voltage of the third synchronizing signal from the second voltage to the first voltage to obtain a fourth synchronizing signal, and sending the fourth synchronizing signal to the bidirectional interface. Through adding the power supply switching module, the adjustment of the power supply voltage is realized, and the bidirectional interface supports receiving and transmitting of synchronous signals of various first voltages, so that the flexibility is high.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a display driver circuit, chip, and device. Background Technology

[0002] In the field of electronics, display drivers require bidirectional I / O (Input / Output). Bidirectional I / O means that the signal pins within the display driver can function as both input pins to receive signals and output pins to send signals. Therefore, there is a pressing need for a display driver circuit configured within the display driver to provide bidirectional I / O functionality. Summary of the Invention

[0003] This application provides a display driver circuit, chip, and device that can be used to provide bidirectional I / O functionality. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a display driving circuit, the circuit including a power switching module, an internal logic module, and a bidirectional interface;

[0005] The power switching module is used to adjust the power supply voltage of the internal logic module, and the power supply voltage is used to supply power to the unit in the internal logic module that is connected to the bidirectional interface.

[0006] The internal logic module is used to receive the first synchronization signal sent by the bidirectional interface, convert the voltage of the first synchronization signal from a first voltage to a second voltage to obtain a second synchronization signal, and send the second synchronization signal to the first unit. The first voltage is determined based on the adjusted power supply voltage.

[0007] Alternatively, the internal logic module is configured to receive the third synchronization signal sent by the first unit, convert the voltage of the third synchronization signal from the second voltage to the first voltage to obtain a fourth synchronization signal, and send the fourth synchronization signal to the bidirectional interface.

[0008] In one possible implementation, the internal logic module includes an output path and an input path;

[0009] The output path is used to receive the third synchronization signal sent by the first unit, convert the third synchronization signal into the fourth synchronization signal, and send the fourth synchronization signal to the bidirectional interface.

[0010] The input path is used to receive the first synchronization signal sent by the bidirectional interface, convert the first synchronization signal into the second synchronization signal, and send the second synchronization signal to the first unit.

[0011] In one possible implementation, the output path is configured with a voltage converter, an input buffer, and an output driver;

[0012] The input buffer is used to receive the third synchronization signal sent by the first unit and to perform signal protection on the third synchronization signal. The signal protection is used to suppress at least one of noise or voltage fluctuation.

[0013] The voltage converter is used to convert the protected third synchronization signal into the fourth synchronization signal;

[0014] The output driver is used to perform a drive enhancement on the fourth synchronization signal and send the enhanced fourth synchronization signal to the bidirectional interface.

[0015] In one possible implementation, the input path is configured with a first driving module, a level adjustment module, and a second driving module;

[0016] The first driver module is configured to receive a first synchronization signal sent by the bidirectional interface and perform driver enhancement on the first synchronization signal;

[0017] The level adjustment module is used to convert the enhanced first synchronization signal into the second synchronization signal;

[0018] The second drive module is used to output the second synchronization signal to the first unit.

[0019] In one possible implementation, the circuit further includes a first control module, which is used to adjust the operating mode of the output path, including an open-drain mode or a push-pull mode.

[0020] The output path is used to send the fourth synchronization signal to the bidirectional interface based on open-drain mode or push-pull mode.

[0021] In one possible implementation, the circuit further includes a second control module, which is used to set the operating mode of the display driver circuit to an input mode or an output mode. In the input mode, the internal logic module receives a first synchronization signal sent by the bidirectional interface, and in the output mode, the internal logic module sends the fourth synchronization signal to the bidirectional interface.

[0022] In one possible implementation, in the input mode, the input path in the internal logic module is enabled and the output path is disabled; in the output mode, the output path in the internal logic module is enabled and the input path is disabled; the input path is used to receive the first synchronization signal sent by the bidirectional interface; and the output path is used to send the fourth synchronization signal to the bidirectional interface.

[0023] The second control module includes an input control module and an output control module;

[0024] The input control module is used to receive an input enable signal and control the conduction of the input path in the internal logic module based on the input enable signal.

[0025] The output control module is used to receive an output enable signal and control the conduction of the output path in the internal logic module based on the output enable signal.

[0026] In one possible implementation, the internal logic module includes multiple output paths and multiple input paths, with different power supply voltages for different output paths and different power supply voltages for different input paths.

[0027] The power switching module is used to turn on any one of the multiple output paths based on a setting signal, and the power supply voltage of the output path turned on by different setting signals is different.

[0028] Alternatively, the power switching module is used to activate any one of the multiple input paths based on the setting signal, wherein the power supply voltage of the input path activated by different setting signals is different.

[0029] In a second aspect, a display driver chip is provided, the chip including the display driver circuit of the first aspect or any possible implementation of the first aspect.

[0030] Thirdly, a display device is provided, which includes the display driver chip shown in the second aspect.

[0031] The technical solution provided in this application brings at least the following beneficial effects:

[0032] A power switching module is incorporated into the display driver circuit, enabling adjustment of the supply voltage. The bidirectional interface supports the transmission and reception of various synchronization signals based on primary voltages, offering high flexibility. This bidirectional interface facilitates communication with external modules, allowing for the transmission and reception of synchronization signals regardless of the external module connected to the bidirectional interface. It is compatible with a wide range of external modules, ensuring high versatility. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1This is a schematic diagram of a display driver circuit provided by related technologies;

[0035] Figure 2 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of another display driving circuit provided in an embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the structure of a second control module provided in an embodiment of this application;

[0038] Figure 5 This is a schematic diagram of an output path structure provided in an embodiment of this application;

[0039] Figure 6 This is a schematic diagram of an input path provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram of the structure of a power switching module provided in an embodiment of this application;

[0041] Figure 8 This is a schematic diagram of an output path provided in an embodiment of this application;

[0042] Figure 9 This is a schematic diagram of the structure of an output control module and an output path provided in an embodiment of this application;

[0043] Figure 10 This is a schematic diagram of another display driving circuit provided in the embodiments of this application;

[0044] Figure 11 This is a schematic diagram of the structure of a first control module provided in an embodiment of this application;

[0045] Figure 12 This is a schematic diagram illustrating the conduction of another output path provided in an embodiment of this application;

[0046] Figure 13 This is a schematic diagram of signal level simulation provided in an embodiment of this application;

[0047] Figure 14 This is another signal level simulation diagram provided in the embodiments of this application;

[0048] Figure 15 This is another signal level simulation diagram provided in the embodiments of this application;

[0049] Figure 16 This is a schematic diagram of an input path structure provided in an embodiment of this application;

[0050] Figure 17 This is a schematic diagram illustrating the connection of another input path provided in an embodiment of this application;

[0051] Figure 18 This is yet another signal level simulation diagram provided in the embodiments of this application;

[0052] Figure 19 This is a schematic diagram illustrating another input path provided in an embodiment of this application;

[0053] Figure 20 This is a schematic diagram of another display driving circuit provided in the embodiments of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0055] With the development of electronic technology, more and more display devices are equipped with display driver circuits, such as smartphones, tablets, televisions, smartwatches, and car infotainment screens. Display driver circuits are used to transmit synchronization signals to achieve data synchronization between the sending and receiving ends. For example, the two ends of the display driver circuit are connected to the image source and the display panel. During the data exchange between the image source and the display panel, synchronization signals need to be transmitted through the display driver circuit to achieve timing synchronization.

[0056] In some cases, display driver circuits have bidirectional I / O (input / output) requirements. For example, in addition to sending the image signal to be displayed to the display panel, the image source also receives status information returned by the display panel. This status information indicates the power status of the display panel, whether there are any operational abnormalities, temperature status, or internal configuration status, etc. Therefore, the display driver circuit needs to send synchronization signals to both the display panel and the image source.

[0057] Figure 1 A display driving circuit is provided for related technologies. This circuit includes a MOS (Metal Oxide Semiconductor Field Effect Transistor), logic gates, diodes, resistors, a level adapter, and I / O ports. The MOS transistor utilizes its gate to control the drain-source switching, thereby achieving level conversion, signal driving, and direction control. Figure 1 In this circuit, the MOSFET adopts a complementary structure formed by the upper P and lower N structure, which belongs to the CMOS inverter. In the following text, the P-MOSFET will be referred to as the P-MOSFET and the N-MOSFET as the N-MOSFET. The complementary structure of the upper P and lower N can reduce the on-resistance, speed up the switching speed, and optimize the symmetry of high and low level drive.

[0058] Figure 1 The logic gates in the module include NAND and NOR gates, used to perform logical operations on the input signals to control the conduction of MOSFETs based on the operation results, thereby achieving bidirectional switching. Diodes provide unidirectional conduction and are used to suppress high voltage on the bus, protecting internal circuitry by quickly discharging when the I / O port is subjected to an impact, preventing circuit damage. Level adapters adjust the voltage of the input signals to adapt to different units, enabling signal transmission across units.

[0059] Figure 1 The IVOSS (Insulated Voltage Optimized Surge Earth System) is used for grounding. The power supply lines include VDDI (Voltage Drain Drain Input) and VDD (Voltage Drain Drain). VDDI provides 1.8V, and VDD provides 0.9V. VDD supplies power to the internal basic logic units in the display driver circuit, while VDDI supplies power to the I / O interfaces within the display driver circuit and the modules connected to those I / O interfaces.

[0060] The display driver circuit includes I / O ports on the right side and OEN, A, Y, and IEN interfaces on the left side. The OEN interface receives output enable signals, and the IEN interface receives input enable signals. These enable signals, including both output and input enable signals, are first sent to a logic gate via a CMOS inverter. After being processed by the logic gate, the switching direction of the MOS transistor connected to the logic gate's output is controlled to determine whether the I / O interface is used for receiving or transmitting signals.

[0061] Taking a low-level input enable signal as an example, the input enable signal received through the IEN interface is sent to a NAND gate on the input path of the Y port after passing through a CMOS inverter and level conversion. The NAND gate outputs an IN signal, which is then sent to an inverter on the input path. The inverter inverts the IN signal and outputs an INB signal. The INB and IN signals are then sent to a CMOS transmission gate formed by P-channel and N-channel transistors to control its conduction and cutoff. Whether the CMOS transmission gate is conducting affects whether the N-channel transistor is conducting. For example, with a low-level input enable signal, the IN signal output by the NAND gate controls the conduction of the CMOS transmission gate and the N-channel transistor. The signal received by the I / O interface can then be sent to the Y port through the N-channel transistor and continue to be transmitted downstream through the Y port, for example, sending a signal to an image source connected to the Y port. If the input enable signal is high, the IN signal output by the NAND gate will turn off the CMOS transmission gate and N transistor on the input path. In this case, even if the I / O interface receives a signal, the received signal cannot be sent to the Y port through the input path. Therefore, the I / O interface is not used to receive signals.

[0062] Taking a low-level output enable signal as an example, the output enable signal received through the OEN interface is sent to a NOR gate on the output path of port A via a MOSFET. Based on the low-level output enable signal, the NOR gate controls the MOSFET connected to the output side to turn on, pushing the signal received through port A to the I / O interface. Alternatively, the NOR gate controls the MOSFET connected to the output side to turn off based on the high-level output enable signal.

[0063] The OEN and IEN interfaces allow control over whether the display driver circuit operates in input or output mode, i.e., whether the I / O interface is used for input or output signals. However, Figure 1 The display driver circuit shown, while capable of bidirectional communication, does not support dual power supplies. For example, Figure 1 The display driver circuit and the units connected to the I / O interface in the display are all powered by 1.8V, and only support the transmission of synchronization signals adapted to 1.8V, resulting in low versatility. Furthermore, Figure 1 The display driver circuit shown is also not suitable for open-drain mode, for example, Figure 1 The output stage in the model is a push-pull structure, which does not meet the "open drain, external pull-up" requirement of the open-drain mode, and the hardware structure cannot support it.

[0064] This application provides a display driver circuit that supports multiple power supply voltages. See also... Figure 2 The display driving circuit includes a power switching module 01, an internal logic module 02, and a bidirectional interface 03. The display driving circuit is connected to a first unit via the internal logic module 02 and to a second unit via the bidirectional interface 03, for transmitting synchronization signals between the first and second units.

[0065] Figure 2 In this configuration, internal logic module 02 is connected to bidirectional interface 03. It receives a first synchronization signal from bidirectional interface 03, converts the voltage of the first synchronization signal from a first voltage to a second voltage to obtain a second synchronization signal, and sends the second synchronization signal to the first unit. Alternatively, it receives a third synchronization signal from the first unit, converts the voltage of the third synchronization signal from a second voltage to a first voltage to obtain a fourth synchronization signal, and sends the fourth synchronization signal to bidirectional interface 03. Power switching module 01 is connected to internal logic module 02 and is used to adjust the power supply voltage of internal logic module 02. This power supply voltage is used to power the units in internal logic module 02 connected to bidirectional interface 03.

[0066] In the above embodiments, the internal logic module 02 can be used to send a fourth synchronization signal to the bidirectional interface 03 and also to receive a first synchronization signal sent by the bidirectional interface 03. This can be understood as the display driver circuit's operating modes including input mode and output mode. The relationship between the input mode, output mode, and internal logic module 02 is, for example, that the internal logic module 02 receives the first synchronization signal sent by the bidirectional interface 03 in input mode and sends a fourth synchronization signal to the bidirectional interface 03 in output mode. Therefore, the display driver circuit can also... Figure 3 The diagram shows a second control module 04, which is connected to an internal logic module 02 and is used to set the operating mode of the display driver circuit to input mode or output mode.

[0067] In one possible implementation, the internal logic module 02 includes an input path and an output path. The input path receives a first synchronization signal sent by the bidirectional interface 03, and the output path sends a fourth synchronization signal to the bidirectional interface 03. The description of the input and output paths will be provided below in conjunction with the accompanying drawings. In this case, in input mode, the input path of the internal logic module 02 is active, and the output path is deactivated; conversely, in output mode, the output path of the internal logic module 02 is active, and the input path is deactivated. Based on this, the second control module 04 can switch the operating mode of the display driver circuit by controlling the activation or deactivation of the input and output paths.

[0068] Figure 4 This is a schematic diagram of the structure of a second control module provided in an embodiment of this application. Figure 4 The second control module includes an output control module 041 and an input control module 042. The output control module 041 receives an output enable signal and controls the conduction of the output path in the internal logic module 02 based on the output enable signal. The input control module 042 receives an input enable signal and controls the conduction of the input path in the internal logic module 02 based on the input enable signal.

[0069] For example, when the input enable signal is at its first value and the output enable signal is at its second value, the input path is cut off and the output path is open, so the operating mode is output mode. When the input enable signal is at its third value and the output enable signal is at its fourth value, the input path is open and the output path is cut off, so the operating mode is input mode. The first and third values, and the second and fourth values, can be any different voltage levels. The following explanation uses the first and second values ​​as L (low) voltage levels and the third and fourth values ​​as H (high) voltage levels to illustrate the process of switching operating modes.

[0070] Figure 4 The output control module 041 includes VDD, which is a power network used to power the MOSFETs in the CMOS inverter; IOVSS, which is a ground reference network; OEN, which is the output enable signal; OENB, which is the intermediate signal of the output enable signal; and OENBB, which is the output signal of the output enable signal.

[0071] Figure 4 The CMOS inverter in this circuit is used to invert the output enable signal to enhance drive capability and adjust signal delay, etc. This CMOS inverter has a P-type upper and N-type lower structure. Figure 4 It includes multiple cascaded CMOS inverters for multi-stage inversion of the output enable signal. For example, when OEN is low, the upper P-channel transistor's gate is low and conducting, while the lower N-channel transistor's gate is low and turning off, pulling the output OENB high, which is a high-level signal. Similarly, the OENBB signal is a low-level signal.

[0072] Figure 5 The diagram illustrates multiple output paths included in the internal logic module 02. These are output path 1, formed by the path indicated by the solid line box and the path connected to the right side of the first row power switching module 01; and output path 2, formed by the path indicated by the solid line box and the path connected to the right side of the second row power switching module 01. For a description of output path 1 and output path 2, please refer to [link to documentation]. Figure 9 The relevant content is shown below. See also... Figure 5 Both the first row power switching module 01 and the second row power switching module 02 output NAND results based on OENB, and the output of the path marked by the solid box is also related to OENBB. That is, the output control module 041 can control the conduction and cutoff of the output path by outputting the OENB signal and the OENBB signal.

[0073] Since output path 1 and output path 2 share the path indicated by the solid line box, we will first use... Figure 5 Taking the path marked by the solid line box as an example, this illustrates the process of controlling the opening and closing of the output path through the output control module 041. Figure 5The solid-line box shown includes a cascaded CMOS inverter, a NOR gate, and a level adapter. The input of the NOR gate is connected to the output of the output control module 041, and is used to receive OENBB output by the output control module 041 based on the output enable signal OEN. This NOR gate is also used to receive the n_1 signal received through port A. The n_1 signal is the third synchronization signal to be transmitted in output mode, and can be a clock signal or other analog signals.

[0074] If both the OEN and OENBB signals are low, the NOR gate output will be the inverted form of the n_1 signal, meaning the path is open and the n_1 signal can be transmitted normally. If both the OEN and OENBB signals are high, the NOR gate output will always be low, regardless of the n_1 signal's state. This means the path is closed and the n_1 signal cannot be transmitted.

[0075] Again Figure 5 Taking the power switching module 01 as an example, if the OEN signal is low and the OENB signal is high, the output of the power switching module 01 through the NAND gate is the inverted signal of the 2-to-1 Mux (two-way selector). If the signal output by the two-way selector is an n_1 signal, then the signal output by the power switching module 01 is the inverted n_1 signal, the path is open, and the n_1 signal can be transmitted normally. If the OEN signal is high and the OENB signal is low, regardless of the state of the signal output by the two-way selector or whether the signal output by the two-way selector is an n_1 signal, the output of the NAND gate will always be a high-level signal, meaning that the path is cut off, and the n_1 signal cannot be transmitted. In summary, when the output enable signal OEN is low, both the output path and the path connecting the P-tube and the N-tube are open, allowing the transmission of the n_1 signal. However, when the output enable signal OEN is high, both the output path and the path connecting the P-tube and the N-tube are closed, meaning that even if the internal logic module 02 receives the n_1 signal through port A, it cannot send it to the bidirectional interface 03.

[0076] For example, Figure 4 The input control module 042 includes two control units, each controlling a different input path. Figure 4 The first control unit includes an inverter, a NAND gate, a CMOS inverter, and a level adapter. The SET signal is a setting signal used to switch the power supply voltage; the function of the SET signal will be explained below. The IEN signal refers to the input enable signal.

[0077] Figure 4Within the first control unit of the input control module 042, the SET signal undergoes a level flip after passing through an inverter, for example, flipping from high to low or from low to high. The flipped SET signal and IEN signal are then processed by a NAND gate for NAND logic. When the IEN signal is low, regardless of whether the flipped SET signal is high or low, the NAND gate output NAND result 1 is always low. This NAND result 1 is then flipped by a CMOS inverter to an inverted NAND result 1. The level adapter receives the inverted NAND result 1 through the IN interface and the INB interface, performs differential judgment on the received signals, and outputs a level signal VDDI_A located in the VDDI unit, which belongs to the first voltage. The level signal VDDI_A is then flipped by a CMOS inverter to become the VDDI_B signal. When the SET signal is low and the IEN signal is high, the VDDI_B signal is low and the VDDI_A signal is high.

[0078] Figure 4 The second control unit within the input control module 042 includes a NAND gate, a CMOS inverter, and a level adapter. After receiving the SET and IEN signals, the NAND gate performs NAND logic processing on them. For example, when the IEN signal is low, regardless of whether the SET signal is low or high, the NAND result 2 output by the NAND gate is always low. The NAND result 2 is then flipped by the CMOS inverter. The level adapter receives the NAND result 2 through the INB interface and, after receiving the flipped NAND result 2 through the IN interface, performs a differential judgment on the NAND result 2 and the flipped NAND result 2, outputting a level signal VDDIO_A in VDDIO mode. The level signal VDDIO_A is then flipped by the CMOS inverter to become the VDDIO_B signal. When the SET signal is low and the IEN signal is high, VDDIO_A is low and VDDIO_B is high.

[0079] Similar to the operation of the output control module 041, the input control module 042 can also be connected to the input path of the internal logic module 02 to control whether the input path runs according to the output signal. Figure 6 The input paths connected to the two control units in the input control module 042 are shown. Figure 6 In (1), the input control module 042 corresponds to Figure 4 The first row of control units in the input control module 042. The VDDI_B and VDDI_A signals output by the first row of control units are used for control. Figure 6 (1) The CMOS transmission gate (see solid circle marking) connected to the bidirectional interface 03 is turned on. Figure 6In (2), the input control module 042 corresponds to Figure 4 The second row of control units in the input control module 042. The VDDIO_B and VDDIO_A signals output by the second row of control units are used for control. Figure 6 (2) The CMOS transmission gate (see solid circle marking) connected to the bidirectional interface 03 is turned on.

[0080] For example, if the IEN signal is low, regardless of the SET signal, the NAND result 3 output by both NAND gates will be a high-level signal, VDDIO_A and VDDI_A will be low-level signals, and VDDIO_B and VDDI_B will be high-level signals. Figure 6 In (1) and (2), the second CMOS transmission gate not connected to the bidirectional interface 03 is turned on, while the two CMOS transmission gates connected to the bidirectional interface 03 are turned off. That is, neither input path can transmit the first synchronization signal sent through the bidirectional interface 03. However, if the IEN signal is a high-level signal, one of the two input paths will be turned on. The specific turn-on status can be based on the SET signal setting. The setting process of the SET signal will be explained below.

[0081] based on Figure 4 It can be seen that when both IEN and OEN signals are low, the input path is cut off and the output path is open, and the display driver circuit operates in output mode. When both IEN and OEN signals are high, the output path is cut off and the input path is open, and the display driver circuit operates in output mode.

[0082] In one possible implementation, in addition to selecting the input path or output path initiated in the internal logic module 02 through the second control module 04, the display driver circuit also switches the power supply voltage of the input path or output path based on the power switching module 01.

[0083] In one possible implementation, the internal logic module 02 includes multiple input paths and multiple output paths, with different power supply voltages for different output paths and different power supply voltages for different input paths. Specifically, the power supply voltage of the output path refers to the power supply voltage of the unit connected to the bidirectional interface 03 on the output path, and the power supply voltage of the input path refers to the power supply voltage of the unit connected to the bidirectional interface 03 on the input path. In this case, the power switching module 01 can activate any one of the multiple output paths based on a setting signal, with different power supply voltages for the output paths activated by different setting signals; alternatively, the power switching module 01 can activate any one of the multiple input paths based on a setting signal, with different power supply voltages for the input paths activated by different setting signals.

[0084] Figure 7This is a schematic diagram of the structure of a power switching module 01. Figure 7 The power switching module 01 includes a CMOS transmission gate, a two-way selector, and a NAND gate. Figure 7 IOVSS is used for grounding, and VDD is used for power supply. The 2to1 Mux B is a two-way selector used to receive the SET signal. Based on the SET signal, it selects the output signal to be sent to the NAND gate from the signals input from interface A and interface B, thus enabling the output path of the two-way selector to be activated.

[0085] Figure 7 In the middle, interface A of the two-way selector is connected to two transmission gates. The two transmission gates operate mutually exclusively; that is, when one transmission gate is on, the other is off. The on / off state of the transmission gates is controlled by the SEL signal. The SEL signal is used to control the operating mode of the output path. The process of controlling the operating mode can be found in the relevant description in the following embodiments. Figure 5 Taking the example of the process by which the power switching module 01 conducts an output path based on the SEL and SET signals, we can illustrate the process. Figure 5 The two 2-way selectors are 2to 1Mux and 2to 1Mux B, where B indicates inversion, meaning that the two 2-way selectors select signals received from different interfaces A and B as output signals based on the same SET signal.

[0086] Figure 5 The diagram shows two output paths, output path 1 and output path 2. Both output paths share a single N-transistor, and are connected via different P-transistors and bidirectional interface 03. Figure 5 Different P-type transistors are identified using dotted lines; each P-type transistor has a different supply voltage. Figure 5 In the diagram, the power supply voltage for the P-transistor in output path 1 is 1.8V, and the power supply voltage for the P-transistor in output path 2 is 1.2V. Therefore, the power supply voltage for output path 1 is 1.8V, and the power supply voltage for output path 2 is 1.2V.

[0087] See Figure 5 In the first row, the power switching module 01 is connected to two cascaded CMOS inverters. After the SEL interface receives the SEL signal, it outputs the SELB signal through the CMOS inverter. The SELB signal is then output as the SELBH signal through the CMOS inverter. The SELBH signal is sent to the two transmission gates of the power switching module 01 in the first row, the transmission gate in the power switching module 01 in the second row, and the NAND gate in the second row that is indirectly connected to the power switching module 01 through the CMOS inverter.

[0088] The power switching module 01 in the first row receives the SELBH signal, the n_1 signal, and the low-level signal LOW, in addition to the SELBH signal via the transmission gate. Optionally, the signal on the port connecting the two transmission gates is SELB, which is complementary to the SELBH signal, to control the input. Based on the high / low relationship between the SELBH and SELB signals, one of the two transmission gates is active at any given time. Figure 5 In the process, since the SEL signal is low, the SELB signal is high, and the SELBH signal is low, the first transmission gate in the power conversion module 01 is turned on, and the second transmission gate is turned off. The signal sent to the interface A of the two-way selector is the n_1 signal received by the first transmission gate.

[0089] Optionally, the two-way selector also receives a LOW signal through interface B, and then selects the output signal to be sent to the NAND gate based on the SET signal. For example, when the SET signal is low, interface A is selected, and the signal input from the two-way selector to the NAND gate is the n_1 signal received through interface A. After receiving the n_1 signal and the OENB signal, the NAND gate can perform a NAND operation on the n_1 signal and the OENB signal to obtain the NAND result 1. When the OENB signal is high, the NAND result 1 is the inverted n_1 signal. The n_1 signal can turn on the P transistor with a supply voltage of 1.8V on output path 1, that is, output path 1 configured by the first row power switching module 01 is turned on.

[0090] The power conversion module 01 in the second row, after receiving the SET signal, will process the SET signal and output the SET_O signal. The level of the SET_O signal is in phase with the SET signal, but the difference is that the driving capability of the SET_O signal is stronger than that of the SET signal.

[0091] The SET_O signal output from the two-way selector is sent to a NAND gate indirectly connected via a CMOS inverter and a transmission gate. After receiving the SET_O and SELBH signals, the NAND gate performs NAND processing on the SET_O and SELBH signals, outputting a signal BQ. This BQ signal is then inverted by the CMOS inverter and output as an AQ signal. Optionally, the CMOS inverter is connected to the transmission gate in the power conversion module 01 to input the AQ signal to the transmission gate.

[0092] Figure 5 In the process, since the SEL signal is low, the SELBH signal is also low, and the SET and SET_O signals are low, the SELBH and SET_O signals are high along with the unprocessed BQ signal, and the AQ signal sent from the CMOS inverter to the transmission gate is low.

[0093] In the power conversion circuit 01 in the second row, since the AQ and SELBH signals are low and the BQ signal is high, the first transmission gate is turned on. The signal input to interface A of the two-way selector is the n_1 signal, and the signal input to interface B is the LOW signal. Based on the SET signal being low, the signal sent by the two-way selector to the NAND gate is the LOW signal received through interface B. A NAND operation is performed on the LOW signal and the OENB signal to obtain NAND result 2. Since the LOW signal is low, regardless of the state of OENB, the NAND result 2 output by the power conversion module 01 in the second row is always a high-level signal, and the n_1 signal cannot be transmitted. Furthermore, since the signal output by the power switching module 01 is a high-level signal, after multi-stage inversion by the CMOS inverter and voltage conversion by the level adapter, this signal will cause the P-transistor with a supply voltage of 1.2V to... Figure 5 As shown, Off (cutoff) means that the output path 2 where the power conversion circuit 02 in the second row is located is in the cutoff state.

[0094] If the SET signal undergoes a level shift, the activated output path will also shift. See [link / reference]. Figure 8 , Figure 8 The SET signal switches from low level to high level. Figure 8 In the NAND gate, the SET and SET_O signals are high, the SEL and SELBH signals are low, and the SELB signal is high. The NAND result of the SELBH and SET_O signals, the BQ signal, remains high, and the AQ signal is low. In both power conversion modules 01, the first CMOS transmission gate is turned on, sending the n_1 signal to the two-way selector. The first row of two-way selectors, based on the high SET signal, selects the input signal of interface B as the output signal, outputting a low-level signal to the NAND gate. The NAND result 1 output by the NAND gate is a high-level signal. The second row of two-way selectors, based on the high SET signal, outputs the n_1 signal received through interface A to the NAND gate. The conduction status of the two P transistors is as follows: Figure 8 As shown.

[0095] based on Figure 5 and Figure 8 It can be seen that when the SET signal is low, the supply voltage of output path 1 is 1.8V, and when the SET signal is high, the supply voltage of output path 2 is 1.2V. Furthermore, Figure 5 and Figure 8 The purpose is to illustrate how the SET signal controls the conduction process of different output paths, not to limit the level of the SET signal and its corresponding supply voltage. For example... Figure 5 and Figure 8 As shown, other correspondences can also be used, which will not be repeated here.

[0096] In one possible implementation, the power switching module 01 can also switch the input path in input mode, see [reference]. Figure 6 , Figure 6 The inverter connected to bidirectional interface 03 on input path 1, as shown in (1), has a supply voltage of 1.8V. Figure 6 (2) shows that the inverter connected to the bidirectional interface 03 on input path 2 is supplied with a voltage of 1.2V. The inverters on both input path 1 and output path 2 are connected to two CMOS transmission gates. The connected CMOS transmission gates and inverters are located in the same cell; therefore, Figure 6 The power supply voltage for input path 1 is 1.8V, and the power supply voltage for input path 2 is 1.2V. Figure 6 CMOS transmission gates and Figure 5 The CMOS transmission gates are represented by different symbols. Figure 6 The diagram shows the transistor-level detail symbols of a CMOS transmission gate. Figure 5 The symbol shown is an abstract switch symbol for a CMOS transmission gate, but the two CMOS transmission gates have the same function: selectively passing signals.

[0097] Next, combine Figure 6 The description explains the operation of the power switching module 01 in input mode. Figure 6 The power switching module 01 and the input control unit 042 are integrated into the same module, namely... Figure 6 The NAND gate used to receive SET and IEN signals is used not only to control whether the input path is cut off according to the IEN signal, but also to select the input path to be turned on from multiple input paths according to the SET signal.

[0098] Figure 6 In this context, IN signal refers to the input signal, INB is the inverted version of IN signal, LOW signal refers to the ground signal, and VDDIO_O refers to the signal transmitted via VDDIO in VDDIO mode. Figure 6 (2) The output signal. Figure 6 In section (1), an inverter (see the elliptical dashed line) is also configured to output the received IN signal. This inverter inverts the IN signal to obtain the INB signal, which controls the conduction of the transmission gate. Considering that driving the inverter is difficult when the input voltage is relatively low, in VDDI mode, it can be understood that when the supply voltage is 1.8V, an INB signal is generated to reduce the on-resistance of the inverter. In VDDIO mode, it can be understood that when the supply voltage is 1.2V, see... Figure 6 (2) In input path 2, the level conversion module will be used to generate the INB_2 signal in order to reduce the on-resistance of the inverter.

[0099] Figure 6 In this context, the VDDI_A and VDDI_B signals are determined based on the IEN and SET signals. The IEN signal is the input enable signal, and its function will be explained below. When the SET signal is low and the IEN signal is high, Figure 6 In (1), the VDDI_A signal output through the level adapter is high level, and the VDDI_B signal obtained by inverting the VDDI_A signal is low level. Figure 6 In (2), the VDDIO_A signal output through the level adapter is low, and the VDDIO_B signal obtained by inverting the VDDIO_A signal is high.

[0100] exist Figure 6 When the VDDI_B signal is low and the VDDI_A signal is high in (1), Figure 6 (1) and the CMOS transmission gate connected to the bidirectional interface 03 (see Figure 6 The solid-line circular indicator in the diagram is on, while the CMOS transmission gate used to receive the LOW signal is off, meaning that input path 1 can normally transmit the first synchronization signal sent by bidirectional interface 03. Figure 6 In (2), since the VDDIO_A signal is low and the VDDIO_B signal is high, the CMOS transmission gate connected to the bidirectional interface 03 is turned off, and the CMOS transmission gate used to receive the LOW signal is turned on. That is, input path 2 cannot transmit the first synchronization signal sent by the bidirectional interface 03. It can be understood that if the SET signal is low, input path 1 is turned on and input path 2 is turned off. In this case, the power supply voltage of the input path is 1.8V.

[0101] If the SET signal is high and the IEN signal is high... Figure 6 In (1), the VDDI_A signal is low and the VDDI_B signal is high. The CMOS transmission gate connected to the bidirectional interface 03 is turned off, and the CMOS transmission gate receiving the LOW signal is turned on. Input path 1 cannot transmit the first synchronization signal sent by the bidirectional interface 03. Figure 6 In (2), the VDDIO_A signal is high and the VDDIO_B signal is low. Figure 6 In (2), the CMOS transmission gate connected to the bidirectional interface 03 is turned on to receive the first synchronization signal sent from the bidirectional interface 03. In this case, input path 1 is turned off, input path 2 is turned on, and the power supply voltage of the input path is 1.2V.

[0102] For example, after the display driving circuit controls any one path in the internal logic module 02 to be turned on through the second control module 04 and the power switching module 01, it can use the turned-on path and the bidirectional interface 03 to transmit a synchronization signal. If the turned-on path is an output path, the internal logic module 02 can use the output path to receive the third synchronization signal sent by the first unit, convert the third synchronization signal into a fourth synchronization signal, and send the fourth synchronization signal to the bidirectional interface 03.

[0103] The bidirectional interface 03 connects to the second unit, while the first and second units can be any two different units. Figure 8 In this configuration, the first unit is connected to Port A and is a 0.9V matched unit. The second unit is connected to bidirectional interface 03 and can be a 1.2V matched unit or a 1.8V matched unit. The first unit is, for example, an image source, and the second unit is, for example, a display panel.

[0104] For example, the output path is configured with a voltage converter, an input buffer, and an output driver. The input buffer is used to receive a third synchronization signal sent by the first unit and to perform signal protection on the third synchronization signal, the signal protection being used to suppress at least one of noise or voltage fluctuations; the voltage converter is used to convert the protected third synchronization signal into a fourth synchronization signal; the output driver is used to perform drive enhancement on the fourth synchronization signal and send the enhanced fourth synchronization signal to the bidirectional interface 03.

[0105] See Figure 9 The level adapter acts as a voltage converter on the output path. A cascaded CMOS inverter (marked with a solid box) on the left side of the level adapter serves as an input buffer, while a cascaded CMOS inverter (marked with a dashed box) on the right side serves as an output driver. The CMOS inverters (marked with a solid box) shape the third synchronization signal received through port A, adjusting its voltage to make its edges steeper and filtering out noise for a cleaner level. Simultaneously, the input buffers also initially enhance the driving capability of the third synchronization signal, such as compensating for signal attenuation and providing sufficient current or voltage margin for subsequent circuits.

[0106] The level adapter then converts the received third synchronization signal into the first voltage required by subsequent circuits, that is, converts the third synchronization signal into the fourth synchronization signal. Figure 9 In the diagram, the first voltage converted by the level adapters in the first row and the second row is different. The CMOS inverter connected to the right of the level adapter acts as an output driver to further enhance the driving capability, for example, by providing a larger pull-up or pull-down current for the fourth synchronization signal.

[0107] In one possible implementation, the output path in the internal logic module 02 also includes an output unit. The output driver connects to the bidirectional interface 03 through the output unit. That is, the output driver sends an enhanced fourth synchronization signal to the output unit, and the output unit sends the enhanced fourth synchronization signal to the bidirectional interface 03.

[0108] See Figure 9 The output unit includes a MOSFET, resistors, and diodes. The MOSFET controls the circuit's conduction and performs a high-current drive on the received enhanced fourth synchronization signal to provide sufficient drive current for the subsequent load, ensuring signal driving capability. Circularly marked resistors limit the loop current to prevent overcurrent damage to the MOSFET. Diodes are used for reverse protection, freewheeling, and clamping.

[0109] Figure 9 The operating mode of the output unit in the middle can be switched, for example by Figure 9 The push-pull mode shown is adjusted to open-drain mode. In this case, the display driver circuit still functions as before. Figure 10 The diagram shows a first control module 05, which is used to adjust the working mode of the output path. The working mode includes open-drain mode or push-pull mode. The output path can send a fourth synchronization signal to the bidirectional interface 04 based on the open-drain mode or push-pull mode.

[0110] Figure 11 This is a schematic diagram of a first control module 05 provided in an embodiment of this application. The first control module 05 includes cascaded CMOS inverters. After receiving the SEL signal, the first control module 05 performs two-stage inversion on the SEL signal to obtain the SELBH signal.

[0111] The SELBH signal, together with the SET signal, can control the conduction of MOSFETs with different supply voltages in the output unit. Optionally, the two P-tubes supplied by the display driver circuit will selectively conduct based on the setting of the SET signal when the SEL signal is low. If the SEL signal is high, both P-tubes will be off. In this case, the operating mode of the display driver circuit will switch from the push-pull mode of P-tube and N-tube operation to the open-drain mode that depends on the N-tube.

[0112] Figure 12 This is a schematic diagram illustrating the transmission of a fourth synchronization signal according to an embodiment of this application. Figure 12 When the OEN signal is low, the display driver circuit operates in output mode. When the SEL signal is high, the output unit in internal logic module 02 operates in open-drain mode, and the two P transistors connected to the N transistor are both off. The fourth synchronization signal output by the output driver is transmitted to bidirectional interface 03 through the N transistor.

[0113] Figure 12 In the above, the SEL signal is a high-level signal, the SELB signal is a low-level signal, the SELBH signal is a high-level signal, and the second transmission gate of the two CMOS transmission gates connected to the two-way selector is turned on. The signal received by the two-way selector through port A is a low-level signal. Based on the SET signal being a low-level signal, the two-way selector sends the low-level signal received through port A to the NOR gate, and the P transistor connected to the first row power switching module 01 is turned off.

[0114] In the second row, the power switching module 01, because the SELBH signal is high, and the SET signal and SET_O signal are low, the BQ signal output by the NAND gate is high and the AQ signal is low. The first transmission gate of the two CMOS transmission gates connected to the two-way selector is turned on. The signal received by the two-way selector through interface A is the n_1 signal. Based on the low SET signal, the two-way selector sends the low-level signal received through interface B to the NAND gate, and the P-transistor connected to the first row power switching module 01 is turned off.

[0115] If the SET signal is high, the SET_O signal is high, the SELBH signal is high, the NAND result signal output by the NAND gate is low, the AQ signal is high, the second CMOS transmission gate connected to the two-way selector is turned on, the signal received by the two-way selector through interface A is a low-level signal, based on the SET signal being a high-level signal, the two-way selector sends the low-level signal received through interface A to the NAND gate, and the P-transistor connected to the second row power switching module 01 is turned off.

[0116] This can be understood as follows: by setting the SEL signal to a high level, regardless of whether the SET signal is a low or high level, the P-tube connected to the power switching module 01 is turned off. The third synchronization signal on the output path cannot be sent to the bidirectional interface 03 through the P-tube, but is sent to the bidirectional interface 03 through the N-tube. This signal transmission mode based on the N-tube belongs to the open-drain mode.

[0117] For example, the open-drain mode defines the structure of a PAD, where a PAD refers to a unit circuit used for input or output, and the PAD includes the output unit in the above embodiments. Defining the structure of a PAD means that the open-drain mode defines the output unit as including only N-channel transistors for pull-down and excluding P-channel transistors for pull-up. For example... Figure 12 The N-transistor is conducting, while the P-transistors are all turned off, therefore Figure 12The display driver circuit shown operates in open-drain mode. In open-drain mode, there are two states: Hi-Z (high impedance state) and GND (ground). The state switching is based on the conduction status of the N-transistor. If the N-transistor is turned off, the PAD is disconnected from the ground wire and is in the high impedance state. If the N-transistor is not turned off, it is in the ground state.

[0118] Figure 13 This application provides a simulation result of an open-drain mode operation. The input indicates the third synchronization signal received through port A. The frequency of this third synchronization signal is 50 MHz (megahertz). Descriptions of the SEL, OEN, IEN, and SET signals can be found in the above embodiments and will not be repeated here. P Gate_VDDI indicates the signal at the gate of the P-transistor connected to the VDDI voltage, P Gate_VDDIO indicates the signal at the gate of the P-transistor connected to the VDDIO voltage, and NPAD indicates... Figure 12 The signal sent to the N-transistor is indicated by a dashed line. PAD indicates whether PAD is open or grounded. The N-transistor can be turned on or off according to the NPAD operation.

[0119] Figure 12 In the middle, based on the OEN signal being low, the display driver circuit operates in output mode; based on the SEL signal being low, the output unit in the internal logic module 02 operates in push-pull mode, and a P transistor connected to the N transistor is turned on. Figure 14 It shows Figure 5 The corresponding simulation results are as follows: when the supply voltage is 1.8V. Figure 15 It shows Figure 8 The corresponding simulation results for the supply voltage of 1.2V are as follows: Figure 14 and Figure 15 The meaning of each signal can be found in [reference]. Figure 13 The meaning of each signal shown.

[0120] In one possible implementation, the input path of the internal logic module 02 is configured with a first driving module, a level adjustment module, and a second driving module; the first driving module is used to receive a first synchronization signal sent by the bidirectional interface and perform driving enhancement on the first synchronization signal; the level adjustment module is used to convert the enhanced first synchronization signal into a second synchronization signal; and the second driving module is used to output the second synchronization signal to the first unit.

[0121] Figure 16In the diagram, the inverter, indicated by the dashed box, serves as the first driving module; the N-transistor and CMOS transmission gate, indicated by the solid box, serve as the level adjustment module; and the CMOS inverter and NOR gate, indicated by the dotted box, serve as the second driving module. After receiving the first synchronization signal sent through the CMOS transmission gate, the inverter inverts the first synchronization signal. The inverted first synchronization signal has a stronger driving capability than the received first synchronization signal; for example, the inverter can increase the current capability or reduce the output impedance.

[0122] The level adjustment module utilizes the threshold characteristic of a MOSFET to achieve level shifting, shifting the enhanced first synchronization signal from a first voltage to a second voltage to obtain the second synchronization signal. The second drive module shapes the received second synchronization signal using an NOR gate, and a CMOS inverter buffers the shaped second synchronization signal. The second drive module filters noise within the second synchronization signal, standardizes the high and low levels, and sends the adjusted second synchronization signal to the first unit via the Y port.

[0123] Figure 17 For another signal transmission schematic diagram provided in this application embodiment, see [link to schematic diagram]. Figure 17 When the OEN and IEN signals are high and the SET signal is low, the display driver circuit operates in input mode. The transmission path of the first synchronization signal received by the bidirectional interface 03 can be seen in the dashed box. (Regarding...) Figure 17 The simulation results of the input operations shown can be found in [reference]. Figure 18 , Figure 18 The Y indicator outputs the adjusted second synchronization signal through the Y port, and the PAD indicator outputs the signal through the Y port. Figure 17 The signals transmitted by the dashed lines shown are described in the above embodiments for the IEN and SET signals.

[0124] Similar to the output mode, the power supply voltage of the display driver circuit in the input mode can also include 1.8V or 1.2V. The difference is that the power supply voltage in the input mode is the power supply voltage of the first driver module on the input path. Figure 19 The diagram illustrates operation with a 1.2V supply voltage. The first synchronization signal, received via bidirectional interface 03 (shown by the dashed line), is sent to the NOR gate on the input path connected to the Y port. After logic processing, it is inverted by a CMOS inverter and then sent back to the processed second synchronization signal via the Y interface. For example, in a test scenario with a 50MHz frequency and VDDIO level standard, if the IEN and SET signals are high, the signal output through the Y port is a periodic digital signal waveform with high-low level switching, corresponding to a 50MHz frequency.

[0125] The examples above are intended to illustrate the operation of the display driver circuit, and not to limit the structure of the display driver circuit. Figure 20 Another display driving circuit provided in this application embodiment includes the power switching module 01, internal logic module 02, bidirectional interface 03, second control module 04 and first control module 05. Figure 20 The descriptions of the power switching module 01, bidirectional interface 03, and first control module 05 can be found in the embodiments described above. The input paths of the input control module and internal logic module 02 in the second control module 04 differ from those described in the embodiments above; examples will follow to illustrate this.

[0126] Taking the input control module in the first row as an example, when the IEN signal is high, if the SET signal is low, the inverted SET signal will be high. The NAND processing of the inverted SET signal and the IEN signal will produce a low-level signal. This low-level signal is then output as a high-level signal via a CMOS inverter. Figure 20 The signal received by the first driving module located in the first row is a high-level signal. In this case, the signal output by the NAND gate of the first driving module in the first row is the inverse signal of the first synchronization signal received based on the bidirectional interface 03.

[0127] Taking the input control module in the second row as an example, when the IEN signal is high and the SET signal is low, the signal generated by ANDing the IEN and SET signals is high. This high-level signal, after passing through a CMOS inverter, outputs a low-level signal. In this case, since the signal received by the NAND gate in the first driver module of the second row is low, regardless of the first synchronization signal received through the bidirectional interface 03, the signal output by the NAND gate will always be high. In this situation, the first synchronization signal is transmitted through the input path of the first driver module in the first row, which can be understood as the power supply voltage of the input path in the internal logic module 02 being 1.8V.

[0128] Taking the input control module in the first row as an example, if the IEN signal is high and the SET signal is high, the inverted SET signal is low. The AND-NOT operation between the inverted SET signal and the IEN signal results in a high-level signal. This high-level signal is then output as a low-level signal via a CMOS inverter. Figure 20 The first driving module located in the first row receives a low-level signal. In this case, regardless of the first synchronization signal received through the bidirectional interface 03, the NAND gate output signal of the first driving module in the first row will be a high-level signal.

[0129] Taking the input control module in the second row as an example, when the IEN signal is a high-level signal and the SET signal is a high-level signal, the signal generated by performing AND-NOT processing on the IEN and SET signals is a low-level signal. The signal output by the CMOS inverter from this low-level signal is a high-level signal. In this case, the signal output by the AND gate in the first drive module in the second row is the inverted signal of the first synchronization signal received through the bidirectional interface 03. The input path where the first drive module in the second row is located can realize the transmission of the first synchronization signal, which can be understood as the power supply voltage of the input path being 1.2V.

[0130] If the IEN signal is low, then regardless of whether the SET signal is high or low, Figure 20 The NAND gates in both input control modules output high-level signals, and the NAND gates in both first drive modules output high-level signals at all times.

[0131] In one possible implementation, the truth table of the display driving circuit provided in this application embodiment can be found in Table 1.

[0132] Table 1

[0133]

[0134]

[0135] In Table 1, 1 indicates a high level, 0 indicates a low level, IEN is the input enable signal, OEN is the output enable signal, SEL corresponds to the SEL signal in the above embodiments, and SET corresponds to the SET signal in the above embodiments. When the SEL signal is 1, the output path in the display driver circuit is in open-drain mode; when the SEL signal is 0, the output path in the display driver circuit is in push-pull mode. The SEL signal can be used to set the open-drain mode, causing the "PAD" to enter the Hi-Z (high impedance state) or GND (ground) state. The high impedance state corresponds to the open circuit in the above embodiments.

[0136] When the SET signal is 0, the supply voltage is 1.8V; when the SET signal is 1, the supply voltage is 1.2V. When both the input enable signal and the output enable signal are 0, the display driver circuit operates in output mode; when both the input enable signal and the output enable signal are 1, the display driver circuit operates in input mode.

[0137] In summary, the display driver circuit provided in this application embodiment achieves power supply voltage adjustment by adding a power switching module 01, and the internal logic module 02 achieves power supply separation, supporting operation under multiple voltages and having wide versatility. Furthermore, the output unit in the internal logic module 02 can also adjust the operating mode, operating in both push-pull and open-drain modes, offering high flexibility.

[0138] In an exemplary embodiment, this application also provides a display driver chip, which includes the display driver circuit mentioned in the above embodiments.

[0139] In an exemplary embodiment, this application also provides a display device, which includes the display driver chip mentioned in the above embodiments.

[0140] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0141] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0142] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A display driving circuit, characterized in that, The circuit includes a power switching module, an internal logic module, and a bidirectional interface. The display driving circuit is connected to the first unit through the internal logic module. The power switching module is used to adjust the power supply voltage of the internal logic module, and the power supply voltage is used to supply power to the unit in the internal logic module that is connected to the bidirectional interface. The internal logic module is used to receive the first synchronization signal sent by the bidirectional interface, convert the voltage of the first synchronization signal from a first voltage to a second voltage to obtain a second synchronization signal, and send the second synchronization signal to the first unit. The first voltage is determined based on the adjusted power supply voltage. Alternatively, the internal logic module is configured to receive the third synchronization signal sent by the first unit, convert the voltage of the third synchronization signal from the second voltage to the first voltage to obtain a fourth synchronization signal, and send the fourth synchronization signal to the bidirectional interface.

2. The circuit according to claim 1, characterized in that, The internal logic module includes output paths and input paths; The output path is used to receive the third synchronization signal sent by the first unit, convert the third synchronization signal into the fourth synchronization signal, and send the fourth synchronization signal to the bidirectional interface. The input path is used to receive the first synchronization signal sent by the bidirectional interface, convert the first synchronization signal into the second synchronization signal, and send the second synchronization signal to the first unit.

3. The circuit according to claim 2, characterized in that, The output path is equipped with a voltage converter, an input buffer, and an output driver; The input buffer is used to receive the third synchronization signal sent by the first unit and to perform signal protection on the third synchronization signal. The signal protection is used to suppress at least one of noise or voltage fluctuation. The voltage converter is used to convert the protected third synchronization signal into the fourth synchronization signal; The output driver is used to perform a drive enhancement on the fourth synchronization signal and send the enhanced fourth synchronization signal to the bidirectional interface.

4. The circuit according to claim 2, characterized in that, The input path is configured with a first driving module, a level adjustment module, and a second driving module. The first driver module is configured to receive a first synchronization signal sent by the bidirectional interface and perform driver enhancement on the first synchronization signal; The level adjustment module is used to convert the enhanced first synchronization signal into the second synchronization signal; The second drive module is used to output the second synchronization signal to the first unit.

5. The circuit according to any one of claims 2-4, characterized in that, The circuit also includes a first control module, which is used to adjust the working mode of the output path, including open-drain mode or push-pull mode. The output path is used to send the fourth synchronization signal to the bidirectional interface based on open-drain mode or push-pull mode.

6. The circuit according to any one of claims 1-4, characterized in that, The circuit also includes a second control module, which is used to set the operating mode of the display driver circuit to an input mode or an output mode. In the input mode, the internal logic module receives the first synchronization signal sent by the bidirectional interface, and in the output mode, the internal logic module sends the fourth synchronization signal to the bidirectional interface.

7. The circuit according to claim 6, characterized in that, In the input mode, the input path in the internal logic module is enabled and the output path is disabled. In the output mode, the output path in the internal logic module is enabled and the input path is disabled. The input path is used to receive the first synchronization signal sent by the bidirectional interface, and the output path is used to send the fourth synchronization signal to the bidirectional interface. The second control module includes an input control module and an output control module; The input control module is used to receive an input enable signal and control the conduction of the input path in the internal logic module based on the input enable signal. The output control module is used to receive an output enable signal and control the conduction of the output path in the internal logic module based on the output enable signal.

8. The circuit according to any one of claims 1-4, characterized in that, The internal logic module includes multiple output paths and multiple input paths. The power supply voltage of different output paths is different, and the power supply voltage of different input paths is also different. The power switching module is used to turn on any one of the multiple output paths based on a setting signal, and the power supply voltage of the output path turned on by different setting signals is different. Alternatively, the power switching module is used to activate any one of the multiple input paths based on the setting signal, wherein the power supply voltage of the input path activated by different setting signals is different.

9. A display driver chip, characterized in that, The display driver chip includes the display driver circuit as described in any one of claims 1-8.

10. A display device, characterized in that, The device includes the display driver chip as described in claim 9.

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