Pixel circuit and display device

Abstract

The invention provides a pixel circuit and a display device. The pixel circuit comprises a pixel driving circuit, N light-emitting elements and N control circuits, n is an integer greater than 1; n is a positive integer smaller than or equal to N; the nth control circuit controls the connection or disconnection between the first electrode of the nth light-emitting element and the second electrode of the nth light-emitting element under the control of the nth control data voltage and the control voltage; or the nth control circuit comprises an nth control transistor and an nth resistance adjusting circuit; the nth resistance adjusting circuit controls the equivalent resistance of the nth control transistor under the control of the nth control data voltage. In at least one embodiment of the invention, a plurality of pixels share one pixel driving circuit, so that the number of driving transistors on a current path is reduced, and the power consumption of the driving transistors is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and a display device. Background Technology

[0002] The display market is currently booming, and with the continued increase in consumer demand for various display products such as laptops, smartphones, TVs, tablets, smartwatches, and fitness trackers, even more new display products will emerge in the future. The related pixel circuits have high power consumption. Summary of the Invention

[0003] The main objective of this invention is to provide a pixel circuit and a display device that solve the problem of high power consumption in related pixel circuits.

[0004] In one aspect, embodiments of the present invention provide a pixel circuit, including a pixel driving circuit, N light-emitting elements, and N control circuits; N is an integer greater than 1; n is a positive integer less than or equal to N; m is a positive integer less than N;

[0005] The pixel driving circuit is used to generate a driving current and output the driving current through the first display node; the first electrode of the first light-emitting element is electrically connected to the first display node, the second electrode of the m-th light-emitting element is electrically connected to the first electrode of the (m+1)-th light-emitting element, and the second electrode of the N-th light-emitting element is electrically connected to the first voltage terminal.

[0006] The nth control circuit is electrically connected to the first electrode, the second electrode, the nth control data line, and the control voltage terminal of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the first electrode and the second electrode of the nth light-emitting element under the control of the nth control data voltage provided by the nth control data line and the control voltage provided by the control voltage terminal; or...

[0007] The nth control circuit includes an nth control transistor and an nth resistance adjustment circuit; the gate of the nth control transistor is electrically connected to the nth control node, the first terminal of the nth control transistor is electrically connected to the first terminal of the nth light-emitting element, and the second terminal of the nth control transistor is electrically connected to the second terminal of the nth light-emitting element; the nth resistance adjustment circuit is electrically connected to the nth control node and the nth control data line respectively, and is used to control the equivalent resistance of the nth control transistor under the control of the nth control data voltage provided by the nth control data line.

[0008] Optionally, the nth control circuit includes an nth on / off control circuit and an nth on / off control node control circuit;

[0009] The nth on / off control circuit is electrically connected to the nth on / off control node, the first electrode of the nth light-emitting element, and the second electrode of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the first electrode of the nth light-emitting element and the second electrode of the nth light-emitting element under the control of the potential of the nth on / off control node;

[0010] The control circuit of the nth on / off control node is electrically connected to the nth control data line, the nth on / off control node, and the control voltage terminal, respectively, and is used to control the potential of the nth on / off control node under the control of the nth control data voltage and the control voltage.

[0011] Optionally, the control circuit of the nth on / off control node includes an nth control data writing circuit and an nth energy storage circuit;

[0012] The nth control data writing circuit is electrically connected to the nth scan terminal, the nth control data line and the nth on / off control node, respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth on / off control node under the control of the nth scan signal provided by the nth scan terminal;

[0013] The first terminal of the nth energy storage circuit is electrically connected to the nth on / off control node, and the second terminal of the nth energy storage circuit is electrically connected to the control voltage terminal. The nth energy storage circuit is used to store electrical energy.

[0014] Optionally, the control circuit of the nth on / off control node further includes the nth first reset circuit;

[0015] The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth on / off control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth on / off control node under the control of the reset control signal provided by the reset control terminal.

[0016] Optionally, the control circuit of the nth on / off control node includes an nth control data writing circuit, an nth energy storage circuit, and an nth node control circuit;

[0017] The nth control data writing circuit is electrically connected to the nth scan end, the nth control data line and the nth node respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth node under the control of the nth scan signal provided by the nth scan end;

[0018] The first terminal of the nth energy storage circuit is electrically connected to the nth node, and the second terminal of the nth energy storage circuit is electrically connected to the control voltage terminal. The nth energy storage circuit is used to store electrical energy.

[0019] The nth node control circuit is electrically connected to the nth node, the nth on / off control node, the second voltage terminal, and the third voltage terminal, respectively, and is used to control the connection or disconnection between the nth on / off control node and the second voltage terminal, and to control the connection or disconnection between the nth on / off control node and the third voltage terminal under the control of the potential of the nth node.

[0020] Optionally, the control circuit of the nth on / off control node further includes the nth first reset circuit;

[0021] The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth node under the control of the reset control signal provided by the reset control terminal.

[0022] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a display light emission control circuit;

[0023] The display light emission control circuit is electrically connected to the light emission control terminal, the first display node, and the first electrode of the first light emission element, respectively, and is used to control the connection or disconnection between the first display node and the first electrode of the first light emission element under the control of the light emission control signal provided by the light emission control terminal.

[0024] Optionally, the nth control circuit further includes an nth display light-emitting control circuit; the nth on / off control node control circuit includes an nth control data writing circuit, an nth writing control circuit, an nth first reset circuit, an nth energy storage circuit, an nth compensation control circuit, and an nth set circuit;

[0025] The first electrode of the nth light-emitting element is electrically connected to the nth display node;

[0026] The nth display light emission control circuit is electrically connected to the light emission control terminal, the nth display node, and the first pole of the nth light emission element, and is used to control the connection or disconnection between the nth display node and the first pole of the nth light emission element under the control of the light emission control signal provided by the light emission control terminal;

[0027] The nth control data writing circuit is electrically connected to the nth scan end, the nth control data line and the nth node respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth node under the control of the nth scan signal provided by the nth scan end;

[0028] The nth write control circuit is electrically connected to the write control terminal, the control voltage terminal, and the nth node, respectively, and is used to write the control voltage to the nth node under the control of the write control signal provided by the write control terminal;

[0029] The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth on / off control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth on / off control node under the control of the reset control signal provided by the reset control terminal;

[0030] The first terminal of the nth energy storage circuit is electrically connected to the nth node, and the second terminal of the nth energy storage circuit is electrically connected to the nth on / off control node. The nth energy storage circuit is used to store electrical energy.

[0031] The nth compensation control circuit is electrically connected to the compensation control terminal, the nth on / off control node, and the second electrode of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the nth on / off control node and the second electrode of the nth light-emitting element under the control of the compensation control signal provided by the compensation control terminal;

[0032] The nth set circuit is electrically connected to the scanning terminal, the nth reference voltage terminal, and the first electrode of the nth light-emitting element, respectively, and is used to write the nth reference voltage provided by the nth reference voltage terminal into the first electrode of the nth light-emitting element under the control of the scanning signal provided by the scanning terminal.

[0033] Optionally, the control circuit of the nth on / off control node further includes the nth second reset circuit;

[0034] The nth second reset circuit is electrically connected to the reset control terminal, the second initial voltage terminal and the nth node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the nth node under the control of the reset control signal.

[0035] Optionally, the nth resistor adjustment circuit includes an nth data writing circuit and an nth control energy storage circuit;

[0036] The nth data writing circuit is electrically connected to the nth data writing control terminal, the nth control data line and the nth control node, respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth control node under the control of the nth data writing control signal provided by the nth data writing control terminal.

[0037] The nth control energy storage circuit is electrically connected to the nth control node and is used to maintain the potential of the nth control node.

[0038] Optionally, the nth resistor adjustment circuit includes an nth data writing circuit, an nth compensation control circuit, an nth control energy storage circuit, an nth first initialization circuit, an nth first display control circuit, and an nth second display control circuit;

[0039] The first terminal of the nth control transistor is electrically connected to the first terminal of the nth light-emitting element through the nth first display control circuit, and the second terminal of the nth control transistor is electrically connected to the second terminal of the nth light-emitting element through the nth second display control circuit;

[0040] The nth first display control circuit is electrically connected to the nth display control terminal, and is used to control the connection or disconnection between the first electrode of the nth control transistor and the first electrode of the nth light-emitting element under the control of the nth display control signal provided by the nth display control terminal;

[0041] The nth second display control circuit is electrically connected to the nth display control terminal, and is used to control the connection or disconnection between the second electrode of the nth control transistor and the second electrode of the nth light-emitting element under the control of the nth display control signal provided by the nth display control terminal;

[0042] The nth control energy storage circuit is electrically connected to the nth control node and is used to maintain the potential of the nth control node;

[0043] The nth data writing circuit is electrically connected to the nth data writing control terminal, the nth control data line and the first pole of the nth control transistor, respectively, and is used to write the nth control data voltage provided by the nth control data line into the first pole of the nth control transistor under the control of the nth data writing control signal provided by the nth data writing control terminal;

[0044] The nth compensation control circuit is electrically connected to the nth data write control terminal, the nth control node, and the second pole of the nth control transistor, respectively, and is used to control the connection or disconnection between the nth control node and the second pole of the nth control transistor under the control of the nth data write control signal;

[0045] The nth first initialization circuit is electrically connected to the initial control terminal, the first initial voltage terminal and the nth control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth control node under the control of the initial control signal provided by the initial control terminal.

[0046] Optionally, the nth control circuit includes an nth control transistor and an nth resistor adjustment circuit; the pixel circuit further includes a display control circuit.

[0047] The second electrode of the Nth light-emitting element is electrically connected to the first voltage terminal through the display control circuit;

[0048] The display control circuit includes a display switch circuit and a switch control circuit;

[0049] The display switch circuit is electrically connected to the switch control node, the second electrode of the Nth light-emitting element, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the second electrode of the Nth light-emitting element and the first voltage terminal under the control of the potential of the switch control node.

[0050] The switch control circuit is electrically connected to the switch control node, the light emission control terminal, and the pulse signal providing terminal, respectively, and is used to control the connection between the switch control node and the light emission control terminal or the pulse signal providing terminal.

[0051] Optionally, the nth on / off control circuit includes an nth first transistor, the nth control data writing circuit includes an nth second transistor, and the nth energy storage circuit includes an nth storage capacitor;

[0052] The gate of the nth first transistor is electrically connected to the nth on / off control node, the first electrode of the nth first transistor is electrically connected to the first electrode of the nth light-emitting element, and the second electrode of the nth first transistor is electrically connected to the second electrode of the nth light-emitting element.

[0053] The gate of the nth second transistor is electrically connected to the nth scan terminal, the first terminal of the nth second transistor is electrically connected to the nth control data line, and the second terminal of the nth second transistor is electrically connected to the nth on / off control node.

[0054] The first terminal of the nth storage capacitor is electrically connected to the nth on / off control node, and the second terminal of the nth storage capacitor is electrically connected to the control voltage terminal.

[0055] Optionally, the nth first reset circuit includes the nth third transistor;

[0056] The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth on / off control node.

[0057] Optionally, the nth control data writing circuit includes the nth second transistor, the nth energy storage circuit includes the nth storage capacitor, and the nth node control circuit includes the nth fourth transistor and the nth fifth transistor;

[0058] The gate of the nth second transistor is electrically connected to the nth scan terminal, the first electrode of the nth second transistor is electrically connected to the nth control data line, and the second electrode of the nth second transistor is electrically connected to the nth node;

[0059] The first terminal of the nth storage capacitor is electrically connected to the nth node, and the second terminal of the nth storage capacitor is electrically connected to the control voltage terminal.

[0060] The gate of the nth fourth transistor is electrically connected to the nth node, the first terminal of the nth fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the nth fourth transistor is electrically connected to the nth on / off control node.

[0061] The gate of the nth fifth transistor is electrically connected to the nth node, the first terminal of the nth fifth transistor is electrically connected to the nth on / off control node, and the second terminal of the nth fifth transistor is electrically connected to the third voltage terminal.

[0062] Optionally, the nth first reset circuit includes the nth third transistor;

[0063] The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth node.

[0064] Optionally, the display light-emitting control circuit includes a sixth transistor;

[0065] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first display node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the first light-emitting element.

[0066] Optionally, the nth display light emission control circuit includes the nth sixth transistor, the nth control data writing circuit includes the nth seventh transistor, the nth writing control circuit includes the nth eighth transistor, the nth first reset circuit includes the nth third transistor, the nth energy storage circuit includes the nth storage capacitor, the nth compensation control circuit includes the nth ninth transistor, and the nth set circuit includes the nth tenth transistor.

[0067] The gate of the nth sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the nth sixth transistor is electrically connected to the nth display node, and the second electrode of the nth sixth transistor is electrically connected to the first electrode of the nth light-emitting element.

[0068] The gate of the nth seventh transistor is electrically connected to the nth scan terminal, the first terminal of the nth seventh transistor is electrically connected to the nth control data line, and the second terminal of the nth seventh transistor is electrically connected to the nth node;

[0069] The gate of the nth eighth transistor is electrically connected to the write control terminal, the first terminal of the nth eighth transistor is electrically connected to the control voltage terminal, and the second terminal of the nth eighth transistor is electrically connected to the nth node.

[0070] The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth on / off control node.

[0071] The first end of the nth storage capacitor is electrically connected to the nth node, and the second end of the nth storage capacitor is electrically connected to the nth on / off control node.

[0072] The gate of the nth ninth transistor is electrically connected to the compensation control terminal, the first electrode of the nth ninth transistor is electrically connected to the nth on / off control node, and the second electrode of the nth ninth transistor is electrically connected to the second electrode of the nth light-emitting element.

[0073] The gate of the nth tenth transistor is electrically connected to the scanning terminal, the first terminal of the nth tenth transistor is electrically connected to the nth reference voltage terminal, and the second terminal of the nth tenth transistor is electrically connected to the first terminal of the nth light-emitting element.

[0074] Optionally, the nth second reset circuit includes the nth eleventh transistor;

[0075] The gate of the nth eleventh transistor is electrically connected to the reset control terminal, the first terminal of the nth eleventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the nth eleventh transistor is electrically connected to the nth node.

[0076] Optionally, the nth data writing circuit includes the nth twelfth transistor, and the nth control energy storage circuit includes the nth control capacitor;

[0077] The gate of the nth twelfth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth twelfth transistor is electrically connected to the nth control data line, and the second terminal of the nth twelfth transistor is electrically connected to the nth control node.

[0078] The first terminal of the nth control capacitor is electrically connected to the nth control node, and the second terminal of the nth control capacitor is electrically connected to the reference voltage terminal.

[0079] Optionally, the nth data writing circuit includes the nth twelfth transistor, the nth control energy storage circuit includes the nth control capacitor; the nth first initialization circuit includes the nth thirteenth transistor, the nth first display control circuit includes the nth fourteenth transistor, the nth second display control circuit includes the nth fifteenth transistor; and the nth compensation control circuit includes the nth sixteenth transistor.

[0080] The gate of the nth fourteenth transistor is electrically connected to the nth display control terminal, the first terminal of the nth fourteenth transistor is electrically connected to the first terminal of the nth control transistor, and the second terminal of the nth fourteenth transistor is connected or disconnected from the first terminal of the nth light-emitting element;

[0081] The gate of the nth fifteenth transistor is electrically connected to the nth display control terminal, the first terminal of the nth fifteenth transistor is electrically connected to the second terminal of the nth control transistor, and the second terminal of the nth fifteenth transistor is electrically connected to the second terminal of the nth light-emitting element.

[0082] The first terminal of the nth control capacitor is electrically connected to the nth control node, and the second terminal of the nth control capacitor is electrically connected to the reference voltage terminal.

[0083] The gate of the nth twelfth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth twelfth transistor is electrically connected to the nth control data line, and the second terminal of the nth twelfth transistor is electrically connected to the first terminal of the nth control transistor.

[0084] The gate of the nth sixteenth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth sixteenth transistor is electrically connected to the nth control node, and the second terminal of the nth sixteenth transistor is electrically connected to the second terminal of the nth control transistor.

[0085] The gate of the nth thirteenth transistor is electrically connected to the initial control terminal, the first terminal of the nth thirteenth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth thirteenth transistor is electrically connected to the nth control node.

[0086] Optionally, the display switch circuit includes a seventeenth transistor;

[0087] The gate of the seventeenth transistor is electrically connected to the switch control node, the first terminal of the seventeenth transistor is electrically connected to the second terminal of the Nth light-emitting element, and the second terminal of the seventeenth transistor is electrically connected to the first voltage terminal.

[0088] Optionally, the switch control circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a switch control capacitor;

[0089] The gate of the eighteenth transistor is electrically connected to the reset control terminal, the first terminal of the eighteenth transistor is electrically connected to the control data line, and the second terminal of the eighteenth transistor is electrically connected to the control node.

[0090] The gate of the nineteenth transistor is electrically connected to the switch control node, the first terminal of the nineteenth transistor is electrically connected to the light-emitting control terminal, and the second terminal of the nineteenth transistor is electrically connected to the switch control node.

[0091] The gate of the twentieth transistor is electrically connected to the switch control node, the first terminal of the twentieth transistor is electrically connected to the pulse signal providing terminal, and the second terminal of the twentieth transistor is electrically connected to the switch control node.

[0092] The first terminal of the switch control capacitor is electrically connected to the control node, and the second terminal of the switch control capacitor is electrically connected to the DC voltage terminal.

[0093] Optionally, the switch control circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a first switch control capacitor, and a second switch control capacitor;

[0094] The gate of the 21st transistor is electrically connected to the first reset control terminal, the first terminal of the 21st transistor is electrically connected to the first display control data line, and the second terminal of the 21st transistor is electrically connected to the first control node.

[0095] The gate of the 22nd transistor is electrically connected to the first switch control node, the first terminal of the 22nd transistor is electrically connected to the light-emitting control terminal, and the second terminal of the 22nd transistor is electrically connected to the switch control node.

[0096] The gate of the 23rd transistor is electrically connected to the second reset control terminal, the first terminal of the 23rd transistor is electrically connected to the second display control data line, and the second terminal of the 23rd transistor is electrically connected to the second control node;

[0097] The gate of the 24th transistor is electrically connected to the second switch control node, the first terminal of the 24th transistor is electrically connected to the pulse signal providing terminal, and the second terminal of the 24th transistor is electrically connected to the switch control node.

[0098] The first terminal of the first switch control capacitor is electrically connected to the first switch control node, and the second terminal of the first switch control capacitor is electrically connected to the DC voltage terminal.

[0099] The first end of the second switch control capacitor is electrically connected to the second switch control node, and the second end of the second switch control capacitor is electrically connected to the DC voltage terminal.

[0100] In a second aspect, embodiments of the present invention provide a display device including the pixel circuit described above.

[0101] In at least one embodiment of the present invention, multiple pixels share a single pixel driving circuit, thereby reducing the number of driving transistors in the current path and reducing the power consumption of the driving transistors. Attached Figure Description

[0102] Figure 1A This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0103] Figure 1B This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0104] Figure 2A This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0105] Figure 2B This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0106] Figure 3A This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0107] Figure 3B This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0108] Figure 4A This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0109] Figure 4B This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0110] Figure 5 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0111] Figure 6 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0112] Figure 7 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0113] Figure 8 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0114] Figure 9This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0115] Figure 10 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0116] Figure 11A yes Figure 10 The timing diagram of at least one embodiment of the pixel circuit shown;

[0117] Figure 11B yes Figure 10 A schematic diagram of the working state of at least one embodiment of the pixel circuit during the data writing stage;

[0118] Figure 11C yes Figure 10 A schematic diagram of the operating state of at least one embodiment of the pixel circuit during the initial time period of the light emission stage;

[0119] Figure 12 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0120] Figure 13 yes Figure 12 Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0121] Figure 14 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0122] Figure 15 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0123] Figure 16 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0124] Figure 17A yes Figure 16 The timing diagram of at least one embodiment of the pixel circuit shown;

[0125] Figure 17B yes Figure 16 Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0126] Figure 18A This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0127] Figure 18B This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0128] Figure 18C yes Figure 18B The timing diagram of at least one embodiment of the pixel circuit shown;

[0129] Figure 18D yes Figure 18B Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0130] Figure 19 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0131] Figure 20 yes Figure 19 The timing diagram of at least one embodiment of the pixel circuit shown;

[0132] Figure 21 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0133] Figure 22 yes Figure 21 The timing diagram of at least one embodiment of the pixel circuit shown;

[0134] Figure 23A This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0135] Figure 23B It is a waveform diagram of at least one embodiment of the control voltage;

[0136] Figure 23C It is a waveform diagram of at least one embodiment of the control voltage;

[0137] Figure 23D It is a waveform diagram of at least one embodiment of the control voltage;

[0138] Figure 23E It is a waveform diagram of at least one embodiment of the control voltage;

[0139] Figure 24A This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0140] Figure 24B This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0141] Figure 25A This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0142] Figure 25B This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0143] Figure 26 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0144] Figure 27 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0145] Figure 28 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0146] Figure 29 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0147] Figure 30 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0148] Figure 31 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0149] Figure 32 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0150] Figure 33A This is a schematic diagram of the first arrangement of the sub-pixels in the display area;

[0151] Figure 33B This is a schematic diagram of the second arrangement of sub-pixels in the display area;

[0152] Figure 33C This is a schematic diagram of the third arrangement of sub-pixels in the display area;

[0153] Figure 34 This is a circuit diagram of at least one embodiment of a pixel driving circuit;

[0154] Figure 35 This is a circuit diagram of at least one embodiment of a pixel driving circuit;

[0155] Figure 36 This is a circuit diagram of at least one embodiment of a pixel driving circuit. Detailed Implementation

[0156] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0157] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0158] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0159] The pixel circuit described in this embodiment of the invention includes a pixel driving circuit, N light-emitting elements, and N control circuits; N is an integer greater than 1; n is a positive integer less than or equal to N, and m is a positive integer less than N;

[0160] The pixel driving circuit is used to generate a driving current and output the driving current through the first display node; the first electrode of the first light-emitting element is electrically connected to the first display node, the second electrode of the m-th light-emitting element is electrically connected to the first electrode of the (m+1)-th light-emitting element, and the second electrode of the N-th light-emitting element is electrically connected to the first voltage terminal.

[0161] The nth control circuit is electrically connected to the first electrode, the second electrode, the nth control data line, and the control voltage terminal of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the first electrode and the second electrode of the nth light-emitting element under the control of the nth control data voltage provided by the nth control data line and the control voltage provided by the control voltage terminal; or...

[0162] The nth control circuit includes an nth control transistor and an nth resistance adjustment circuit; the gate of the nth control transistor is electrically connected to the nth control node, the first terminal of the nth control transistor is electrically connected to the first terminal of the nth light-emitting element, and the second terminal of the nth control transistor is electrically connected to the second terminal of the nth light-emitting element; the nth resistance adjustment circuit is electrically connected to the nth control node and the nth control data line respectively, and is used to control the equivalent resistance of the nth control transistor under the control of the nth control data voltage provided by the nth control data line.

[0163] In at least one embodiment of the present invention, N is used as an example of 2 or 3, but this is not a limitation; in specific implementation, N can be an integer greater than 1.

[0164] Optionally, the light-emitting element may be an organic light-emitting diode, a micro light-emitting diode, or a mini light-emitting diode, but is not limited thereto.

[0165] Optionally, the first voltage terminal can be a low voltage terminal, but is not limited thereto.

[0166] In at least one embodiment of the present invention, multiple pixels share a single pixel driving circuit, thereby reducing the number of driving transistors in the current path and reducing the power consumption of the driving transistors.

[0167] like Figure 1AAs shown, the pixel circuit described in this embodiment of the invention includes a pixel driving circuit 10, a first light-emitting element E1, a second light-emitting element E2, a third light-emitting element E3, a first control circuit 11, a second control circuit 12, and a third control circuit 13.

[0168] The pixel driving circuit 10 is used to generate driving current and output the driving current through the first display node NX1;

[0169] The first electrode of the first light-emitting element E1 is electrically connected to the first display node NX1; the second electrode of the first light-emitting element E1 is electrically connected to the first electrode of the second light-emitting element E2.

[0170] The second electrode of the second light-emitting element E2 is electrically connected to the first electrode of the third light-emitting element E3, and the second electrode of the third light-emitting element E3 is electrically connected to the first voltage terminal V1.

[0171] The first control circuit 11 is electrically connected to the first electrode of the first light-emitting element E1, the second electrode of the first light-emitting element E1, the first control data line DA, and the control voltage terminal SWP, respectively, and is used to control the connection or disconnection between the first electrode of the first light-emitting element E1 and the second electrode of the first light-emitting element E1 under the control of the first control data voltage provided by the first control data line DA and the control voltage provided by the control voltage terminal SWP.

[0172] The second control circuit 12 is electrically connected to the first electrode of the second light-emitting element E2, the second electrode of the second light-emitting element E2, the second control data line DB, and the control voltage terminal SWP, respectively, and is used to control the connection or disconnection between the first electrode of the second light-emitting element E2 and the second electrode of the second light-emitting element E2 under the control of the second control data voltage provided by the second control data line DB and the control voltage provided by the control voltage terminal SWP.

[0173] The third control circuit 13 is electrically connected to the first electrode of the third light-emitting element E3, the second electrode of the third light-emitting element E3, the third control data line DC, and the control voltage terminal SWP, respectively, and is used to control the connection or disconnection between the first electrode and the second electrode of the third light-emitting element E3 under the control of the third control data voltage provided by the third control data line DC and the control voltage provided by the control voltage terminal SWP.

[0174] exist Figure 1A In at least one embodiment of the pixel circuit shown, the three light-emitting elements are driven by a pixel driving circuit and three control circuits. The control circuit is used to control the light-emitting duration of the corresponding light-emitting elements to achieve different gray levels.

[0175] Figure 1AIn at least one embodiment of the pixel circuit shown, when in operation, the pixel driving circuit can provide a fixed driving current, and control the light emission duration through the control circuit to achieve different gray levels; or, the pixel driving circuit can provide different driving currents, combined with different light emission durations, to achieve gray level control.

[0176] exist Figure 1A In at least one embodiment of the pixel circuit shown, each control circuit and the corresponding light-emitting element can be regarded as a module. The modules of multiple sub-pixels are connected in series in the current path. Therefore, the total current flowing through each module is the same. The total current of each module is not affected by the driving of other modules. Therefore, each module can achieve grayscale control independently by driving current and duration.

[0177] At least one embodiment of the pixel circuit described in at least one embodiment of the present invention can also improve the poor exposure of the back panel LED (light-emitting diode) when it is in operation. When the light-emitting element is exposed, an effective voltage signal is provided through the corresponding control data line so that the first electrode of the second light-emitting element E2 is connected to the second electrode of the second light-emitting element E2, so that all the current flowing through the light-emitting element flows away through the corresponding transistor, thereby modifying the exposed light-emitting element into a dark spot.

[0178] like Figure 1B As shown, the pixel circuit described in this embodiment of the invention includes a pixel driving circuit 10, a first light-emitting element E1, a second light-emitting element E2, a first control circuit 11, and a second control circuit 12.

[0179] The pixel driving circuit 10 is used to generate driving current and output the driving current through the driving current output terminal IO.

[0180] The first electrode of the first light-emitting element E1 is electrically connected to the driving current output terminal IO; the second electrode of the first light-emitting element E1 is electrically connected to the first electrode of the second light-emitting element E2.

[0181] The second electrode of the second light-emitting element E2 is electrically connected to the first voltage terminal V1;

[0182] The first control circuit 11 is electrically connected to the first electrode of the first light-emitting element E1, the second electrode of the first light-emitting element E1, the first control data line DA, and the control voltage terminal SWP, respectively, and is used to control the connection or disconnection between the first electrode of the first light-emitting element E1 and the second electrode of the first light-emitting element E1 under the control of the first control data voltage provided by the first control data line DA and the control voltage provided by the control voltage terminal SWP.

[0183] The second control circuit 12 is electrically connected to the first electrode of the second light-emitting element E2, the second electrode of the second light-emitting element E2, the second control data line DB, and the control voltage terminal SWP, respectively, and is used to control the connection or disconnection between the first electrode of the second light-emitting element E2 and the second electrode of the second light-emitting element E2 under the control of the second control data voltage provided by the second control data line DB and the control voltage provided by the control voltage terminal SWP.

[0184] In at least one embodiment of the present invention, the nth control circuit includes an nth on / off control circuit and an nth on / off control node control circuit;

[0185] The nth on / off control circuit is electrically connected to the nth on / off control node, the first electrode of the nth light-emitting element, and the second electrode of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the first electrode of the nth light-emitting element and the second electrode of the nth light-emitting element under the control of the potential of the nth on / off control node;

[0186] The control circuit of the nth on / off control node is electrically connected to the nth control data line, the nth on / off control node, and the control voltage terminal, respectively, and is used to control the potential of the nth on / off control node under the control of the nth control data voltage and the control voltage.

[0187] In a specific implementation, the nth control circuit may include an nth on / off control circuit and an nth on / off control node control circuit; the nth on / off control circuit controls the connection or disconnection between the first electrode and the second electrode of the nth light-emitting element under the control of the potential of the nth on / off control node; the nth on / off control node control circuit controls the potential of the nth on / off control node under the control of the nth control data voltage and the control voltage.

[0188] like Figure 2A As shown, in Figure 1A Based on at least one embodiment of the pixel circuit shown,

[0189] The first control circuit includes a first on / off control circuit 111 and a first on / off control node control circuit 112;

[0190] The first on / off control circuit 111 is electrically connected to the first on / off control node N1, the first electrode of the first light-emitting element E1, and the second electrode of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first electrode of the first light-emitting element E1 and the second electrode of the first light-emitting element E1 under the control of the potential of the first on / off control node N1.

[0191] The first on / off control node control circuit 112 is electrically connected to the first control data line DA, the first on / off control node N1 and the control voltage terminal SWP, respectively, and is used to control the potential of the first on / off control node N1 under the control of the first control data voltage provided by the first control data line DA and the control voltage provided by the control voltage terminal SWP.

[0192] The second control circuit includes a second on / off control circuit 121 and a second on / off control node control circuit 122;

[0193] The second on / off control circuit 121 is electrically connected to the second on / off control node N2, the first electrode of the second light-emitting element E2, and the second electrode of the second light-emitting element E2, respectively, and is used to control the connection or disconnection between the first electrode of the second light-emitting element E2 and the second electrode of the second light-emitting element E2 under the control of the potential of the second on / off control node N2.

[0194] The second on / off control node control circuit 122 is electrically connected to the second control data line DB, the second on / off control node N2 and the control voltage terminal SWP, respectively, and is used to control the potential of the second on / off control node N2 under the control of the second control data voltage provided by the second control data line DB and the control voltage provided by the control voltage terminal SWP;

[0195] The third control circuit includes a third on / off control circuit 131 and a third on / off control node control circuit 132;

[0196] The third on / off control circuit 131 is electrically connected to the third on / off control node N3, the first electrode of the third light-emitting element E3, and the second electrode of the third light-emitting element E3, respectively, and is used to control the connection or disconnection between the first electrode of the third light-emitting element E3 and the second electrode of the third light-emitting element E3 under the control of the potential of the third on / off control node N3.

[0197] The third on / off control node control circuit 132 is electrically connected to the third control data line DC, the third on / off control node N3 and the control voltage terminal SWP, respectively, and is used to control the potential of the third on / off control node N3 under the control of the third control data voltage provided by the third control data line DC and the control voltage provided by the control voltage terminal SWP.

[0198] like Figure 2B As shown, in Figure 1B Based on at least one embodiment of the pixel circuit shown,

[0199] The first control circuit includes a first on / off control circuit 111 and a first on / off control node control circuit 112;

[0200] The first on / off control circuit 111 is electrically connected to the first on / off control node N1, the first electrode of the first light-emitting element E1, and the second electrode of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first electrode of the first light-emitting element E1 and the second electrode of the first light-emitting element E1 under the control of the potential of the first on / off control node N1.

[0201] The first on / off control node control circuit 112 is electrically connected to the first control data line DA, the first on / off control node N1 and the control voltage terminal SWP, respectively, and is used to control the potential of the first on / off control node N1 under the control of the first control data voltage provided by the first control data line DA and the control voltage provided by the control voltage terminal SWP.

[0202] The second control circuit includes a second on / off control circuit 121 and a second on / off control node control circuit 122;

[0203] The second on / off control circuit 121 is electrically connected to the second on / off control node N2, the first electrode of the second light-emitting element E2, and the second electrode of the second light-emitting element E2, respectively, and is used to control the connection or disconnection between the first electrode of the second light-emitting element E2 and the second electrode of the second light-emitting element E2 under the control of the potential of the second on / off control node N2.

[0204] The second on / off control node control circuit 122 is electrically connected to the second control data line DB, the second on / off control node N2 and the control voltage terminal SWP, respectively, and is used to control the potential of the second on / off control node N2 under the control of the second control data voltage provided by the second control data line DB and the control voltage provided by the control voltage terminal SWP.

[0205] In at least one embodiment of the present invention, the control circuit of the nth on / off control node includes an nth control data writing circuit and an nth energy storage circuit;

[0206] The nth control data writing circuit is electrically connected to the nth scan terminal, the nth control data line and the nth on / off control node, respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth on / off control node under the control of the nth scan signal provided by the nth scan terminal;

[0207] The first terminal of the nth energy storage circuit is electrically connected to the nth on / off control node, and the second terminal of the nth energy storage circuit is electrically connected to the control voltage terminal. The nth energy storage circuit is used to store electrical energy.

[0208] In a specific implementation, the control circuit of the nth on / off control node may include an nth control data writing circuit and an nth energy storage circuit; the nth control data writing circuit, under the control of the nth scan signal, writes the nth control data voltage into the nth on / off control node; the nth energy storage circuit controls the potential of the nth on / off control node according to the control voltage.

[0209] like Figure 3A As shown, in Figure 2A Based on at least one embodiment of the pixel circuit shown,

[0210] The control circuit of the first on / off control node includes a first control data writing circuit 211 and a first energy storage circuit 210;

[0211] The first control data writing circuit 211 is electrically connected to the first scanning terminal GA, the first control data line DA and the first on / off control node N1 respectively, and is used to write the first control data voltage provided by the first control data line DA into the first on / off control node N1 under the control of the first scanning signal provided by the first scanning terminal GA.

[0212] The first terminal of the first energy storage circuit 210 is electrically connected to the first on / off control node N1, and the second terminal of the first energy storage circuit 210 is electrically connected to the control voltage terminal SWP. The first energy storage circuit 210 is used to store electrical energy.

[0213] The second on / off control node control circuit includes a second control data writing circuit 221 and a second energy storage circuit 220;

[0214] The second control data writing circuit 221 is electrically connected to the second scanning terminal GB, the second control data line DB, and the second on / off control node N2, respectively, and is used to write the second control data voltage provided by the second control data line DB into the second on / off control node N2 under the control of the second scanning signal provided by the second scanning terminal GB.

[0215] The first terminal of the second energy storage circuit 220 is electrically connected to the second on / off control node N2, and the second terminal of the second energy storage circuit 220 is electrically connected to the control voltage terminal SWP. The second energy storage circuit 220 is used to store electrical energy.

[0216] The control circuit of the third on / off control node includes a third control data writing circuit 231 and a third energy storage circuit 230.

[0217] The third control data writing circuit 231 is electrically connected to the third scanning terminal GC, the third control data line DC and the third on / off control node N3 respectively, and is used to write the third control data voltage provided by the third control data line DC into the third on / off control node N3 under the control of the third scanning signal provided by the third scanning terminal GC.

[0218] The first terminal of the third energy storage circuit 230 is electrically connected to the third on / off control node N3, and the second terminal of the third energy storage circuit 230 is electrically connected to the control voltage terminal SWP. The third energy storage circuit 230 is used to store electrical energy.

[0219] exist Figure 3A In at least one of the embodiments shown, the first scanning end, the second scanning end, and the third scanning end can be the same scanning end, or the first scanning end, the second scanning end, and the third scanning end can be different scanning ends.

[0220] like Figure 3B As shown, in Figure 2B Based on at least one embodiment of the pixel circuit shown,

[0221] The control circuit of the first on / off control node includes a first control data writing circuit 211 and a first energy storage circuit 210;

[0222] The first control data writing circuit 211 is electrically connected to the first scanning terminal GA, the first control data line DA and the first on / off control node N1 respectively, and is used to write the first control data voltage provided by the first control data line DA into the first on / off control node N1 under the control of the first scanning signal provided by the first scanning terminal GA.

[0223] The first terminal of the first energy storage circuit 210 is electrically connected to the first on / off control node N1, and the second terminal of the first energy storage circuit 210 is electrically connected to the control voltage terminal SWP. The first energy storage circuit 210 is used to store electrical energy.

[0224] The second on / off control node control circuit includes a second control data writing circuit 221 and a second energy storage circuit 220;

[0225] The second control data writing circuit 211 is electrically connected to the second scanning terminal GB, the second control data line DB, and the second on / off control node N2, respectively, and is used to write the second control data voltage provided by the second control data line DB into the second on / off control node N2 under the control of the second scanning signal provided by the second scanning terminal GB.

[0226] The first terminal of the second energy storage circuit 220 is electrically connected to the second on / off control node N2, and the second terminal of the second energy storage circuit 220 is electrically connected to the control voltage terminal SWP. The second energy storage circuit 220 is used to store electrical energy.

[0227] exist Figure 3B In at least one embodiment shown, the first scanning end and the second scanning end can be the same scanning end, or the first scanning end and the second scanning end can be different scanning ends.

[0228] Optionally, the nth scanning end is a display scanning end; or, the nth control data line is a display data line.

[0229] In at least one embodiment of the present invention, the control circuit of the nth on / off control node further includes the nth first reset circuit;

[0230] The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth on / off control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth on / off control node under the control of the reset control signal provided by the reset control terminal.

[0231] In a specific implementation, the control circuit of the nth on / off control node may further include an nth first reset circuit; the nth first reset circuit, under the control of the reset control signal, writes the first initial voltage into the nth on / off control node.

[0232] like Figure 4A As shown, in Figure 3A Based on at least one embodiment of the pixel circuit shown,

[0233] The first on / off control node control circuit also includes a first first reset circuit 41;

[0234] The first reset circuit 41 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first on / off control node N1, respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the first on / off control node N1 under the control of the reset control signal provided by the reset control terminal RST.

[0235] The second on / off control node control circuit also includes a second first reset circuit 42;

[0236] The second first reset circuit 42 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second on / off control node N2 respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the second on / off control node N2 under the control of the reset control signal provided by the reset control terminal RST.

[0237] The control circuit of the third on / off control node also includes a third first reset circuit 43;

[0238] The third first reset circuit 43 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the third on / off control node N3, respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the third on / off control node N3 under the control of the reset control signal provided by the reset control terminal RST.

[0239] like Figure 4B As shown, in Figure 3B Based on at least one embodiment of the pixel circuit shown,

[0240] The first on / off control node control circuit also includes a first first reset circuit 41;

[0241] The first reset circuit 41 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first on / off control node N1, respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the first on / off control node N1 under the control of the reset control signal provided by the reset control terminal RST.

[0242] The second on / off control node control circuit also includes a second first reset circuit 42;

[0243] The second first reset circuit 42 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second on / off control node N2, respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the second on / off control node N2 under the control of the reset control signal provided by the reset control terminal RST.

[0244] Optionally, the control circuit of the nth on / off control node includes an nth control data writing circuit, an nth energy storage circuit, and an nth node control circuit;

[0245] The nth control data writing circuit is electrically connected to the nth scan end, the nth control data line and the nth node respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth node under the control of the nth scan signal provided by the nth scan end;

[0246] The first terminal of the nth energy storage circuit is electrically connected to the nth node, and the second terminal of the nth energy storage circuit is electrically connected to the control voltage terminal. The nth energy storage circuit is used to store electrical energy.

[0247] The nth node control circuit is electrically connected to the nth node, the nth on / off control node, the second voltage terminal, and the third voltage terminal, respectively, and is used to control the connection or disconnection between the nth on / off control node and the second voltage terminal, and to control the connection or disconnection between the nth on / off control node and the third voltage terminal under the control of the potential of the nth node.

[0248] Optionally, the second voltage terminal can be a high voltage terminal, and the third voltage terminal can be a low voltage terminal, but this is not a limitation.

[0249] like Figure 5 As shown, in Figure 2B Based on at least one embodiment of the driving circuit shown,

[0250] The first on / off control node control circuit includes a first control data writing circuit 211, a first energy storage circuit 210, and a first node control circuit 51;

[0251] The first control data writing circuit 211 is electrically connected to the scanning end GT, the first control data line DA and the first node NC1 respectively, and is used to write the first control data voltage provided by the first control data line DA into the first node NC1 under the control of the scanning signal provided by the scanning end GT.

[0252] The first terminal of the first energy storage circuit 210 is electrically connected to the first node NC1, and the second terminal of the first energy storage circuit 210 is electrically connected to the control voltage terminal SWP. The first energy storage circuit 210 is used to store electrical energy.

[0253] The first node control circuit 51 is electrically connected to the first node NC1, the first on / off control node N1, the second voltage terminal V2, and the third voltage terminal V3, respectively. It is used to control the connection or disconnection between the first on / off control node N1 and the second voltage terminal V2, and to control the connection or disconnection between the first on / off control node N1 and the third voltage terminal V3 under the control of the potential of the first node NC1.

[0254] The second on / off control node control circuit includes a second control data writing circuit 221, a second energy storage circuit 220, and a second node control circuit 52;

[0255] The second control data writing circuit 221 is electrically connected to the scanning end GT, the second control data line DB, and the second node NC2, respectively, and is used to write the second control data voltage provided by the second control data line DB into the second node NC2 under the control of the scanning signal provided by the scanning end GT.

[0256] The first end of the second energy storage circuit 220 is electrically connected to the second node NC2, and the second end of the second energy storage circuit 220 is electrically connected to the control voltage terminal SWP. The second energy storage circuit 220 is used to store electrical energy.

[0257] The second node control circuit 52 is electrically connected to the second node NC2, the second on / off control node N2, the second voltage terminal V2, and the third voltage terminal V3, respectively. It is used to control the connection or disconnection between the second on / off control node N2 and the second voltage terminal V2, and to control the connection or disconnection between the second on / off control node N2 and the third voltage terminal V3, under the control of the potential of the second node NC2.

[0258] exist Figure 5 In at least one embodiment of the pixel circuit shown, both the first scanning end and the second scanning end are scanning ends GT.

[0259] In at least one embodiment of the present invention, the control circuit of the nth on / off control node further includes the nth first reset circuit;

[0260] The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth node under the control of the reset control signal provided by the reset control terminal.

[0261] In a specific implementation, the control circuit of the nth on / off control node may further include an nth first reset circuit; the nth first reset circuit, under the control of the reset control signal, writes the first initial voltage into the nth node.

[0262] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown,

[0263] The first on / off control node control circuit also includes a first first reset circuit 41;

[0264] The first reset circuit 41 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node NC1 respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the first node NC1 under the control of the reset control signal provided by the reset control terminal RST.

[0265] The second on / off control node control circuit also includes a second first reset circuit 42;

[0266] The second first reset circuit 42 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second node NC2 respectively, and is used to write the first initial voltage Vinit provided by the first initial voltage terminal I1 into the second node NC2 under the control of the reset control signal provided by the reset control terminal RST.

[0267] The pixel circuit described in at least one embodiment of the present invention further includes a display light emission control circuit;

[0268] The display light emission control circuit is electrically connected to the light emission control terminal, the first display node, and the first electrode of the first light emission element, respectively, and is used to control the connection or disconnection between the first display node and the first electrode of the first light emission element under the control of the light emission control signal provided by the light emission control terminal.

[0269] like Figure 7 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a display light emission control circuit 71;

[0270] The display light emission control circuit 71 is electrically connected to the light emission control terminal EM, the first display node NX1 and the first electrode of the first light emission element E1, respectively, and is used to control the connection or disconnection between the first display node NX1 and the first electrode of the first light emission element E1 under the control of the light emission control signal provided by the light emission control terminal EM.

[0271] In at least one embodiment of the present invention, the nth control circuit further includes an nth display light emission control circuit; the nth on / off control node control circuit includes an nth control data writing circuit, an nth writing control circuit, an nth first reset circuit, an nth energy storage circuit, an nth compensation control circuit, and an nth set circuit;

[0272] The first electrode of the nth light-emitting element is electrically connected to the nth display node;

[0273] The nth display light emission control circuit is electrically connected to the light emission control terminal, the nth display node, and the first pole of the nth light emission element, and is used to control the connection or disconnection between the nth display node and the first pole of the nth light emission element under the control of the light emission control signal provided by the light emission control terminal;

[0274] The nth control data writing circuit is electrically connected to the nth scan end, the nth control data line and the nth node respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth node under the control of the nth scan signal provided by the nth scan end;

[0275] The nth write control circuit is electrically connected to the write control terminal, the control voltage terminal, and the nth node, respectively, and is used to write the control voltage to the nth node under the control of the write control signal provided by the write control terminal;

[0276] The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth on / off control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth on / off control node under the control of the reset control signal provided by the reset control terminal;

[0277] The first terminal of the nth energy storage circuit is electrically connected to the nth node, and the second terminal of the nth energy storage circuit is electrically connected to the nth on / off control node. The nth energy storage circuit is used to store electrical energy.

[0278] The nth compensation control circuit is electrically connected to the compensation control terminal, the nth on / off control node, and the second electrode of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the nth on / off control node and the second electrode of the nth light-emitting element under the control of the compensation control signal provided by the compensation control terminal;

[0279] The nth set circuit is electrically connected to the scanning terminal, the nth reference voltage terminal, and the first electrode of the nth light-emitting element, respectively, and is used to write the nth reference voltage provided by the nth reference voltage terminal into the first electrode of the nth light-emitting element under the control of the scanning signal provided by the scanning terminal.

[0280] like Figure 8 As shown, in Figure 2B Based on at least one embodiment of the pixel circuit shown,

[0281] The first control circuit also includes a first display light-emitting control circuit 801;

[0282] The first on / off control node control circuit includes a first control data writing circuit 211, a first writing control circuit 811, a first first reset circuit 41, a first energy storage circuit 210, a first compensation control circuit 812, and a first set circuit 813.

[0283] The first electrode of the first light-emitting element E1 is electrically connected to the first display node NX1; the first electrode of the second light-emitting element E2 is electrically connected to the second display node NX2;

[0284] The first display light emission control circuit 801 is electrically connected to the light emission control terminal EM, the first display node NX1 and the first pole of the first light emission element E1, and is used to control the connection or disconnection between the first display node NX1 and the first pole of the first light emission element E1 under the control of the light emission control signal provided by the light emission control terminal EM.

[0285] The first control data writing circuit 211 is electrically connected to the display scanning terminal CGL, the first control data line DA and the first node NC1 respectively, and is used to write the first control data voltage provided by the first control data line DA into the first node NC1 under the control of the display scanning signal provided by the display scanning terminal CGL.

[0286] The first write control circuit 811 is electrically connected to the write control terminal CTL, the control voltage terminal SWP, and the first node NC1, respectively, and is used to write the control voltage provided by the control voltage terminal SWP to the first node under the control of the write control signal provided by the write control terminal CTL.

[0287] The first reset circuit 41 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first on / off control node N1, respectively, and is used to write the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the first on / off control node N1 under the control of the reset control signal provided by the reset control terminal RST.

[0288] The first terminal of the first energy storage circuit 210 is electrically connected to the first node NC1, and the second terminal of the first energy storage circuit 210 is electrically connected to the first on / off control node N1. The first energy storage circuit 210 is used to store electrical energy.

[0289] The first compensation control circuit 812 is electrically connected to the scanning end GT, the first on / off control node N1 and the second pole of the first light-emitting element E1 respectively, and is used to control the connection or disconnection between the first on / off control node N1 and the second pole of the first light-emitting element E1 under the control of the scanning signal provided by the scanning end GT.

[0290] The first setting circuit 813 is electrically connected to the scanning terminal GT, the first reference voltage terminal REF1 and the first electrode of the first light-emitting element E1, respectively, and is used to write the first reference voltage Vref1 provided by the first reference voltage terminal REF1 into the first electrode of the first light-emitting element E1 under the control of the scanning signal provided by the scanning terminal GT.

[0291] The second control circuit also includes a second display light-emitting control circuit 802;

[0292] The second on / off control node control circuit includes a second control data writing circuit 212, a second writing control circuit 821, a second first reset circuit 42, a second energy storage circuit 220, and a second compensation control circuit 822.

[0293] The second display light emission control circuit 802 is electrically connected to the light emission control terminal EM, the second display node NX2, and the first pole of the second light emission element E2, and is used to control the connection or disconnection between the second display node NX2 and the first pole of the second light emission element E2 under the control of the light emission control signal provided by the light emission control terminal EM.

[0294] The second control data writing circuit 212 is electrically connected to the display scanning terminal CGL, the second control data line DB, and the second node NC2, respectively, and is used to write the second control data voltage provided by the second control data line DB into the second node NC2 under the control of the display scanning signal provided by the display scanning terminal CGL.

[0295] The second write control circuit 821 is electrically connected to the write control terminal CTL, the control voltage terminal SWP, and the second node NC2, respectively, and is used to write the control voltage provided by the control voltage terminal SWP into the second node NC2 under the control of the write control signal provided by the write control terminal CTL.

[0296] The second first reset circuit 42 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second on / off control node N2 respectively, and is used to write the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the second on / off control node N2 under the control of the reset control signal provided by the reset control terminal RST.

[0297] The first end of the second energy storage circuit 220 is electrically connected to the second node NC2, and the second end of the second energy storage circuit 220 is electrically connected to the second on / off control node N2. The second energy storage circuit 220 is used to store electrical energy.

[0298] The second compensation control circuit 822 is electrically connected to the scanning end GT, the second on / off control node N2 and the second electrode of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second on / off control node N2 and the second electrode of the second light-emitting element E2 under the control of the scanning signal provided by the scanning end GT.

[0299] The second setting circuit 823 is electrically connected to the scanning terminal GT, the second reference voltage terminal REF2, and the first electrode of the second light-emitting element E2, respectively, and is used to write the second reference voltage Vref2 provided by the second reference voltage terminal REF2 into the first electrode of the second light-emitting element E2 under the control of the scanning signal provided by the scanning terminal GT.

[0300] exist Figure 8 In at least one embodiment shown, the first scanning end and the second scanning end are both display scanning ends CGL, and the compensation control end is a scanning end GT.

[0301] Optionally, the control circuit of the nth on / off control node further includes the nth second reset circuit;

[0302] The nth second reset circuit is electrically connected to the reset control terminal, the second initial voltage terminal and the nth node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the nth node under the control of the reset control signal.

[0303] like Figure 9 As shown, in Figure 8 Based on at least one embodiment of the pixel circuit,

[0304] The first on / off control node control circuit also includes a first second reset circuit 901;

[0305] The first second reset circuit 901 is electrically connected to the reset control terminal RST, the second initial voltage terminal I2 and the first node NC1 respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the first node NC1 under the control of the reset control signal.

[0306] The second on / off control node control circuit also includes a second second reset circuit 902;

[0307] The second reset circuit 902 is electrically connected to the reset control terminal RST, the second initial voltage terminal I2, and the second node NC2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the second node NC2 under the control of the reset control signal.

[0308] Optionally, the light-emitting element may be an organic light-emitting diode, a micro LED, or a mini LED, but is not limited thereto.

[0309] Optionally, the nth on / off control circuit includes an nth first transistor, the nth control data writing circuit includes an nth second transistor, and the nth energy storage circuit includes an nth storage capacitor;

[0310] The gate of the nth first transistor is electrically connected to the nth on / off control node, the first electrode of the nth first transistor is electrically connected to the first electrode of the nth light-emitting element, and the second electrode of the nth first transistor is electrically connected to the second electrode of the nth light-emitting element.

[0311] The gate of the nth second transistor is electrically connected to the nth scan terminal, the first terminal of the nth second transistor is electrically connected to the nth control data line, and the second terminal of the nth second transistor is electrically connected to the nth on / off control node.

[0312] The first terminal of the nth storage capacitor is electrically connected to the nth on / off control node, and the second terminal of the nth storage capacitor is electrically connected to the control voltage terminal.

[0313] like Figure 10 As shown, in Figure 3A Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, the second light-emitting element is a second micro light-emitting diode O2, and the third light-emitting element is a third micro light-emitting diode O3;

[0314] The first on / off control circuit includes a first transistor T11, the first control data writing circuit includes a first transistor T12, and the first energy storage circuit includes a first storage capacitor C1.

[0315] The gate of the first transistor T11 is electrically connected to the first on / off control node N1, the source of the first transistor T11 is electrically connected to the first electrode of the first micro light-emitting diode O1, and the drain of the first transistor T11 is electrically connected to the cathode of the first micro light-emitting diode O1.

[0316] The gate of the first second transistor T12 is electrically connected to the scan terminal GT, the source of the first second transistor T12 is electrically connected to the first control data line DA, and the drain of the first second transistor T12 is electrically connected to the first on / off control node N1.

[0317] The first terminal of the first storage capacitor C1 is electrically connected to the first on / off control node N1, and the second terminal of the first storage capacitor C1 is electrically connected to the control voltage terminal SWP.

[0318] The second on / off control circuit includes a second first transistor T21, the second control data writing circuit includes a second second transistor T22, and the second energy storage circuit includes a second storage capacitor C2.

[0319] The gate of the second first transistor T21 is electrically connected to the second on / off control node N2, the source of the second first transistor T21 is electrically connected to the anode of the second micro light-emitting diode O2, and the drain of the second first transistor T21 is electrically connected to the cathode of the second micro light-emitting diode O2.

[0320] The gate of the second transistor T22 is electrically connected to the scan terminal GT, the source of the second transistor T22 is electrically connected to the second control data line DB, and the drain of the second transistor T22 is electrically connected to the second on / off control node N2.

[0321] The first terminal of the second storage capacitor C2 is electrically connected to the second on / off control node N2, and the second terminal of the second storage capacitor C2 is electrically connected to the control voltage terminal SWP.

[0322] The gate of the third first transistor T31 is electrically connected to the third on / off control node N3, the source of the third first transistor T31 is electrically connected to the anode of the third micro light-emitting diode O3, and the drain of the third first transistor T31 is electrically connected to the cathode of the third micro light-emitting diode O3; the cathode of O3 is electrically connected to the low voltage terminal VSS.

[0323] The gate of the third second transistor T32 is electrically connected to the scan terminal GT, the source of the third second transistor T32 is electrically connected to the third control data line DC, and the drain of the third second transistor T32 is electrically connected to the third on / off control node N3.

[0324] The first terminal of the third storage capacitor C3 is electrically connected to the third on / off control node N3, and the second terminal of the third storage capacitor C3 is electrically connected to the control voltage terminal SWP.

[0325] The pixel driving circuit includes a driving transistor T0, a storage capacitor Cst, a data writing transistor TW, and a first light-emitting control transistor TE1.

[0326] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0327] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the gate of T0.

[0328] The gate of TE1 is electrically connected to the light-emitting control terminal EM, the source of TE1 is electrically connected to the drain of T0, and the source of T0 is electrically connected to the power supply voltage terminal VDD.

[0329] The drain of TE1 is electrically connected to the first display node NX1.

[0330] exist Figure 10 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors.

[0331] exist Figure 10 In at least one embodiment of the pixel circuit shown, the first scanning end, the second scanning end, and the third scanning end are all scanning ends GT.

[0332] Figure 11A yes Figure 10 The timing diagram shows the operation of at least one embodiment of the pixel circuit.

[0333] Figure 10 At least one embodiment of the pixel circuit shown is a 9T4C pixel circuit, with only one driving transistor T0 in the current path, reducing power consumption.

[0334] like Figure 11A As shown, the present invention Figure 10 When at least one embodiment of the pixel circuit shown is in operation, taking the operation process of O1 as an example, a frame display time F1 includes a data writing stage S1 and a light emission stage S2 that are set sequentially.

[0335] Assuming the pixel driving circuit provides the total driving current Id,

[0336] When displaying high grayscale, DA provides a high voltage signal. In the data writing stage S1, the high voltage signal provided by DA is written to the gate of T11 through T12. Even in the light emission stage S2, the potential of the control voltage provided by SWP is pulled down, and the capacitive coupling causes the potential of N1 to become low. The potential of N1 can still turn off T11. At this time, the driving current flowing through O1 is the total driving current Id, the light emission duration of O1 is T, and the light emission brightness of O1 is proportional to Id and T.

[0337] When displaying low grayscale, DA provides the first control data voltage VdataA. In the data writing stage S1, VdataA is written to N1 through T12. In the data writing stage t1, VdataA controls T11, which is in the off state. The current flowing through O1 is Id. In the light emission stage S2, SWP provides a triangular wave voltage. The control voltage provided by SWP gradually decreases. Due to the coupling effect of C1, the potential of N1 decreases. After time t1, the potential of N1 decreases so that T11 is turned on. The current flowing through O1 flows away through T11. The current flowing through O1 is 0, and O1 does not emit light. The light emission brightness of O1 is Id×t2, where t2 is less than T. t2 is related to the triangular wave voltage and VdataA. After the triangular wave voltage is fixed, the light emission time t2 is adjusted by different Vdata provided by DA, thereby adjusting the grayscale brightness and thus achieving different grayscale control.

[0338] The grayscale control for O2 and O3 is the same as that for O1.

[0339] like Figure 11A As shown, the present invention Figure 10 In at least one embodiment of the pixel circuit shown, when in operation, a frame display time F1 includes a data writing phase S1 and a light emission phase S2 that are set sequentially.

[0340] During the data writing phase S1, GT provides a low-voltage signal, such as Figure 11B As shown, T12, T22, and T32 are turned on. DA provides the first control data voltage VdataA to N1, DB provides the second control data voltage VdataB to N2, and DC provides the third control data voltage to N3. At this time, EM provides a high voltage signal, TE1 is turned off, and O1, O2, and O3 do not emit light. TW is turned on, and DT provides the display data voltage Vdata to the gate of T0.

[0341] During the light emission phase S2, GT provides a high voltage signal, EM provides a low voltage signal, and TE is turned on.

[0342] At the beginning of the luminescence stage S2, as Figure 11C As shown, T11, T21, and T31 are all turned off, and T0 drives O1, O2, and O3 to emit light;

[0343] During the light-emitting stage S2, SWP provides a triangular wave voltage. The potential of the control voltage provided by SWP decreases. Due to the coupling effect of C1, the potential of N1 decreases to control T11 to turn on or off. Due to the coupling effect of C2, the potential of N2 decreases to control T21 to turn on or off. Due to the coupling effect of C3, the potential of N3 decreases to control T31 to turn on or off.

[0344] like Figure 12 As shown, in Figure 3B Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, and the second light-emitting element is a second micro light-emitting diode O2;

[0345] The first on / off control circuit includes a first transistor T11, the first control data writing circuit includes a first transistor T12, and the first energy storage circuit includes a first storage capacitor C1.

[0346] The gate of the first transistor T11 is electrically connected to the first on / off control node N1, the source of the first transistor T11 is electrically connected to the first electrode of the first micro light-emitting diode O1, and the drain of the first transistor T11 is electrically connected to the cathode of the first micro light-emitting diode O1.

[0347] The gate of the first second transistor T12 is electrically connected to the scan terminal GT, the source of the first second transistor T12 is electrically connected to the first control data line DA, and the drain of the first second transistor T12 is electrically connected to the first on / off control node N1.

[0348] The first terminal of the first storage capacitor C1 is electrically connected to the first on / off control node N1, and the second terminal of the first storage capacitor C1 is electrically connected to the control voltage terminal SWP.

[0349] The second on / off control circuit includes a second first transistor T21, the second control data writing circuit includes a second second transistor T22, and the second energy storage circuit includes a second storage capacitor C2.

[0350] The gate of the second first transistor T21 is electrically connected to the second on / off control node N2, the source of the second first transistor T21 is electrically connected to the anode of the second micro light-emitting diode O2, and the drain of the second first transistor T21 is electrically connected to the cathode of the second micro light-emitting diode O2.

[0351] The gate of the second transistor T22 is electrically connected to the scan terminal GT, the source of the second transistor T22 is electrically connected to the second control data line DB, and the drain of the second transistor T22 is electrically connected to the second on / off control node N2.

[0352] The first terminal of the second storage capacitor C2 is electrically connected to the second on / off control node N2, and the second terminal of the second storage capacitor C2 is electrically connected to the control voltage terminal SWP.

[0353] The cathode of O2 is electrically connected to the low-voltage terminal VSS.

[0354] exist Figure 12 In at least one embodiment of the pixel circuit shown, there is a first scanning terminal and a second scanning terminal.

[0355] Figure 13 yes Figure 12 The timing diagram shows the operation of at least one embodiment of the pixel circuit.

[0356] exist Figure 13 In the diagram, the current flowing through O1 is labeled Id_O1, and the current flowing through O2 is labeled Id_O2.

[0357] exist Figure 13 As shown, t11 is the first emission time, and t12 is the second emission time. The first emission time t11 is the emission time of O1, and the second emission time t12 is the emission time of O2.

[0358] like Figure 14 As shown, in Figure 3A Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, the second light-emitting element is a second micro light-emitting diode O2, and the third light-emitting element is a third micro light-emitting diode O3;

[0359] The first on / off control circuit includes a first transistor T11, the first control data writing circuit includes a first transistor T12, and the first energy storage circuit includes a first storage capacitor C1.

[0360] The gate of the first transistor T11 is electrically connected to the first on / off control node N1, the source of the first transistor T11 is electrically connected to the first electrode of the first micro light-emitting diode O1, and the drain of the first transistor T11 is electrically connected to the cathode of the first micro light-emitting diode O1.

[0361] The gate of the first second transistor T12 is electrically connected to the first scan terminal GA, the source of the first second transistor T12 is electrically connected to the first control data line DA, and the drain of the first second transistor T12 is electrically connected to the first on / off control node N1.

[0362] The first terminal of the first storage capacitor C1 is electrically connected to the first on / off control node N1, and the second terminal of the first storage capacitor C1 is electrically connected to the control voltage terminal SWP.

[0363] The second on / off control circuit includes a second first transistor T21, the second control data writing circuit includes a second second transistor T22, and the second energy storage circuit includes a second storage capacitor C2.

[0364] The gate of the second first transistor T21 is electrically connected to the second on / off control node N2, the source of the second first transistor T21 is electrically connected to the anode of the second micro light-emitting diode O2, and the drain of the second first transistor T21 is electrically connected to the cathode of the second micro light-emitting diode O2.

[0365] The gate of the second transistor T22 is electrically connected to the second scan terminal GB, the source of the second transistor T22 is electrically connected to the second control data line DB, and the drain of the second transistor T22 is electrically connected to the second on / off control node N2.

[0366] The first terminal of the second storage capacitor C2 is electrically connected to the second on / off control node N2, and the second terminal of the second storage capacitor C2 is electrically connected to the control voltage terminal SWP.

[0367] The gate of the third first transistor T31 is electrically connected to the third on / off control node N3, the source of the third first transistor T31 is electrically connected to the anode of the third micro light-emitting diode O3, and the drain of the third first transistor T31 is electrically connected to the cathode of the third micro light-emitting diode O3; the cathode of O3 is electrically connected to the low voltage terminal VSS.

[0368] The gate of the third second transistor T32 is electrically connected to the third scan terminal GC, the source of the third second transistor T32 is electrically connected to the third control data line DC, and the drain of the third second transistor T32 is electrically connected to the third on / off control node N3.

[0369] The first terminal of the third storage capacitor C3 is electrically connected to the third on / off control node N3, and the second terminal of the third storage capacitor C3 is electrically connected to the control voltage terminal SWP.

[0370] The pixel driving circuit includes a driving transistor T0, a storage capacitor Cst, a data writing transistor TW, and a first light-emitting control transistor TE1.

[0371] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0372] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the gate of T0.

[0373] The gate of TE1 is electrically connected to the light-emitting control terminal EM, the source of TE1 is electrically connected to the drain of T0, and the source of T0 is electrically connected to the power supply voltage terminal VDD.

[0374] The drain of TE1 is electrically connected to the first display node NX1.

[0375] exist Figure 14 In at least one embodiment of the pixel circuit shown, DT, DA, DB, and DC can be the same data line. The display data voltage, first control data voltage, second control data voltage, and third control data voltage are written into the pixel circuit by time-division control through GT, GA, GB, and GC, thereby reducing the number of data lines and reducing crosstalk between data voltage signals.

[0376] Optionally, the nth first reset circuit includes the nth third transistor;

[0377] The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth on / off control node.

[0378] like Figure 15 As shown, in Figure 12 Based on at least one embodiment of the pixel circuit shown, the first on / off control node control circuit further includes a first first reset circuit, and the second on / off control node control circuit further includes a second first reset circuit.

[0379] The first reset circuit includes a first third transistor T13;

[0380] The gate of the first third transistor T13 is electrically connected to the reset control terminal RST, the source of the first third transistor T13 is electrically connected to the first initial voltage terminal I1, and the drain of the first third transistor T13 is electrically connected to the first on / off control node N1.

[0381] The second first reset circuit includes a second third transistor T23;

[0382] The gate of the second third transistor T23 is electrically connected to the reset control terminal RST, the source of the second third transistor T23 is electrically connected to the first initial voltage terminal I1, and the drain of the second third transistor T23 is electrically connected to the second on / off control node N2.

[0383] exist Figure 15 In at least one embodiment shown, all transistors are p-type transistors.

[0384] This invention Figure 15 In at least one embodiment of the pixel circuit shown, during operation, in the reset phase prior to the data writing phase, RST provides a low voltage signal, T13 and T23 are turned on, I1 applies a first initial voltage Vint1 to N1, and I2 applies a second initial voltage Vint2 to N2 to control T11 and T21 to be turned off.

[0385] Optionally, the nth control data writing circuit includes the nth second transistor, the nth energy storage circuit includes the nth storage capacitor, and the nth node control circuit includes the nth fourth transistor and the nth fifth transistor;

[0386] The gate of the nth second transistor is electrically connected to the nth scan terminal, the first electrode of the nth second transistor is electrically connected to the nth control data line, and the second electrode of the nth second transistor is electrically connected to the nth node;

[0387] The first terminal of the nth storage capacitor is electrically connected to the nth node, and the second terminal of the nth storage capacitor is electrically connected to the control voltage terminal.

[0388] The gate of the nth fourth transistor is electrically connected to the nth node, the first terminal of the nth fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the nth fourth transistor is electrically connected to the nth on / off control node.

[0389] The gate of the nth fifth transistor is electrically connected to the nth node, the first terminal of the nth fifth transistor is electrically connected to the nth on / off control node, and the second terminal of the nth fifth transistor is electrically connected to the third voltage terminal.

[0390] Optionally, the nth first reset circuit includes the nth third transistor;

[0391] The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth node.

[0392] Optionally, the display light-emitting control circuit includes a sixth transistor;

[0393] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first display node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the first light-emitting element.

[0394] like Figure 16 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, and the second light-emitting element is a second micro light-emitting diode O2;

[0395] The display light-emitting control circuit includes a sixth transistor T6;

[0396] The gate of the sixth transistor T6 is electrically connected to the light-emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the first display node NX1, and the drain of the sixth transistor T6 is electrically connected to the anode of O1.

[0397] The first control data writing circuit includes a first second transistor T12; the first energy storage circuit includes a first storage capacitor C1; the first node control circuit includes a first fourth transistor T14 and a first fifth transistor T15; and the first on / off control circuit includes a first first transistor T11.

[0398] The gate of the first transistor T11 is electrically connected to the first on / off control node N1, the source of the first transistor T11 is electrically connected to the anode of O1, and the drain of the first transistor T11 is electrically connected to the cathode of O1.

[0399] The gate of the first second transistor T12 is electrically connected to the scan terminal GT, the source of the first second transistor T12 is electrically connected to the first control data line DA, and the drain of the first second transistor T12 is electrically connected to the first node NC1.

[0400] The first terminal of the first storage capacitor C1 is electrically connected to the first node NC1, and the second terminal of the first storage capacitor C1 is electrically connected to the control voltage terminal SWP.

[0401] The gate of the first fourth transistor T14 is electrically connected to the first node NC1, the source of the first fourth transistor T14 is electrically connected to the high voltage terminal VGH, and the drain of the first fourth transistor T14 is electrically connected to the first on / off control node N1.

[0402] The gate of the first fifth transistor T15 is electrically connected to the first node NC1, the source of the first fifth transistor T15 is electrically connected to the first on / off control node N1, and the drain of the first fifth transistor T15 is electrically connected to the low-level terminal VGL.

[0403] The second control data writing circuit includes a second second transistor T22; the second energy storage circuit includes a second storage capacitor C2; the second node control circuit includes a second fourth transistor T24 and a second fifth transistor T25; and the second on / off control circuit includes a second first transistor T21.

[0404] The gate of the second first transistor T21 is electrically connected to the second on / off control node N2, the source of the second first transistor T21 is electrically connected to the anode of O2, and the drain of the second first transistor T21 is electrically connected to the cathode of O2.

[0405] The gate of the second transistor T22 is electrically connected to the scan terminal GT, the source of the second transistor T22 is electrically connected to the second control data line DB, and the drain of the second transistor T22 is electrically connected to the second node NC2.

[0406] The first end of the second storage capacitor C2 is electrically connected to the second node NC2, and the second end of the second storage capacitor C2 is electrically connected to the control voltage terminal SWP.

[0407] The gate of the second fourth transistor T24 is electrically connected to the second node NC2, the source of the second fourth transistor T24 is electrically connected to the high voltage terminal VGH, and the drain of the second fourth transistor T24 is electrically connected to the second on / off control node N2.

[0408] The gate of the second fifth transistor T15 is electrically connected to the second node NC2, the source of the second fifth transistor T25 is electrically connected to the second on / off control node N2, and the drain of the second fifth transistor T25 is electrically connected to the low-level terminal VGL.

[0409] The cathode of O2 is electrically connected to the low-voltage terminal VSS;

[0410] The pixel driving circuit includes a driving transistor T0, a storage capacitor Cst, a data writing transistor TW, a light-emitting control transistor TE, a compensation control transistor TS, and a reset transistor TR.

[0411] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0412] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the source of T0.

[0413] The gate of TE is electrically connected to the light-emitting control terminal EM, the source of TE is electrically connected to the power supply voltage terminal VDD, the drain of TE is electrically connected to the source of T0, and the drain of T0 is electrically connected to the first display node NX1.

[0414] The gate of TS is electrically connected to the scan terminal GT, the source of TS is electrically connected to the gate of T0, and the drain of TS is electrically connected to the drain of T0.

[0415] The gate of TR is electrically connected to the reset control terminal RST, the source of TR is electrically connected to the first initial voltage terminal I1, and the drain of TR is electrically connected to the gate of T0.

[0416] Figure 17A yes Figure 16 The timing diagram shows the operation of at least one embodiment of the pixel circuit. Figure 17B yes Figure 16 Simulation timing diagram of at least one embodiment of the pixel circuit shown.

[0417] In this invention Figure 16 In at least one embodiment of the pixel circuit shown, a set of inverters is added to the control circuit (the first control circuit includes a first inverter, which includes T14 and T15; the second control circuit includes a second inverter, which includes T24 and T25). By using the inverters, T11 and T21 are turned off or on through VGH and VGL, which improves the problem that the luminous brightness of O1 and O2 gradually decreases when they stop emitting light during the light-emitting stage.

[0418] like Figure 17A As shown, the present invention Figure 16In at least one embodiment of the pixel circuit shown, when in operation, a frame display time F1 includes a reset phase S0, a data writing phase S1, and a light emission phase S2.

[0419] During the reset phase S0, RST provides a low voltage signal, TR is turned on, and I1 provides a first initial voltage Vint1 to the gate of T0 to control T0 to be turned on when the data write phase S1 begins.

[0420] During the data writing phase S1, GT provides a low voltage signal, TW is turned on, TS is turned on, DT provides the display data voltage Vdata to the source of T0, the gate of T0 is connected to the drain of T0, and Cst is charged through Vdata until the gate potential of T0 becomes Vdata+Vth, where Vth is the threshold voltage of T0.

[0421] During the data writing phase S1, GT provides a low voltage signal, T12 and T22 are turned on, DA provides the first control data voltage VdataA to NC1, and DB provides the second control data voltage VdataB to NC2; T11 and T21 are turned off, and T0 drives O1 and O2 to emit light.

[0422] During the light-emitting stage S2, SWP provides a triangular wave signal. The control voltage provided by SWP decreases, and through the coupling effect of C1 and C2, the potentials of N1 and N2 decrease, controlling T11 and T12 to turn off or on.

[0423] When T11 is turned on, the driving current flows through T11 and O1 does not emit light;

[0424] When T21 is turned on, the driving current flows through T21 and O2 does not emit light.

[0425] Optionally, the first voltage terminal can be a low voltage terminal, the second voltage terminal can be a high voltage terminal, and the third voltage terminal can be a low-level terminal.

[0426] like Figure 18A As shown, in Figure 16 Based on at least one embodiment of the pixel circuit shown, the first on / off control node control circuit further includes a first first reset circuit, and the second on / off control node control circuit further includes a second first reset circuit.

[0427] The first reset circuit includes a first third transistor T13;

[0428] The gate of the first third transistor T13 is electrically connected to the reset control terminal RST, the source of the first third transistor T13 is electrically connected to the first initial voltage terminal I1, and the drain of the first third transistor T13 is electrically connected to the first on / off control node N1.

[0429] The second first reset circuit includes a second third transistor T23;

[0430] The gate of the second third transistor T23 is electrically connected to the reset control terminal RST, the source of the second third transistor T23 is electrically connected to the first initial voltage terminal I1, and the drain of the second third transistor T23 is electrically connected to the second on / off control node N2.

[0431] This invention Figure 18A In at least one embodiment of the pixel circuit shown, during operation, in the reset phase, T13 and T23 are turned on, and I1 provides a first initial voltage Vint1 to N1 and N2.

[0432] This invention Figure 18B At least one embodiment of the pixel circuit shown is Figure 16 The difference in at least one embodiment of the pixel circuit shown is that:

[0433] The pixel driving circuit includes a driving transistor T0, a data writing transistor TW, and a storage capacitor Cst;

[0434] The source of T0 is electrically connected to the power supply voltage terminal VDD, and the drain of T0 is electrically connected to the source of T6.

[0435] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the gate of T0.

[0436] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0437] Figure 18C yes Figure 18B The timing diagram shows the operation of at least one embodiment of the pixel circuit. Figure 18D yes Figure 18B Simulation timing diagram of at least one embodiment of the pixel circuit shown.

[0438] Optionally, the nth display light emission control circuit includes the nth sixth transistor, the nth control data writing circuit includes the nth seventh transistor, the nth writing control circuit includes the nth eighth transistor, the nth first reset circuit includes the nth third transistor, the nth energy storage circuit includes the nth storage capacitor, the nth compensation control circuit includes the nth ninth transistor, and the nth set circuit includes the nth tenth transistor.

[0439] The gate of the nth sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the nth sixth transistor is electrically connected to the nth display node, and the second electrode of the nth sixth transistor is electrically connected to the first electrode of the nth light-emitting element.

[0440] The gate of the nth seventh transistor is electrically connected to the nth scan terminal, the first terminal of the nth seventh transistor is electrically connected to the nth control data line, and the second terminal of the nth seventh transistor is electrically connected to the nth node;

[0441] The gate of the nth eighth transistor is electrically connected to the write control terminal, the first terminal of the nth eighth transistor is electrically connected to the control voltage terminal, and the second terminal of the nth eighth transistor is electrically connected to the nth node.

[0442] The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth on / off control node.

[0443] The first end of the nth storage capacitor is electrically connected to the nth node, and the second end of the nth storage capacitor is electrically connected to the nth on / off control node.

[0444] The gate of the nth ninth transistor is electrically connected to the compensation control terminal, the first electrode of the nth ninth transistor is electrically connected to the nth on / off control node, and the second electrode of the nth ninth transistor is electrically connected to the second electrode of the nth light-emitting element.

[0445] The gate of the nth tenth transistor is electrically connected to the scanning terminal, the first terminal of the nth tenth transistor is electrically connected to the nth reference voltage terminal, and the second terminal of the nth tenth transistor is electrically connected to the first terminal of the nth light-emitting element.

[0446] Optionally, the nth second reset circuit includes the nth eleventh transistor;

[0447] The gate of the nth eleventh transistor is electrically connected to the reset control terminal, the first terminal of the nth eleventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the nth eleventh transistor is electrically connected to the nth node.

[0448] like Figure 19 As shown, in Figure 8 Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, and the second light-emitting element is a second micro light-emitting diode O2;

[0449] The first display light-emitting control circuit includes a first sixth transistor T16; the first control data writing circuit includes a first seventh transistor T17; the first writing control circuit includes a first eighth transistor T18; the first first reset circuit includes a first third transistor T13; the first energy storage circuit includes a first storage capacitor C1; the first compensation control circuit includes a first ninth transistor T19; the first set circuit includes a first tenth transistor T110; and the first on / off control circuit includes a first first transistor T11.

[0450] The gate of T11 is electrically connected to the first on / off control node N1, the source of T11 is electrically connected to the anode of O1, and the drain of T11 is electrically connected to the cathode of O1.

[0451] The gate of the first sixth transistor T16 is electrically connected to the light-emitting control terminal EM, the source of the first sixth transistor T16 is electrically connected to the first display node NX1, and the drain of the first sixth transistor T16 is electrically connected to the anode of O1.

[0452] The gate of the first seventh transistor T17 is electrically connected to the display scanning terminal CGL, the source of the first seventh transistor T17 is electrically connected to the first control data line DA, and the drain of the first seventh transistor is electrically connected to the first node NC1.

[0453] The gate of the first eighth transistor T18 is electrically connected to the write control terminal CTL, the source of the first eighth transistor T18 is electrically connected to the control voltage terminal SWP, and the drain of the first eighth transistor T18 is electrically connected to the first node NC1.

[0454] The gate of the first third transistor T13 is electrically connected to the reset control terminal RST, the source of the first third transistor T13 is electrically connected to the first initial voltage terminal I1, and the drain of the first third transistor T13 is electrically connected to the first on / off control node N1.

[0455] The first end of the first storage capacitor C1 is electrically connected to the first node NC1, and the second end of the first storage capacitor C1 is electrically connected to the first on / off control node N1.

[0456] The gate of the first ninth transistor T19 is electrically connected to the scanning terminal GT, the source of the first ninth transistor T19 is electrically connected to the first on / off control node N1, and the drain of the first ninth transistor T19 is electrically connected to the cathode of O1.

[0457] The gate of T110 is electrically connected to the scanning terminal GT, the source of T110 is electrically connected to the first reference voltage terminal REF1, and the drain of T110 is electrically connected to the anode of O1.

[0458] The second display light-emitting control circuit includes a second sixth transistor T26; the second control data writing circuit includes a second seventh transistor T27; the second writing control circuit includes a second eighth transistor T28; the second first reset circuit includes a second third transistor T23; the second energy storage circuit includes a second storage capacitor C2; the second compensation control circuit includes a second ninth transistor T29; the second set circuit includes a second tenth transistor T210; and the second on / off control circuit includes a second first transistor T21.

[0459] The gate of T21 is electrically connected to the second on / off control node N2, the source of T21 is electrically connected to the anode of O2, and the drain of T21 is electrically connected to the cathode of O2.

[0460] The gate of the second sixth transistor T26 is electrically connected to the light-emitting control terminal EM, the source of the second sixth transistor T26 is electrically connected to the second display node NX2, and the drain of the second sixth transistor T26 is electrically connected to the anode of O2.

[0461] The gate of the second seventh transistor T27 is electrically connected to the display scanning terminal CGL, the source of the second seventh transistor T27 is electrically connected to the second control data line DB, and the drain of the second seventh transistor is electrically connected to the second node NC1.

[0462] The gate of the second eighth transistor T28 is electrically connected to the write control terminal CTL, the source of the second eighth transistor T28 is electrically connected to the control voltage terminal SWP, and the drain of the second eighth transistor T28 is electrically connected to the second node NC2.

[0463] The gate of the second third transistor T23 is electrically connected to the reset control terminal RST, the source of the second third transistor T23 is electrically connected to the first initial voltage terminal I1, and the drain of the second third transistor T23 is electrically connected to the second on / off control node N2.

[0464] The first end of the second storage capacitor C2 is electrically connected to the second node NC2, and the second end of the second storage capacitor C2 is electrically connected to the second on / off control node N2.

[0465] The gate of the second ninth transistor T29 is electrically connected to the scan terminal GT, the source of the second ninth transistor T29 is electrically connected to the second on / off control node N2, and the drain of the second ninth transistor T29 is electrically connected to the cathode of O2.

[0466] The gate of T210 is electrically connected to the scan terminal GT, the source of T210 is electrically connected to the second reference voltage terminal REF2, and the drain of T210 is electrically connected to the anode of O2.

[0467] The cathode of O1 is electrically connected to the low-voltage terminal VSS;

[0468] The pixel driving circuit includes a driving transistor T0, a storage capacitor Cst, a data writing transistor TW, a light-emitting control transistor TE, a compensation control transistor TS, and a reset transistor TR.

[0469] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0470] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the source of T0.

[0471] The gate of TE is electrically connected to the light-emitting control terminal EM, the source of TE is electrically connected to the power supply voltage terminal VDD, the drain of TE is electrically connected to the source of T0, and the drain of T0 is electrically connected to the first display node NX1.

[0472] The gate of TS is electrically connected to the scan terminal GT, the source of TS is electrically connected to the gate of T0, and the drain of TS is electrically connected to the drain of T0.

[0473] The gate of TR is electrically connected to the reset control terminal RST, the source of TR is electrically connected to the first initial voltage terminal I1, and the drain of TR is electrically connected to the gate of T0.

[0474] exist Figure 19 In at least one embodiment shown, all transistors are p-type transistors, but this is not a limitation.

[0475] Optionally, the compensation control end is the scanning end, and both the first scanning end and the second scanning end are display scanning ends (CGL).

[0476] Figure 20 yes Figure 19 The timing diagram shows the operation of at least one embodiment of the pixel circuit.

[0477] like Figure 20 As shown, the present invention Figure 19In at least one embodiment of the pixel circuit shown, when in operation, a frame display time F1 includes a reset phase S0, a data writing phase S1, and a light emission phase S2 that are set sequentially.

[0478] During the reset phase S0, RST provides a low voltage signal, TR is turned on, I1 provides a first initial voltage Vint1 to the gate of T0 so that T0 can be turned on when the data write phase S1 begins, and I1 provides Vint1 to N1 and N2 so that T11 and T21 are turned off.

[0479] During the data writing phase S1, GT is turned on, TW and TS are turned on, and DT provides the display data voltage Vdata to the source of T0;

[0480] When the data writing phase S1 begins, T0 is turned on, and Vdata charges Cst through TW, T0 and TS until T0 is turned off. The gate potential of T0 is Vdata + Vth, and Vth is the threshold voltage of T0.

[0481] During the data writing phase S1, GT provides a low voltage signal, and both T110 and T210 are turned on. REF1 provides the first reference voltage Vref1 to the anode of O1, and REF2 provides the second reference voltage Vref2 to the anode of O2. The potential of N1 is Vint1, the potential of the source of T12 is Vref1, the potential of N2 is Vint1, the potential of the source of T22 is Vref2, and the gate-source voltage Vgs1 of T11 is equal to Vint1 - Vref1. Vgs1 is less than Vth1, Vth1 is the threshold voltage of T11, T11 is turned on, T19 is turned on, and the potential of N1 is Vref1 + Vth1, which compensates for the threshold voltage of T11; the gate-source voltage Vgs2 of T21 is equal to Vint1 - Vref2, Vgs2 is less than Vth2, Vth2 is the threshold voltage of T21, T21 is turned on, T29 is turned on, and the potential of N2 is Vref2 + Vth2, which compensates for the threshold voltage of T21;

[0482] During the data writing phase S1, CGL provides a low voltage signal, T17 and T18 are turned on, DA provides the first control data voltage VdataA to N1, and DB provides the second control data voltage VdataB to N2.

[0483] During the light-emitting stage S2, CTL provides a low voltage signal, T18 and T28 are turned on, SWP provides a control voltage to NC1 and NC2, SWP provides a triangular wave signal, the potential of the control voltage provided by SWP decreases, and through the coupling effect of C1 and C2, the potential of N1 and N2 decreases.

[0484] During the light-emitting stage S2, when T11 is turned on, the driving current flows through T11, and O1 does not emit light; when T21 is turned on, the driving current flows through T21, and O2 does not emit light.

[0485] like Figure 21 As shown, in Figure 8 Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, and the second light-emitting element is a second micro light-emitting diode O2;

[0486] The first display light-emitting control circuit includes a first sixth transistor T16; the first control data writing circuit includes a first seventh transistor T17; the first writing control circuit includes a first eighth transistor T18; the first first reset circuit includes a first third transistor T13; the first energy storage circuit includes a first storage capacitor C1; the first compensation control circuit includes a first ninth transistor T19; the first set circuit includes a first tenth transistor T110; and the first on / off control circuit includes a first first transistor T11.

[0487] The gate of T11 is electrically connected to the first on / off control node N1, the source of T11 is electrically connected to the anode of O1, and the drain of T11 is electrically connected to the cathode of O1.

[0488] The gate of the first sixth transistor T16 is electrically connected to the light-emitting control terminal EM, the source of the first sixth transistor T16 is electrically connected to the first display node NX1, and the drain of the first sixth transistor T16 is electrically connected to the anode of O1.

[0489] The gate of the first seventh transistor T17 is electrically connected to the scan terminal GT, the source of the first seventh transistor T17 is electrically connected to the first control data line DA, and the drain of the first seventh transistor is electrically connected to the first node NC1.

[0490] The gate of the first eighth transistor T18 is electrically connected to the write control terminal CTL, the source of the first eighth transistor T18 is electrically connected to the control voltage terminal SWP, and the drain of the first eighth transistor T18 is electrically connected to the first node NC1.

[0491] The gate of the first third transistor T13 is electrically connected to the reset control terminal RST, the source of the first third transistor T13 is electrically connected to the first initial voltage terminal I1, and the drain of the first third transistor T13 is electrically connected to the first on / off control node N1.

[0492] The first end of the first storage capacitor C1 is electrically connected to the first node NC1, and the second end of the first storage capacitor C1 is electrically connected to the first on / off control node N1.

[0493] The gate of the first ninth transistor T19 is electrically connected to the display scanning terminal CGL, the source of the first ninth transistor T19 is electrically connected to the first on / off control node N1, and the drain of the first ninth transistor T19 is electrically connected to the cathode of O1.

[0494] The gate of T110 is electrically connected to the display scanning terminal CGL, the source of T110 is electrically connected to the first reference voltage terminal REF1, and the drain of T110 is electrically connected to the anode of O1.

[0495] The second display light-emitting control circuit includes a second sixth transistor T26; the second control data writing circuit includes a second seventh transistor T27; the second writing control circuit includes a second eighth transistor T28; the second first reset circuit includes a second third transistor T23; the second energy storage circuit includes a second storage capacitor C2; the second compensation control circuit includes a second ninth transistor T29; the second set circuit includes a second tenth transistor T210; and the second on / off control circuit includes a second first transistor T21.

[0496] The gate of T21 is electrically connected to the second on / off control node N2, the source of T21 is electrically connected to the anode of O2, and the drain of T21 is electrically connected to the cathode of O2.

[0497] The gate of the second sixth transistor T26 is electrically connected to the light-emitting control terminal EM, the source of the second sixth transistor T26 is electrically connected to the second display node NX2, and the drain of the second sixth transistor T26 is electrically connected to the anode of O2.

[0498] The gate of the second seventh transistor T27 is electrically connected to the scan terminal GT, the source of the second seventh transistor T27 is electrically connected to the second control data line DB, and the drain of the second seventh transistor is connected to the second node NC2.

[0499] The gate of the second eighth transistor T28 is electrically connected to the write control terminal CTL, the source of the second eighth transistor T28 is electrically connected to the control voltage terminal SWP, and the drain of the second eighth transistor T28 is electrically connected to the second node NC2.

[0500] The gate of the second third transistor T23 is electrically connected to the reset control terminal RST, the source of the second third transistor T23 is electrically connected to the first initial voltage terminal I1, and the drain of the second third transistor T23 is electrically connected to the second on / off control node N2.

[0501] The first end of the second storage capacitor C2 is electrically connected to the second node NC2, and the second end of the second storage capacitor C2 is electrically connected to the second on / off control node N2.

[0502] The gate of the second ninth transistor T29 is electrically connected to the display scanning terminal CGL, the source of the second ninth transistor T29 is electrically connected to the second on / off control node N2, and the drain of the second ninth transistor T29 is electrically connected to the cathode of O2.

[0503] The gate of T210 is electrically connected to the display scanning terminal CGL, the source of T210 is electrically connected to the second reference voltage terminal REF2, and the drain of T210 is electrically connected to the anode of O2.

[0504] The cathode of O1 is electrically connected to the low-voltage terminal VSS;

[0505] The pixel driving circuit includes a driving transistor T0, a storage capacitor Cst, a data writing transistor TW, a light-emitting control transistor TE, a compensation control transistor TS, and a reset transistor TR.

[0506] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0507] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the source of T0.

[0508] The gate of TE is electrically connected to the light-emitting control terminal EM, the source of TE is electrically connected to the power supply voltage terminal VDD, the drain of TE is electrically connected to the source of T0, and the drain of T0 is electrically connected to the first display node NX1.

[0509] The gate of TS is electrically connected to the scan terminal GT, the source of TS is electrically connected to the gate of T0, and the drain of TS is electrically connected to the drain of T0.

[0510] The gate of TR is electrically connected to the reset control terminal RST, the source of TR is electrically connected to the first initial voltage terminal I1, and the drain of TR is electrically connected to the gate of T0.

[0511] exist Figure 21In at least one embodiment of the pixel circuit shown, TW, TS, and TR are all n-type transistors; T17, T19, and T110 are all n-type transistors; and T27, T29, and T210 are all n-type transistors.

[0512] Figure 22 yes Figure 21 The timing diagram shows the operation of at least one embodiment of the pixel circuit.

[0513] like Figure 22 As shown, the present invention Figure 21 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a reset phase S0, a data writing phase S1, and a light emission phase S2 that are set sequentially.

[0514] During the reset phase S0, RST provides a high voltage signal, TR is turned on, and I1 provides a first initial voltage Vint1 to the gate of T0 so that T0 can be turned on when the data write phase S1 begins; T13 and T23 are turned on, and I1 provides Vint1 to N1 and N2 to control T11 and T21 to be turned off.

[0515] During the reset phase S0 and the data write phase S1, CGL provides a high voltage signal, and both T110 and T210 are turned on. REF1 provides the first reference voltage Vref1 to the anode of O1, and REF2 provides the second reference voltage Vref2 to the anode of O2. The potential of N1 is Vint1, the potential of the source of T12 is Vref1, the potential of N2 is Vint1, the potential of the source of T22 is Vref2, and the gate-source voltage Vgs1 of T11 is equal to Vint1 - Vr. ef1, Vgs1 is less than Vth1, Vth1 is the threshold voltage of T11, T11 is turned on, T19 is turned on, the potential of N1 is Vref1+Vth1, which compensates for the threshold voltage of T11; the gate-source voltage Vgs2 of T21 is equal to Vint1-Vref2, Vgs2 is less than Vth2, Vth2 is the threshold voltage of T21, T21 is turned on, T29 is turned on, the potential of N2 is Vref2+Vth2, which compensates for the threshold voltage of T21;

[0516] During the data writing phase S1, GT provides a high voltage signal, T17 and T27 are turned on, DA provides a first control data voltage VdataA to NC1 to change the potential of N1 accordingly; DB provides a second control data voltage VdataB to NC2 to change the potential of N2 accordingly.

[0517] During the data writing phase S1, GT provides a high voltage signal, TW is turned on, TS is turned on, and DT provides the display data voltage Vdata to the source of T0;

[0518] At the start of the data writing phase S1, T0 is turned on, and Vdata charges Cst through TW, T0 and TS until T0 is turned off. The gate potential of T0 is Vdata + Vth.

[0519] During the light-emitting stage S2, EM provides a low voltage signal, CTL provides a low voltage signal, TE is turned on, T0 generates a drive current Id, T18 and T28 are turned on, SWP provides a control voltage to NC1 and NC2, SWP provides a triangular wave voltage, the potential of the control voltage provided by SWP decreases, and through the coupling effect of C1 and C2, the potential of N1 and N2 decreases.

[0520] During the light-emitting stage S2, when T11 is turned on, the driving current flows through T11, and O1 does not emit light; when T21 is turned on, the driving current flows through T21, and O2 does not emit light.

[0521] Figure 23A At least one embodiment of the pixel circuit shown is Figure 21 The differences between at least one embodiment of the pixel circuit shown are as follows:

[0522] It also includes the first eleventh transistor T111 and the second eleventh transistor T211;

[0523] The gate of the first eleventh transistor T111 is electrically connected to the reset control terminal RST, the source of the first eleventh transistor T111 is electrically connected to the second initial voltage terminal I2, and the drain of the first eleventh transistor T111 is electrically connected to the first node NC1.

[0524] The gate of the second eleventh transistor T211 is electrically connected to the reset control terminal RST, the source of the second eleventh transistor T211 is electrically connected to the second initial voltage terminal I2, and the drain of the second eleventh transistor T211 is electrically connected to the second node NC2.

[0525] Both T111 and T211 are n-type transistors.

[0526] This invention Figure 23A In at least one embodiment of the pixel circuit, during operation, in the reset phase S0, RST provides a high voltage signal, T111 and T211 are both turned on, and I2 provides a second initial voltage Vint2 to NC1 and NC2.

[0527] like Figure 23B As shown, the control voltage provided by the SWP can be the first type of triangular wave voltage;

[0528] like Figure 23CAs shown, the control voltage provided by SWP can be a second type of triangular wave voltage, which is a sawtooth voltage.

[0529] like Figure 23D As shown, the control voltage provided by the SWP can be the first type of V-wave voltage;

[0530] like Figure 23E As shown, the control voltage provided by the SWP can be the second type of V-shaped angle wave voltage.

[0531] like Figure 24A As shown, the pixel circuit of at least one embodiment of the present invention includes a pixel driving circuit 10, a first light-emitting element E1, a second light-emitting element E2, a third light-emitting element E3, a fourth light-emitting element E4, a first control circuit, a second control circuit, a third control circuit, and a fourth control circuit.

[0532] The first control circuit includes a first control transistor TC1 and a first resistance adjustment circuit 241; the second control circuit includes a second control transistor TC2 and a second resistance adjustment circuit 242; the third control circuit includes a third control transistor TC3 and a third resistance adjustment circuit 243; and the fourth control circuit includes a fourth control transistor TC4 and a fourth resistance adjustment circuit 244.

[0533] The pixel driving circuit 10 is used to generate driving current and output the driving current through the first display node NX1; the first electrode of the first light-emitting element E1 is electrically connected to the first display node NX1.

[0534] The second terminal of E1 is electrically connected to the first terminal of E2, the second terminal of E2 is electrically connected to the first terminal of E3, the second terminal of E3 is electrically connected to the first terminal of E4, and the second terminal of E4 is electrically connected to the first voltage terminal V1.

[0535] The gate of the first control transistor TC1 is electrically connected to the first control node NK1, the source of the first control transistor TC1 is electrically connected to the first terminal of the first light-emitting element E1, and the drain of the first control transistor TC1 is electrically connected to the second terminal of the first light-emitting element E1.

[0536] The first resistance adjustment circuit 241 is electrically connected to the first control node NK1 and the first control data line DA, respectively, and is used to control the equivalent resistance of the first control transistor TC1 under the control of the first control data voltage provided by the first control data line DA.

[0537] The gate of the second control transistor TC2 is electrically connected to the second control node NK2, the source of the second control transistor TC2 is electrically connected to the first terminal of the second light-emitting element E2, and the drain of the second control transistor TC2 is electrically connected to the second terminal of the second light-emitting element E2.

[0538] The second resistance adjustment circuit 242 is electrically connected to the second control node NK2 and the second control data line DB, respectively, and is used to control the equivalent resistance of the second control transistor TC2 under the control of the second control data voltage provided by the second control data line DB.

[0539] The gate of the third control transistor TC3 is electrically connected to the third control node NK3, the source of the third control transistor TC3 is electrically connected to the first terminal of the third light-emitting element E3, and the drain of the third control transistor TC3 is electrically connected to the second terminal of the third light-emitting element E3.

[0540] The third resistance adjustment circuit 243 is electrically connected to the third control node NK3 and the third control data line DC, respectively, and is used to control the equivalent resistance of the third control transistor TC3 under the control of the third control data voltage provided by the third control data line DC.

[0541] The gate of the fourth control transistor TC4 is electrically connected to the fourth control node NK4, the source of the fourth control transistor TC4 is electrically connected to the first terminal of the fourth light-emitting element E4, and the drain of the fourth control transistor TC4 is electrically connected to the second terminal of the fourth light-emitting element E4.

[0542] The fourth resistance adjustment circuit 244 is electrically connected to the fourth control node NK4 and the fourth control data line DD, respectively, and is used to control the equivalent resistance of the fourth control transistor TC4 under the control of the fourth control data voltage provided by the fourth control data line DD.

[0543] When the pixel circuit described in at least one embodiment of the present invention is working, the light-emitting diodes in multiple adjacent sub-pixels share a pixel driving circuit. The pixel driving circuit provides the highest gray level driving current to each light-emitting diode. By adjusting the equivalent resistance of each control transistor through each control data voltage, the control transistors can draw different amounts of current, thereby making the gray level flowing through each micro light-emitting diode individually controllable.

[0544] This invention Figure 24AIn at least one embodiment of the pixel circuit shown, when in operation, the light-emitting diodes in four adjacent sub-pixels share a pixel driving circuit. The pixel driving circuit provides the highest grayscale driving current to each light-emitting diode. By adjusting the equivalent resistance of each control transistor through each control data voltage, the control transistors can draw different amounts of current, thereby making the grayscale flowing through each micro light-emitting diode individually controllable.

[0545] like Figure 24B As shown, the pixel circuit of at least one embodiment of the present invention includes a pixel driving circuit 10, a first light-emitting element E1, a second light-emitting element E2, a first control circuit, and a second control circuit.

[0546] The first control circuit includes a first control transistor TC1 and a first resistance adjustment circuit 241; the second control circuit includes a second control transistor TC2 and a second resistance adjustment circuit 242.

[0547] The pixel driving circuit 10 is used to generate driving current and output the driving current through the first display node NX1; the first electrode of the first light-emitting element E1 is electrically connected to the first display node NX1.

[0548] The second terminal of E1 is electrically connected to the first terminal of E2, and the second terminal of E2 is electrically connected to the first voltage terminal V1.

[0549] The gate of the first control transistor TC1 is electrically connected to the first control node NK1, the source of the first control transistor TC1 is electrically connected to the first terminal of the first light-emitting element E1, and the drain of the first control transistor TC1 is electrically connected to the second terminal of the first light-emitting element E1.

[0550] The first resistance adjustment circuit 241 is electrically connected to the first control node NK1 and the first control data line DA, respectively, and is used to control the equivalent resistance of the first control transistor TC1 under the control of the first control data voltage provided by the first control data line DA.

[0551] The gate of the second control transistor TC2 is electrically connected to the second control node NK2, the source of the second control transistor TC2 is electrically connected to the first terminal of the second light-emitting element E2, and the drain of the second control transistor TC2 is electrically connected to the second terminal of the second light-emitting element E2.

[0552] The second resistance adjustment circuit 242 is electrically connected to the second control node NK2 and the second control data line DB, respectively, and is used to control the equivalent resistance of the second control transistor TC2 under the control of the second control data voltage provided by the second control data line DB.

[0553] This invention Figure 24BIn at least one embodiment of the pixel circuit shown, when in operation, the light-emitting diodes in two adjacent sub-pixels share a pixel driving circuit. The pixel driving circuit provides the highest grayscale driving current to each light-emitting diode. By adjusting the equivalent resistance of each control transistor through each control data voltage, the control transistors can draw different amounts of current, thereby making the grayscale flowing through each micro light-emitting diode individually controllable.

[0554] In at least one embodiment of the present invention, the nth resistor adjustment circuit includes an nth data writing circuit and an nth control energy storage circuit;

[0555] The nth data writing circuit is electrically connected to the nth data writing control terminal, the nth control data line and the nth control node, respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth control node under the control of the nth data writing control signal provided by the nth data writing control terminal.

[0556] The nth control energy storage circuit is electrically connected to the nth control node and is used to maintain the potential of the nth control node.

[0557] like Figure 25A As shown, in Figure 24A Based on at least one embodiment of the pixel circuit shown, the first resistance adjustment circuit includes a first data writing circuit 2511 and a first control energy storage circuit 2512.

[0558] The first data writing circuit 2511 is electrically connected to the first data writing control terminal GT1, the first control data line DA and the first control node NK1 respectively, and is used to write the first control data voltage provided by the first control data line DA into the first control node NK1 under the control of the first data writing control signal provided by the first data writing control terminal GT1.

[0559] The first control energy storage circuit 2512 is electrically connected to the first control node NK1 and is used to maintain the potential of the first control node NK1.

[0560] The second resistance adjustment circuit includes a second data writing circuit 2521 and a second control energy storage circuit 2522;

[0561] The second data writing circuit 2521 is electrically connected to the second data writing control terminal GT2, the second control data line DB and the second control node NK2 respectively, and is used to write the second control data voltage provided by the second control data line DB into the second control node NK2 under the control of the second data writing control signal provided by the second data writing control terminal GT2.

[0562] The second control energy storage circuit 2522 is electrically connected to the second control node NK2 and is used to maintain the potential of the second control node NK2;

[0563] The third resistance adjustment circuit includes a second data writing circuit 2531 and a third control energy storage circuit 2532;

[0564] The third data writing circuit 2531 is electrically connected to the third data writing control terminal GT3, the third control data line DC and the third control node NK3 respectively, and is used to write the third control data voltage provided by the third control data line DC into the third control node NK3 under the control of the third data writing control signal provided by the third data writing control terminal GT3.

[0565] The third control energy storage circuit 2532 is electrically connected to the third control node NK3 and is used to maintain the potential of the third control node NK3.

[0566] The fourth resistance adjustment circuit includes a fourth data writing circuit 2541 and a fourth control energy storage circuit 2542.

[0567] The fourth data writing circuit 2541 is electrically connected to the fourth data writing control terminal GT4, the fourth control data line DD and the fourth control node NK4 respectively, and is used to write the fourth control data voltage provided by the fourth control data line DD into the fourth control node NK4 under the control of the fourth data writing control signal provided by the fourth data writing control terminal GT.

[0568] The fourth control energy storage circuit 2542 is electrically connected to the fourth control node NK4 and is used to maintain the potential of the fourth control node NK4.

[0569] like Figure 25B As shown, in Figure 24B Based on at least one embodiment of the pixel circuit shown, the first resistance adjustment circuit includes a first data writing circuit 2511 and a first control energy storage circuit 2512.

[0570] The first data writing circuit 2511 is electrically connected to the first data writing control terminal GT1, the first control data line DA and the first control node NK1 respectively, and is used to write the first control data voltage provided by the first control data line DA into the first control node NK1 under the control of the first data writing control signal provided by the first data writing control terminal GT1.

[0571] The first control energy storage circuit 2512 is electrically connected to the first control node NK1 and is used to maintain the potential of the first control node NK1.

[0572] The second resistance adjustment circuit includes a second data writing circuit 2521 and a second control energy storage circuit 2522;

[0573] The second data writing circuit 2521 is electrically connected to the second data writing control terminal GT2, the second control data line DB and the second control node NK2 respectively, and is used to write the second control data voltage provided by the second control data line DB into the second control node NK2 under the control of the second data writing control signal provided by the second data writing control terminal GT2.

[0574] The second control energy storage circuit 2522 is electrically connected to the second control node NK2 and is used to maintain the potential of the second control node NK2.

[0575] In at least one embodiment of the present invention, the nth resistor adjustment circuit includes an nth data writing circuit, an nth compensation control circuit, an nth control energy storage circuit, an nth first initialization circuit, an nth first display control circuit, and an nth second display control circuit;

[0576] The first terminal of the nth control transistor is electrically connected to the first terminal of the nth light-emitting element through the nth first display control circuit, and the second terminal of the nth control transistor is electrically connected to the second terminal of the nth light-emitting element through the nth second display control circuit;

[0577] The nth first display control circuit is electrically connected to the nth display control terminal, and is used to control the connection or disconnection between the first electrode of the nth control transistor and the first electrode of the nth light-emitting element under the control of the nth display control signal provided by the nth display control terminal;

[0578] The nth second display control circuit is electrically connected to the nth display control terminal, and is used to control the connection or disconnection between the second electrode of the nth control transistor and the second electrode of the nth light-emitting element under the control of the nth display control signal provided by the nth display control terminal;

[0579] The nth control energy storage circuit is electrically connected to the nth control node and is used to maintain the potential of the nth control node;

[0580] The nth data writing circuit is electrically connected to the nth data writing control terminal, the nth control data line and the first pole of the nth control transistor, respectively, and is used to write the nth control data voltage provided by the nth control data line into the first pole of the nth control transistor under the control of the nth data writing control signal provided by the nth data writing control terminal;

[0581] The nth compensation control circuit is electrically connected to the nth data write control terminal, the nth control node, and the second pole of the nth control transistor, respectively, and is used to control the connection or disconnection between the nth control node and the second pole of the nth control transistor under the control of the nth data write control signal;

[0582] The nth first initialization circuit is electrically connected to the initial control terminal, the first initial voltage terminal and the nth control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth control node under the control of the initial control signal provided by the initial control terminal.

[0583] like Figure 26 As shown, in Figure 24B Based on at least one embodiment of the pixel circuit shown, the first resistance adjustment circuit includes a first data writing circuit 2511, a first compensation control circuit 2510, a first control energy storage circuit 2512, a first first initialization circuit 2513, a first first display control circuit 2514, and a first second display control circuit 2515.

[0584] The source of the first control transistor TC1 is electrically connected to the first electrode of the first light-emitting element E1 through the first first display control circuit 2514, and the source of the first control transistor TC1 is electrically connected to the second electrode of the first light-emitting element E1 through the first second display control circuit 2515.

[0585] The first display control circuit 2514 is electrically connected to the first display control terminal EM1 and is used to control the connection or disconnection between the source of the first control transistor TC1 and the first terminal of the first light-emitting element E1 under the control of the first display control signal provided by the first display control terminal EM1.

[0586] The first second display control circuit 2515 is electrically connected to the first display control terminal EM1 and is used to control the connection or disconnection between the drain of the first control transistor TC1 and the second terminal of the first light-emitting element E1 under the control of the first display control signal provided by the first display control terminal EM1.

[0587] The first control energy storage circuit 2512 is electrically connected to the first control node NK1 and is used to maintain the potential of the first control node NK1.

[0588] The first data writing circuit 2511 is electrically connected to the first data writing control terminal GT1, the first control data line DA and the source of the first control transistor TC1, respectively, and is used to write the first control data voltage provided by the first control data line DA to the source of the first control transistor TC1 under the control of the first data writing control signal provided by the first data writing control terminal GT1.

[0589] The first compensation control circuit 2510 is electrically connected to the drain of the first data write control terminal GT1, the first control node NK1 and the first control transistor TC1 respectively, and is used to control the connection or disconnection between the drain of the first control node NK1 and the drain of the first control transistor TC1 under the control of the first data write control signal.

[0590] The first initialization circuit 2513 is electrically connected to the initial control terminal RST_A, the first initial voltage terminal I1 and the first control node NK1 respectively, and is used to write the first initial voltage provided by the first initial voltage terminal I1 into the first control node NK1 under the control of the initial control signal provided by the initial control terminal RST_A.

[0591] The second resistance adjustment circuit includes a second data writing circuit 2521, a second compensation control circuit 2520, a second control energy storage circuit 2522, a second first initialization circuit 2523, a second first display control circuit 2524, and a second second display control circuit 2525;

[0592] The source of the second control transistor TC2 is electrically connected to the first electrode of the second light-emitting element E2 through the second first display control circuit 2524, and the source of the second control transistor TC2 is electrically connected to the second electrode of the second light-emitting element E2 through the second second display control circuit 2525.

[0593] The second first display control circuit 2524 is electrically connected to the second display control terminal EM2 and is used to control the connection or disconnection between the source of the second control transistor TC2 and the first terminal of the second light-emitting element E2 under the control of the second display control signal provided by the second display control terminal EM2.

[0594] The second second display control circuit 2525 is electrically connected to the second display control terminal EM2 and is used to control the connection or disconnection between the drain of the second control transistor TC2 and the second terminal of the second light-emitting element E2 under the control of the second display control signal provided by the second display control terminal EM2.

[0595] The second control energy storage circuit 2522 is electrically connected to the second control node NK2 and is used to maintain the potential of the second control node NK2;

[0596] The second data writing circuit 2521 is electrically connected to the second data writing control terminal GT2, the second control data line DB, and the source of the second control transistor TC2, respectively, and is used to write the second control data voltage provided by the second control data line DB to the source of the second control transistor TC2 under the control of the second data writing control signal provided by the second data writing control terminal GT2.

[0597] The second compensation control circuit 2520 is electrically connected to the drain of the second data write control terminal GT2, the second control node NK2 and the second control transistor TC2 respectively, and is used to control the connection or disconnection between the drain of the second control node NK2 and the second control transistor TC2 under the control of the second data write control signal provided by GT2.

[0598] The second first initialization circuit 2523 is electrically connected to the initial control terminal RST_A, the first initial voltage terminal I1 and the second control node NK2, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal I1 into the second control node NK2 under the control of the initial control signal provided by the initial control terminal RST_A.

[0599] Optionally, the nth control circuit includes an nth control transistor and an nth resistor adjustment circuit; the pixel circuit further includes a display control circuit.

[0600] The second electrode of the Nth light-emitting element is electrically connected to the first voltage terminal through the display control circuit;

[0601] The display control circuit includes a display switch circuit and a switch control circuit;

[0602] The display switch circuit is electrically connected to the switch control node, the second electrode of the Nth light-emitting element, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the second electrode of the Nth light-emitting element and the first voltage terminal under the control of the potential of the switch control node.

[0603] The switch control circuit is electrically connected to the switch control node, the light emission control terminal, and the pulse signal providing terminal, respectively, and is used to control the connection between the switch control node and the light emission control terminal or the pulse signal providing terminal.

[0604] like Figure 27 As shown, in Figure 25B Based on at least one embodiment of the pixel circuit shown, the pixel circuit further includes a display control circuit;

[0605] The second electrode of the second light-emitting element E2 is electrically connected to the first voltage terminal V1 through the display control circuit;

[0606] The display control circuit includes a display switch circuit 271 and a switch control circuit 272;

[0607] The display switch circuit 271 is electrically connected to the switch control node NKC, the second electrode of the second light-emitting element E2 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the second electrode of the second light-emitting element E2 and the first voltage terminal V1 under the control of the potential of the switch control node NKC.

[0608] The switch control circuit 272 is electrically connected to the switch control node NKC, the light emission control terminal EM, and the pulse signal providing terminal HF, respectively, and is used to control the connection between the switch control node NKC and the light emission control terminal EM or the pulse signal providing terminal HF.

[0609] This invention Figure 27 In at least one embodiment of the pixel circuit shown, when in operation, the switch control circuit 272 controls the switch control node NKC to connect with the light emission control terminal EM or the pulse signal providing terminal HF, wherein the pulse signal providing terminal HF can provide a high-frequency pulse signal;

[0610] When NKC and EM are connected, during the light-emitting stage, the display switch circuit 271 controls the second electrode of the second light-emitting element E2 to be connected to the first voltage terminal V1 under the control of the potential of the switch control node NKC.

[0611] When NKC and HF are connected, during the light-emitting stage, when HF provides an effective voltage signal, the display switch circuit 271 controls the second electrode of the second light-emitting element E2 to be connected to the first voltage terminal V1 under the control of the potential of the switch control node NKC.

[0612] Optionally, the nth data writing circuit includes the nth twelfth transistor, and the nth control energy storage circuit includes the nth control capacitor;

[0613] The gate of the nth twelfth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth twelfth transistor is electrically connected to the nth control data line, and the second terminal of the nth twelfth transistor is electrically connected to the nth control node.

[0614] The first terminal of the nth control capacitor is electrically connected to the nth control node, and the second terminal of the nth control capacitor is electrically connected to the reference voltage terminal.

[0615] like Figure 28 As shown, in Figure 25A Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, the second light-emitting element is a second micro light-emitting diode O2, the third light-emitting element is a third micro light-emitting diode O3, and the fourth light-emitting element is a fourth micro light-emitting diode O4.

[0616] The anode of O1 is electrically connected to the first display node NX1, the cathode of O1 is electrically connected to the anode of O2, the cathode of O2 is electrically connected to the anode of O3, and the cathode of O3 is electrically connected to the anode of O4.

[0617] The first data writing circuit includes a first twelfth transistor T112, and the first control energy storage circuit includes a first control capacitor CK1.

[0618] The gate of the first twelfth transistor T112 is electrically connected to the first data write control terminal GT1, the source of the first twelfth transistor T112 is electrically connected to the first control data line DA, and the drain of the first twelfth transistor T112 is electrically connected to the first control node NK1.

[0619] The first terminal of the first control capacitor CK1 is electrically connected to the first control node NK1, and the second terminal of the first control capacitor CK1 is electrically connected to the reference voltage terminal REF; the reference voltage terminal is used to provide a reference voltage Vref.

[0620] The second data writing circuit includes a second twelfth transistor T212, and the second control energy storage circuit includes a second control capacitor CK2.

[0621] The gate of the second twelfth transistor T212 is electrically connected to the second data write control terminal GT2, the source of the second twelfth transistor T212 is electrically connected to the second control data line DB, and the drain of the second twelfth transistor T212 is electrically connected to the second control node NK2.

[0622] The first terminal of the second control capacitor CK2 is electrically connected to the second control node NK2, and the second terminal of the second control capacitor CK2 is electrically connected to the reference voltage terminal REF.

[0623] The third data writing circuit includes a third twelfth transistor T312, and the third control energy storage circuit includes a third control capacitor CK3;

[0624] The gate of the third twelfth transistor T312 is electrically connected to the third data write control terminal GT3, the source of the third twelfth transistor T312 is electrically connected to the third control data line DC, and the drain of the third twelfth transistor T312 is electrically connected to the third control node NK3.

[0625] The first terminal of the third control capacitor CK3 is electrically connected to the third control node NK3, and the second terminal of the third control capacitor CK3 is electrically connected to the reference voltage terminal REF.

[0626] The fourth data writing circuit includes a fourth twelfth transistor T412, and the fourth control energy storage circuit includes a fourth control capacitor CK4;

[0627] The gate of the fourth twelfth transistor T412 is electrically connected to the fourth data write control terminal GT4, the source of the fourth twelfth transistor T412 is electrically connected to the fourth control data line DD, and the drain of the fourth twelfth transistor T412 is electrically connected to the fourth control node NK4.

[0628] The first terminal of the fourth control capacitor CK4 is electrically connected to the fourth control node NK4, and the second terminal of the fourth control capacitor CK4 is electrically connected to the reference voltage terminal REF.

[0629] This invention Figure 28 In at least one embodiment of the pixel circuit shown, during operation, the pixel driving circuit generates a driving current during the light-emitting phase.

[0630] During the data writing phase preceding the light emission phase, GT1, GT2, GT3, and GT4 all provide low-voltage signals. DA provides a first control data voltage to NK1, and CK1 maintains the potential of NK1. DB provides a second control data voltage to NK2, and CK2 maintains the potential of NK2. DC provides a third control data voltage to NK3, and CK3 maintains the potential of NK3. DD provides a fourth control data voltage to NK4, and CK4 maintains the potential of NK4. The equivalent resistance of TC1 is controlled by the first control data voltage, the equivalent resistance of TC2 is controlled by the second control data voltage, the equivalent resistance of TC3 is controlled by the third control data voltage, and the equivalent resistance of TC4 is controlled by the fourth control data voltage.

[0631] like Figure 29 As shown, in Figure 25B Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, and the second light-emitting element is a second micro light-emitting diode O2;

[0632] The anode of O1 is electrically connected to the first display node NX1, and the cathode of O1 is electrically connected to the anode of O2.

[0633] The first data writing circuit includes a first twelfth transistor T112, and the first control energy storage circuit includes a first control capacitor CK1.

[0634] The gate of the first twelfth transistor T112 is electrically connected to the first data write control terminal GT1, the source of the first twelfth transistor T112 is electrically connected to the first control data line DA, and the drain of the first twelfth transistor T112 is electrically connected to the first control node NK1.

[0635] The first terminal of the first control capacitor CK1 is electrically connected to the first control node NK1, and the second terminal of the first control capacitor CK1 is electrically connected to the reference voltage terminal REF; the reference voltage terminal is used to provide a reference voltage Vref.

[0636] The second data writing circuit includes a second twelfth transistor T212, and the second control energy storage circuit includes a second control capacitor CK2.

[0637] The gate of the second twelfth transistor T212 is electrically connected to the second data write control terminal GT2, the source of the second twelfth transistor T212 is electrically connected to the second control data line DB, and the drain of the second twelfth transistor T212 is electrically connected to the second control node NK2.

[0638] The first end of the second control capacitor CK2 is electrically connected to the second control node NK2, and the second end of the second control capacitor CK2 is electrically connected to the reference voltage terminal REF.

[0639] Optionally, the nth data writing circuit includes the nth twelfth transistor, the nth control energy storage circuit includes the nth control capacitor; the nth first initialization circuit includes the nth thirteenth transistor, the nth first display control circuit includes the nth fourteenth transistor, the nth second display control circuit includes the nth fifteenth transistor; and the nth compensation control circuit includes the nth sixteenth transistor.

[0640] The gate of the nth fourteenth transistor is electrically connected to the nth display control terminal, the first terminal of the nth fourteenth transistor is electrically connected to the first terminal of the nth control transistor, and the second terminal of the nth fourteenth transistor is electrically connected to the first terminal of the nth light-emitting element.

[0641] The gate of the nth fifteenth transistor is electrically connected to the nth display control terminal, the first terminal of the nth fifteenth transistor is electrically connected to the second terminal of the nth control transistor, and the second terminal of the nth fifteenth transistor is electrically connected to the second terminal of the nth light-emitting element.

[0642] The first terminal of the nth control capacitor is electrically connected to the nth control node, and the second terminal of the nth control capacitor is electrically connected to the reference voltage terminal.

[0643] The gate of the nth twelfth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth twelfth transistor is electrically connected to the nth control data line, and the second terminal of the nth twelfth transistor is electrically connected to the first terminal of the nth control transistor.

[0644] The gate of the nth sixteenth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth sixteenth transistor is electrically connected to the nth control node, and the second terminal of the nth sixteenth transistor is electrically connected to the second terminal of the nth control transistor.

[0645] The gate of the nth thirteenth transistor is electrically connected to the initial control terminal, the first terminal of the nth thirteenth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth thirteenth transistor is electrically connected to the nth control node.

[0646] Figure 30 As shown, in Figure 26 Based on at least one embodiment of the pixel circuit shown, the first light-emitting element is a first micro light-emitting diode O1, and the second light-emitting element is a second micro light-emitting diode O2;

[0647] The anode of O1 is electrically connected to the first display node NX1, and the cathode of O1 is electrically connected to the anode of O2.

[0648] The first data writing circuit includes a first twelfth transistor T112; the first control energy storage circuit includes a first control capacitor NK1; the first first initialization circuit includes a first thirteenth transistor T113; the first first display control circuit includes a first fourteenth transistor T114; the first second display control circuit includes a first fifteenth transistor T115; and the first compensation control circuit includes a first sixteenth transistor T116.

[0649] The gate of the first fourteenth transistor T114 is electrically connected to the first display control terminal EM1, the source of the first fourteenth transistor T114 is electrically connected to the source of the first control transistor TC1, and the drain of the first fourteenth transistor T114 is electrically connected to the first terminal of the first light-emitting element E1.

[0650] The gate of the first fifteenth transistor T115 is electrically connected to the first display control terminal EM1, the source of the first fifteenth transistor T115 is electrically connected to the drain of the first control transistor TC1, and the drain of the first fifteenth transistor T115 is electrically connected to the second terminal of the first light-emitting element E1.

[0651] The first terminal of the first control capacitor CK1 is electrically connected to the first control node NK1, and the second terminal of the first control capacitor CK1 is electrically connected to the reference voltage terminal REF.

[0652] The gate of the first twelfth transistor T112 is electrically connected to the first data write control terminal GT1, the source of the first twelfth transistor T112 is electrically connected to the first control data line DA, and the drain of the first twelfth transistor T112 is electrically connected to the source of the first control transistor TC1.

[0653] The gate of the first sixteenth transistor T116 is electrically connected to the first data write control terminal GT1, the source of the first sixteenth transistor T116 is electrically connected to the first control node NK1, and the drain of the first sixteenth transistor T116 is electrically connected to the drain of the first control transistor TC1.

[0654] The gate of the first thirteenth transistor T113 is electrically connected to the initial control terminal RST_A, the source of the first thirteenth transistor T113 is electrically connected to the first initial voltage terminal I1, and the drain of the first thirteenth transistor T113 is electrically connected to the first control node NK1.

[0655] The second data writing circuit includes a second twelfth transistor T212; the second control energy storage circuit includes a second control capacitor NK2; the second first initialization circuit includes a second thirteenth transistor T213; the second first display control circuit includes a second fourteenth transistor T214; the second second display control circuit includes a second fifteenth transistor T215; and the second compensation control circuit includes a second sixteenth transistor T216.

[0656] The gate of the second fourteenth transistor T214 is electrically connected to the second display control terminal EM2, the source of the second fourteenth transistor T214 is electrically connected to the source of the second control transistor TC2, and the drain of the second fourteenth transistor T214 is electrically connected to the first terminal of the second light-emitting element E2.

[0657] The gate of the second fifteenth transistor T115 is electrically connected to the second display control terminal EM2, the source of the second fifteenth transistor T215 is electrically connected to the drain of the second control transistor TC2, and the drain of the second fifteenth transistor T215 is electrically connected to the second terminal of the second light-emitting element E2.

[0658] The first terminal of the second control capacitor CK2 is electrically connected to the second control node NK2, and the second terminal of the second control capacitor CK2 is electrically connected to the reference voltage terminal REF.

[0659] The gate of the second twelfth transistor T212 is electrically connected to the second data write control terminal GT2, the source of the second twelfth transistor T212 is electrically connected to the second control data line DB, and the drain of the second twelfth transistor T212 is electrically connected to the source of the second control transistor TC2.

[0660] The gate of the second sixteenth transistor T216 is electrically connected to the second data write control terminal GT2, the source of the second sixteenth transistor T216 is electrically connected to the second control node NK2, and the drain of the second sixteenth transistor T216 is electrically connected to the drain of the second control transistor TC2.

[0661] The gate of the second thirteenth transistor T213 is electrically connected to the initial control terminal RST_A, the source of the second thirteenth transistor T213 is electrically connected to the first initial voltage terminal I1, and the drain of the second thirteenth transistor T113 is electrically connected to the second control node NK2.

[0662] The cathode of O2 is electrically connected to the low-voltage terminal VSS.

[0663] This invention Figure 30 In at least one embodiment of the pixel circuit shown, during operation, the pixel driving circuit generates a driving current during the light-emitting phase.

[0664] A reset stage and a data writing stage are set between the light emission stage;

[0665] During the reset phase, RST_A provides a low voltage signal, T113 and T213 are both turned on, and I1 provides a first initial voltage Vint1 to NK1 and NK2 so that TC1 and TC2 can be turned on when the data write phase begins.

[0666] During the data writing phase, GT1 and GT2 both provide low voltage signals, T112 and T116 are turned on, and DA provides the first control data voltage VdataA to the source of TC1; T212 and T216 are turned on, and DB provides the second control data voltage VdataB to the source of TC2.

[0667] At the start of the data writing phase, T116 is turned on, and VdataA charges CK1 through T112, TC1 and T116 until TC1 is turned off. The gate potential of TC1 is VdataA + Vth1, where Vth1 is the threshold voltage of TC1.

[0668] At the start of the data writing phase, T216 is turned on, and VdataB charges CK2 through T212, TC2 and T216 until TC2 is turned off. The gate potential of TC2 is VdataB + Vth2, where Vth2 is the threshold voltage of TC2.

[0669] During the light-emitting stage, the pixel driving circuit generates a driving current, and T114, T115, T214 and T215 are turned on. The equivalent resistance of TC1 is controlled by VdataA and the equivalent resistance of TC2 is controlled by VdataB, so that each control transistor draws a different amount of current, thereby making the grayscale flowing through each micro light-emitting diode individually controllable.

[0670] Optionally, the display switch circuit includes a seventeenth transistor;

[0671] The gate of the seventeenth transistor is electrically connected to the switch control node, the first terminal of the seventeenth transistor is electrically connected to the second terminal of the Nth light-emitting element, and the second terminal of the seventeenth transistor is electrically connected to the first voltage terminal.

[0672] Optionally, the switch control circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a switch control capacitor;

[0673] The gate of the eighteenth transistor is electrically connected to the reset control terminal, the first terminal of the eighteenth transistor is electrically connected to the control data line, and the second terminal of the eighteenth transistor is electrically connected to the control node.

[0674] The gate of the nineteenth transistor is electrically connected to the switch control node, the first terminal of the nineteenth transistor is electrically connected to the light-emitting control terminal, and the second terminal of the nineteenth transistor is electrically connected to the switch control node.

[0675] The gate of the twentieth transistor is electrically connected to the switch control node, the first terminal of the twentieth transistor is electrically connected to the pulse signal providing terminal, and the second terminal of the twentieth transistor is electrically connected to the switch control node.

[0676] The first terminal of the switch control capacitor is electrically connected to the control node, and the second terminal of the switch control capacitor is electrically connected to the DC voltage terminal.

[0677] Figure 31 At least one embodiment of the pixel circuit shown is Figure 29 The difference in at least one embodiment of the pixel circuit shown is that:

[0678] It also includes a display switch control circuit and a switch control circuit;

[0679] The display switch circuit includes a seventeenth transistor T017;

[0680] The gate of the seventeenth transistor T017 is electrically connected to the switch control node NKC, the source of the seventeenth transistor T017 is electrically connected to the second terminal of the second light-emitting element E2, and the drain of the seventeenth transistor T017 is electrically connected to the low voltage terminal VSS.

[0681] The switching control circuit includes the eighteenth transistor T018, the nineteenth transistor T019, the twentieth transistor T020, and the switching control capacitor CK;

[0682] The gate of the eighteenth transistor T018 is electrically connected to the reset control terminal RST, the source of the eighteenth transistor T018 is electrically connected to the control data line DTC, and the drain of the eighteenth transistor T018 is electrically connected to the control node NC.

[0683] The gate of the nineteenth transistor T019 is electrically connected to the switch control node NKC, the source of the nineteenth transistor T019 is electrically connected to the light emission control terminal EM, and the drain of the nineteenth transistor T019 is electrically connected to the switch control node NKC.

[0684] The gate of the twentieth transistor T020 is electrically connected to the switch control node NKC, the source of the twentieth transistor T020 is electrically connected to the pulse signal providing terminal HF, and the drain of the twentieth transistor T020 is electrically connected to the switch control node NKC.

[0685] The first terminal of the switch control capacitor CK is electrically connected to the control node NC, and the second terminal of the switch control capacitor CK is electrically connected to the low voltage terminal VSS.

[0686] This invention Figure 31 At least one embodiment of the pixel circuit shown adds T017, T018, T019 and T020. During the reset phase, RST provides a low voltage signal, T108 is turned on, and DTC provides control data voltage to NC. When the control data voltage is a low voltage signal, T019 is turned on, and NKC and EM are connected. When the control data voltage is a high voltage signal, T020 is turned on, and NKC and HF are connected.

[0687] Optionally, the switch control circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a first switch control capacitor, and a second switch control capacitor;

[0688] The gate of the 21st transistor is electrically connected to the first reset control terminal, the first terminal of the 21st transistor is electrically connected to the first display control data line, and the second terminal of the 21st transistor is electrically connected to the first control node.

[0689] The gate of the 22nd transistor is electrically connected to the first switch control node, the first terminal of the 22nd transistor is electrically connected to the light-emitting control terminal, and the second terminal of the 22nd transistor is electrically connected to the switch control node.

[0690] The gate of the 23rd transistor is electrically connected to the second reset control terminal, the first terminal of the 23rd transistor is electrically connected to the second display control data line, and the second terminal of the 23rd transistor is electrically connected to the second control node;

[0691] The gate of the 24th transistor is electrically connected to the second switch control node, the first terminal of the 24th transistor is electrically connected to the pulse signal providing terminal, and the second terminal of the 24th transistor is electrically connected to the switch control node.

[0692] The first terminal of the first switch control capacitor is electrically connected to the first switch control node, and the second terminal of the first switch control capacitor is electrically connected to the DC voltage terminal.

[0693] The first end of the second switch control capacitor is electrically connected to the second switch control node, and the second end of the second switch control capacitor is electrically connected to the DC voltage terminal.

[0694] Figure 32 At least one embodiment of the pixel circuit shown is Figure 29 The difference in at least one embodiment of the pixel circuit shown is that:

[0695] It also includes a display switch control circuit and a switch control circuit;

[0696] The display switch circuit includes a seventeenth transistor T017;

[0697] The gate of the seventeenth transistor T017 is electrically connected to the switch control node NKC, the source of the seventeenth transistor T017 is electrically connected to the second terminal of the second light-emitting element E2, and the drain of the seventeenth transistor T017 is electrically connected to the low voltage terminal VSS.

[0698] The switch control circuit includes a 21st transistor T021, a 22nd transistor T022, a 23rd transistor T023, a 24th transistor T024, a first switch control capacitor CKC1, and a second switch control capacitor CKC2.

[0699] The gate of the 21st transistor T021 is electrically connected to the first reset control terminal RA, the source of the 21st transistor T021 is electrically connected to the first display control data line DXA, and the drain of the 21st transistor T021 is electrically connected to the first switch control node NKC1.

[0700] The gate of the 22nd transistor T022 is electrically connected to the first switch control node NKC1, the source of the 22nd transistor T022 is electrically connected to the light emission control terminal EM, and the drain of the 22nd transistor T022 is electrically connected to the switch control node NKC.

[0701] The gate of the 23rd transistor T023 is electrically connected to the second reset control terminal RB, the source of the 23rd transistor T023 is electrically connected to the second display control data line DXB, and the drain of the 23rd transistor T023 is electrically connected to the second switch control node NKC2.

[0702] The gate of the 24th transistor T024 is electrically connected to the second switch control node NKC2, the source of the 24th transistor T024 is electrically connected to the pulse signal providing terminal HF, and the drain of the 24th transistor T024 is electrically connected to the switch control node NKC.

[0703] The first terminal of the first switch control capacitor CKC1 is electrically connected to the first switch control node NKC1, and the second terminal of the first switch control capacitor CKC1 is electrically connected to the low voltage terminal VSS.

[0704] The first terminal of the second switch control capacitor CKC2 is electrically connected to the second switch control node NKC2, and the second terminal of the second switch control capacitor CKC2 is electrically connected to the low voltage terminal VSS.

[0705] The cathode of O1 is electrically connected to the low-voltage terminal VSS.

[0706] This invention Figure 32At least one embodiment of the pixel circuit shown adds T017, T021, T022, T023, T024, CKC1 and CKC2;

[0707] During the reset phase, RA and RB provide low voltage signals, T021 and T023 are turned on, DXA provides the first display control data voltage to NKC1, DXB provides the second display control data voltage to NKC2, CKC1 maintains the potential of NKC1, and CK2 maintains the potential of NKC2.

[0708] When the first display control data voltage is a low voltage signal and the second display control data voltage is a high voltage signal, T022 is turned on, T024 is turned off, and EM and NKC are connected.

[0709] When the second display control data voltage is a low voltage signal and the first display control data voltage is a high voltage signal, T024 is turned on and T022 is turned off, connecting HF and NKC.

[0710] In at least one embodiment of the present invention, VDD-VSS can be adjusted according to the actual voltage required in the current path. For example, when one LED in the current path is not emitting light, VDD-VSS can reduce the voltage across one LED, thereby reducing power consumption.

[0711] like Figure 33A As shown, A0 is the effective display area of ​​the display panel, P1 is the first sub-pixel, P2 is the second sub-pixel, P3 is the third sub-pixel, and PM is the Mth sub-pixel; the sub-pixels to which different light-emitting elements in a pixel circuit belong can extend horizontally.

[0712] like Figure 33B As shown, A0 is the effective display area of ​​the display panel, P1 is the first sub-pixel, P2 is the second sub-pixel, P3 is the third sub-pixel, and PM is the Mth sub-pixel; the sub-pixels to which different light-emitting elements in a pixel circuit belong can extend vertically.

[0713] like Figure 33C As shown, A0 is the effective display area of ​​the display panel, P1 is the first sub-pixel, P2 is the second sub-pixel, P3 is the third sub-pixel, and PM is the Mth sub-pixel; the sub-pixels to which different light-emitting elements in a pixel circuit belong can be arranged in an array.

[0714] like Figure 34As shown, at least one embodiment of the pixel driving circuit may include a driving transistor T0, a data writing transistor TW, a first light-emitting control transistor TE1, and a storage capacitor Cst;

[0715] The source of T0 is electrically connected to the power supply voltage terminal VDD, and the drain of T0 is electrically connected to the source of TE1.

[0716] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the gate of T0.

[0717] The gate of TE1 is electrically connected to the light-emitting control terminal EM, and the drain of TE1 is electrically connected to the first display node NX.

[0718] The first terminal of Cst is electrically connected to the gate of T0, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0719] like Figure 35 As shown, at least one embodiment of the pixel driving circuit may include a driving transistor T0, a first light-emitting control transistor TE1, a data writing transistor TW, a first reset transistor TR1, a second reset transistor TR2, a compensation control transistor TS, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0720] The source of T0 is electrically connected to the power supply voltage terminal VDD, and the drain of T0 is electrically connected to the source of TE1.

[0721] The first terminal of Cst1 is electrically connected to the gate of T0, the second terminal of Cst1 is electrically connected to the first terminal of Cst2, and the second terminal of Cst2 is electrically connected to the second reference voltage terminal REF2.

[0722] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the second terminal of Cst1.

[0723] The gate of TR1 is electrically connected to the reset control terminal RST, the source of TR1 is electrically connected to the first initial voltage terminal I1, and the drain of TR1 is electrically connected to the gate of T0.

[0724] The gate of TR2 is electrically connected to the scan signal terminal CG, the source of TR2 is electrically connected to the first reference voltage terminal REF1, and the drain of TR2 is electrically connected to the second terminal of Cst2.

[0725] The gate of TS is electrically connected to the scan signal terminal CG, the source of TS is electrically connected to the gate of T0, and the drain of TS is electrically connected to the drain of T0.

[0726] The drain of TE1 is electrically connected to the first display node NX1.

[0727] like Figure 36 As shown, at least one embodiment of the pixel driving circuit may include a driving transistor T0, a first light-emitting control transistor TE1, a data writing transistor TW, a first reset transistor TR1, a second reset transistor TR2, a third reset transistor TR3, a fourth reset transistor TR4, a compensation control transistor TS, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0728] The source of T0 is electrically connected to the power supply voltage terminal VDD, and the drain of T0 is electrically connected to the source of TE1.

[0729] The first terminal of Cst1 is electrically connected to the gate of T0, and the second terminal of Cst1 is electrically connected to the first terminal of Cst2.

[0730] The gate of TW is electrically connected to the scan terminal GT, the source of TW is electrically connected to the data line DT, and the drain of TW is electrically connected to the second terminal of Cst2.

[0731] The gate of TR1 is electrically connected to the reset control terminal RST, the source of TR1 is electrically connected to the first initial voltage terminal I1, and the drain of TR1 is electrically connected to the gate of T0.

[0732] The gate of TR2 is electrically connected to the scan signal terminal CG, the source of TR2 is electrically connected to the second reference voltage terminal REF2, and the drain of TR2 is electrically connected to the second terminal of Cst1.

[0733] The gate of TR3 is electrically connected to the reset control RST, the source of TR3 is electrically connected to the second reference voltage terminal REF2, and the drain of TR2 is electrically connected to the second terminal of Cst1.

[0734] The gate of TR4 is electrically connected to the light-emitting control terminal EM, the source of TR4 is electrically connected to the first reference voltage terminal REF1, and the drain of TR4 is electrically connected to the second terminal of Cst2.

[0735] The gate of TS is electrically connected to the scan signal terminal CG, the source of TS is electrically connected to the gate of T0, and the drain of TS is electrically connected to the drain of T0.

[0736] The drain of TE1 is electrically connected to the first display node NX1.

[0737] The display device described in this embodiment of the invention includes the pixel circuit described above.

[0738] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that, It includes a pixel driving circuit, N light-emitting elements, and N control circuits; N is an integer greater than 1; n is a positive integer less than or equal to N; m is a positive integer less than N; The pixel driving circuit is used to generate driving current and output the driving current through the first display node; The first electrode of the first light-emitting element is electrically connected to the first display node; the second electrode of the m-th light-emitting element is electrically connected to the first electrode of the (m+1)-th light-emitting element; the second electrode of the N-th light-emitting element is electrically connected to the first voltage terminal. The nth control circuit is electrically connected to the first electrode of the nth light-emitting element, the second electrode of the nth light-emitting element, the nth control data line, and the control voltage terminal, respectively, and is used to control the connection or disconnection between the first electrode and the second electrode of the nth light-emitting element under the control of the nth control data voltage provided by the nth control data line and the control voltage provided by the control voltage terminal; or... The nth control circuit includes an nth control transistor and an nth resistor adjustment circuit; The gate of the nth control transistor is electrically connected to the nth control node, the first electrode of the nth control transistor is electrically connected to the first electrode of the nth light-emitting element, and the second electrode of the nth control transistor is electrically connected to the second electrode of the nth light-emitting element. The nth resistor adjustment circuit is electrically connected to the nth control node and the nth control data line, respectively, and is used to control the equivalent resistance of the nth control transistor under the control of the nth control data voltage provided by the nth control data line.

2. The pixel circuit as described in claim 1, characterized in that, The nth control circuit includes an nth on / off control circuit and an nth on / off control node control circuit; The nth on / off control circuit is electrically connected to the nth on / off control node, the first electrode of the nth light-emitting element, and the second electrode of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the first electrode of the nth light-emitting element and the second electrode of the nth light-emitting element under the control of the potential of the nth on / off control node; The control circuit of the nth on / off control node is electrically connected to the nth control data line, the nth on / off control node, and the control voltage terminal, respectively, and is used to control the potential of the nth on / off control node under the control of the nth control data voltage and the control voltage.

3. The pixel circuit as described in claim 2, characterized in that, The control circuit of the nth on / off control node includes an nth control data writing circuit and an nth energy storage circuit; The nth control data writing circuit is electrically connected to the nth scan terminal, the nth control data line and the nth on / off control node, respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth on / off control node under the control of the nth scan signal provided by the nth scan terminal; The first terminal of the nth energy storage circuit is electrically connected to the nth on / off control node, and the second terminal of the nth energy storage circuit is electrically connected to the control voltage terminal. The nth energy storage circuit is used to store electrical energy.

4. The pixel circuit as described in claim 3, characterized in that, The control circuit of the nth on / off control node also includes the nth first reset circuit; The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth on / off control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth on / off control node under the control of the reset control signal provided by the reset control terminal.

5. The pixel circuit as described in claim 2, characterized in that, The control circuit of the nth on / off control node includes the nth control data writing circuit, the nth energy storage circuit, and the nth node control circuit; The nth control data writing circuit is electrically connected to the nth scan end, the nth control data line and the nth node respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth node under the control of the nth scan signal provided by the nth scan end; The first terminal of the nth energy storage circuit is electrically connected to the nth node, and the second terminal of the nth energy storage circuit is electrically connected to the control voltage terminal. The nth energy storage circuit is used to store electrical energy. The nth node control circuit is electrically connected to the nth node, the nth on / off control node, the second voltage terminal, and the third voltage terminal, respectively, and is used to control the connection or disconnection between the nth on / off control node and the second voltage terminal, and to control the connection or disconnection between the nth on / off control node and the third voltage terminal under the control of the potential of the nth node.

6. The pixel circuit as described in claim 5, characterized in that, The control circuit of the nth on / off control node also includes the nth first reset circuit; The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth node under the control of the reset control signal provided by the reset control terminal.

7. The pixel circuit as described in claim 5 or 6, characterized in that, It also includes a display light-emitting control circuit; The display light emission control circuit is electrically connected to the light emission control terminal, the first display node, and the first electrode of the first light emission element, respectively, and is used to control the connection or disconnection between the first display node and the first electrode of the first light emission element under the control of the light emission control signal provided by the light emission control terminal.

8. The pixel circuit as described in claim 2, characterized in that, The nth control circuit further includes an nth display light-emitting control circuit; the nth on / off control node control circuit includes an nth control data writing circuit, an nth writing control circuit, an nth first reset circuit, an nth energy storage circuit, an nth compensation control circuit, and an nth set circuit; The first electrode of the nth light-emitting element is electrically connected to the nth display node; The nth display light emission control circuit is electrically connected to the light emission control terminal, the nth display node, and the first pole of the nth light emission element, and is used to control the connection or disconnection between the nth display node and the first pole of the nth light emission element under the control of the light emission control signal provided by the light emission control terminal; The nth control data writing circuit is electrically connected to the nth scan end, the nth control data line and the nth node respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth node under the control of the nth scan signal provided by the nth scan end; The nth write control circuit is electrically connected to the write control terminal, the control voltage terminal, and the nth node, respectively, and is used to write the control voltage to the nth node under the control of the write control signal provided by the write control terminal; The nth first reset circuit is electrically connected to the reset control terminal, the first initial voltage terminal and the nth on / off control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth on / off control node under the control of the reset control signal provided by the reset control terminal; The first terminal of the nth energy storage circuit is electrically connected to the nth node, and the second terminal of the nth energy storage circuit is electrically connected to the nth on / off control node. The nth energy storage circuit is used to store electrical energy. The nth compensation control circuit is electrically connected to the compensation control terminal, the nth on / off control node, and the second electrode of the nth light-emitting element, respectively, and is used to control the connection or disconnection between the nth on / off control node and the second electrode of the nth light-emitting element under the control of the compensation control signal provided by the compensation control terminal; The nth set circuit is electrically connected to the scanning terminal, the nth reference voltage terminal, and the first electrode of the nth light-emitting element, respectively, and is used to write the nth reference voltage provided by the nth reference voltage terminal into the first electrode of the nth light-emitting element under the control of the scanning signal provided by the scanning terminal.

9. The pixel circuit as described in claim 8, characterized in that, The control circuit of the nth on / off control node also includes the nth second reset circuit; The nth second reset circuit is electrically connected to the reset control terminal, the second initial voltage terminal and the nth node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the nth node under the control of the reset control signal.

10. The pixel circuit as described in claim 1, characterized in that, The nth resistor adjustment circuit includes an nth data writing circuit and an nth control energy storage circuit; The nth data writing circuit is electrically connected to the nth data writing control terminal, the nth control data line and the nth control node, respectively, and is used to write the nth control data voltage provided by the nth control data line into the nth control node under the control of the nth data writing control signal provided by the nth data writing control terminal. The nth control energy storage circuit is electrically connected to the nth control node and is used to maintain the potential of the nth control node.

11. The pixel circuit as described in claim 1, characterized in that, The nth resistor adjustment circuit includes an nth data writing circuit, an nth compensation control circuit, an nth control energy storage circuit, an nth first initialization circuit, an nth first display control circuit, and an nth second display control circuit; The first terminal of the nth control transistor is electrically connected to the first terminal of the nth light-emitting element through the nth first display control circuit, and the second terminal of the nth control transistor is electrically connected to the second terminal of the nth light-emitting element through the nth second display control circuit; The nth first display control circuit is electrically connected to the nth display control terminal, and is used to control the connection or disconnection between the first electrode of the nth control transistor and the first electrode of the nth light-emitting element under the control of the nth display control signal provided by the nth display control terminal; The nth second display control circuit is electrically connected to the nth display control terminal, and is used to control the connection or disconnection between the second electrode of the nth control transistor and the second electrode of the nth light-emitting element under the control of the nth display control signal provided by the nth display control terminal; The nth control energy storage circuit is electrically connected to the nth control node and is used to maintain the potential of the nth control node; The nth data writing circuit is electrically connected to the nth data writing control terminal, the nth control data line and the first pole of the nth control transistor, respectively, and is used to write the nth control data voltage provided by the nth control data line into the first pole of the nth control transistor under the control of the nth data writing control signal provided by the nth data writing control terminal; The nth compensation control circuit is electrically connected to the nth data write control terminal, the nth control node, and the second pole of the nth control transistor, respectively, and is used to control the connection or disconnection between the nth control node and the second pole of the nth control transistor under the control of the nth data write control signal; The nth first initialization circuit is electrically connected to the initial control terminal, the first initial voltage terminal and the nth control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the nth control node under the control of the initial control signal provided by the initial control terminal.

12. The pixel circuit as described in claim 10 or 11, characterized in that, The nth control circuit includes an nth control transistor and an nth resistor adjustment circuit; the pixel circuit also includes a display control circuit. The second electrode of the Nth light-emitting element is electrically connected to the first voltage terminal through the display control circuit; The display control circuit includes a display switch circuit and a switch control circuit; The display switch circuit is electrically connected to the switch control node, the second electrode of the Nth light-emitting element, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the second electrode of the Nth light-emitting element and the first voltage terminal under the control of the potential of the switch control node. The switch control circuit is electrically connected to the switch control node, the light emission control terminal, and the pulse signal providing terminal, respectively, and is used to control the connection between the switch control node and the light emission control terminal or the pulse signal providing terminal.

13. The pixel circuit as described in claim 3, characterized in that, The nth on / off control circuit includes an nth first transistor, the nth control data writing circuit includes an nth second transistor, and the nth energy storage circuit includes an nth storage capacitor; The gate of the nth first transistor is electrically connected to the nth on / off control node, the first electrode of the nth first transistor is electrically connected to the first electrode of the nth light-emitting element, and the second electrode of the nth first transistor is electrically connected to the second electrode of the nth light-emitting element. The gate of the nth second transistor is electrically connected to the nth scan terminal, the first terminal of the nth second transistor is electrically connected to the nth control data line, and the second terminal of the nth second transistor is electrically connected to the nth on / off control node. The first terminal of the nth storage capacitor is electrically connected to the nth on / off control node, and the second terminal of the nth storage capacitor is electrically connected to the control voltage terminal.

14. The pixel circuit as described in claim 4, characterized in that, The nth first reset circuit includes the nth third transistor; The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth on / off control node.

15. The pixel circuit as described in claim 5, characterized in that, The nth control data writing circuit includes the nth second transistor, the nth energy storage circuit includes the nth storage capacitor, and the nth node control circuit includes the nth fourth transistor and the nth fifth transistor; The gate of the nth second transistor is electrically connected to the nth scan terminal, the first terminal of the nth second transistor is electrically connected to the nth control data line, and the second terminal of the nth second transistor is electrically connected to the nth node; The first end of the nth storage capacitor is electrically connected to the nth node, and the second end of the nth storage capacitor is electrically connected to the control voltage terminal; The gate of the nth fourth transistor is electrically connected to the nth node, the first terminal of the nth fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the nth fourth transistor is electrically connected to the nth on / off control node. The gate of the nth fifth transistor is electrically connected to the nth node, the first terminal of the nth fifth transistor is electrically connected to the nth on / off control node, and the second terminal of the nth fifth transistor is electrically connected to the third voltage terminal.

16. The pixel circuit as described in claim 6, characterized in that, The nth first reset circuit includes the nth third transistor; The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth node.

17. The pixel circuit as described in claim 7, characterized in that, The display light-emitting control circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first display node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the first light-emitting element.

18. The pixel circuit as described in claim 8, characterized in that, The nth display light emission control circuit includes the nth sixth transistor, the nth control data writing circuit includes the nth seventh transistor, the nth writing control circuit includes the nth eighth transistor, the nth first reset circuit includes the nth third transistor, the nth energy storage circuit includes the nth storage capacitor, the nth compensation control circuit includes the nth ninth transistor, and the nth set circuit includes the nth tenth transistor. The gate of the nth sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the nth sixth transistor is electrically connected to the nth display node, and the second electrode of the nth sixth transistor is electrically connected to the first electrode of the nth light-emitting element. The gate of the nth seventh transistor is electrically connected to the nth scan terminal, the first terminal of the nth seventh transistor is electrically connected to the nth control data line, and the second terminal of the nth seventh transistor is electrically connected to the nth node; The gate of the nth eighth transistor is electrically connected to the write control terminal, the first terminal of the nth eighth transistor is electrically connected to the control voltage terminal, and the second terminal of the nth eighth transistor is electrically connected to the nth node. The gate of the nth third transistor is electrically connected to the reset control terminal, the first terminal of the nth third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth third transistor is electrically connected to the nth on / off control node. The first end of the nth storage capacitor is electrically connected to the nth node, and the second end of the nth storage capacitor is electrically connected to the nth on / off control node. The gate of the nth ninth transistor is electrically connected to the compensation control terminal, the first electrode of the nth ninth transistor is electrically connected to the nth on / off control node, and the second electrode of the nth ninth transistor is electrically connected to the second electrode of the nth light-emitting element. The gate of the nth tenth transistor is electrically connected to the scanning terminal, the first terminal of the nth tenth transistor is electrically connected to the nth reference voltage terminal, and the second terminal of the nth tenth transistor is electrically connected to the first terminal of the nth light-emitting element.

19. The pixel circuit as described in claim 9, characterized in that, The nth second reset circuit includes the nth eleventh transistor; The gate of the nth eleventh transistor is electrically connected to the reset control terminal, the first terminal of the nth eleventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the nth eleventh transistor is electrically connected to the nth node.

20. The pixel circuit as described in claim 10, characterized in that, The nth data writing circuit includes the nth twelfth transistor, and the nth control energy storage circuit includes the nth control capacitor; The gate of the nth twelfth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth twelfth transistor is electrically connected to the nth control data line, and the second terminal of the nth twelfth transistor is electrically connected to the nth control node. The first terminal of the nth control capacitor is electrically connected to the nth control node, and the second terminal of the nth control capacitor is electrically connected to the reference voltage terminal.

21. The pixel circuit as described in claim 11, characterized in that, The nth data writing circuit includes the nth twelfth transistor, the nth control energy storage circuit includes the nth control capacitor; the nth first initialization circuit includes the nth thirteenth transistor, the nth first display control circuit includes the nth fourteenth transistor, and the nth second display control circuit includes the nth fifteenth transistor. The nth compensation control circuit includes the nth sixteenth transistor; The gate of the nth fourteenth transistor is electrically connected to the nth display control terminal, the first terminal of the nth fourteenth transistor is electrically connected to the first terminal of the nth control transistor, and the second terminal of the nth fourteenth transistor is connected or disconnected from the first terminal of the nth light-emitting element; The gate of the nth fifteenth transistor is electrically connected to the nth display control terminal, the first terminal of the nth fifteenth transistor is electrically connected to the second terminal of the nth control transistor, and the second terminal of the nth fifteenth transistor is electrically connected to the second terminal of the nth light-emitting element. The first terminal of the nth control capacitor is electrically connected to the nth control node, and the second terminal of the nth control capacitor is electrically connected to the reference voltage terminal. The gate of the nth twelfth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth twelfth transistor is electrically connected to the nth control data line, and the second terminal of the nth twelfth transistor is electrically connected to the first terminal of the nth control transistor. The gate of the nth sixteenth transistor is electrically connected to the nth data write control terminal, the first terminal of the nth sixteenth transistor is electrically connected to the nth control node, and the second terminal of the nth sixteenth transistor is electrically connected to the second terminal of the nth control transistor. The gate of the nth thirteenth transistor is electrically connected to the initial control terminal, the first terminal of the nth thirteenth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the nth thirteenth transistor is electrically connected to the nth control node.

22. The pixel circuit as described in claim 12, characterized in that, The display switch circuit includes a seventeenth transistor; The gate of the seventeenth transistor is electrically connected to the switch control node, the first terminal of the seventeenth transistor is electrically connected to the second terminal of the Nth light-emitting element, and the second terminal of the seventeenth transistor is electrically connected to the first voltage terminal.

23. The pixel circuit as described in claim 22, characterized in that, The switching control circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a switching control capacitor; The gate of the eighteenth transistor is electrically connected to the reset control terminal, the first terminal of the eighteenth transistor is electrically connected to the control data line, and the second terminal of the eighteenth transistor is electrically connected to the control node. The gate of the nineteenth transistor is electrically connected to the switch control node, the first terminal of the nineteenth transistor is electrically connected to the light-emitting control terminal, and the second terminal of the nineteenth transistor is electrically connected to the switch control node. The gate of the twentieth transistor is electrically connected to the switch control node, the first terminal of the twentieth transistor is electrically connected to the pulse signal providing terminal, and the second terminal of the twentieth transistor is electrically connected to the switch control node. The first terminal of the switch control capacitor is electrically connected to the control node, and the second terminal of the switch control capacitor is electrically connected to the DC voltage terminal.

24. The pixel circuit as described in claim 22, characterized in that, The switch control circuit includes a 21st transistor, a 22nd transistor, a 23rd transistor, a 24th transistor, a first switch control capacitor, and a second switch control capacitor. The gate of the 21st transistor is electrically connected to the first reset control terminal, the first terminal of the 21st transistor is electrically connected to the first display control data line, and the second terminal of the 21st transistor is electrically connected to the first control node. The gate of the 22nd transistor is electrically connected to the first switch control node, the first terminal of the 22nd transistor is electrically connected to the light-emitting control terminal, and the second terminal of the 22nd transistor is electrically connected to the switch control node. The gate of the 23rd transistor is electrically connected to the second reset control terminal, the first terminal of the 23rd transistor is electrically connected to the second display control data line, and the second terminal of the 23rd transistor is electrically connected to the second control node. The gate of the 24th transistor is electrically connected to the second switch control node, the first terminal of the 24th transistor is electrically connected to the pulse signal providing terminal, and the second terminal of the 24th transistor is electrically connected to the switch control node. The first terminal of the first switch control capacitor is electrically connected to the first switch control node, and the second terminal of the first switch control capacitor is electrically connected to the DC voltage terminal. The first end of the second switch control capacitor is electrically connected to the second switch control node, and the second end of the second switch control capacitor is electrically connected to the DC voltage terminal.

25. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 24.

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