Scanning driving circuit and electronic device

Abstract

The invention relates to a scan driving circuit and an electronic device. The scan driving circuit includes a switching circuit configured to transfer a third voltage to a first node in response to a carry signal and a first clock signal, and transfer the third voltage to a second node in response to the first clock signal; a first output transistor connected between a first voltage terminal and an output terminal and configured to operate in response to a second signal of the second node, where the first voltage terminal receives a first voltage; and a second output transistor connected between the output terminal and a second clock terminal and configured to operate in response to a first signal of the first node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0056541, filed on April 29, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to electronic devices, and more specifically, to scan drive circuits and electronic devices including scan drive circuits. Background Technology

[0004] Generally, electronic devices include pixels connected to data lines and scan lines. Each pixel includes a light-emitting element and pixel circuitry for controlling the light-emitting element. The pixel circuitry can supply a current to the light-emitting element corresponding to a data signal. Furthermore, light with a predetermined brightness can be generated in response to the current flowing through the light-emitting element.

[0005] The scan drive circuit outputs a scan signal to sequentially drive the scan lines. Summary of the Invention

[0006] According to an embodiment of this disclosure, a scan driving circuit includes: a switching circuit configured to transmit a third voltage to a first node in response to a carry signal and a first clock signal, and to transmit the third voltage to a second node in response to the first clock signal; a first output transistor connected between a first voltage terminal and an output terminal, and the first output transistor being configured to operate in response to a second signal of the second node, wherein the first voltage terminal receives the first voltage; and a second output transistor connected between the output terminal and the second clock terminal, and the second output transistor being configured to operate in response to a first signal of the first node.

[0007] In embodiments of this disclosure, the third voltage is a direct current (DC) voltage used to turn on each of the first output transistor and the second output transistor.

[0008] In embodiments of this disclosure, the switching circuit transmits one of the second voltage and the third voltage to the first node in response to the carry signal and the first clock signal, and the switching circuit transmits one of the second voltage and the third voltage to the second node in response to the first clock signal.

[0009] In embodiments of this disclosure, the second voltage is lower than or equal to the first voltage, and the third voltage is lower than the second voltage.

[0010] In embodiments of this disclosure, the switching circuit includes: a first transistor connected between a third voltage terminal receiving the third voltage and the first node, and the first transistor including a gate electrode connected to a carry terminal receiving the carry signal; a second transistor connected between the third node and the first node, and the second transistor including a gate electrode connected to the carry terminal; a third transistor connected between a second voltage terminal receiving the second voltage and the third node, and the third transistor including a gate electrode connected to a first clock terminal receiving the first clock signal; a fourth transistor connected between the third voltage terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock terminal; and a fifth transistor connected between the second voltage terminal and the second node, and the fifth transistor including a gate electrode connected to the first clock terminal.

[0011] In embodiments of this disclosure, the first transistor and the second transistor are transistors of different types from each other.

[0012] In embodiments of this disclosure, the fourth transistor and the fifth transistor are transistors of different types from each other.

[0013] In embodiments of this disclosure, the scan driving circuit further includes a capacitor connected between the first node and the output terminal.

[0014] In embodiments of this disclosure, the first clock signal and the second clock signal provided to the second clock terminal have the same frequency and different phases.

[0015] According to an embodiment of this disclosure, a scan driving circuit includes: a first switching circuit configured to transmit one of a second voltage and a third voltage to a first node in response to a carry signal and a first clock signal; a second switching circuit configured to transmit one of the second voltage and the third voltage to a second node in response to the first clock signal; a first output transistor connected between a first voltage terminal and an output terminal and configured to operate in response to a second signal of the second node, wherein the first voltage terminal receives the first voltage; and a second output transistor connected between the output terminal and the second clock terminal and configured to operate in response to a first signal of the first node.

[0016] In embodiments of this disclosure, the third voltage is a direct current (DC) voltage used to turn on each of the first output transistor and the second output transistor.

[0017] In embodiments of this disclosure, the second voltage is lower than or equal to the first voltage, and the third voltage is lower than the second voltage.

[0018] In embodiments of this disclosure, the first switching circuit includes: a first transistor connected between a third voltage terminal receiving the third voltage and the first node, and the first transistor includes a gate electrode connected to a carry terminal receiving the carry signal; a second transistor connected between the third node and the first node, and the second transistor includes a gate electrode connected to the carry terminal; and a third transistor connected between a second voltage terminal receiving the second voltage and the third node, and the third transistor includes a gate electrode connected to a first clock terminal receiving the first clock signal.

[0019] In embodiments of this disclosure, the second switching circuit includes: a fourth transistor connected between the third voltage terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock terminal; and a fifth transistor connected between the second voltage terminal and the second node, and the fifth transistor including a gate electrode connected to the first clock terminal.

[0020] According to embodiments of this disclosure, an electronic device includes: a display panel including pixels; a scan driving circuit configured to provide a scan signal to the pixels; a drive controller configured to provide a start signal, a first clock signal, and a second clock signal to the scan driving circuit; and a voltage generator configured to provide a first voltage, a second voltage, and a third voltage to the scan driving circuit, wherein the scan driving circuit includes: a switching circuit configured to transmit the third voltage to a first node in response to the start signal and the first clock signal, and to transmit the third voltage to a second node in response to the first clock signal; a first output transistor connected between a first voltage terminal receiving the first voltage and an output terminal outputting the scan signal, and the first output transistor being configured to operate in response to a second signal of the second node; and a second output transistor connected between the output terminal and a second clock terminal receiving the second clock signal, and the second output transistor being configured to operate in response to the first signal of the first node.

[0021] In embodiments of this disclosure, the third voltage is a direct current (DC) voltage used to turn on each of the first output transistor and the second output transistor.

[0022] In embodiments of this disclosure, the switching circuit transmits one of the second voltage and the third voltage to the first node in response to the start signal and the first clock signal, and the switching circuit transmits one of the second voltage and the third voltage to the second node in response to the first clock signal.

[0023] In embodiments of this disclosure, the second voltage is lower than or equal to the first voltage, and the third voltage is lower than the second voltage.

[0024] In embodiments of this disclosure, the switching circuit includes: a first transistor connected between a third voltage terminal receiving the third voltage and the first node, and the first transistor including a gate electrode connected to a carry terminal receiving the carry signal; a second transistor connected between the third node and the first node, and the second transistor including a gate electrode connected to the carry terminal; a third transistor connected between a second voltage terminal receiving the second voltage and the third node, and the third transistor including a gate electrode connected to a first clock terminal receiving the first clock signal; a fourth transistor connected between the third voltage terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock terminal; and a fifth transistor connected between the second voltage terminal and the second node, and the fifth transistor including a gate electrode connected to the first clock terminal.

[0025] In embodiments of this disclosure, the first transistor and the second transistor are transistors of different types from each other, and the fourth transistor and the fifth transistor are transistors of different types from each other. Attached Figure Description

[0026] The above and other features of the present invention will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0027] Figure 1 This is a diagram illustrating an electronic device according to an embodiment of the present invention.

[0028] Figure 2 This is a block diagram of an electronic device according to an embodiment of the present invention.

[0029] Figure 3 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0030] Figure 4 It is used to describe Figure 3 The timing diagram of pixel operations is shown in the figure.

[0031] Figure 5This is a block diagram of a scan drive circuit according to an embodiment of the present invention.

[0032] Figure 6 This is a block diagram of a first scan driving circuit according to an embodiment of the present invention.

[0033] Figure 7 This is a circuit diagram of the driver stage according to an embodiment of the present invention.

[0034] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E It is a circuit diagram used to describe the operation of the driver level.

[0035] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E It is a timing diagram used to describe the operation of the driver level.

[0036] Figure 10 This is a diagram illustrating the result of the operation of the analog drive level according to an embodiment of the present invention.

[0037] Figure 11 This is a circuit diagram of the driver stage according to an embodiment of the present invention. Detailed Implementation

[0038] In this specification, the description of a first component (or area, layer, part, etc.) being "on" a second component, "connected to" a second component, or "coupled to" a second component means that the first component is directly on the second component, connected to or coupled to the second component, or that a third component is located between the first component and the second component.

[0039] Throughout this specification and the accompanying drawings, the same symbols (e.g., reference characters and reference numerals) refer to the same elements. Furthermore, various thicknesses, lengths, and angles are shown, and while the arrangements shown do represent embodiments of the inventive concept, it will be understood that various modifications to the thicknesses, lengths, and angles can be made within the spirit and scope of this disclosure, and that this disclosure is not necessarily limited to the specific thicknesses, lengths, and angles shown. The term "and / or" includes one or more combinations of the associated listed items.

[0040] Although the terms "first," "second," etc., can be used to describe various components, the components should not be construed as being limited by the terms. The terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of the invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. As used herein, singular terms may include plural forms unless the context clearly indicates otherwise.

[0041] Furthermore, terms such as “below,” “under,” “above,” and “above” may be used to describe the relationships between the components shown in the accompanying drawings. These terms serve as spatial relative concepts and are based on the directions indicated in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device in the drawings is flipped, then an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0042] Unless otherwise specified, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formalized sense.

[0043] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0044] Figure 1 This is a diagram illustrating an electronic device DD according to an embodiment of the present invention.

[0045] Reference Figure 1 The illustration shows an example of a portable terminal as an electronic device DD according to an embodiment of the present invention. Portable terminals may include, for example, tablet PCs, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, and watch-type electronic devices. However, the invention is not limited thereto. In addition to large electronic equipment (such as televisions or billboards), the invention can also be used for small and medium-sized electronic devices (such as personal computers, laptops, newsstands, car navigation systems, and cameras). The above examples are provided as embodiments without departing from the concept of the invention, and it is obvious that the electronic device DD can be applied to any other electronic device(s).

[0046] like Figure 1As shown, the display surface on which the image is displayed is parallel to a plane defined by a first direction DR1 and a second direction DR2. For example, the electronic device DD may include multiple regions separated from each other on the display surface. The display surface includes a display area DA in which the image is displayed and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. For example, the display area DA may have a rectangular shape. The non-display area NDA at least partially surrounds the display area DA. Furthermore, for example, the electronic device DD may include a shape that is partially curved.

[0047] Figure 2 This is a block diagram of an electronic device DD according to an embodiment of the present invention.

[0048] Reference Figure 2 The electronic device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, a scan drive circuit 300, a transmit drive circuit 400, and a voltage generator 500.

[0049] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 converts the image signal RGB into an image data signal DS and outputs the image data signal DS. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a transmit control signal ECS.

[0050] The data drive circuit 200 receives the data control signal DCS and the image data signal DS from the drive controller 100. The data drive circuit 200 converts the image data signal DS into a data signal and then outputs the data signal to the multiple data lines DL1 to DLm, which will be described later.

[0051] The scan drive circuit 300 receives the scan control signal SCS from the drive controller 100. In response to receiving the scan control signal SCS, the scan drive circuit 300 can output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1.

[0052] The transmit drive circuit 400 receives the transmit control signal ECS from the drive controller 100. In response to receiving the transmit control signal ECS, the transmit drive circuit 400 can output the transmit signal to the transmit lines EML1 to EMLn.

[0053] Voltage generator 500 generates voltages to operate the display panel DP. In embodiments of the invention, voltage generator 500 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2 for the operation of the display panel DP. In embodiments of the invention, voltage generator 500 may generate a driving voltage VD for the operation of the scan driving circuit 300. In embodiments of the invention, the driving voltage VD may include a first voltage VGH1, a second voltage VGH2, and a third voltage VGL.

[0054] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, emission lines EML1 to EMLn, data lines DL1 to DLm and pixels PX.

[0055] The display panel (DP) includes active areas (AA) and passive areas (NAA). Active areas (AA) can correspond to... Figure 1 The electronic device DD shown in the figure has a display area DA, and the non-active area NAA can correspond to Figure 1 The non-display area NDA of the electronic device DD shown in the figure.

[0056] In an embodiment of the present invention, pixel PX can be placed in the active region AA of the display panel DP. Scan driving circuit 300 and emission driving circuit 400 can be placed in the non-active region NAA of the display panel DP. In an embodiment of the present invention, scan driving circuit 300 is arranged adjacent to a first side of the active region AA. Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 extend from scan driving circuit 300 in a first direction DR1. Emission driving circuit 400 is arranged adjacent to a second side of the active region AA. Emission lines EML1 to EMLn extend from emission driving circuit 400 in a direction opposite to the first direction DR1.

[0057] Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, as well as transmit lines EML1 to EMLn, are arranged spaced apart from each other in the second direction DR2. Data lines DL1 to DLm extend from the data drive circuit 200 in the opposite direction to the second direction DR2 and are arranged spaced apart from each other in the first direction DR1.

[0058] exist Figure 2In the example shown, the scan driving circuit 300 and the emission driving circuit 400 are arranged facing each other, and the pixel PX is located between the scan driving circuit 300 and the emission driving circuit 400, but this disclosure is not limited thereto. For example, the scan driving circuit 300 and the emission driving circuit 400 may be placed adjacent to each other in the non-active area NAA of the display panel DP. In embodiments of the invention, the scan driving circuit 300 and the emission driving circuit 400 may be implemented using a single circuit.

[0059] Multiple pixels (PX) are electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, emission lines EML1 to EMLn, and data lines DL1 to DLm. For example, each of the multiple pixels (PX) can be electrically connected to four scan lines and one emission line. For example, as... Figure 2 As shown, the first row of pixels PX can be connected to scan lines GIL1, GCL1, GWL1, and GWL2, as well as the emission line EML1. Furthermore, the i-th row of pixels PX can be connected to scan lines GILi, GCLi, GWLi, and GWLi+1, as well as the emission line EML1. The n-th row of pixels PX can be connected to scan lines GILn, GCLn, GWLn, and GWLn+1, as well as the emission line EMLn.

[0060] Each of the multiple pixels PX includes a light-emitting element ED (see Figure 3 ) and the pixel circuit PXC used to control the emission of the light-emitting element ED (see Figure 3 The pixel circuit PXC may include one or more transistors and one or more capacitors. The scan drive circuit 300 and the emitter drive circuit 400 may include transistors formed using the same process as the pixel circuit PXC.

[0061] The scan driving circuit 300 according to an embodiment of the present invention is placed in the non-active region NAA of the display panel DP. The scan driving circuit 300 according to an embodiment of the present invention can minimize the circuit area by including a minimum number of transistors. Therefore, the electronic device DD (see...) Figure 1 Minimize the area of ​​the non-display area NDA corresponding to the non-active area NAA of the display panel DP.

[0062] Figure 3 This is a circuit diagram of pixel PX according to an embodiment of the present invention.

[0063] Figure 3 The circuit diagram of pixel PX is shown, and pixel PX is connected to... Figure 2The j-th data line DLj (also called data line DLj) among the data lines DL1 to DLm, the i-th scan line GILi (also called scan line GILi), GCLi (also called scan line GCLi) and GWLi (also called scan line GWLi) among the scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, and the i-th emitter line EMLi (also called emitter line EMLi) among the emitter lines EML1 to EMLn are shown.

[0064] Figure 2 Each of the multiple pixels PX shown can have the same characteristics as... Figure 3 The same circuit configuration is shown for pixel PX.

[0065] Reference Figure 3 According to an embodiment of the present invention, a pixel PX of an electronic device includes a pixel circuit PXC and at least one light-emitting element ED. In an embodiment of the present invention, the light-emitting element ED may be a light-emitting diode. In an embodiment of the present invention, a pixel PX is described as including one light-emitting element ED. The pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a capacitor Cst.

[0066] In embodiments of the present invention, each of the first transistor T1 to the seventh transistor T7 is a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present invention is not limited thereto. For example, each of the first transistor T1 to the seventh transistor T7 may be an N-type transistor using oxide semiconductor as the semiconductor layer.

[0067] In embodiments of the present invention, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the other transistors (a plurality of other transistors) among the first transistor T1 to the seventh transistor T7 may be P-type transistors. Furthermore, the circuit configuration of pixel PX according to embodiments of the present invention is not limited to... Figure 3 The embodiments described herein can be implemented in a modified manner.

[0068] Scan lines GILi, GCLi, GWLi, and GWLi+1 can transmit scan signals GIi, GCI, GWi, and GWi+1, respectively. Transmit line EMLi can transmit transmit signal EMi. Data line DLj transmits data signal Dj. Data signal Dj can have input to electronic device DD (see...). Figure 1 ) image signal RGB (see Figure 2The corresponding voltage levels are: the first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3, and the fourth driving voltage line VL4, which can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2.

[0069] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting element ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Dj transmitted via the data line DLj based on the switching operation of the second transistor T2, and can then supply the drive current Id to the light-emitting element ED.

[0070] The second transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLi. The second transistor T2 can be turned on in response to the scan signal GWi transmitted through the scan line GWLi, and can transmit the data signal Dj transmitted through the data line DLj to the first electrode of the first transistor T1.

[0071] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The third transistor T3 can be turned on in response to the scan signal GCI transmitted through the scan line GCLi, and therefore, the gate electrode and the second electrode of the first transistor T1 can be connected to each other, that is, the first transistor T1 can be connected in a diode manner.

[0072] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3 through which the first initialization voltage VINT1 is transmitted, and a gate electrode connected to the scan line GILi. The fourth transistor T4 can be turned on in response to the scan signal GIi transmitted via the scan line GILi, thereby transmitting the first initialization voltage VINT1 to the gate electrode of the first transistor T1. Therefore, an initialization operation can be performed to initialize the voltage of the gate electrode of the first transistor T1.

[0073] The fifth transistor T5 includes a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emitter line EMLi.

[0074] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the emission line EMLi.

[0075] The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on in response to the transmit signal EMi transmitted through the transmit line EMi. In this way, the first drive voltage ELVDD can be compensated by the diode-connected transistor T1 to supply the light-emitting element ED.

[0076] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4, and a gate electrode connected to the scan line GWLi+1. The seventh transistor T7 is turned on in response to the scan signal GWi+1 transmitted through the scan line GWLi+1, and bypasses the current of the anode of the light-emitting element ED to the fourth driving voltage line VL4.

[0077] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting element ED can be connected to the second driving voltage line VL2, and the second driving voltage ELVSS is transmitted to the second driving voltage line VL2. The pixel circuit PXC according to embodiments of the present invention is not limited to... Figure 3 The pixel circuit PXC is shown in the figure. The number of transistors, the number of capacitors, and their connections in the pixel circuit PXC can be modified in various ways.

[0078] Figure 4 It is used to describe Figure 3 The timing diagram of pixel operations is shown in the figure.

[0079] Reference Figure 3 and Figure 4 A frame Fs can include an initialization period, a data programming and compensation period, and a transmission period.

[0080] When a scan signal GIi with a low level is provided through scan line GILi during the initialization cycle, the fourth transistor T4 is turned on. The first initialization voltage VINT1 is transmitted through the fourth transistor T4 to the gate electrode of the first transistor T1 in order to initialize the first transistor T1.

[0081] Next, when a scan signal GCI with a low level is supplied through scan line GCLi during the data programming and compensation cycle, the third transistor T3 is turned on. The first transistor T1 is connected to the third transistor T3 in a diode manner, and is therefore forward biased. At this time, when a scan signal GWi with a low level is supplied through scan line GWLi, the second transistor T2 is turned on. In this case, a compensation voltage is applied to the gate electrode of the first transistor T1, which is obtained by reducing the voltage of the data signal Dj supplied from data line DLj to the threshold voltage of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage.

[0082] When the first driving voltage ELVDD and the compensation voltage are applied to opposite terminals (e.g., opposite electrodes) of capacitor Cst, the charge corresponding to the difference between the first driving voltage ELVDD and the compensation voltage can be stored in capacitor Cst.

[0083] Simultaneously, when a low-level scan signal GWi+1 is provided to the gate electrode of the seventh transistor T7 through scan line GWLi+1, the seventh transistor T7 is turned on. With the seventh transistor T7 turned on, the anode of the light-emitting element ED is electrically connected to the fourth driving voltage line VL4. Therefore, the anode of the light-emitting element ED can be initialized to the second initialization voltage VINT2.

[0084] Next, during the emission cycle, the emission signal EMi supplied from the emission line EMi changes from a high level to a low level. During the emission cycle, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission signal EMi with a low level. In this case, a drive current Id is generated according to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and the drive current Id is supplied to the light-emitting element ED through the sixth transistor T6, and the drive current Id flows through the light-emitting element ED. The light-emitting element ED can emit light with a brightness corresponding to the drive current Id.

[0085] Figure 5 This is a block diagram of a scan drive circuit 300 according to an embodiment of the present invention.

[0086] Reference Figure 5 The scan drive circuit 300 includes a first scan drive circuit 310, a second scan drive circuit 320, and a third scan drive circuit 330.

[0087] The first scan drive circuit 310 outputs scan signals GW1 to GWn+1 in response to the scan control signal SCS. In embodiments of the present invention, the scan signals GW1 to GWn+1 can be sequentially transitioned to a first level (e.g., a low level).

[0088] The second scan drive circuit 320 outputs scan signals GC1 to GCn in response to the scan control signal SCS. The scan signals GC1 to GCn can be sequentially transitioned to a first level (e.g., a low level).

[0089] The third scan drive circuit 330 outputs scan signals GI1 to GIn in response to the scan control signal SCS. The scan signals GI1 to GIn can be sequentially transitioned to a first level (e.g., a low level).

[0090] Figure 6 This is a block diagram of the first scan driving circuit 310 according to an embodiment of the present invention.

[0091] Reference Figure 6 The first scan drive circuit 310 includes drive stages ST1 to STn+1.

[0092] Each of the drive levels ST1 to STn+1 from Figure 2 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2. Each of the drive stages ST1 to STn+1 receives a drive voltage VD.

[0093] The driving voltage VD includes a first voltage VGH1, a second voltage VGH2, and a third voltage VGL. The first voltage VGH1, the second voltage VGH2, and the third voltage VGL can be drawn from... Figure 2 The voltage generator 500 shown in the figure is provided.

[0094] In an embodiment of the present invention, drive stages ST1 to STn+1 respectively output scan signals GW1 to GWn+1. Scan signals GW1 to GWn+1 can be provided to... Figure 2 The scan lines GWL1 to GWLn+1 are shown in the figure.

[0095] The first driver stage ST1 receives the start signal FLM as a carry signal. Each of the second driver stages ST2 to the (n+1)th driver stage STn+1 has a dependent connection, meaning that a scan signal output from a previous driver stage is received as a carry signal. For example, the scan signal GWi output from the i-th driver stage STi can be provided as the carry signal for the (i+k)-th driver stage STi+k (where "i" and "k" are positive integers). For example, the second driver stage ST2 receives the scan signal GW1 output from the first driver stage ST1 as a carry signal. The third driver stage ST3 receives the scan signal GW2 output from the second driver stage ST2 as a carry signal. Figure 6The diagram shows that the i-th driver stage STi receives the scan signal from the (i-1)-th driver stage STi-1 as a carry signal, but the present invention is not limited thereto.

[0096] Although Figure 6 Only the first scan drive circuit 310 is shown in the image, but... Figure 5 Each of the second scan drive circuit 320 and the third scan drive circuit 330 shown may also include the same components as the first scan drive circuit 310.

[0097] Figure 7 This is a circuit diagram of the driver stage ST1 according to an embodiment of the present invention.

[0098] Reference Figure 7 The driver stage ST1 includes transistors M1 through M7 and capacitor C1. Additionally, the driver stage ST1 includes a first clock terminal CK1, a second clock terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1, a second voltage terminal VIN2, a third voltage terminal VIN3, and an output terminal OUT.

[0099] The driver stage ST1 responds to the first clock signal CLK1 and the second clock signal CLK2 received through the first clock terminal CK1 and the second clock terminal CK2, respectively, and the carry signal (i.e., the start signal FLM) received through the carry input terminal CIN, and outputs the scan signal GW1 to the output terminal OUT.

[0100] Each of the first voltage VGH1, second voltage VGH2, and third voltage VGL transmitted to the first voltage terminal VIN1, the second voltage terminal VIN2, and the third voltage terminal VIN3 can be a direct current (DC) voltage with a predetermined voltage level. In embodiments of the invention, each of the first voltage VGH1 and the second voltage VGH2 can have a voltage level higher than the third voltage VGL. In embodiments of the invention, the second voltage VGH2 can have a voltage level lower than the first voltage VGH1. However, the invention is not limited thereto. In embodiments of the invention, the second voltage VGH2 can be a voltage level lower than or equal to the first voltage VGH1.

[0101] In an embodiment of the present invention, the third voltage VGL may be a DC voltage used to turn on both the sixth transistor M6 and the seventh transistor M7.

[0102] In an embodiment of the present invention, the first clock signal CLK1 and the second clock signal CLK2 may have the same frequency and different phases.

[0103] The switching circuit SWC is connected to the second voltage terminal VIN2, the third voltage terminal VIN3, the first clock terminal CK1, and the carry input terminal CIN. In response to the first clock signal CLK1 received at the first clock terminal CK1, the switching circuit SWC outputs a second signal to the second node QB. In response to the first clock signal CLK1 received at the first clock terminal CK1 and the carry signal FLM received at the carry input terminal CIN, the switching circuit SWC outputs a first signal to the first node Q.

[0104] The switching circuit SWC includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5.

[0105] The first transistor M1 is connected between the third voltage terminal VIN3 and the first node Q, and includes a gate electrode connected to the carry input terminal CIN.

[0106] The second transistor M2 is connected between the third node A and the first node Q, and includes a gate electrode connected to the carry input terminal CIN.

[0107] The third transistor M3 is connected between the second voltage terminal VIN2 and the third node A, and includes a gate electrode connected to the first clock terminal CK1.

[0108] The fourth transistor M4 is connected between the third voltage terminal VIN3 and the second node QB, and includes a gate electrode connected to the first clock terminal CK1.

[0109] The fifth transistor M5 is connected between the second voltage terminal VIN2 and the second node QB, and includes a gate electrode connected to the first clock terminal CK1.

[0110] The sixth transistor M6 is connected between the first voltage terminal VIN1 and the output terminal OUT, and includes a gate electrode connected to the second node QB. The sixth transistor M6 may be referred to as the "first output transistor".

[0111] The seventh transistor M7 is connected between the output terminal OUT and the second clock terminal CK2, and includes a gate electrode connected to the first node Q. The seventh transistor M7 can be referred to as the "second output transistor".

[0112] Capacitor C1 is connected between the first node Q and the output terminal OUT.

[0113] In embodiments of the present invention, each of the first transistor M1, the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 is a P-type transistor having LTPS as its semiconductor layer. Each of the second transistor M2 and the fifth transistor M5 may be an N-type transistor having oxide semiconductor as its semiconductor layer. However, the present invention is not limited thereto.

[0114] The first driver stage ST1 can output a scan signal GW1 through seven transistors (i.e., first transistor M1 to seventh transistor M7) and a capacitor C1. Scan drive circuit 300 (see...) Figure 2 The circuit area can be minimized by minimizing the number of transistors and capacitors included in the first drive stage ST1.

[0115] Although Figure 7 Only the first drive stage ST1 is shown in the image, but Figure 6 Each of the second drive stage ST2, the third drive stage ST3, the fourth drive stage ST4, ... and the (n+1)th drive stage STn+1 shown may include... Figure 7 The circuit configuration of the first drive stage ST1 shown is similar to that of the circuit configuration.

[0116] Figure 6 Each of some of the drive levels ST1 to STn+1 shown (e.g., odd-numbered drive levels ST1, ST3, ... and STn+1) may include […]. Figure 7 The circuit configuration of the first drive stage ST1 shown is the same as that of the circuit configuration.

[0117] Figure 6 Each of the other drive levels in drive levels ST1 to STn+1 shown (e.g., even-numbered drive levels ST2, ST4, ..., STn) may include those with... Figure 7 The diagram shows some different circuit configurations for the first driver stage ST1. For example, the first clock terminal CK1 of each of the even-numbered driver stages ST2, ST4, ... and STn can receive the second clock signal CLK2, and the second clock terminal CK2 of each of the even-numbered driver stages ST2, ST4, ... and STn can receive the first clock signal CLK1.

[0118] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E This is a circuit diagram used to describe the operation of the first drive stage ST1.

[0119] Figure 9A , Figure 9B , Figure 9C, Figure 9D and Figure 9E It is a timing diagram used to describe the operation of the first drive stage ST1.

[0120] Reference Figure 8A and Figure 9A During the first cycle P1, each of the carry signal (i.e., the start signal FLM) and the first clock signal CLK1 is at a low level L, and the second clock signal CLK2 is at a high level H.

[0121] When the start signal FLM is at a low level L, the first transistor M1 is turned on and the second transistor M2 is turned off. With the first transistor M1 turned on, the first node Q is at a low level L corresponding to the third voltage VGL. The seventh transistor M7 can be turned on in response to the first signal S_Q of the first node Q having a first low level LV1.

[0122] When the first clock signal CLK1 is at a low level L, each of the third transistor M3 and the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off.

[0123] Even when the third transistor M3 is turned on to transfer the second voltage VGH2 to the second node QB, the fourth transistor M4 is turned on, and therefore, the second node QB can discharge to the third voltage VGL.

[0124] The sixth transistor M6 can be turned on in response to the second signal of the second node QB.

[0125] The first voltage VGH1 can be output to the output terminal OUT via the sixth transistor M6, which is turned on by the second signal of the second node QB. Furthermore, the second clock signal CLK2, which has a high level, can be output to the output terminal OUT via the seventh transistor M7, which is turned on in response to the first signal S_Q. Therefore, the scan signal GW1 is at a high level H.

[0126] During the first cycle P1, the third voltage VGL, which is a DC voltage, can be transmitted to the first node Q. Therefore, during the first cycle P1, the first signal S_Q of the first node Q can be stably maintained at the first low level LV1. Since the first signal S_Q of the first node Q is maintained at a constant voltage level, the seventh transistor M7 can be stably kept on.

[0127] Furthermore, during the first cycle P1, the second signal of the second node QB can be stably maintained at the first low level LV1. Since the second signal of the second node QB remains at a constant voltage level, the sixth transistor M6 can be stably kept on. Therefore, the scan signal GW1 can be stably maintained at the high level H.

[0128] Reference Figure 8B and Figure 9B During the second cycle P2, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0129] When the start signal FLM is at a high level H, the second transistor M2 is turned on and the first transistor M1 is turned off.

[0130] When the first clock signal CLK1 is at a high level H, the fifth transistor M5 is turned on, and each of the third transistor M3 and the fourth transistor M4 is turned off.

[0131] With the fifth transistor M5 turned on, the second voltage VGH2 is transmitted to the second node QB. The sixth transistor M6 turns off in response to the second signal at the second node QB.

[0132] Because the second transistor M2 is turned on but the third transistor M3 is turned off, the first signal S_Q of the first node Q can be held in the previous state (i.e., the first low level LV1) by capacitor C1.

[0133] Because the seventh transistor M7 is turned on while the first signal S_Q is held at the first low level LV1, the second clock signal CLK2 at the high level H is output to the output terminal OUT through the seventh transistor M7. Therefore, during the second cycle P2, the scan signal GW1 is at the high level H.

[0134] Reference Figure 8C and Figure 9C During the third cycle P3, each of the start signal FLM and the first clock signal CLK1 is at a high level H, and the second clock signal CLK2 is at a low level L.

[0135] When the start signal FLM is at a high level H, the second transistor M2 is turned on and the third transistor M3 is turned off.

[0136] When the first clock signal CLK1 is at a high level H, the fifth transistor M5 is turned on, and each of the third transistor M3 and the fourth transistor M4 is turned off.

[0137] When the seventh transistor M7 is turned on during the second cycle P2, and then the second clock signal CLK2 transitions from high level H to low level L during the third cycle P3, the second clock signal CLK2 at low level L is output to the output terminal OUT through the seventh transistor M7. Therefore, during the third cycle P3, the scan signal GW1 is at low level L.

[0138] As the scan signal GW1 of the output terminal OUT changes from high level H to low level L, the voltage level of the first signal S_Q of the first node Q can be changed from the first capacitor C1 to a second low level LV2, which is lower than the first low level LV1.

[0139] As the voltage level of the first signal S_Q decreases, the seventh transistor M7 can be fully turned on. Therefore, during the third cycle P3, the scan signal GW1 can be held at the low level L of the second clock signal CLK2.

[0140] Reference Figure 8D and Figure 9D During the fourth cycle P4, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0141] When the start signal FLM is at a high level H, the second transistor M2 is turned on and the first transistor M1 is turned off.

[0142] When the first clock signal CLK1 is at a high level H, the fifth transistor M5 is turned on, and each of the third transistor M3 and the fourth transistor M4 is turned off.

[0143] With the fifth transistor M5 turned on, the second voltage VGH2 is transmitted to the second node QB. The sixth transistor M6 turns off in response to the second signal at the second node QB.

[0144] Because the second transistor M2 is turned on, but the third transistor M3 is turned off, the first signal S_Q of the first node Q can be held in the previous state (i.e., the first low level LV1) by capacitor C1.

[0145] When the seventh transistor M7 is turned on during the third cycle P3, and then the second clock signal CLK2 transitions from low level L to high level H during the fourth cycle P4, the second clock signal CLK2 at high level H during the fourth cycle P4 is output to the output terminal OUT through the seventh transistor M7. Therefore, during the fourth cycle P4, the scan signal GW1 is at high level H.

[0146] As the scan signal GW1 of the output terminal OUT changes from low level L to high level H, the voltage level of the first signal S_Q of the first node Q can be changed by capacitor C1 to the first low level LV1, which is higher than the second low level LV2.

[0147] Even if the voltage level of the first signal S_Q becomes the first low level LV1, the seventh transistor M7 is turned on, so the voltage level of the scan signal GW1 during the fourth cycle P4 can be equal to the high level H of the second clock signal CLK2.

[0148] Reference Figure 8E and Figure 9E During the fifth cycle P5, each of the start signal FLM and the second clock signal CLK2 is at a high level H, and the first clock signal CLK1 is at a low level L.

[0149] When the start signal FLM is at a high level H, the second transistor M2 is turned on and the first transistor M1 is turned off.

[0150] When the first clock signal CLK1 is at a low level L, each of the third transistor M3 and the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off.

[0151] Even when the third transistor M3 is turned on to transfer the second voltage VGH2 to the second node QB, the fourth transistor M4 is turned on, and therefore, the second node QB can discharge to the third voltage VGL.

[0152] The sixth transistor M6 can be turned on in response to the second signal of the second node QB.

[0153] The first voltage VGH1 can be output to the output terminal OUT through the conducting sixth transistor M6.

[0154] Furthermore, the second voltage VGH2 at the high level can be transmitted to the first node Q through the third transistor M3 and the second transistor M2, which are turned on during the fifth cycle P5. When the voltage level of the first signal S_Q at the first node Q changes to the high voltage level HV, the seventh transistor M7 is turned off.

[0155] Because the scan signal GW1 at the output terminal OUT is at a high level H during the fourth cycle P4, the scan signal GW1 can be held at a high level H by capacitor C1 during the fifth cycle P5.

[0156] During the fifth cycle P5, the second signal of the second node QB can be stably maintained at the first low level LV1. With the second signal of the second node QB maintained at a constant voltage level, the sixth transistor M6 can be stably kept on. Therefore, the scan signal GW1 can be stably maintained at the high level H.

[0157] Throughout the first cycle P1 to the fifth cycle P5, the second voltage VGH2 can be transmitted to the first node Q and the second node QB, and can be used to turn off the sixth transistor M6 and the seventh transistor M7. Therefore, the second voltage VGH2 can be set to a voltage level sufficient to turn off the sixth transistor M6 and the seventh transistor M7. For example, the second voltage VGH2 can have a voltage level approximately 1 to 2 V lower than the first voltage VGH1. By setting the second voltage VGH2 to a voltage level lower than the first voltage VGH1, the power consumption of the driver stage ST1 can be reduced.

[0158] Figure 10 This is a diagram illustrating the result of the operation of the analog drive level according to an embodiment of the present invention.

[0159] exist Figure 10 In the diagram, the numbers described on the vertical axis represent the voltage levels corresponding to the start signal FLM, the first clock signal CLK1, the second clock signal CLK2, the first signal S_Q of the first node Q, the second signal S_QB of the second node QB, and the third signal S_A of the third node A, respectively. However, the invention is not limited thereto.

[0160] Reference Figure 7 and Figure 10 It can be seen that the drive stage ST1 in each period from the first cycle P1 to the fifth cycle P5 is in accordance with... Figures 8A to 8E and Figures 9A to 9E It operates in the same way as described in [the document / document].

[0161] During each of the first cycle P1, the second cycle P2, the fourth cycle P4, and the fifth cycle P5, the driver stage ST1 outputs the scan signal GW1 at a high level. During the third cycle P3, the driver stage ST1 outputs the scan signal GW1 at a low level.

[0162] When the start signal FLM is held high (i.e., during each of the second, third, fourth, and fifth cycles P2 and P5), the second transistor M2 is turned on. As the on-state of the second transistor M2 is prolonged, the stress on the second transistor M2 can increase based on the voltage difference between its drain and source (i.e., the voltage difference between the third node A and the first node Q). Figure 10 As shown, the third signal S_A of the third node A can have a waveform similar to the first signal S_Q of the first node Q. Therefore, because the voltage difference between the drain and source of the second transistor M2 is small, damage to the second transistor M2 can be prevented.

[0163] Figure 11 This is a circuit diagram of the drive stage ST1a according to an embodiment of the present invention.

[0164] Reference Figure 11 The drive stage ST1a includes a first switching circuit SWC1, a second switching circuit SWC2, a first output transistor M6, a second output transistor M7, and a capacitor C1.

[0165] The first switching circuit SWC1 includes a first transistor M1, a second transistor M2, and a third transistor M3. The second switching circuit SWC2 includes a fourth transistor M4 and a fifth transistor M5.

[0166] The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first output transistor M6, the second output transistor M7, and the capacitor C1 and Figure 7 The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first output transistor M6, the second output transistor M7, and the capacitor C1 shown are the same, and therefore, any additional descriptions that may be redundant are omitted or briefly discussed to avoid redundancy.

[0167] The first switching circuit SWC1 is connected to the second voltage terminal VIN2, the third voltage terminal VIN3, the first clock terminal CK1, and the carry input terminal CIN. In response to the first clock signal CLK1 transmitted to the first clock terminal CK1 and the start signal FLM transmitted to the carry input terminal CIN, the first switching circuit SWC1 outputs a first signal to the first node Q.

[0168] The first switching circuit SWC1, in response to the first clock signal CLK1 and the start signal FLM, transmits either the second voltage VGH2 or the third voltage VGL to the first node Q.

[0169] The second switching circuit SWC2 is connected to the second voltage terminal VIN2, the third voltage terminal VIN3, and the first clock terminal CK1. In response to the first clock signal CLK1 transmitted to the first clock terminal CK1, the second switching circuit SWC2 outputs a second signal to the second node QB.

[0170] The second switching circuit SWC2 responds to the first clock signal CLK1 by transmitting either the second voltage VGH2 or the third voltage VGL to the second node QB.

[0171] Although embodiments of the invention have been described for illustrative purposes, those skilled in the art will understand that various modifications and substitutions can be made to the embodiments of the invention without departing from the scope and spirit of the invention.

[0172] According to embodiments of the present invention, a scan drive circuit comprising a minimum number of transistors and capacitors can be implemented. Therefore, the circuit area of ​​the scan drive circuit can be minimized. As the circuit area of ​​the scan drive circuit is minimized, the bezel area of ​​the electronic device can also be minimized. Furthermore, power consumption can be reduced by lowering the voltage level of the voltage used for the internal operation of the scan drive circuit.

[0173] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A scanning drive circuit, wherein, The scanning drive circuit includes: A switching circuit is configured to transmit a third voltage to a first node in response to a carry signal and a first clock signal, and to transmit the third voltage to a second node in response to the first clock signal; A first output transistor is connected between a first voltage terminal and an output terminal, and the first output transistor is configured to operate in response to a second signal from the second node, wherein the first voltage terminal receives a first voltage; and A second output transistor is connected between the output terminal and the second clock terminal, and the second output transistor is configured to operate in response to a first signal from the first node.

2. The scanning drive circuit according to claim 1, wherein, The third voltage is a DC voltage used to turn on each of the first output transistor and the second output transistor.

3. The scanning drive circuit according to claim 1, wherein, The switching circuit, in response to the carry signal and the first clock signal, transmits one of the second voltage and the third voltage to the first node, and the switching circuit, in response to the first clock signal, transmits one of the second voltage and the third voltage to the second node.

4. The scanning drive circuit according to claim 3, wherein, The second voltage is lower than or equal to the first voltage, and the third voltage is lower than the second voltage.

5. The scanning drive circuit according to claim 3, wherein, The switching circuit includes: A first transistor is connected between a third voltage terminal receiving the third voltage and the first node, and the first transistor includes a gate electrode connected to a carry terminal receiving the carry signal. A second transistor is connected between the third node and the first node, and the second transistor includes a gate electrode connected to the carry terminal; A third transistor is connected between a second voltage terminal receiving the second voltage and the third node, and the third transistor includes a gate electrode connected to a first clock terminal receiving the first clock signal; A fourth transistor is connected between the third voltage terminal and the second node, and the fourth transistor includes a gate electrode connected to the first clock terminal; and A fifth transistor is connected between the second voltage terminal and the second node, and the fifth transistor includes a gate electrode connected to the first clock terminal.

6. The scanning drive circuit according to claim 5, wherein, The first transistor and the second transistor are transistors of different types, and The fourth transistor and the fifth transistor are transistors of different types.

7. The scanning drive circuit according to claim 1, wherein, The scanning drive circuit also includes: A capacitor is connected between the first node and the output terminal.

8. The scanning drive circuit according to claim 1, wherein, The first clock signal and the second clock signal provided to the second clock terminal have the same frequency and different phases.

9. An electronic device, wherein, The electronic device includes: Display panel, including pixels; A scan drive circuit configured to provide a scan signal to the pixel; The drive controller is configured to provide a start signal, a first clock signal, and a second clock signal to the scan drive circuit; and A voltage generator is configured to provide a first voltage, a second voltage, and a third voltage to the scan drive circuit. The scanning drive circuit includes: A switching circuit is configured to transmit the third voltage to a first node in response to the start signal and the first clock signal, and to transmit the third voltage to a second node in response to the first clock signal; A first output transistor is connected between a first voltage terminal receiving the first voltage and an output terminal outputting the scan signal, and the first output transistor is configured to operate in response to a second signal from the second node; and A second output transistor is connected between the output terminal and a second clock terminal that receives the second clock signal, and the second output transistor is configured to operate in response to a first signal from the first node.

10. The electronic device according to claim 9, wherein, The switching circuit, in response to the start signal and the first clock signal, transmits one of the second voltage and the third voltage to the first node, and the switching circuit, in response to the first clock signal, transmits one of the second voltage and the third voltage to the second node.

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