Data storage memory

Abstract

The invention relates to a data storage. The data memory in one aspect comprises: an input trigger circuit for receiving external write-in data; and the FIFO circuit is used for receiving the write-in data transmitted by the input trigger circuit, and data write-in delay can be reduced on the basis of realizing a first-in first-out structure.

Description

Technical Field

[0001] This application relates to the field of digital circuit technology, and in particular to a data storage device. Background Technology

[0002] In digital integrated circuits, First-In-First-Out (FIFO) memory is generally used as a buffer for data exchange in sequential logic circuits. However, digital integrated circuits contain various delays such as gate delay and line delay. For memory, the processes of writing and reading data themselves have delays, and the logic processing before and after data is written also has delays. In sequential logic circuit design, the smaller the delay between two stages of devices, the higher the operating frequency of the circuit can be.

[0003] Therefore, there is an urgent need for a data storage device that can reduce its own latency. Summary of the Invention

[0004] Therefore, it is necessary to provide a data storage device that can reduce its latency in order to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a data storage device, comprising:

[0006] Input trigger circuit, used to receive externally written data;

[0007] A FIFO circuit is used to receive write data transmitted by an input trigger circuit.

[0008] In related technologies, FIFO circuits typically consist of a dual-port RAM, a write controller, and a read controller. Writing data to the FIFO circuit involves address decoding, row and column selection, control signal processing, and charging and discharging of the drive capacitor, resulting in significant write latency. However, the data memory provided in this application incorporates an input trigger circuit before the internal write terminal of the FIFO circuit. When writing data to the data memory, the input trigger circuit first receives the write data and then transmits it to the FIFO circuit. This eliminates the need for the write data to be directly input to the FIFO circuit's data input terminal. Furthermore, the data write operation of the input trigger circuit primarily involves gate delay, which is smaller than the input delay of the FIFO circuit. Therefore, using the data memory provided in the first aspect can reduce data write latency while achieving a first-in-first-out (FIFO) structure.

[0009] In one embodiment, the input trigger circuit is also used to pass the written data to the external read terminal of the data storage device;

[0010] The data storage device also includes:

[0011] The first control circuit is configured to control the input of the internal write enable terminal of the FIFO circuit to be false when the output of the internal empty signal terminal of the FIFO circuit is true and the input of the external read enable terminal of the data storage is true, and to control the output of the external empty signal terminal of the data storage to be true when the output of the internal empty signal terminal is true and the input trigger circuit is empty.

[0012] In one embodiment, the output of the input trigger circuit is connected to the input of the input trigger circuit;

[0013] The data storage device also includes a first control circuit;

[0014] The first control circuit is used to control the external full signal output of the data storage to be true when the internal full signal output of the FIFO circuit is true and the input trigger circuit is not empty.

[0015] In one embodiment, the data memory further includes a first control circuit, which includes: an OR gate element OR1, a record trigger D1, an AND gate element AND1, an AND gate element AND2, an AND gate element AND3, an AND gate element AND4, an AND gate element AND5, a NOT gate element NOT1, a NOT gate element NOT2, a NOT gate element NOT3, a NOT gate element NOT4, a selector MUX1, and a selector MUX2; wherein,

[0016] The first input of OR gate element OR1 is connected to the external write enable terminal of the data storage, the second input of OR gate element OR1 is connected to the output of AND gate element AND3, and the output of OR gate element OR1 is connected to the input of record trigger D1.

[0017] The output of the record flip-flop D1 is connected to the first input of AND gate element AND1, the input of NOT gate element NOT2, and the first input of AND gate element AND2.

[0018] The second input terminal of AND gate element AND1 is connected to the output terminal of selector MUX1, and the output terminal of AND gate element AND1 is connected to the internal write enable terminal of FIFO circuit;

[0019] The output of NOT gate element NOT2 is connected to the first input of AND gate element AND5;

[0020] The second input terminal of AND gate element AND2 is connected to the internal full signal terminal of the FIFO circuit, and the output terminal of AND gate element AND2 is connected to the external full signal terminal of the data storage and the first input terminal of AND gate element AND3.

[0021] The second input terminal of the AND gate element AND3 is connected to the output terminal of the NOT gate element NOT3;

[0022] The input of NOT3 is connected to the external read enable terminal of the data storage device;

[0023] The second input terminal of AND gate element AND5 is connected to the internal empty signal terminal of the FIFO circuit, and the output terminal of AND gate element AND5 is connected to the external empty signal terminal of the data storage device.

[0024] The input of NOT gate element NOT1 is connected to the internal full signal terminal of the FIFO circuit, and the output of NOT gate element NOT1 is connected to the first input of selector MUX1;

[0025] The control terminal of selector MUX1 is connected to the internal empty signal terminal, and the second input terminal of selector MUX1 is connected to the output terminal of NOT gate element NOT3. When the output of the internal empty signal terminal is false, selector MUX1 outputs the signal output by NOT gate element NOT1. When the output of the internal empty signal terminal is true, selector MUX1 outputs the signal output by NOT gate element NOT3.

[0026] The input of NOT gate 4 is connected to the internal empty signal terminal, and the output of NOT gate 4 is connected to the first input of AND gate 4.

[0027] The second input terminal of the AND gate element AND4 is connected to the external read enable terminal of the data storage device, and the output terminal of the AND gate element AND4 is connected to the internal read enable terminal;

[0028] The second input terminal of AND gate element AND5 is connected to the internal empty signal terminal, and the output terminal of AND gate element AND5 is connected to the external empty signal terminal of the data storage device.

[0029] The control terminal of selector MUX2 is connected to the internal empty signal terminal. The first input terminal of selector MUX2 is connected to the internal read terminal of the FIFO circuit. The second input terminal of MUX2 is connected to the output terminal of the input trigger circuit. The output terminal of selector MUX2 is connected to the external read terminal of the data storage. When the output of the internal empty signal terminal is false, selector MUX2 outputs the data output from the internal read terminal. When the output of the internal empty signal terminal is true, selector MUX2 outputs the data output from the input trigger circuit.

[0030] In one embodiment, the input triggering circuit includes an enable trigger D2, the control terminal of which is connected to an external write enable terminal; the first input terminal of the enable trigger D2 serves as the external write terminal of the data storage, the second input terminal of the enable trigger D2 is connected to the output terminal of the enable trigger D2, and the output terminal of the enable trigger D2 is connected to the internal write terminal of the FIFO circuit and the second input terminal of the selector MUX2; when the input of the external write enable terminal is true, the enable trigger D2 receives the data input from the external write terminal, and when the input of the external write enable terminal is false, the enable trigger D2 receives the data output by the enable trigger D2.

[0031] Secondly, this application also provides a data storage device, comprising:

[0032] The FIFO circuit is used to output data to the output trigger circuit under the control of the second control circuit.

[0033] The output trigger circuit has its first input terminal connected to the internal read terminal of the FIFO circuit, and its second input terminal connected to the output terminal of the output trigger circuit. The output terminal of the output trigger circuit serves as the external output terminal of the data storage device.

[0034] The second control circuit is used for:

[0035] When the input of the external read enable terminal of the data storage is true, the control output trigger circuit outputs data to the outside of the data storage.

[0036] If the internal empty signal terminal of the FIFO circuit outputs false, and the external read enable terminal input is true or the output trigger circuit is empty, then the FIFO circuit is controlled to output data to the output trigger circuit.

[0037] When the input to the external read enable terminal is false and the output trigger circuit is not empty, the FIFO circuit is controlled not to output data and the output trigger circuit is controlled to receive the data output by the output trigger circuit.

[0038] In this way, by connecting the external read terminal and the internal read terminal of the FIFO circuit through the output flip-flop, and using the input flip-flop to temporarily store the read data, the delay of reading data from the corresponding address in the FIFO circuit is reduced to the gate delay of the output flip-flop, thus reducing the data read latency. Simultaneously, the second control circuit controls the output flip-flop to receive its own output data when the output flip-flop is not empty and no external data is needed, achieving a self-holding function. When the external read enable input is true, the control circuit outputs data to the outside of the data storage, ensuring that the entire data read logic of the data storage is consistent with the FIFO circuit. Using the data storage provided in the second aspect can reduce data read latency while implementing a first-in-first-out (FIFO) structure.

[0039] In one embodiment, the first input terminal of the output trigger circuit is connected to the external write terminal of the data storage device via a second control circuit; the second control circuit is further configured to:

[0040] When the internal empty signal terminal of the FIFO circuit outputs true, the first input terminal of the control output trigger circuit receives the data input from the external write terminal of the data storage and controls the input of the internal write enable terminal to be false.

[0041] When the internal empty signal terminal of the FIFO circuit outputs false, the first input terminal of the control output trigger circuit receives the data output from the internal read terminal.

[0042] When the internal empty signal terminal outputs true and the output trigger circuit is empty, the external empty signal terminal of the control data storage device outputs true.

[0043] When the external write enable input of the data storage is true, if the internal empty signal is false, or if the output trigger circuit is not empty and the external read enable input is false, the internal write enable input of the FIFO circuit is set to true.

[0044] In one embodiment, the second control circuit is further configured to control the external full signal terminal of the data storage to output true when the internal full signal terminal of the FIFO circuit outputs true and the output trigger circuit is not empty.

[0045] In one embodiment, the second control circuit includes: AND gates AND6, AND7, AND8, AND9, and AND10; OR gates OR2 and OR3; NOT gates NOT5, NOT6, NOT7, and NOT8; a selector MUX3; and a record trigger D3, wherein:

[0046] The first input of AND gate element AND6 is connected to the external write enable terminal of the data storage device, the second input of AND gate element AND6 is connected to the output terminal of OR gate element OR2, and the output terminal of AND gate element AND6 is connected to the internal write enable terminal of the FIFO circuit.

[0047] The first input of OR2 is connected to the output of NOT5, the second input of OR2 is connected to the output of AND9, and the output of OR2 is also connected to the first input of OR3.

[0048] The second input of OR gate element OR3 is connected to the external write enable terminal, and the output of OR gate element OR3 is connected to the input of record trigger D3;

[0049] The input of NOT gate element NOT5 is connected to the internal empty signal terminal of the FIFO circuit, and the output of NOT gate element NOT5 is also connected to the first input of AND gate element AND8.

[0050] The output of the record flip-flop D3 is connected to the input of NOT7, the first input of AND9, and the first input of AND7.

[0051] The second input terminal of AND gate element AND9 is connected to the output terminal of NOT gate element NOT8. The output terminal of AND gate element AND9 is also connected to the input terminal of NOT gate element NOT6 and the control terminal of the output trigger circuit.

[0052] The input of the NOT gate element NOT8 is connected to the external read enable terminal of the data storage;

[0053] The second input of AND gate element AND7 is connected to the internal full-signal terminal of the FIFO circuit;

[0054] The output of NOT gate element NOT6 is connected to the second input of AND gate element AND8;

[0055] The output of AND gate element AND8 is connected to the internal read enable terminal of the FIFO circuit;

[0056] The output of NOT gate element NOT7 is connected to the first input of AND gate element AND10;

[0057] The second input terminal of AND gate element AND10 is connected to the internal empty signal terminal, and the output terminal of AND gate element AND10 is connected to the external empty signal terminal of the FIFO circuit.

[0058] The output of selector MUX3 is connected to the first input of the output trigger circuit. The first input of selector MUX3 is connected to the internal read terminal. The second input of selector MUX3 is connected to the external write terminal of the data storage. The control terminal of selector MUX3 is connected to the internal empty signal terminal. When the output of the internal empty signal terminal is true, selector MUX3 outputs the data written by the external write input terminal. When the output of the internal empty signal terminal is false, selector MUX3 outputs the data output by the internal read terminal.

[0059] In one embodiment, the output trigger circuit includes an enable trigger D4, the control terminal of which is connected to the output terminal of the AND gate element AND9, the first input terminal of which is connected to the output terminal of the selector MUX3, and the second input terminal of which is connected to the output terminal of which.

[0060] When the output of AND gate element AND9 is true, enable flip-flop D4 receives the data output by enable flip-flop D4; when the output of AND gate element AND9 is false, enable flip-flop D4 receives the data output by selector MUX3. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This provides an example of an application scenario for FIFO circuits as data storage in related technologies.

[0063] Figure 2 This is a block diagram of a data storage device with reduced write latency in one embodiment;

[0064] Figure 3 This is a schematic block diagram of the FIFO circuit in one embodiment;

[0065] Figure 4 Here is a block diagram of a data storage device with reduced write latency in another embodiment;

[0066] Figure 5 Here is a block diagram of a data storage device with reduced write latency in yet another embodiment;

[0067] Figure 6 This is a schematic diagram of the circuit structure of a data memory that reduces write latency in one embodiment;

[0068] Figure 7 To adopt Figure 2 The following are examples of application scenarios for data storage devices;

[0069] Figure 8 This is a block diagram of a data memory structure for reducing read latency in one embodiment;

[0070] Figure 9 Here is a block diagram of a data memory with reduced read latency in another embodiment;

[0071] Figure 10 This is a schematic diagram of the circuit structure of a data memory that reduces read latency in one embodiment;

[0072] Figure 11 To adopt Figure 8 The image shows an example of an application scenario for a data storage device.

[0073] Figure label:

[0074] 100 Input trigger circuit; 200 FIFO circuit; 210 Dual-port random access memory; 220 Write controller; 230 Read controller; 300 First control circuit; 400 Output trigger circuit; 500 Second control circuit. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0076] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0077] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0078] Please refer to Figure 1 This provides an example of an application scenario where a FIFO circuit is used as a data storage device in related technologies. For example... Figure 1As shown, the FIFO circuit is positioned between two combinational logic circuits in a sequential logic circuit, serving as a buffer for exchanging data. The FIFO circuit itself has delays during the writing and reading processes, and there are also delays before data is written to and after it is read from the FIFO circuit.

[0079] like Figure 1 As shown, the write latency of a FIFO circuit includes the combinational logic delay 0 and the FIFO write latency itself, while the read latency of a FIFO circuit includes the FIFO read latency itself and the combinational logic delay 1. If the write latency and read latency of a FIFO circuit are unbalanced, for example, if the combinational logic delay 0 is large while the combinational logic delay 1 is small, the combinational logic delay 0 plus the FIFO write latency itself will limit the circuit's operating frequency; conversely, if the combinational logic delay 1 is large while the combinational logic delay 0 is small, the combinational logic delay 1 plus the FIFO read latency itself will limit the circuit's operating frequency.

[0080] This application has been approved. Figure 2 , Figures 4 to 6 The illustrated embodiment provides a data storage device with extremely low write latency and capable of first-in-first-out functionality, through... Figures 8 to 10 The illustrated embodiment provides a data memory with extremely low read latency and first-in-first-out functionality, offering convenience and flexibility for sequential logic circuit design. It allows for targeted optimization of write or read latency, enabling the circuit to achieve higher operating frequencies. It should be noted that... Figures 2 to 6 , Figures 8 to 10 In the diagram, blue lines represent data flow, and black lines represent control signal flow.

[0081] In one exemplary embodiment, please refer to Figure 2 A data storage device is provided, including an input trigger circuit 100 and a FIFO circuit 200.

[0082] The input trigger circuit 100 is used to receive externally written data; the FIFO circuit 200 is used to receive the written data transmitted by the input trigger circuit 100.

[0083] like Figure 2 As shown, the input terminal of the input trigger circuit 100 serves as the external write terminal din2 of the data storage, and the output terminal of the input trigger circuit 100 is connected to the internal write terminal din1 of the FIFO circuit 200.

[0084] Among them, the internal write terminal din1 is the data write terminal of the FIFO circuit 200 inside the data memory, and the external write terminal din2 is the data write terminal of the entire data memory.

[0085] In this embodiment, an input trigger connects the external write terminal din2 and the internal write terminal din1 of the FIFO circuit 200. The input trigger circuit 100 receives external write data, while the FIFO circuit 200 receives the write data transmitted by the input trigger circuit 100 but does not directly receive data. Thus, the data write delay of the data memory is equal to the write delay of the input trigger circuit 100. The write process of the FIFO circuit 200 includes address decoding, row and column selection, control signal processing, and charging and discharging of the drive capacitor, resulting in a relatively large write delay. In contrast, the write delay of the input trigger circuit 100 is mainly due to gate delay, which is much smaller than that of the FIFO circuit 200. Therefore, the data memory provided in this application can reduce the data write delay while implementing a first-in-first-out structure.

[0086] In one possible implementation, please refer to Figure 3 The FIFO circuit 200 includes a dual-port random-access memory 210 (RAM), a write controller 220, and a read controller 230.

[0087] For example, the dual-port random access memory 210 can be implemented based on static random access memory (SRAM), a latch, or a flip-flop. When write enable is active, data input from the data write terminal (i.e., the internal write terminal din1w_en1din1) is written to the storage location indicated by the write address in the dual-port random access memory 210; when read enable is active, data is read from the storage location indicated by the read address and output, where the FIFO depth = the capacity of the dual-port random access memory / the data bit width.

[0088] The write controller 220 records the write address to be written next. The write address is initialized to 0. Each time the write enable is active, the write address is incremented by 1 (if the write address is the FIFO depth minus 1, the write address returns to 0). The write controller 220 also uses the write address and read address to determine whether the FIFO circuit 200 is full (i.e., all addresses in the dual-port random access memory have valid data).

[0089] The read controller 230 records the read address to be read next. The read address is initialized to 0, and increments by 1 each time the read enable is enabled (if the read address is the FIFO depth minus 1, the read address returns to 0). The read controller also needs to determine whether the FIFO circuit 200 is empty (i.e., all addresses of the dual-port RAM have no valid data) based on the write address and read address.

[0090] The specific implementation of the FIFO circuit 200 in the data storage provided in this application embodiment is not limited to... Figure 3 The structure shown. Figure 3 This is just one of many implementation methods, and this application does not limit the specific implementation method of the FIFO circuit 200.

[0091] In one exemplary embodiment, please continue to refer to Figure 2 The internal write enable terminal w_en1 of the FIFO circuit 200 is connected to the external write enable terminal w_en2 of the data storage device. The internal full signal terminal f1 of the FIFO circuit 200 is connected to the external full signal terminal f2 of the data storage device. The internal read terminal dout1 of the FIFO circuit 200 is connected to the external read terminal dout2 of the data storage device. The internal read enable terminal r_en1 of the FIFO circuit 200 is connected to the external read enable terminal r_en2 of the data storage device. The internal empty signal terminal e1 of the FIFO circuit 200 is connected to the external empty signal terminal e2 of the data storage device.

[0092] In this embodiment, when the write enable of the data storage is valid, the write enable of the FIFO circuit 200 is also valid, and it can receive data input from the input trigger. When reading data from the data storage, i.e., when the read enable of the data storage is valid, the read enable of the FIFO circuit 200 is also valid, and it can output data. When the FIFO circuit 200 is full, the full signal of the FIFO circuit 200 is valid, and the data storage also outputs a full signal. When the empty signal of the FIFO circuit 200 is valid, the data storage also outputs an empty signal.

[0093] In one exemplary embodiment, please refer to Figure 4 In the provided data memory, the input trigger circuit 100 is also used to transfer the written data to the external read terminal of the data memory. The data memory also includes a first control circuit 300.

[0094] like Figure 4 As shown, the internal write enable terminal w_en1, internal full signal terminal f1, internal read enable terminal r_en1, and internal empty signal terminal e1 of the FIFO circuit 200 are connected to the external write enable terminal w_en2, external full signal terminal f2, external read enable terminal r_en2, and external empty signal terminal e2 of the data storage device through the first control circuit 300.

[0095] The first control circuit 300 is used to control the internal write enable input of the FIFO circuit 200 to be false when the internal empty signal terminal e1 of the FIFO circuit 200 is true and the external read enable terminal r_en2 of the data storage is true. Specifically, the output of the internal empty signal terminal e1 being true and the external read enable terminal r_en2 being true indicates that data needs to be read externally, but the FIFO circuit 200 is empty. In this case, controlling the input of the internal write enable terminal r_en1 of the FIFO circuit 200 to be false means that if data is written to the data storage, the FIFO circuit 200 will not receive the data transmitted by the input trigger circuit 100, but will directly transmit the data to the external read terminal for external reading.

[0096] In this embodiment, a true input or output is represented by an input or output bit "1", or a high level input / output; a false input or output is represented by an input or output bit "0", or a low level input / output.

[0097] Using the data storage provided in this embodiment, when the FIFO circuit 200 is empty and data needs to be read from the outside, the FIFO circuit 200 is controlled not to write the currently input data, but to directly output the data. This eliminates the need to write to the FIFO circuit 200 and then read from it, thereby improving the data reading speed and reducing the data storage latency in this scenario.

[0098] In this embodiment, the first control circuit 300 is used to control the external empty signal terminal e2 of the data storage device to output true when the internal empty signal terminal e1 outputs true and the input trigger circuit 100 is empty. Here, a true output from the internal empty terminal indicates that the FIFO circuit 200 is empty. In this embodiment, when both the FIFO circuit 200 and the input trigger circuit 100 are empty, the data storage device is considered empty, and the external empty signal terminal e2 outputs true. In this embodiment, the depth of the data storage device is the depth of the FIFO circuit 200 plus 1.

[0099] In one exemplary embodiment, please refer to Figure 5 In this embodiment, the output terminal of the input trigger circuit 100 is connected to the output terminal of the input trigger circuit 100. In this embodiment, the data storage includes a first control circuit 300. For example... Figure 5 As shown, the internal write enable terminal w_en1, internal full signal terminal f1, internal read enable terminal r_en1, and internal empty signal terminal e1 of the FIFO circuit 200 are connected to the external write enable terminal w_en2, external full signal terminal f2, external read enable terminal r_en2, and external empty signal terminal e2 of the data storage device through the first control circuit 300.

[0100] In this embodiment, the first control circuit 300 is used to control the external full signal terminal f2 of the data storage to output true when the internal full signal terminal f1 of the FIFO circuit 200 outputs true and the input trigger circuit 100 is not empty.

[0101] For example, the first control circuit 300 determines whether the input trigger circuit 100 is empty when the input of the internal full signal terminal f1 is true by recording the write enable signal input to the external write enable terminal w_en2, the full signal output to the internal full signal terminal f1, and the read enable signal to the external read enable terminal r_en2. For example, in the previous clock cycle, the output of the internal full signal terminal f1 was true, the input of the external read enable terminal was false, and the input of the external write enable terminal w_en2 was true. The input trigger circuit 100 received externally written data. In the current clock cycle, the input of the external read enable terminal r_en2 is still false. At this time, there is data in the input trigger circuit 100 that needs to be output, but the FIFO circuit 200 is full. Therefore, the input trigger circuit 100 writes the written data back to the input trigger circuit 100, that is, the input trigger circuit 100 is not empty. The output of the external full signal terminal f2 is true, which tells the external logic circuit that the data memory is full.

[0102] In one exemplary embodiment, please refer to Figure 6 The data storage device also includes a first control circuit 300, which includes: an OR gate element OR1, a record trigger D1, an AND gate element AND1, an AND gate element AND2, an AND gate element AND3, an AND gate element AND4, an AND gate element AND5, a NOT gate element NOT1, a NOT gate element NOT2, a NOT gate element NOT3, a NOT gate element NOT4, a selector MUX1, and a selector MUX2.

[0103] The first input of OR1 is connected to the external write enable terminal w_en2 of the data storage, the second input of OR1 is connected to the output of AND3, and the output of OR1 is connected to the input of record trigger D1.

[0104] The output of the record flip-flop D1 is connected to the first input of AND gate AND1, the input of NOT gate NOT2, and the first input of AND gate AND2.

[0105] The second input of AND gate element AND1 is connected to the output of selector MUX1, and the output of AND gate element AND1 is connected to the internal write enable terminal w_en1 of FIFO circuit 200.

[0106] The output of NOT gate element NOT2 is connected to the first input of AND gate element AND5.

[0107] The second input terminal of AND gate element AND2 is connected to the internal full signal terminal f1 of FIFO circuit 200, and the output terminal of AND gate element AND2 is connected to the external full signal terminal f2 of data storage and the first input terminal of AND gate element AND3.

[0108] The second input of the AND gate element AND3 is connected to the output of the NOT gate element NOT3.

[0109] The input of NOT3 is connected to the external read enable terminal r_en2 of the data storage.

[0110] The second input terminal of AND gate element AND5 is connected to the internal empty signal terminal e1 of FIFO circuit 200, and the output terminal of AND gate element AND5 is connected to the external empty signal terminal e2 of data storage.

[0111] The input of NOT gate element NOT1 is connected to the internal full signal terminal f1 of FIFO circuit 200, and the output of NOT gate element NOT1 is connected to the first input terminal of selector MUX1.

[0112] The control terminal of selector MUX1 is connected to the internal empty signal terminal e1, and the second input terminal of selector MUX1 is connected to the output terminal of NOT gate element NOT3. When the output of the internal empty signal terminal e1 is false, selector MUX1 outputs the signal output by NOT gate element NOT1. When the output of the internal empty signal terminal e1 is true, selector MUX1 outputs the signal output by NOT gate element NOT3.

[0113] The input of NOT gate 4 is connected to the internal empty signal terminal e1, and the output of NOT gate 4 is connected to the first input of AND gate 4.

[0114] The second input of AND gate element AND4 is connected to the external read enable terminal r_en2 of the data storage, and the output of AND gate element AND4 is connected to the internal read enable terminal r_en1.

[0115] The second input terminal of AND gate element AND5 is connected to the internal empty signal terminal e1, and the output terminal of AND gate element AND5 is connected to the external empty signal terminal e2 of the data storage.

[0116] The control terminal of selector MUX2 is connected to the internal empty signal terminal e1. The first input terminal of selector MUX2 is connected to the internal read terminal dout1 of FIFO circuit 200. The second input terminal of MUX2 is connected to the output terminal of input trigger circuit 100. The output terminal of selector MUX2 is connected to the external read terminal of data storage. When the output of internal empty signal terminal e1 is false, selector MUX2 outputs the data output by internal read terminal dout1. When the output of internal empty signal terminal e1 is true, selector MUX2 outputs the data output by input trigger circuit 100.

[0117] In this embodiment, a 1-bit recording flip-flop D1 is used to record whether the data in the input trigger circuit 100 is valid. This 1-bit recording flip-flop D1 can be called the input valid bit. If the write enable of the data storage is valid in the current clock cycle (i.e., the external write enable terminal w_en2 is true), then the input valid bit will be 1 in the next clock cycle. If the input valid bit in the recording flip-flop D1 is 1 in the current clock cycle, the FIFO circuit 200 is full, and the read enable of the data storage is invalid, then the input valid bit will also be 1 in the next clock cycle; otherwise, the input valid bit will be 0 in the next clock cycle. It can be seen that: if external data is written in the current clock cycle, the input trigger circuit 100 will not be empty in the next clock cycle; if the input trigger circuit 100 is not empty, the FIFO circuit 200 is full, and no external data is read out in the current clock cycle, then the input trigger circuit 100 will return from its output to its input in the next clock cycle, the input trigger circuit 100 will not be empty, and the data storage will output a full signal. In all but these two cases, the input trigger circuit 100 for the next clock cycle is empty.

[0118] The following scenarios indicate that the input trigger circuit 100 will be empty in the next clock cycle: If the input trigger circuit 100 is empty in the current clock cycle and no data is written externally, then the input trigger circuit 100 will remain empty in the next clock cycle. If the input trigger circuit 100 is not empty and the FIFO circuit 200 is not full and is not empty, then in the next clock cycle, the data in the input trigger circuit 100 will be transferred to the FIFO circuit 200 for storage, and the input trigger circuit 100 will be empty. If the input trigger circuit 100 is not empty, the FIFO circuit 200 is empty, and the external read enable is true in the current clock cycle, then in the next clock cycle, the data in the input trigger circuit 100 will be directly transferred to the external read terminal. If the input trigger circuit 100 is not empty, the FIFO circuit 200 is empty, and the external read enable is false in the current clock cycle, then in the next clock cycle, the data in the input trigger circuit 100 will be transferred to the FIFO circuit 200 for storage, and the input trigger circuit 100 will be empty.

[0119] In this embodiment, when the valid bit of the input in the current clock cycle is 0, the write enable of the FIFO circuit 200 in the next clock cycle is invalid, that is, the internal write enable terminal w_en1 is false. In other words, when the input trigger circuit 100 is empty, the FIFO circuit 200 has no data to write, and controls the internal write enable terminal w_en1 to be false.

[0120] When the valid input bit is 1, if the internal empty signal terminal e1 outputs true, then the input signal of the internal write enable terminal w_en1 of the FIFO circuit 200 is equal to the inverted external read enable signal of the data storage. That is, in the current clock cycle, if the FIFO circuit 200 is empty and the input trigger circuit 100 is not empty, and if the external read enable terminal r_en2 input is true, then the internal write enable terminal w_en1 input in the next clock cycle is controlled to be false through the NOT gate element NOT3, the selector MUX1, the AND gate element AND1, and the selector MUX2, and the data in the input trigger is directly output to the external read terminal.

[0121] In this embodiment, when the external read enable terminal r_en2 is true and the internal empty signal terminal e1 is false, the internal read enable terminal r_en1 outputs true, and data is read from the FIFO circuit 200.

[0122] In this embodiment, the output signal of the external full signal terminal f2 is equal to the AND operation of the output signal of the internal full signal terminal f1 and the output signal of the recording trigger D1; that is, when the input trigger circuit 100 is not empty and the FIFO circuit 200 is full, the data memory outputs a full signal.

[0123] In this embodiment, the output signal of the external empty signal terminal e2 is equal to the AND operation of the inverted output signal of the internal empty signal terminal e1 and the output signal of the recording trigger D1; that is, when the FIFO circuit 200 is empty and the input trigger circuit 100 is empty, the data memory output empty signal is valid.

[0124] In one possible implementation, please continue to refer to Figure 6 The input trigger circuit 100 includes an enable trigger D2. The control terminal of the enable trigger D2 is connected to the external write enable terminal w_en2; the first input terminal of the enable trigger D2 serves as the external write terminal din2 of the data storage device; the second input terminal of the enable trigger D2 is connected to the output terminal of the enable trigger D2; the output terminal of the enable trigger D2 is connected to the internal write terminal din1w_en1 of the FIFO circuit 200 and the second input terminal of the selector MUX2; when the input of the external write enable terminal w_en2 is true, the enable trigger D2 receives the data input from the external write terminal din2; when the input of the external write enable terminal w_en2 is false, the enable trigger D2 receives the data output from the enable trigger D2.

[0125] In one possible implementation, the input trigger circuit 100 includes a write selector and a write trigger. The control terminal of the write selector is connected to an external write enable terminal w_en2. The first input terminal of the write selector serves as the external write terminal din2 of the data storage device. The second input terminal of the write selector serves as the output terminal connected to the write trigger. The output terminal of the write trigger is connected to the input terminal of the write trigger. The output terminal of the write trigger is connected to the internal write terminal din1w_en1 of the FIFO circuit 200 and the second input terminal of the write selector. In this embodiment, the write selector and the write trigger are used to implement the function of the input trigger circuit 100. The write latency of the data storage device in this embodiment includes the write selector latency plus the write trigger write latency.

[0126] The data storage device provided in this embodiment achieves the same first-in-first-out storage function as the FIFO circuit 200 in related technologies, while reducing the write latency of the data storage device.

[0127] Please refer to Figure 7 , for adoption Figure 2 , Figures 4 to 6 The illustrated embodiment provides an example of a data storage scenario where a large delay margin is provided for the preceding stage circuit by reducing write latency.

[0128] In one exemplary embodiment, please refer to Figure 8 A data storage device is provided, including a FIFO circuit 200, an output trigger circuit 400, and a second control circuit 500.

[0129] The FIFO circuit 200 is used to output data to the output trigger circuit 400 under the control of the second control circuit 500.

[0130] The output trigger circuit 400 has its first input terminal connected to the internal read terminal dout1 of the FIFO circuit 200, and its second input terminal connected to the output terminal of the output trigger circuit 400. The output terminal of the output trigger circuit 400 serves as the external output terminal of the data storage device.

[0131] like Figure 8 As shown, the internal write enable terminal w_en1, internal full signal terminal f1, internal read enable terminal r_en1, and internal empty signal terminal e1 of the FIFO circuit 200 are connected to the external write enable terminal w_en2, external full signal terminal f2, external read enable terminal r_en2, and external empty signal terminal e2 of the data storage device through the second control circuit 500.

[0132] The second control circuit 500 is used to: control the output trigger circuit 400 to output data to the outside of the data storage device when the input of the external read enable terminal r_en2 of the data storage device is true; control the FIFO circuit 200 to output data to the output trigger circuit 400 when the input of the external read enable terminal r_en2 is true or the output trigger circuit 400 is empty; and control the FIFO circuit 200 not to output data and control the output trigger circuit 400 to receive the data output by the output trigger circuit 400 when the input of the external read enable terminal r_en2 is false and the output trigger circuit 400 is not empty.

[0133] Specifically, when the input of the external read enable terminal r_en2 of the data storage is true, the data in the output trigger circuit 400 is output. At the same time, the FIFO circuit 200 is controlled to output data to the output trigger circuit 400, that is, the input of the internal read enable terminal r_en1 is controlled to be true, so that the data stored in the data storage of the output trigger circuit 400 is the first data to enter.

[0134] In this scenario, if the internal empty signal terminal e1 of the FIFO circuit 200 is false, and the external read enable terminal r_en2 is true, it indicates that the data from the output trigger circuit 400 is about to be output to the data memory. Therefore, it is necessary to control the FIFO circuit 200 to output data to the output trigger circuit 400, and control the internal read enable terminal r_en1 of the FIFO circuit 200 to output true. If the output trigger circuit 400 is empty while the FIFO circuit 200 is not empty, then the FIFO circuit 200 is controlled to output data to the output trigger circuit 400. For example, if the external read enable terminal r_en2 is true in the current clock cycle, in the next clock cycle, the data in the output trigger circuit 400 will be output to the data memory. If the output trigger circuit 400 is empty, the corresponding latest-in-first-out data in the data memory at this time needs to be stored in the output trigger circuit 400.

[0135] Specifically, when the external read enable input is false and the output trigger circuit 400 is not empty, the FIFO circuit 200 is controlled not to output data, and the output trigger circuit 400 is controlled to receive the data output by the output trigger circuit 400. In this way, the output trigger circuit 400 achieves data self-holding when the data memory does not need to output data.

[0136] In this embodiment, an output trigger connects the external read terminal and the internal read terminal dout1 of the FIFO circuit 200. The input trigger circuit 100 is used to temporarily store the read data. This reduces the delay of reading data from the corresponding address in the FIFO circuit 200 to the gate delay of the output trigger circuit 400, thus reducing the data read latency. Simultaneously, the second control circuit 500 controls the output trigger circuit 400 to receive its own output data when the output trigger circuit 400 is not empty and no external data is needed, achieving a data self-holding function. When the input of the external read enable terminal r_en2 is true, the output trigger circuit 400 is controlled to output data to the outside of the data storage, making the entire data read logic of the data storage consistent with that of the FIFO circuit 200. The data storage provided in this embodiment can reduce data read latency while implementing a first-in-first-out structure.

[0137] In one exemplary embodiment, based on Figure 8 Please refer to the embodiments shown. Figure 9 The first input terminal of the output trigger circuit 400 is connected to the external write terminal din2 of the data storage device through the second control circuit 500. The second control circuit 500 is also used to: control the first input terminal of the output trigger circuit 400 to receive the data input from the external write terminal din2 of the data storage device and control the input of the internal write enable terminal w_en1 to be false when the output of the internal empty signal terminal e1 of the FIFO circuit 200 is false; control the first input terminal of the output trigger circuit 400 to receive the data output from the internal read terminal dout1 when the output of the internal empty signal terminal e1 is true and the output trigger circuit 400 is empty; control the output of the external empty signal terminal e2 of the data storage device to be true when the external write enable terminal w_en2 of the data storage device is true, and if the internal empty signal terminal e1 is false, or if the output trigger circuit 400 is not empty and the external read enable terminal r_en2 is false, control the input of the internal write enable terminal w_en1 of the FIFO circuit 200 to be true.

[0138] In this implementation, when the internal empty signal terminal e1 outputs true (i.e., the internal FIFO circuit 200 is empty), by controlling the input of the internal write enable terminal w_en1 to be false, the data input from the external write terminal din2 is directly stored in the data trigger circuit without going through the empty FIFO circuit 200. Compared to directly using the FIFO circuit 200, which requires writing data to the FIFO circuit 200 and then reading it out, this implementation can reduce the data write latency and read latency of the data memory when the FIFO circuit 200 is empty, as well as the memory and power consumption.

[0139] When the internal empty signal terminal e1 of the FIFO circuit 200 is false, the first input terminal of the control output trigger circuit 400 receives the data output from the internal read terminal dout1 of the FIFO circuit 200.

[0140] Specifically, when the internal empty signal terminal e1 outputs true and the output trigger circuit 400 is empty, that is, when there is no data stored in the FIFO circuit 200 and the output trigger circuit 400, the external empty signal terminal e2 of the control data storage device outputs true.

[0141] Specifically, if the external write enable terminal w_en2 of the data storage is false, the internal write enable terminal w_en1 must be false. If the external write enable terminal w_en2 of the data storage is true, there are only two cases where the internal control internal write enable terminal w_en1 is true: one is that the internal empty signal terminal e1 output is false, and the other is that the output trigger circuit 400 is not empty and the external read enable terminal r_en2 input is false.

[0142] In one exemplary embodiment, please continue to refer to Figure 9 The second control circuit 500 is also used to control the external full signal terminal f2 of the data storage device to output true when the internal full signal terminal f1 of the FIFO circuit 200 outputs true and the output trigger circuit 400 is not empty. In this embodiment, the depth of the data storage device is the depth of the FIFO circuit 200 plus 1.

[0143] In one exemplary embodiment, please refer to Figure 10 ,based on Figure 8 In the illustrated embodiment, the second control circuit 500 in the data memory includes AND gates AND6, AND7, AND8, AND9, and AND10, OR gates OR2 and OR3, NOT gates NOT5, NOT6, NOT7, NOT8, a selector MUX3, and a record trigger D3, wherein:

[0144] The first input of AND gate AND6 is connected to the external write enable terminal w_en2 of the data storage, the second input of AND gate AND6 is connected to the output terminal of OR gate OR2, and the output terminal of AND gate AND6 is connected to the internal write enable terminal w_en1 of FIFO circuit 200.

[0145] The first input of OR2 is connected to the output of NOT5, the second input of OR2 is connected to the output of AND9, and the output of OR2 is also connected to the first input of OR3.

[0146] The second input of OR gate element OR3 is connected to the external write enable terminal w_en2, and the output of OR gate element OR3 is connected to the input of record trigger D3.

[0147] The input of NOT gate element NOT5 is connected to the internal empty signal terminal e1 of FIFO circuit 200, and the output of NOT gate element NOT5 is also connected to the first input terminal of AND gate element AND8.

[0148] The output of the record flip-flop D3 is connected to the input of NOT7, the first input of AND9, and the first input of AND7.

[0149] The second input terminal of AND gate element AND9 is connected to the output terminal of NOT gate element NOT8. The output terminal of AND gate element AND9 is also connected to the input terminal of NOT gate element NOT6 and the control terminal of output trigger circuit 400.

[0150] The input of the NOT gate element NOT8 is connected to the external read enable terminal r_en2 of the data storage.

[0151] The second input of AND gate element AND7 is connected to the internal full signal terminal f1 of FIFO circuit 200.

[0152] The output of NOT gate element NOT6 is connected to the second input of AND gate element AND8.

[0153] The output of AND gate element AND8 is connected to the internal read enable terminal r_en1 of FIFO circuit 200.

[0154] The output of NOT gate element NOT7 is connected to the first input of AND gate element AND10;

[0155] The second input terminal of AND gate element AND10 is connected to the internal empty signal terminal e1, and the output terminal of AND gate element AND10 is connected to the external empty signal terminal e2 of FIFO circuit 200.

[0156] The output of selector MUX3 is connected to the first input of output trigger circuit 400. The first input of selector MUX3 is connected to the internal read terminal dout1. The second input of selector MUX3 is connected to the external write terminal din2 of data storage. The control terminal of selector MUX3 is connected to the internal empty signal terminal e1. When the internal empty signal terminal e1 is true, selector MUX3 outputs the data written by the external write input terminal. When the internal empty signal terminal e1 is false, selector MUX3 outputs the data output by the internal read terminal dout1.

[0157] In this embodiment, a 1-bit recording flip-flop D3 is used to record whether the data in the output trigger circuit 400 is valid. This 1-bit recording flip-flop D3 can be called the output valid bit. If the external write enable is valid or the FIFO circuit 200 is not empty in the current clock cycle, the output valid bit in the next clock cycle is 1. If the output valid bit is 1 and the external read enable is 0 in the current clock cycle, the output valid bit in the next clock cycle is also 1; otherwise, the output valid bit in the next clock cycle is 1. It can be seen that: ① In the current clock cycle, if external data is written, the output trigger circuit 400 will not be empty in the next clock cycle. Specifically, if the FIFO circuit 200 is empty in the current clock cycle, the output trigger circuit 400 will select the data input from the external write terminal din2 in the next clock cycle. If the FIFO circuit 200 is empty in the current clock cycle, the output trigger circuit 400 will select the data output from the internal output terminal of the FIFO circuit 200 in the next clock cycle, and the data input from the external write terminal din2 will be written into the FIFO circuit 200. ② In the current clock cycle, if FIFO circuit 200 is not empty, then output trigger circuit 400 will not be empty in the next clock cycle. ③ In the current clock cycle, if output trigger circuit 400 is not empty and no external data is read, then output trigger circuit 400 will not be empty in the next clock cycle. Except for the above three cases, output trigger circuit 400 will be empty in the next clock cycle.

[0158] In this embodiment, if the external write enable terminal w_en2 is false, then the internal write enable terminal w_en1 must be false; if the external write enable terminal is true, then the internal write enable terminal w_en1 is true only in the following two cases: ① the internal empty signal terminal e1 outputs false; ② the valid bit is 1 and the external read enable terminal r_en2 is true, that is, the output of the record flip-flop D3 is true and the external read enable terminal r_en2 input is true.

[0159] In this embodiment, if the output of the internal empty signal terminal e1 is true, then the input of the internal read enable terminal r_en1 must be false; if the output of the internal empty signal terminal e1 is false, the valid bit is 0 or the input of the external read enable terminal r_en2 is true, then the input of the internal read enable terminal r_en1 is true, otherwise the input of the internal read enable terminal r_en1 is false.

[0160] In this embodiment, the output of the external full signal terminal f2 is equal to the AND operation of the internal full signal terminal f1 and the effective bits. The output of the external empty signal terminal e2 is equal to the AND operation of the internal empty signal terminal e1 and the inverted effective bits.

[0161] In one possible implementation, please refer to Figure 10The output trigger circuit 400 includes an enable trigger D4. The control terminal of the enable trigger D4 is connected to the output terminal of the AND gate element AND9, the first input terminal of the enable trigger D4 is connected to the output terminal of the selector MUX3, and the second input terminal of the enable trigger D4 is connected to the output terminal of the enable trigger D4. When the output of the AND gate element AND9 is true, the enable trigger D4 receives the data output by the enable trigger D4; when the output of the AND gate element AND9 is false, the enable trigger D4 receives the data output by the selector MUX3.

[0162] In one possible implementation, the output trigger circuit 400 includes an output selector and an output trigger. For example, the output trigger and the write trigger in the previous implementation can be implemented as edge triggers.

[0163] In this embodiment, the control terminal of the output selector is connected to the output terminal of the AND gate element AND9, the first input terminal of the output selector is connected to the output terminal of the selector MUX3, the second input terminal of the output selector is connected to the output terminal of the output flip-flop, and the output terminal of the output selector is connected to the input terminal of the output flip-flop. The output terminal of the output flip-flop also serves as the external read terminal of the data storage device. In this embodiment, the output selector and the output flip-flop are used to implement the function of the output triggering circuit 400. The read delay of the data storage device in this embodiment includes the output selector delay plus the output flip-flop output delay.

[0164] The data storage device provided in this embodiment achieves the same first-in-first-out (FIFO) storage function as the FIFO circuit 200 in related technologies, while reducing the read latency of the data storage device. Please refer to... Figure 11 , for adoption Figures 8 to 10 The illustrated embodiment provides an example of a data storage scenario where a larger delay margin is provided for the subsequent stage circuit by reducing the read latency.

[0165] The data storage provided in the embodiments of this application, based on the FIFO circuit 200 in the related art, adds a trigger circuit and a small number of logic gates to achieve the same first-in-first-out storage function as the original FIFO circuit 200. At the same time, it reduces the write latency while keeping the data read latency basically unchanged, or reduces the read latency while keeping the data write latency basically unchanged. This provides technicians in the field of digital integrated circuit design with more flexible data buffer storage device selection, improves the timing logic circuit latency optimization efficiency, increases the chip operating frequency, and improves chip performance.

[0166] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0167] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data storage device, characterized in that, The data storage device includes: Input trigger circuit, used to receive externally written data; A FIFO circuit is used to receive the write data transmitted by the input trigger circuit.

2. The data storage device according to claim 1, characterized in that, The input trigger circuit is also used to transmit the written data to the external read terminal of the data storage device; The data storage device further includes: A first control circuit is configured to control the input of the internal write enable terminal of the FIFO circuit to be false when the output of the internal empty signal terminal of the FIFO circuit is true and the input of the external read enable terminal of the data storage is true, and to control the output of the external empty signal terminal of the data storage to be true when the output of the internal empty signal terminal is true and the input trigger circuit is empty.

3. The data storage device according to claim 1, characterized in that, The output terminal of the input trigger circuit is connected to the input terminal of the input trigger circuit; The data storage device further includes a first control circuit; The first control circuit is used to control the external full signal terminal of the data storage to output true when the internal full signal terminal of the FIFO circuit outputs true and the input trigger circuit is not empty.

4. The data storage device according to claim 1, characterized in that, The data storage device further includes a first control circuit, which comprises: an OR gate element OR1, a record trigger D1, an AND gate element AND1, an AND gate element AND2, an AND gate element AND3, an AND gate element AND4, an AND gate element AND5, a NOT gate element NOT1, a NOT gate element NOT2, a NOT gate element NOT3, a NOT gate element NOT4, a selector MUX1, and a selector MUX2; wherein, The first input of the OR gate element OR1 is connected to the external write enable terminal of the data storage device, the second input of the OR gate element OR1 is connected to the output terminal of the AND gate element AND3, and the output terminal of the OR gate element OR1 is connected to the input terminal of the record trigger D1. The output of the recording trigger D1 is connected to the first input of the AND gate element AND1, the input of the NOT gate element NOT2, and the first input of the AND gate element AND2. The second input terminal of the AND gate element AND1 is connected to the output terminal of the selector MUX1, and the output terminal of the AND gate element AND1 is connected to the internal write enable terminal of the FIFO circuit. The output of NOT gate element NOT2 is connected to the first input of AND gate element AND5; The second input terminal of the AND gate element AND2 is connected to the internal full signal terminal of the FIFO circuit, and the output terminal of the AND gate element AND2 is connected to the external full signal terminal of the data storage and the first input terminal of the AND gate element AND3. The second input terminal of the AND gate element AND3 is connected to the output terminal of the NOT gate element NOT3; The input terminal of the NOT gate element NOT3 is connected to the external read enable terminal of the data storage device; The second input terminal of the AND gate element AND5 is connected to the internal empty signal terminal of the FIFO circuit, and the output terminal of the AND gate element AND5 is connected to the external empty signal terminal of the data storage device; The input terminal of the NOT gate element NOT1 is connected to the internal full signal terminal of the FIFO circuit, and the output terminal of the NOT gate element NOT1 is connected to the first input terminal of the selector MUX1. The control terminal of the selector MUX1 is connected to the internal empty signal terminal, and the second input terminal of the selector MUX1 is connected to the output terminal of the NOT gate element NOT3. When the output of the internal empty signal terminal is false, the selector MUX1 outputs the signal output by the NOT gate element NOT1. When the output of the internal empty signal terminal is true, the selector MUX1 outputs the signal output by the NOT gate element NOT3. The input terminal of the NOT gate element NOT4 is connected to the internal empty signal terminal, and the output terminal of the NOT gate element NOT4 is connected to the first input terminal of the AND gate element AND4. The second input terminal of the AND gate element AND4 is connected to the external read enable terminal of the data storage device, and the output terminal of the AND gate element AND4 is connected to the internal read enable terminal; The second input terminal of the AND gate element AND5 is connected to the internal empty signal terminal, and the output terminal of the AND gate element AND5 is connected to the external empty signal terminal of the data storage device; The control terminal of selector MUX2 is connected to the internal empty signal terminal. The first input terminal of selector MUX2 is connected to the internal readout terminal of the FIFO circuit. The second input terminal of MUX2 is connected to the output terminal of the input trigger circuit. The output terminal of selector MUX2 is connected to the external readout terminal of the data storage device. When the output of the internal empty signal terminal is false, selector MUX2 outputs the data output by the internal readout terminal. When the output of the internal empty signal terminal is true, selector MUX2 outputs the data output by the input trigger circuit.

5. The data storage device according to claim 4, characterized in that, The input triggering circuit includes an enable trigger D2, the control terminal of which is connected to the external write enable terminal; the first input terminal of the enable trigger D2 serves as the external write terminal of the data storage device, the second input terminal of the enable trigger D2 is connected to the output terminal of the enable trigger D2, and the output terminal of the enable trigger D2 is connected to the internal write terminal of the FIFO circuit and the second input terminal of the selector MUX2; when the input of the external write enable terminal is true, the enable trigger D2 receives the data input from the external write terminal, and when the input of the external write enable terminal is false, the enable trigger D2 receives the data output from the enable trigger D2.

6. A data storage device, characterized in that, The data storage device includes: The FIFO circuit is used to output data to the output trigger circuit under the control of the second control circuit. The output trigger circuit has a first input terminal connected to the internal read terminal of the FIFO circuit, a second input terminal connected to the output terminal of the output trigger circuit, and the output terminal of the output trigger circuit serves as the external output terminal of the data storage device. The second control circuit is used for: When the input to the external read enable terminal of the data storage is true, the output trigger circuit is controlled to output data to the outside of the data storage. If the output of the internal empty signal terminal of the FIFO circuit is false, and the input of the external read enable terminal is true or the output trigger circuit is empty, then the FIFO circuit is controlled to output data to the output trigger circuit. When the input to the external read enable terminal is false and the output trigger circuit is not empty, the FIFO circuit is controlled not to output data and the output trigger circuit is controlled to receive the data output by the output trigger circuit.

7. The data storage device according to claim 6, characterized in that, The first input terminal of the output trigger circuit is connected to the external write terminal of the data storage device through the second control circuit; the second control circuit is also used for: When the internal empty signal terminal of the FIFO circuit outputs true, the first input terminal of the output trigger circuit is controlled to receive the data input from the external write terminal of the data storage device and the input of the internal write enable terminal of the FIFO circuit is controlled to be false. When the internal empty signal terminal of the FIFO circuit outputs false, the first input terminal of the output trigger circuit is controlled to receive the data output by the internal readout terminal. When the internal empty signal terminal outputs true and the output trigger circuit is empty, the external empty signal terminal of the data storage device is controlled to output true. When the external write enable input of the data storage is true, if the internal empty signal input is false, or if the output trigger circuit is not empty and the external read enable input is false, the internal write enable input of the FIFO circuit is controlled to be true.

8. The data storage device according to claim 6, characterized in that, The second control circuit is also used to control the external full signal terminal of the data storage device to output true when the internal full signal terminal of the FIFO circuit outputs true and the output trigger circuit is not empty.

9. The data storage device according to claim 6, characterized in that, The second control circuit includes: AND gates AND6, AND7, AND8, AND9, and AND10; OR gates OR2 and OR3; NOT gates NOT5, NOT6, NOT7, and NOT8; a selector MUX3; and a record trigger D3, wherein: The first input of the AND gate element AND6 is connected to the external write enable terminal of the data storage device, the second input of the AND gate element AND6 is connected to the output terminal of the OR gate element OR2, and the output terminal of the AND gate element AND6 is connected to the internal write enable terminal of the FIFO circuit. The first input of OR2 is connected to the output of NOT5, the second input of OR2 is connected to the output of AND9, and the output of OR2 is also connected to the first input of OR3. The second input of the OR gate element OR3 is connected to the external write enable terminal, and the output of the OR gate element OR3 is connected to the input of the record trigger D3. The input terminal of the NOT gate element NOT5 is connected to the internal empty signal terminal of the FIFO circuit, and the output terminal of the NOT gate element NOT5 is also connected to the first input terminal of the AND gate element AND8. The output of the recording trigger D3 is connected to the input of the NOT gate element NOT7, the first input of the AND gate element AND9, and the first input of the AND gate element AND7. The second input terminal of the AND gate element AND9 is connected to the output terminal of the NOT gate element NOT8, and the output terminal of the AND gate element AND9 is also connected to the input terminal of the NOT gate element NOT6 and the control terminal of the output trigger circuit. The input terminal of the NOT gate element NOT8 is connected to the external read enable terminal of the data storage device; The second input terminal of the AND gate element AND7 is connected to the internal full signal terminal of the FIFO circuit; The output of NOT gate element NOT6 is connected to the second input of AND gate element AND8; The output of the AND gate element AND8 is connected to the internal read enable terminal of the FIFO circuit. The output of the NOT gate element NOT7 is connected to the first input of the AND gate element AND10; The second input terminal of the AND gate element AND10 is connected to the internal empty signal terminal, and the output terminal of the AND gate element AND10 is connected to the external empty signal terminal of the FIFO circuit. The output terminal of the selector MUX3 is connected to the first input terminal of the output trigger circuit. The first input terminal of the selector MUX3 is connected to the internal read terminal. The second input terminal of the selector MUX3 is connected to the external write terminal of the data storage device. The control terminal of the selector MUX3 is connected to the internal empty signal terminal. When the output of the internal empty signal terminal is true, the selector MUX3 outputs the data written by the external write input terminal. When the output of the internal empty signal terminal is false, the selector MUX3 outputs the data output by the internal read terminal.

10. The data storage device according to claim 9, characterized in that, The output trigger circuit includes an enable trigger D4, the control terminal of which is connected to the output terminal of the AND gate element AND9, the first input terminal of which is connected to the output terminal of the selector MUX3, and the second input terminal of which is connected to the output terminal of the enable trigger D4. When the output of AND gate element AND9 is true, the enable trigger D4 receives the data output by the enable trigger D4; when the output of AND gate element AND9 is false, the enable trigger D4 receives the data output by the selector MUX3.

Images