Read time overhead and power optimization for command queues in memory devices

Abstract

The present disclosure relates to read time overhead and power optimization for command queues in memory devices. A device includes a memory cell array having a first word line coupled to at least a subset of the array, a queue, and control logic. The control logic: detects a first read command to read first data from a first page of the subset; accesses a second read command in the queue, the second read command to read second data from a second page of the subset; causes a voltage applied to the word line to ramp to an initial value; causes the voltage to move to a target value; directs a page buffer to sense the first data from a first bit line coupled to the first page of the subset; directs the page buffer to sense the second data from a second bit line coupled to the second page of the subset; and causes the word line to discharge.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on May 11, 2022, with application number 202210532871.2 and entitled "Read time overhead and power optimization for command queues in memory devices". Technical Field

[0003] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to read time overhead and power optimization for command queues in memory devices. Background Technology

[0004] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0005] In one aspect, this disclosure is directed to an apparatus comprising: a memory cell array including a first word line coupled to at least one subset of the memory cell array; a queue implemented within the memory cell array; and control logic coupled to the first word line and the queue, the control logic performing operations including: detecting the first read command to read first data from a first page of the subset of the array; accessing a second read command in the queue, the second read command being to read second data from a second page of the subset of the array; causing a voltage applied to the first word line to ramp up to an initial value; causing the voltage applied to the first word line to move to a target value to set the read operation; guiding a page buffer to sense the first data from a first bit line of the first page coupled to the subset of the array; guiding the page buffer to sense the second data from a second bit line of the second page coupled to the second page of the subset of the array; and causing the first word line to discharge.

[0006] In another aspect, this disclosure relates to a method comprising: detecting, via control logic coupled to a first word line and a queue within a memory device, a first read command to read first data from a first page of a subset of a memory cell array; accessing, via the control logic, a second read command in the queue, the second read command being to read second data from a second page of the subset of the array; causing, via the control logic, a voltage applied to the first word line to ramp up to an initial value; causing, via the control logic, the voltage applied to the first word line to move to a target value to set up a read operation; directing, via the control logic, a page buffer to sense the first data from a first bit line of the first page of the subset coupled to the array; directing, via the control logic, the page buffer to sense the second data from a second bit line of the second page of the subset coupled to the array; and causing, via the control logic, the first word line to discharge.

[0007] In another aspect, this disclosure relates to a method comprising: detecting a first set of read commands for reading first data from a first lower page of a first TLC of a memory cell array via control logic coupled to a three-level cell (TLC) word line and a queue within a memory device; accessing, via the control logic, a second set of read commands in the queue for reading second data from a second lower page of a second TLC of the memory cell array; causing, via the control logic, a voltage applied to the TLC word line to ramp up to an initial value; causing, via the control logic, the voltage applied to the TLC word line to move to a target value to set up a read operation; directing, via the control logic, a page buffer to sense a first portion of the first data from a first bit line of the first lower page of the first TLC coupled to the array; directing, via the control logic, the page buffer to sense a second portion of the first data from a second bit line of the first lower page coupled to the first TLC; and causing, via the control logic, the voltage applied to the TLC word line to move back to the target value to set up a read operation again. Attached Figure Description

[0008] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0009] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0010] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0011] Figure 2A-2C This is a reference based on the embodiments. Figure 1BA schematic diagram of a portion of the memory cell array in the described type of memory.

[0012] Figure 3 According to the embodiments, see reference Figure 1B A schematic block diagram of a portion of the memory cell array used in the type of memory described.

[0013] Figure 4 This is a conceptual depiction of the threshold voltage distribution of a plurality of memory cells in a memory array according to an embodiment.

[0014] Figure 5 It is a conceptual description of the threshold voltage distribution of multiple memory cells at a stage after programming, used in various embodiments.

[0015] Figure 6 This is a graph illustrating the voltage waveform associated with a single read command of a single-level cell in a certain memory device, according to an embodiment.

[0016] Figure 7 This is a graph illustrating the voltage waveform associated with a combined read operation of two read commands for two single-level cells of a processing memory device, according to an embodiment.

[0017] Figure 8 This is a diagram illustrating the distribution of threshold voltages associated with three possible pages to which the three-level unit of the memory device can be programmed, according to an exemplary embodiment.

[0018] Figures 9A-9B This is a graph illustrating the voltage waveform associated with a combined read operation, according to an embodiment, of processing multiple read commands for pages from multiple three-level cells of a memory device.

[0019] Figure 10 This is a graph illustrating the voltage waveform associated with a combined read operation according to an embodiment, which involves executing two read commands to process different blocks in a plane pointing to a memory device.

[0020] Figure 11 This is a graph illustrating the command timing waveform associated with the voltage waveform of a single read command and the combined read operation of multiple read commands, according to an embodiment.

[0021] Figure 12 This is a flowchart of an example method for executing a combined read operation of two read commands for processing two single-level units, according to some embodiments.

[0022] Figure 13 This is a flowchart of an example method, according to some embodiments, for performing a combined read operation of two read commands to process pages of multiple three-level units.

[0023] Figure 14 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0024] Embodiments of this disclosure relate to read time overhead and power optimization for command queues in memory devices. In some memory devices, a memory subsystem controller includes a command queue in which commands, generally in a first-in-first-out (FIFO) order, are buffered and processed from the host system or generated locally by the memory subsystem controller. Such commands include erase commands to erase physical blocks of memory, write commands to program certain data (e.g., one page at a time) to one or more dies (or planes) of the memory device, or read commands to read certain data outputs from one or more dies (or planes) of the memory device (e.g., one page at a time). In some such memory devices, as a read command reaches the top of the command queue, it is sent to the target die to read data from the address contained in the read command.

[0025] In various embodiments, each read command includes specific overhead, comprising a certain amount of time (e.g., a "time period") for each of the following stages of the read operation: First, a time period causing the voltage applied to all word lines of the die to ramp up to an initial voltage. Second, a time period causing the voltage applied to the selected word line to move to a target value set for the word line used in the read operation. Third, a time period pre-charging the bit lines of the pages (addressed in the read command) of the memory cell array coupled to the planar die. Fourth, a time period sensing the data stored in the page and thus reading the data into a latch or register of the page buffer. In some embodiments, the pre-charging time period is eliminated if the bit lines have already been charged or if data sensing involves charging simultaneously sufficient to read data from the memory cell. Fifth, a recovery time period in which the word lines and bit lines are discharged from the previously applied voltage. Because these time periods apply to the processing of each read command through each target die, processing multiple read commands causes this time overhead to accumulate into a significant cumulative overhead.

[0026] This disclosure addresses the above and other drawbacks by employing queues (e.g., command queues) stored either on the die or in the plane of the memory device receiving the command to be processed. Because read commands following the current command being processed by the memory device are stored locally in the command queue, the memory device can perform combined read operations that process each of the current (or first) read command and subsequent (or second) read commands during the same (e.g., combined) read operation. Embodiments of the invention achieve significant overhead savings when the first and second read commands are consecutive read commands on the same word line. For example, in one embodiment, the first and second read commands point to two different memory cells coupled to the same word line.

[0027] In these embodiments, the memory device includes a memory cell array comprising a first word line coupled to at least a subset of the memory cell array. A queue may also be located (or implemented) within the array, for example, within a plane or die targeted by some read command. Control logic for the memory device may be coupled to the first word line and the queue. The control logic may be adapted to guide a combined read operation, which is generally performed as follows, but will be discussed in more detail later: The control logic may detect a first read command to read first data from a first page of a subset of the array. The control logic may access a second read command in the queue, the second read command being to read second data from a second page of a subset of the array. The control logic may cause the voltage applied to the first word line to ramp up to an initial value and then cause the voltage applied to the first word line to move to a target value to set up the read operation. The control logic may guide a page buffer to precharge the first bit line coupled to the first page of the subset of the array and sense the first data. The control logic may guide a page buffer to precharge the second bit line coupled to the second page of the subset of the array and sense the second data. The control logic may cause the first word line and the bit line to discharge.

[0028] In this way, the stages of word line voltage ramp-up, word line voltage move to the target value, and word line voltage discharge can overlap for two read commands, thereby saving the overhead time associated with these actions when performing combined read operations. Word line discharge can be part of a recovery period involving the time it takes for data to be ready to be read and the time when processing the next read command begins. In different embodiments, the combination of time savings from all three of these time periods involves a saving of between one-third and one-half of the entire read operation time. The overhead savings can become more complex when performing combined read operations for three, four, or more consecutive read commands pointing to the same word line.

[0029] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, reducing the cumulative overhead time required to process read commands (specifically, consecutive read commands in a queue pointing to the same word line). This reduction in overhead time for processing multiple read commands can be extended from reads from a single-level cell (SLC) to reads from a three-level cell (TLC), a four-level cell (QLC), and so on, as will be discussed in more detail. Some overhead time savings can also be achieved when performing selected combinations of read operations to process random read commands, as also discussed later. Those skilled in the art will appreciate other advantages of the read command handling optimizations within the memory device discussed below.

[0030] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0031] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0032] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0033] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0034] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing means (e.g., a processor).

[0035] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 can provide data for storage at the memory subsystem 110 and can request retrieval of data from the memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0036] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0037] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0038] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0039] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0040] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0041] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0042] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0043] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0044] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1A The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0045] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0046] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0047] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 having control logic (e.g., local media controller 135) on the die and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0048] In some embodiments, memory device 130 includes page buffer 152, which provides circuitry for programming data into and reading data from memory cells of memory device 130. Memory device 130 may additionally include queues 131 (e.g., command queues) stored within a memory array of memory device 130, such as on a die or plane of memory device 130. In alternative embodiments, queue 131 may be located on a local media buffer external to the memory array. Control logic of local media controller 135 may be adapted to read commands buffered in queue 131, identify subsequent commands pointing to the same word line as the currently being processed command, and guide combined read operations in which, for example, as part of a combined read operation, both the current command and the subsequent command are processed simultaneously.

[0049] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0050] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells arranged in logical rows are typically connected to the same access line (e.g., a word line), while memory cells arranged in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown) can be programmed to one of at least two target data states. In some embodiments, the memory cell array 104 includes a queue 131 implemented within the memory cells of the memory cell array 104. The queue 131 may also be located in the local media buffer or local memory of the local media controller 135 (illustrated in dashed lines). The queue 131 may refer to the command queue as mentioned herein.

[0051] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0052] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to addresses.

[0053] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transmission to the memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer 152 of memory device 130 (e.g., at least a portion thereof). Page buffer 152 may further include sensing devices (e.g., a sensing amplifier) ​​to sense the data status of the memory cells of memory cell array 104, for example by sensing the status of data lines connected to the memory cells. Status register 122 may communicate with I / O control circuitry system 112 and local memory controller 135 to latch status information for output to memory subsystem controller 115.

[0054] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0055] For example, a command can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 121 for programming memory cell array 104.

[0056] In this embodiment, the cache register 118 may be omitted, and data may be written directly to the data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0057] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0058] Figure 2A-2C It can be, for example, part of memory cell array 104 according to an embodiment in reference. Figure 1B A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to... Figure 2A Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0059] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cell 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain transistor). Select transistors 2100 to 210 M They can be connected together to select line 214, such as the source select line (SGS), and select transistors 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0060] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 in the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0061] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0062] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0063] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as... Figure 2A As shown in the diagram. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0064] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202...N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0065] Although Figure 2A Although bit lines 2043 and 2045 are not explicitly depicted in the figure, it is evident from the figure that bit line 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell. This is in conjunction with the discussion of NAND flash memory. Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0066] Figure 2B It can be, for example, part of memory cell array 104 in reference Figure 1B Another schematic diagram of a portion of the memory cell array 200B used in the type of memory described. Figure 2B Elements with the same number in the text correspond to elements such as those mentioned above. Figure 2A The description provided. Figure 2BFurther details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of the NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040-204 via a select transistor 212 (e.g., a drain select transistor, commonly referred to as a select gate drain). M And a selection transistor 210 (e.g., a source selection transistor, often referred to as a select gate source) is selectively connected to a common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via selection lines 2150-215. K A bias voltage is applied to its corresponding bit line 204 to selectively activate a specific selection transistor 212 located between the NAND string 206 and the bit line 204. A selection transistor 210 can be activated by applying a bias voltage to selection line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells interconnected by specific sub-lines 202 can be collectively referred to as a layer.

[0067] Figure 2C It can be, for example, part of memory cell array 104 in reference Figure 1B Another schematic diagram of a portion of the memory cell array 200C used in the type of memory described. Figure 2C Elements with the same number in the text correspond to elements such as those mentioned above. Figure 2A The provided description. The memory cell array 200C may contain, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, an access (e.g., a word) line 202, a data (e.g., a bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C.

[0068] Figure 2C The diagram depicts the NAND string 206 being grouped into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may represent those NAND strings 206 that are associated with, for example, a single select line 215 of select line 2150. The source 216 of memory cell block 250 may be associated with memory cell block 250. LThe source 216 is the same as the source. For example, each memory cell block 2500-250 L They can be selectively connected together to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 are respectively connected to memory cell blocks 2500-250. L Access lines 202 and select lines 214 and 215 of any other memory cell block may not have a direct connection.

[0069] Bit line 2040 to 204 M It can be connected (e.g., selectively connected) to a buffer portion 240 that may be part of a page buffer 152 of the memory device 130. The buffer portion 240 may correspond to a memory plane (e.g., memory cell block 2500-250). L (The set). Buffer section 240 may include sensing circuitry (which may include a sensing amplifier) ​​for sensing the data value indicated on the corresponding bit line 204.

[0070] Figure 3 This can be used as a reference. Figure 1B A block diagram of a portion of a memory cell array 300 in a memory of the described type. The memory cell array 300 is depicted having four memory planes 350 (e.g., memory planes 3500-3503), each communicating with a corresponding buffer portion 240, which together form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 may communicate together with the page buffer 352. Each memory plane 350 is depicted containing L+1 memory cell blocks 250 (e.g., memory cell blocks 2500-250...). L ).

[0071] Figure 4 It is a conceptual description of the threshold voltage range of multiple memory cells. Figure 4 Examples illustrating the threshold voltage range and distribution of a group of sixteen-level memory cells, such as QLC memory cells. For instance, such memory cells could be programmed to fall within sixteen different threshold voltage ranges from 4300 to 4300. 15 A threshold voltage (Vt) is defined within a range, with each threshold voltage range representing the data state corresponding to a four-bit bit pattern. The width of threshold voltage range 4300 is typically greater than the width of the other threshold voltage ranges 4301-430. 15 Because the memory cells are typically all in a data state corresponding to the threshold voltage range of 4300, a subset of those memory cells is then programmed to have a threshold voltage range of 4301-4300. 15The threshold voltage is within a certain range. Because programming operations are generally controlled in a more incremental manner compared to erasing operations, these threshold voltages range from 4301 to 4301. 15 It can tend to have a more compact distribution.

[0072] Threshold voltage ranges: 4300, 4301, 4302, 4303, 4304, 4305, 4306, 4307, 4308, 4309, 430 10 430 11 430 12 430 13 430 14 and 430 15 Each can represent a corresponding data state, for example, L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15. As an example, if the threshold voltage of a memory cell is within the first threshold voltage range of sixteen threshold voltage ranges 4300, the memory cell can store data state L0 with a logical value of '1111', and this is commonly referred to as the erase state of the memory cell. If the threshold voltage is within the second threshold voltage range of sixteen threshold voltage ranges 4301, the memory cell can store data state L1 with a logical value of '0111'. If the threshold voltage is within the third threshold voltage range of sixteen threshold voltage ranges 4302, the memory cell can store data state L2 with a logical value of '0011', and so on. Table 1 provides one possible correspondence between data states and their corresponding logical data values. Other assignments of data states to logical data values ​​are known or conceivable. As used herein, a memory cell that remains in the lowest data state (e.g., erase state or L0 data state) will be considered programmed to the lowest data state.

[0073]

[0074] Table 1

[0075] Figure 5 It is a conceptual description of the threshold voltage distribution of multiple memory cells after programming. Figure 5 Threshold voltage distribution 530 d -530 d+1 This can indicate when the programming operation of the memory cell is completed. Figure 4 The threshold voltage range is 4300-430. 15 A portion of the distribution. (Reference) Figure 5Upon completion of programming, adjacent threshold voltage distributions 530 are typically separated by a tolerance 532 (e.g., dead space). Applying a sensed voltage (e.g., read voltage) within the tolerance 532 to the control gate of the multiple memory cells can be used to distinguish the threshold voltage distributions 530. d The memory cell (and any lower threshold voltage distribution) with threshold voltage distribution 530 d+1 The memory cells (and any higher threshold voltage distribution).

[0076] Figure 6 This is a graph illustrating the voltage waveform associated with a single read command of a single-level cell in a certain memory device according to an embodiment. For example, each read command includes specific overhead, comprising a certain amount of time for each of the following stages of the read operation. During a first time period (T1), control logic (e.g., of the local media controller 135) causes the voltage applied to all word lines of the plane or die to ramp up to an initial voltage. During a second time period (T2), control logic causes the voltage applied to the selected word line (WLsel) to move to a target value (V) set for the word line used for the read operation. target Furthermore, during the second time period (T2), the control logic causes the unselected word line (WLunsel) to continue to increase voltage so that the NAND string (e.g., NAND string 206) can be turned on when selected.

[0077] Further reference Figure 6 In one embodiment, during a third time period (T3), the control logic causes pre-charging of the bit lines (BLs) of a page (addressed in a read command) of the memory cell array coupled to the die or plane. The control logic may also cause pre-charging of the set of BLs associated with the page. Additionally, during the third time period, the control logic causes the page buffer to sense the data stored in the page, and thus read the data into a latch or register of the page buffer. In some embodiments, the third time period does not include pre-charging in cases where the bit lines are already charged or the data sensing involves charging simultaneously sufficient to read data from a memory cell. Pre-charging, as a specific or separate operation, can therefore be considered optional, but is described and discussed throughout this disclosure. Finally, during a fourth time period (T4), the control logic causes the selected word lines and unselected word lines, as well as the bit lines, to discharge for recovery purposes before another read command of the array can be processed. Furthermore, during the fourth time period, the control signal (R / B#) identifying the word lines moves to a high value, indicating that the memory device is ready for a new command (compared to a busy state). Additionally, during the fourth time period, the read port (array R / B#) of the memory cell array (coupled to word lines and bit lines) is indicated to have data ready to be read before the next read command begins processing. In one embodiment, this read port is located on the die being read.

[0078] Figure 7 This is a graph illustrating the voltage waveform associated with a combined read operation of two read commands from two single-level cells of a processing memory device, according to an embodiment. Therefore, in some embodiments, Figure 7 The word line selected is a single-level cell word line. While the second time period (T2) may take longer than the indicated time, the marked second time period does not overlap with the third time period (T3) because the third time period will be reused to process subsequent commands. In one embodiment, only the third time period, indicated by T3', is repeated to process the second read command. Therefore, during the T3' time period, the control logic optionally precharges at least the second bit line (BL) of the second page (addressed in the second read command retrieved from queue 131) of the memory cell array coupled to the die or plane. Additionally, during the T3' time period, the control logic causes the page buffer to sense the second data stored in the second page and thus read the second data into a latch or register of the page buffer. These third time periods T3 and T3' may have different lengths. For example, in one embodiment, the T3 time period is between 1 and 4 microseconds (μs) shorter than T3'. Figure 7 In one embodiment, the fourth time period (T4) reserved for recovery is instead followed by the second or third time period or T3'.

[0079] In one embodiment, further reference Figure 6 and Figure 7 T1 is approximately 10 microseconds (μs), T2 is approximately 5.9 μs, T3 is approximately 14.4 μs, T3' is approximately 18.1 μs, and T4 is approximately 6.8 μs. Therefore, in embodiments where the first, second, and fourth time periods overlap for combined read operations, a total time overhead saving of approximately 22.7 μs is achieved when processing two read commands as a combined read operation. These are estimates of the time overhead reduction; different varying time values ​​for these time periods are expected in other embodiments or memory cells of other sizes. This time saving can be considered approximately 55% for reading the second SLC. Because time periods T1 to T4 apply to the processing of each read command for each target die, combining three or more read commands into a single read operation is expected to significantly increase the amount of time overhead reduction.

[0080] Figure 8This is a diagram illustrating the threshold voltage distributions associated with three possible pages to which a three-level cell (TLC) of a memory device is programmable according to an exemplary embodiment. These three pages comprise a lower page (LP), an upper page (UP), and an additional page (UP), each having eight voltage distributions within which multiple TLCs can be programmed. As can be observed, to read data from these three pages from multiple TLCs, two read commands are processed for the LP, three read commands for the UP, and two read commands for the XP. Because a single word line can be coupled to multiple TLC pages, a word line can be coupled to more than one TLC. Therefore, this disclosure can be applied to reading data output from two LPs of two different TLCs, from two UPs of two different TLCs, or from two XPs of two different TLCs in combined read operations.

[0081] Moreover, if reference Figures 9A-9B The discussion suggests that performing combined read operations as disclosed herein can be done while processing sequential read commands associated with reading data from pages of multiple TLCs. Therefore, in some embodiments, Figure 7 The selected word line is a three-level unit word line. The first read command will perform a first read operation on the lower pages of multiple TLCs, and the second read command will perform a second read operation on the lower pages. In other embodiments, the first read command will perform a first read operation on additional pages of multiple TLCs, and the second read command will perform a second read operation on the additional pages. In yet another embodiment, the first read command will perform a first read operation on one of the lower or upper pages of multiple TLCs, and the second read command will perform a second read operation on said lower or upper page.

[0082] Figures 9A-9B This is a graph illustrating the voltage waveform associated with a combined read operation, according to an embodiment, of processing multiple read commands for pages from a plurality of three-level cell (TLC) memory devices. See reference... Figure 8 As discussed, these multiple read commands can be two read commands used for the lower page, upper page, or additional pages of multiple TLCs. Figures 9A-9B The waveform illustrates the execution of a combined read operation pointing to any two pages of a multi-level unit (e.g., MLC, QLC, PLC, etc.). In various embodiments, the waveform progresses through eight time periods, the first four of which are comparable to a reference. Figure 7 The overlapping periods among the four time periods discussed.

[0083] More specifically, the control logic may detect a first read command set to read first data from a first lower page of a first TLC of the memory cell array. The control logic may further access a second read command set to read second data from a second lower page of a second TLC of the memory cell array. This may be achieved via... Figure 9A The first four time periods described process the first set of read commands. In this TLC embodiment, the control logic causes the voltage applied to the TLC word line to ramp up to an initial value during the first time period (T1). The control logic causes the voltage applied to the TLC word line to move to a target value during the second time period (T2) to set up the read operation. During the third time period (T3), the control logic boots the page buffer and optionally precharges the first bit line of the first lower page of the first TLC coupled to the array and senses the first portion of the first data. (See reference...) Figure 7 Similarly, the second and third time periods may overlap, but for simplicity, they are described as non-overlapping, and therefore the third time period is equivalent to the fourth time period. Additionally, during the fourth time period (T4), the control logic boot page buffer optionally precharges the second bit line coupled to the first lower page of the first TLC and senses the second portion of the first data.

[0084] For further reference Figure 9B According to some embodiments, the control logic can be implemented in... Figures 9A-9B The second set of read commands is processed in the second half of the combined read operation. In these embodiments, the control logic causes the voltage applied to the TLC word line to move back to the target value during the fifth time period (T5) to reset the read operation. The control logic further directs the page buffer to optionally precharge the third bit line of the second lower page of the second TLC coupled to the array and sense the first portion of the second data during the sixth time period (T6). The control logic may further direct the page buffer to optionally precharge the fourth bit line of the second lower page of the second TLC coupled to the array and sense the second portion of the second data during the seventh time period (T7). Finally, the control logic may cause the TLC word line to discharge, and also cause the unselected word line and bit line to discharge during recovery or the eighth time period (T8). Because four read commands are processed for the same word line, the first and eighth time periods are used only once (instead of four times) and the second time period is used only twice, such as T2 and T5, instead of four times, thereby achieving a significant reduction in the time overhead of reading two LPs (or two UPs or two XPs) of multiple TLCs.

[0085] Figure 10 This is a graph illustrating the voltage waveforms associated with a combined read operation, according to an embodiment, of executing two read commands to process different blocks in a plane pointing to a memory device. Although Figure 10 The embodiments are similar to Figure 7 The embodiment is similar, but the difference is that consecutive read commands (from queue 131) do not point to the same word line. Therefore, when processing the first read command (according to...) Figure 6 After that, the control logic can cause the unselected word lines and the selected word lines to process the second read command pointing to another block of the plane (according to...). Figure 6 The data can float during the read operation. Therefore, data can be read during a combined read operation and multiple pre-charged word lines (associated with the pages of both different read commands) and bit lines can be discharged simultaneously. This saves time required for the recovery period of a second (or any subsequent) read command.

[0086] If the unselected word line remains at a high voltage (due to the floating word line), the memory cells in the previously selected block are placed under stress, which can cause read interference in those memory cells. Therefore, to reduce the potential read interference to nearby cells before moving to read from the next block, the control logic can slightly discharge the word line, for example, from 8V to 7V in one embodiment. The probability of read interference can be further reduced by causing a recovery operation to be performed after executing a threshold number of consecutive read commands across multiple word lines. The control logic can also turn off the block selector without time loss.

[0087] Figure 11 This is a graph illustrating the command timing waveforms associated with the voltage waveform of a single read command and the combined read operation of multiple read commands, according to an embodiment. In one embodiment, by way of example only, the control logic may direct a first read operation to retrieve page_N, a second read operation to retrieve page_N+1, and a combined third read operation to retrieve pages_N+2 and page_N+3. As illustrated, the values ​​of each incoming read command R / B#, array R / B, internal page data, unselected WL, selected WL, secondary data cache (SDC) data, and primary data cache (PDC) data are respectively illustrated as control signal waveforms, voltage waveforms, and block waveforms. In various embodiments, the controller 115 sends the read command (30h) to the control logic of the memory device 130 (e.g., local media controller 135) instead of interleaving the read command (30h) with the cache command (31h).

[0088] In this way, the control logic can control the cache (as associated with page buffers 152 and 352) more independently and simplify the control sequence, thereby enabling data transfers to be hidden during the WL recovery period. For example, as will be explained, the management of internal data movement by the memory device 130 can be dynamic based on latch availability. Furthermore, the PDC can be disregarded in relation to data transfers.

[0089] like Figure 11As explained, internal pages can be read from memory cells during the recovery period, thus enabling data transfer to be hidden during this time period. Sometimes, data stored in the SDC latch can be transferred from memory device 130 later. Because the transfer of SDC data off the die is performed when the select gate has been timed out, controller 115 can send a cache release command to the die when the select gate has been timed out and subsequently release a specific SDC latch for storing new data from the die. In this way, the read data timing output can be decoupled from the presentation of subsequent commands (unlike the usual cache management approach).

[0090] Therefore, refer to another source Figure 7 The control logic may additionally receive a first cache release command associated with a latch in the page buffer and cause the first data to be stored in the latch in the page buffer. The control logic may additionally receive a second cache release command associated with a latch and cause the second data to be stored in the latch in the page buffer. Reference may be made to memory device 130, which performs these actions to release data from the cache to free the (SDC) latch for storing additional data being read from the memory cell array. In one embodiment, the second cache release command is received after the first cache release command.

[0091] Additionally, see other references Figures 9A-9B After the first four time periods, the control logic may additionally receive a first cache release command associated with the page buffer latch, causing a first portion of the first data to be stored in the latch; receive a second cache release command associated with the page buffer latch, causing a second portion of the first data to be stored in the latch. In one embodiment, the second cache release command is received after the first cache release command. Additionally, after the second four time periods, the control logic may additionally receive a third cache release command associated with the page buffer latch, causing a first portion of the second data to be stored in the latch; receive a fourth cache release command associated with the page buffer latch, causing a second portion of the second data to be stored in the latch. In one embodiment, the fourth cache release command is received after the third cache release command. In this way, the same page buffer and latch can be shared when reading data from the SDC.

[0092] Figure 12This is a flowchart illustrating an example method 1200 for executing a combined read operation of two read commands for processing two single-level units, according to some embodiments. Method 1200 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 1200 is performed by… Figure 1A-1B The local media controller 135, coupled to page buffers (e.g., page buffer 152) and queues (e.g., queue 131), performs the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0093] At operation 1210, the first command is detected. For example, the processing logic detects a first read command to read first data from the first page of a subset of the memory cell array. The memory cell array may be coupled to the first word line and the previously mentioned queue.

[0094] At operation 1220, a second command is accessed. For example, a second read command in the logical access queue is processed, which reads second data from the second page of a subset of the array. In some embodiments, the second read command is associated with the first read command in the queue.

[0095] At operation 1230, the voltage is ramped up. For example, the processing logic causes the voltage applied to the first word line to ramp up to its initial value.

[0096] At operation 1240, the voltage is shifted. For example, the processing logic causes the voltage applied to the first word line to be shifted to the target value to set the read operation.

[0097] At operation 1250, the bit line is sensed. For example, the processing logic bootstraps the page buffer to sense the first data from the first bit line of the first page coupled to the first subset of the array. In some embodiments, the processing logic also bootstraps the page buffer to precharge the first bit line before sensing the first data.

[0098] At operation 1260, another bit is sensed. For example, the processing logic bootstraps the page buffer to sense the second data from the second bit line of the second page coupled to a subset of the array. In some embodiments, the processing logic also bootstraps the page buffer to precharge the second bit line before sensing the second data.

[0099] At operation 1270, the word line is discharged. For example, the processing logic causes the first word line and bit line to discharge. In various embodiments, the operations of causing the voltage applied to the first word line to ramp up, causing the voltage applied to the first word line to move to the target value, and causing the first word line to discharge are performed only once when processing both the first read command and the second read command.

[0100] Figure 13 This is a flowchart of an example method 1300, according to some embodiments, of executing a combined read operation of two read commands for processing pages of multiple three-level units. Method 1300 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 1300 is performed by… Figure 1A-1B The local media controller 135, coupled to page buffers (e.g., page buffer 152) and queues (e.g., queue 131), performs the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0101] At operation 1310, the first command is detected. For example, the processing logic detects a first read command set that reads first data from the first lower page of the first TLC of the memory cell array. The first TLC may be coupled to a three-level cell (TCL) word line and a queue.

[0102] At operation 1320, a second command is accessed. For example, a second set of read commands in the logical access queue is processed to read second data from a second lower page of a second TLC of the memory cell array. In one embodiment, the second set of read commands is associated with a first set of read commands.

[0103] At operation 1330, the voltage is ramped up. For example, the processing logic causes the voltage applied to the TLC word line to ramp up to its initial value.

[0104] At operation 1340, the voltage is shifted. For example, the processing logic causes the voltage applied to the TLC word line to be shifted to a target value to set up the read operation.

[0105] At operation 1350, the bit line is sensed. For example, the processing logic boots the page buffer to sense a first portion of the first data from the first bit line of the first lower page of the first TLC coupled to the array. In some embodiments, the processing logic also boots the page buffer to precharge the first bit line before sensing the first portion of the first data.

[0106] At operation 1360, another bit line is sensed. For example, the processing logic boots the page buffer to sense a second portion of the first data from a second bit line coupled to a first lower page of the first TLC. In some embodiments, the processing logic also precharges the second bit line by boots the page buffer before sensing the second portion of the first data.

[0107] At operation 1370, the word line is discharged. For example, the processing logic causes the voltage applied to the TLC word line to move back to the target value to reset the read operation. In other embodiments, method 1300 is applied to the top page (UP) of multiple TLCs or to the extra page (XP) of multiple TLCs.

[0108] In another embodiment, the processing logic boot page buffer precharges the third bit line of the second lower page of the second TLC coupled to the array and senses the first portion of the second data. The processing logic boot page buffer precharges the fourth bit line of the second lower page of the second TLC coupled to the array and senses the second portion of the second data. The processing logic causes the TLC word lines and bit lines to discharge to perform a recovery operation.

[0109] Figure 14 This describes an instance machine of computer system 1400, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1400 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of the memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0110] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0111] Example computer system 1400 includes a processing device 1402, a main memory 1404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1410 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1418, which communicate with each other via a bus 1430.

[0112] Processing device 1402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 1402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1402 is configured to execute instructions 1428 to perform the operations and steps discussed herein. Computer system 1400 may additionally include a network interface device 1412 for communication on network 1420.

[0113] Data storage system 1418 may include machine-readable storage medium 1424 (also referred to as computer-readable medium) on which one or more instruction sets 1428 or software embodying any or more of the methods or functions described herein are stored. Data storage system 1418 may additionally include the previously discussed local media controller 135, page buffer 152 or 352, and queue 131. Instructions 1428 may also reside wholly or at least partially within main memory 1404 and / or processing device 1402 during execution by computer system 1400, which also constitute machine-readable storage medium. Machine-readable medium 1424, data storage system 1418, and / or main memory 1404 may correspond to... Figure 1A The memory subsystem 110.

[0114] In one embodiment, instruction 1426 includes instructions for implementing a controller (e.g., Figure 1A The memory subsystem controller 115) provides functional instructions. Although the machine-readable storage medium 1424 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0115] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0116] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0117] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0118] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0119] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0120] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. An apparatus comprising: A memory cell array, comprising first word lines coupled to at least a subset of the memory cell array; as well as The control logic coupled to the first word line performs operations including the following: Detect a first read command to read first data from the first page of the subset of the array and a second read command to read second data from the second page of the subset of the array in the queue; This causes the voltage applied to the first word line to move to the target value; This causes the page buffer to sense the first data from the first bit line coupled to the first page and the second data from the second bit line coupled to the second page; as well as This caused the first word line to discharge.

2. The apparatus of claim 1, further comprising the queue coupled to the control logic, wherein the second read command is stored sequentially in the queue along with the first read command, and wherein causing the page buffer to sense the first data and the second data further comprises causing the page buffer to precharge the first bit line and the second bit line.

3. The apparatus of claim 1, further comprising causing the voltage applied to the first word line to ramp up to an initial value, which, together with the operations of causing the voltage applied to the first word line to move to the target value and causing the first word line to discharge, is caused to be executed only once by the control logic.

4. The apparatus of claim 1, wherein the operation further comprises: Receive a first cache release command associated with at least a first latch of the page buffer; and This causes the first data to be stored in the first latch of the page buffer.

5. The apparatus of claim 4, wherein the operation further comprises: Receive a second cache release command associated with at least a second latch of the page buffer; and This causes the second data to be stored in the second latch of the page buffer.

6. The apparatus of claim 1, wherein the subset of the array is configured as a single-level cell (SLC) memory.

7. The apparatus of claim 1, wherein the first read command is to perform a first read operation on a lower page or an upper page of a plurality of cells configured as one of the following memories: a multi-level cell (MLC) memory, a three-level cell (TLC) memory, a four-level cell (QLC) memory, or a five-level cell (PLC) memory, and wherein the second read command is to perform a second read operation on the lower page or the upper page.

8. The apparatus of claim 1, wherein the first read command is a first read operation of an additional page of a plurality of cells configured as one of the following memories: a three-level cell TLC memory, a four-level cell QLC memory, or a five-level cell PLC memory, and wherein the second read command is a second read operation of the additional page.

9. An apparatus comprising: A memory cell array, comprising first word lines coupled to at least a subset of the memory cell array; as well as The control logic coupled to the first word line performs operations including the following: Access a first set of read commands to read first data from a first lower page of a first subset of a memory cell array, the memory cell array being configured as one of the following: a multi-level cell (MLC) memory, a three-level cell (TLC) memory, a four-level cell (QLC) memory, or a five-level cell (PLC) memory, wherein the first subset of the array is coupled to a word line of the array. This causes the voltage applied to the word line to move to the target value; This causes the page buffer to sense a first portion of the first data from the first bit line coupled to the first lower page, and to sense a second portion of the first data from the second bit line of the first lower page coupled to the first subset of the array. as well as This causes the voltage applied to the word line to move back to the target value.

10. The apparatus of claim 9, further comprising a queue coupled to the control logic, the queue for storing the first read command set and a second read command set consecutive in the queue with respect to the first read command set, and wherein causing the page buffer to sense the first portion and the second portion of the first data further comprises causing the page buffer to precharge the first bit line and the second bit line.

11. The apparatus of claim 9, wherein the operation further comprises: Receive a first cache release command associated with a first latch of the page buffer; This causes the first portion of the first data to be stored in the first latch; Receive a second cache release command associated with the second latch of the page buffer; as well as This causes the second portion of the first data to be stored in the second latch.

12. The apparatus of claim 9, wherein the operation further comprises: Access a second set of read commands to read second data from a second lower page of a second subset of the memory cell array; This causes the page buffer to precharge the third bit line of the second lower page of the second subset coupled to the array, and senses the first portion of the second data; This causes the page buffer to precharge the fourth bit line of the second lower page of the second subset coupled to the array and sense the second portion of the second data; as well as This causes the word line to discharge.

13. The apparatus of claim 12, wherein the operation further comprises: Receive a third cache release command associated with the latch of the page buffer; This causes the first portion of the second data to be stored in the latch; Receive a fourth cache release command associated with the latch of the page buffer; as well as This causes the second portion of the second data to be stored in the latch.

14. An apparatus comprising: A memory cell array, comprising first word lines coupled to at least a subset of the memory cell array; A page buffer includes multiple latches to cache data read from the array; as well as Control logic, coupled to the first word line and the page buffer, performs operations including the following in response to receiving a first read command from the processing device: This causes the voltage applied to the first word line to move to the target value; This causes the page buffer to sense first data from the first bit line of the first page of the subset coupled to the array; Receive from the processing device a first cache release command associated with at least a first latch of the plurality of latches; as well as In response to the first cache release command and during the recovery period of the first word line, the first data is stored in the first latch.

15. The apparatus of claim 14, wherein receiving the first cache release command is in response to a timed output of the select gate of the array.

16. The apparatus of claim 14, wherein the operation further comprises: The storage of the first data in the first latch of the page buffer is managed based on the availability of latches among the plurality of latches; as well as In response to receiving a second cache release command, the first data is transmitted to the processing device.

17. The apparatus of claim 16, wherein neither the first cache release command nor the second cache release command is a subsequent cache command received from the processing apparatus.

18. The apparatus of claim 14, wherein the first read command and the second read command are stored consecutively in a queue, and wherein the operation further comprises: Receive the second read command to read second data from the second page of the subset of the array; After the voltage applied to the first word line moves to the target value, the page buffer is caused to sense the second data from the second bit line coupled to the second page; Before receiving the first cache release command, a second cache release command associated with at least a second latch of the plurality of latches is received; as well as In response to the second cache release command and before the recovery period of the first word line, the second data is caused to be stored in the second latch of the page buffer.

19. The apparatus of claim 18, wherein the operation further comprises receiving the second cache release command in response to a timing output of the select gate of the array.

20. The apparatus of claim 18, wherein the operation further comprises: The storage of the first data in the first latch and the storage of the second data in the second latch of the page buffer are managed based on the availability of latches among the plurality of latches. as well as In response to receiving a third cache release command, the first data and the second data are transmitted to the processing device.

Images