Radiation-proof memristor synaptic circuit

Abstract

The invention discloses an anti-radiation memristor synaptic circuit, which relates to the technical field of neural network integrated circuits, and is characterized in that on the basis of a four-memristor synaptic circuit, two memristors are reserved to realize the conversion of weight polarity, and the other two memristors are replaced by invariable resistors; the nonlinear and asymmetrical influence of the four memristors on a weight updating curve is reduced; meanwhile, when the memristor synaptic circuit receives an external voltage Vin, due to the fact that the memristor M1 and the memristor M2 are in opposite polarities, under the action of the external voltage, the memristor M1 and the memristor M2 show opposite conductance change trends and are subjected to voltage division with the resistor R1 and the resistor R2 respectively, and the memristor M1 and the memristor M2 are subjected to voltage division with the resistor R1 and the resistor R2 respectively; in this way, the voltage difference between the intermediate node of the first voltage dividing branch and the intermediate node of the second voltage dividing branch is changed from a positive value to a negative value or from the negative value to the positive value, so that the weight updating function of the memristor synaptic circuit is not affected under irradiation, and the weight updating range is expanded.

Description

Technical Field

[0001] This invention relates to the field of neural network integrated circuit technology, and in particular to a radiation-resistant memristor synapse circuit. Background Technology

[0002] Synapses are the core units for information transmission and integration in biological neural networks, and their biomimetic design is key to building efficient artificial neural network hardware systems. Traditional CMOS synaptic circuits are limited by high power consumption, low integration, and volatile weights, making it difficult to meet the needs of large-scale neuromorphic computing. Memristors, with their continuously adjustable resistance, non-volatile storage, nanoscale characteristics, and synaptic-like dynamic properties, provide an ideal solution to overcome this bottleneck. The resistance value of a memristor can accurately map the synaptic connection strength, and its conductance update mechanism naturally simulates the plastic behavior of synapses.

[0003] The most important performance characteristics of memristors as synaptic units are the linearity and symmetry of their conductance update curves. Studies have found that irradiation can impair the linearity of weight updates in memristors, which in turn affects the weight update performance of memristor-based synaptic circuits. However, current memristor synaptic circuits often rely on external inverters or complex conversion modules to adjust the weight signs, leading to circuit redundancy and reduced energy efficiency. Furthermore, most current research on memristor synaptic circuits is based on simulations using the HP memristor model, but there may be significant differences between the performance of the ideal model and the actual circuit.

[0004] To address the problems existing in current memristor synaptic circuits, researchers have proposed a four-memristor bridge synaptic circuit composed of TiO2 memristors, similar to the Whitston bridge. Figure 5 As shown, the circuit consists of a four-memristor bridge circuit for weight control and a transistor differential amplifier for voltage-to-current conversion; when the input terminal V in When a positive or negative voltage pulse is applied, the resistance of memristors of different polarities will change, thereby achieving different synaptic weights. However, under different irradiation conditions, since the weight of a four-memristor synapse is expressed by the four memristors, its weight update curve exhibits nonlinearity and asymmetry during the update process. Furthermore, the linearity of the weight update will degrade under irradiation, resulting in a smaller weight update range. Summary of the Invention

[0005] This invention provides a radiation-resistant memristor synapse circuit that can solve the problems in the prior art where the weight update curve exhibits nonlinearity and asymmetry during the update process, and the linearity of the weight update degrades under irradiation, resulting in a small weight update range.

[0006] This invention provides a radiation-resistant memristor synapse circuit, including a weight control circuit and a subtractor circuit; The weight control circuit includes memristors M1 and M2, resistors R1 and R2; wherein the output terminal of memristor M1 and resistor R1 are connected in series to form a first voltage divider branch, and the output terminal of memristor M2 and resistor R2 are connected in series to form a second voltage divider branch. The input terminals of memristor M1 in the first voltage divider branch and the input terminals of memristor M2 in the second voltage divider branch are connected in parallel to receive an external voltage V. in ; The output terminal of memristor M1 is also connected to the non-inverting input terminal of the subtractor circuit, and the output terminal of memristor M2 is also connected to the inverting input terminal of the subtractor circuit. The subtractor circuit adjusts and outputs the synaptic weighting voltage V by measuring the voltage difference between the output terminals of memristor M1 and memristor M2. out .

[0007] Preferably, the subtractor circuit includes resistors R3, R4, R5, and R6, and an operational amplifier U; The non-inverting input terminal of the operational amplifier U is connected to the output terminal of the memristor M1 through resistor R3. One end of resistor R5 is connected to the output terminal of memristor M1, and the other end of resistor R5 is grounded. The inverting input of operational amplifier U is connected to the output of memristor M2 via resistor R4. One end of resistor R6 is connected to the output of memristor M2, and the other end of resistor R6 is connected to the output of operational amplifier U. The output of operational amplifier U outputs a synaptic weighting voltage V. out .

[0008] Preferably, the resistance values ​​of resistor R1 and resistor R2 are equal; The memristors M1 and M2 are made of Al-doped HfO. x / TiO x Composite structure.

[0009] Preferably, the resistors R3, R4, R5, and R6 satisfy the following formula: R3 / R4=R5 / R6=k; Where: k represents the weight amplification factor.

[0010] Preferably, the synaptic weighting voltage V out Represented as: ; in: express t The synaptic weight voltage output at any given time; express t The voltage at the output terminal of memristor M1 in the first voltage divider branch at any given moment; expresst The voltage at the output terminal of memristor M2 in the second voltage divider branch at any given moment; Indicates the irradiated environment t Time-of-flight memristor M 1. Dynamic resistance value; Indicates the irradiated environment t Time-of-use memristor M 2. Dynamic resistance value; express t The external voltage input at all times; Weight of synaptic circuits w for: ; By adjusting and The resistance relationship is used to achieve positive, negative, or zero weights.

[0011] Preferably, the implementation weight is positive, negative, or zero, including: By setting To realize the weight of synaptic circuits w It is positive; By setting To realize the weight of synaptic circuits w Zero; By setting To realize the weight of synaptic circuits w It is negative.

[0012] Preferably, the nonlinear value of the weight w of the synaptic circuit is updated. Represented as: ; in: Indicates the first n Weight values ​​under each pulse; Indicates the first n Ideal linear weight values ​​under each pulse; This represents the maximum weight value; This represents the minimum weight value.

[0013] Preferably, the nonlinear value of the weight w of the synaptic circuit is updated. Nonlinear values ​​under different irradiation environments The changes include: Nonlinear values ​​under proton irradiation From 0.109 to 0.212; Nonlinear values ​​under gamma irradiation From 0.038 to 0.091; Under neutron irradiation, nonlinear values It rose from 0.137 to 0.231.

[0014] This invention provides a radiation-resistant memristor synapse circuit, which has the following advantages compared with the prior art: This invention forms a first voltage divider branch by connecting memristor M1 and resistor R1 in series, and a second voltage divider branch by connecting memristor M2 and resistor R2 in series. The first and second voltage divider branches are connected in parallel to receive an external voltage V. in In other words, this invention, based on a four-memristor synaptic circuit, retains two memristors to achieve the weight polarity shift, and replaces the other two memristors with constant resistors, reducing the nonlinearity and asymmetry impact of the four memristors on the weight update curve; simultaneously, when the memristor synaptic circuit receives an external voltage V... in Since memristors M1 and M2 are in opposite polarities, under the influence of external voltage, they will exhibit opposite conductance trends and divide the voltage with resistors R1 and R2 respectively. This will cause the voltage difference between the intermediate nodes of the first and second voltage divider branches, i.e., the voltage between the output terminals of memristor M1 and M2 in the first and second voltage divider branches, to change from positive to negative or vice versa. This ensures that the weight update function of the memristor synapse circuit is not affected by irradiation, i.e., there will be no degradation in the linearity of the weight update, thus expanding the weight update range. Attached Figure Description

[0015] Figure 1 A schematic diagram of a single memristor synapse structure for a radiation-resistant memristor synapse circuit provided in an embodiment of the present invention; Figure 2 A single HfO of a radiation-resistant memristor synaptic circuit provided in an embodiment of the present invention x / TiO x A schematic diagram comparing the conductivity update curves and synaptic weight update curves of memristor synapses before and after proton irradiation; Figure 3 A single Al:HfO synaptic circuit for a radiation-resistant memristor provided in an embodiment of the present invention x / TiO x A schematic diagram comparing the conductivity update curves and synaptic weight update curves of memristor synapses before and after gamma irradiation. Figure 4 A single Mg:HfO ... x A schematic diagram comparing the conductivity update curves and synaptic weight update curves of memristor synapses before and after atmospheric neutron irradiation; Figure 5 A schematic diagram of a four-memristor synapse circuit for radiation-resistant memristor synapse circuit provided in an embodiment of the present invention; Figure 6 A four-HfO resistant memristor synaptic circuit provided in this embodiment of the invention x / TiO x A schematic diagram of the M1 / M2 conductance update curves and synaptic weight update curves of memristor synapses before and after proton irradiation; Figure 7 A radiation-resistant memristor synaptic circuit with four Al:HfO components is provided in an embodiment of the present invention. x / TiO x A schematic diagram of the M1 / M2 conductance update curves and synaptic weight update curves of memristor synapses before and after gamma irradiation; Figure 8 A single Mg:HfO ... x A schematic diagram of the M1 / M2 conductance update curves and synaptic weight update curves of memristor synapses before and after atmospheric neutron irradiation; Figure 9 A schematic diagram of the overall synaptic circuit structure of a radiation-resistant memristor synaptic circuit provided in an embodiment of the present invention; Figure 10 An irradiation-resistant memristor synapse circuit provided in this embodiment of the invention has an irradiation-resistant HfO. x / TiO x A schematic diagram of the M1 / M2 conductance update curves and synaptic weight update curves of memristor synapses before and after proton irradiation; Figure 11 An irradiation-resistant Al:HfO memristor synapse circuit provided in this embodiment of the invention x / TiO x A schematic diagram of the M1 / M2 conductance update curves and synaptic weight update curves of memristor synapses before and after gamma irradiation; Figure 12 An irradiation-resistant memristor synaptic circuit provided in this embodiment of the invention uses Mg:HfO. x A schematic diagram of the M1 / M2 conductance update curves and synaptic weight update curves of memristor synapses before and after atmospheric neutron irradiation. Detailed Implementation

[0016] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0017] See Figure 9 This invention provides a radiation-resistant memristor synaptic circuit. Based on an improved memristor model, this invention studies the weight update process of three classic memristor synaptic circuits under normal conditions. Then, based on an irradiated memristor model, it explores the impact of irradiation on the weight update of the synaptic circuit. Furthermore, it proposes a radiation-resistant synaptic circuit that can maintain good weight update performance under irradiation conditions. Finally, combining the image recognition performance of memristor-based artificial neural networks, the impact of irradiation on memristor artificial neural networks is studied, providing theoretical support for the development of highly biomimetic neuromorphic chips in space applications. Specific research content includes: I. The effect of irradiation on the updating of synaptic weights in a single memristor.

[0018] In neuromorphic systems constructed using memristors, information transmission between neural nodes can be achieved through single memristor synapses. This basic architecture embodies the simplest interconnection scheme. The memristor, as the core synaptic functional unit, is connected at both ends to the output end of the preneuron and the input end of the postneuron, respectively. Its dynamically adjustable conductance state characterizes the synaptic weights between neurons.

[0019] like Figure 1 As shown, the core functions of a single memristor as a synapse include weight update and data retention. Non-volatile memristors with good linearity of conductance update are ideal synaptic devices. However, when memristors are applied to space neuromorphic chips, the impact of the complex space irradiation environment on conductance update must be considered, which will directly affect the weight update function of the synapse.

[0020] Based on the single-irradiation memristor model, HfO x / TiO x Simulation studies were conducted on proton irradiation damage to single-memristor synapses, such as... Figure 2 This demonstrates that when the current neuron receives the same pulse voltage, a single HfO x / TiO x Conductivity response curves of memristor synapses before and after irradiation, and continuous weight update curves when used as a single memristor synapse.

[0021] In this study, a formula for normalized nonlinear values ​​was introduced to quantitatively describe the degree of nonlinearity of the weight update curve, expressed as: .

[0022] in: w ( n ) indicates the first n Weight values ​​under each pulse; linear w ( n ) indicates the first n Ideal linear weight values ​​under each pulse; wmax and w min This represents the maximum and minimum weight values.

[0023] It can be seen that single HfO x / TiO x Memristor synapses achieve weight updates and retention both before and after irradiation, and the synaptic weight values ​​can be modulated according to the number of pulses. However, after proton irradiation, the weight update of a single memristor synapse becomes non-linear, which prevents the weights from updating according to the initial design settings. Under proton irradiation, HfO x / TiO x The nonlinearity of the weight update of a single memristor synapse increased from 0.191 to 0.317; and correspondingly, the LTD process of a single memristor under irradiation cannot recover to the initial original conductance state, which makes the range of the weight update curve after irradiation smaller. At low weight values, the weight cannot be updated normally, thus affecting the function of the memristor neural network based on the memristor synapse.

[0024] like Figure 3 As shown, the conductivity response curves of a single Al:HfOx / TiOx memristor synapse before and after gamma irradiation are displayed when the current neuron is input with the same pulse voltage, as well as the continuous weight update curve when it is a single memristor synapse; it can be found that under gamma irradiation, the single Al:HfOx... x / TiO x The memristor synapse also achieved weight updating and retention, and maintained similar weight update curves before and after irradiation. This allows the memristor synapse to update its weights normally under gamma irradiation as designed; this is thanks to Al:HfO. x / TiO x The memristor maintains a relatively linear conductance update curve even under 1 M rad (Si) gamma irradiation, unlike the effect of proton irradiation on HfO. x / TiO x The effect of memristor synapses on the inability to return to the initial resistive state, under gamma irradiation, Al:HfO x / TiO x The linearity of weight updates in single memristor synapses only degrades slightly, Al:HfO x / TiO x The nonlinearity of weight update for single-memristor synapses increased from 0.08 to 0.195 under gamma irradiation, while still maintaining normal updates for synaptic weights between 0 and 1, demonstrating the performance of Al:HfO-based synapses. x / TiO x The single memristor synapse of a memristor has a certain degree of radiation resistance.

[0025] like Figure 4As shown, this illustrates the effect of the same pulse voltage input to a single Mg:HfO neuron. x The conductance response curves of the memristor synapse before and after neutron irradiation, and the continuous weight update curve when it is a single memristor synapse; it can be found that under atmospheric neutron irradiation, the single Mg:HfO x Memristor synapses also achieve weight updates and retention, but due to Mg:HfO x Memristor at 2.7 × 10 11 n / cm 2 Under atmospheric neutron flux, the linearity of conductivity renewal in the LTD process deteriorates, leading to changes in the Mg:HfO content. x The weight update curve of a single memristor synapse in a memristor becomes more nonlinear, and Mg:HfO x Memristors also exhibited a failure to return to their initial conductance state under atmospheric neutron irradiation, causing the single Mg:HfOx memristor synapse to exhibit the same behavior as that of a single HfOx / TiO2 under proton irradiation. x Memristor synapses also fail to update weights normally at low weight values; before and after atmospheric neutron irradiation, Mg:HfO x The weight update nonlinearity of single memristor synapses is at a high level, among which Mg:HfO x The weight update nonlinearity of a single memristor synapse under atmospheric neutron irradiation increased from 0.174 to 0.314, compared to a single HfO synapse. x / TiO x Changes in memristor synapses under proton irradiation and single Al:HfO x / TiO x Changes in memristor synapses under gamma irradiation, and Mg:HfO under atmospheric neutron irradiation. x The weight update curve of a single memristor synapse has more pronounced nonlinear characteristics, which may adversely affect the performance of memristor neural networks based on this memristor synapse.

[0026] In summary, although synaptic circuits composed of a single memristor have advantages such as fewer memristors, simpler structure, smaller area, and lower power consumption, there are certain limitations to using a single memristor to simulate a synapse. Since the conductance of memristors is always positive, only positive synaptic weights can be achieved. This means that when a single memristor synapse is used as network hardware, additional circuit design is required to achieve negative and zero weights.

[0027] II. The effect of irradiation on the synaptic weight update of a quaternary memristor.

[0028] To address the limitation that single-memristor synapses can only simulate positive weights, researchers proposed a four-memristor bridge synapse circuit in 2011, similar to the Whitstone bridge, composed of TiO2 memristors. The structure is as follows: Figure 5As shown; the circuit consists of a four-megristor bridge circuit for weight control and a transistor differential amplifier for voltage-to-current conversion; when the input terminal V in When a positive or negative voltage pulse is applied, the resistance of memristors of different polarities will change, thereby achieving different synaptic weights.

[0029] Specifically, when the excitation voltage V in When applied to the input terminals, the resistance of the memristors changes according to their polarity. When a positive voltage is applied, the memristor values ​​of M1 and M4 (forward bias) decrease, while the memristor values ​​of M2 and M3 (reverse bias) increase. At this time, the voltage at point A will definitely be higher than that at point B, and the circuit will output a positive voltage V. out A positive synaptic weight is obtained when a reverse voltage is applied. Conversely, when a reverse voltage is applied, the memristor values ​​of M1 and M4 (positive polarity bias) increase, and the memristor values ​​of M2 and M3 (reverse polarity bias) decrease. At this time, the voltage at point A must be lower than that at point B, resulting in a negative synaptic weight.

[0030] The voltage of each memristor is expressed as follows: .

[0031] .

[0032] .

[0033] .

[0034] According to the voltage divider law, V can be obtained. out and V in The relationship is represented as: .

[0035] The four-memristor synapse circuit transforms the synaptic weighting from the resistance of a single memristor synapse into the voltage difference between points A and B and V. in The ratio is used to achieve positive, negative, and zero weights; therefore, the weight w is expressed as: .

[0036] when When w is positive, w is a positive weight value; conversely, when w is negative, w is a negative weight value. When w is a negative weight value, When w represents the zero weight value, it can be expressed by the formula: .

[0037] The above analysis shows that by applying an external voltage excitation to the four-memristor synapse circuit, the weight value w can be changed by relying on the resistance change of memristors with different polarities, effectively achieving positive, negative, and zero weights. Furthermore, since the resistance change of most memristors has a certain degree of symmetry, the weight update of the four-memristor synapse is relatively linear. However, when the resistance change of the memristor becomes nonlinear under irradiation, the weight update curve of the four-memristor synapse will also be affected accordingly. To verify this hypothesis, this invention established a four-memristor synapse circuit in SPICE software and placed it into the memristor model under normal conditions and the memristor model under irradiation to observe the effect of irradiation on the weight update curve of the four-memristor synapse circuit.

[0038] like Figure 6 As shown, this is based on HfO under proton irradiation. x / TiO x The conductance update curve and synapse weight update curve of the four memristor synapse circuit are shown. Here, M1 and M4 are set to high resistance state, and M2 and M3 are set to low resistance state. Positive and negative voltage pulses with an amplitude of 2V and a pulse width of 10ns are applied to test the weight update curve of the four memristor synapses. It can be seen that M1 and M4 are in opposite resistance change processes to M2 and M3. This allows the four memristor synapses under normal conditions to achieve complete positive and negative zero weights. Furthermore, benefiting from the symmetry of the memristor conductance update, the synapse weight update curve is also relatively linear.

[0039] After proton irradiation, the conductance update curves of the four memristors decrease linearly, corresponding to a non-linear weight update curve for the synaptic circuit, and HfO... x / TiO x Memristors exhibit a phenomenon where the conductance update process fails to return to the initial resistance state under proton irradiation, resulting in a region with a small voltage response at the end of the weight update. However, compared to a single memristor synapse circuit, this four-memristor synapse circuit demonstrates better device nonlinearity tolerance. The change in the synapse weight update curve before and after irradiation is much smaller than that of a single memristor synapse, and the weight update nonlinearity value increases from 0.15 to 0.22.

[0040] like Figure 7 As shown, it is based on Al:HfO x / TiO x The weight update curves of the four memristor synapses and the conductance update curves of each memristor under gamma irradiation show that under gamma irradiation, the four Al:HfO x / TiO x Memristor synapses also achieve weight updating and retention. This is because a single memristor can maintain good linearity of conductance update under gamma irradiation, and the change in the device's conductance update curve before and after irradiation is minimal. Therefore, based on Al:HfO... x / TiOx The four memristor synapses of the memristor maintained similar weight update curves before and after gamma irradiation. Although the linearity of the weight update curve decreased under gamma irradiation, with the nonlinearity increasing from 0.09 to 0.19, it still remained at a good level. The memristor synapses could update their weights normally under gamma irradiation as designed, indicating that the Al:HfO-based... x / TiO x The four memristor synapses of a memristor have certain radiation resistance characteristics.

[0041] like Figure 8 As shown, it is based on Mg:HfO x The weight update curves of the four memristor synapses and the conductance update curves of each memristor under atmospheric neutron irradiation show that under atmospheric neutron irradiation, the four Mg:HfO x Memristor synapses also achieve weight updates and retention, but due to Mg:HfO x The nonlinearity and asymmetry of the memristor's LTD / LTP conductance update process exacerbate the nonlinearity of synaptic weight updates, leading to the four Mg:HfO x The weighting curves of memristor synapses exhibit asymmetry; simultaneously, due to Mg:HfO x Memristors cannot return to their initial conductance state after atmospheric neutron irradiation, making them based on Mg:HfO... x Memristor synapses and mono-Mg:HfO x Memristor synapses also exhibited a narrowing of their weight range; tetraMg:HfO x The nonlinearity of the weight update of memristor synapses increased from 0.191 before irradiation to 0.245 after irradiation.

[0042] Since the weights of a quad memristor synapse are expressed by four memristors, it achieves zero and negative weights, which are not possible with a single memristor synapse. Furthermore, it can use two memristors of opposite polarities to offset certain non-idealities. It can be seen that the memristor synapse circuit is an effective means to avoid the impact of the non-idealities of a single device on the performance changes of the synapse in the network. However, the drawbacks of the quad memristor synapse are also obvious. The range of weight updates is very small, only ±0.1. Therefore, when applying the quad memristor synapse, it is necessary to consider the network's limitation on the range of synapse weights, or design corresponding peripheral circuits to amplify the weights, in order to use it normally in a memristor neural network.

[0043] III. Design of Radiation-Resistant Synaptic Circuits.

[0044] The four-memristor synapse circuit achieves positive and negative zero weights compared to the single-memristor synapse. However, because its weights are represented by four memristors, the linearity of the weight update curve is not high, the weight update range is small, and the linearity of the weight update degrades under irradiation. Therefore, this invention optimizes the four-memristor synapse circuit by retaining two memristors to achieve the weight polarity transition and replacing two of the memristors with constant resistors. This reduces the nonlinear effect of the four memristors on the weight update curve while also reducing the impact of irradiation on the synapse weight update. The radiation-resistant synapse circuit structure is as follows: Figure 9 As shown.

[0045] The synaptic circuit consists of two memristors M1 and M2 and two resistors R1 and R2 forming the weight control section. The four resistors on the right and the operational amplifier form a subtractor used to calculate the voltage difference between node A and node B. When the synapse receives an applied voltage V... in Since M1 and M2 are of opposite polarities, under positive excitation (negative excitation) V in Under the influence of irradiation, M1 and M2 will exhibit opposite conductance change trends and will divide the voltage with R1 and R2 respectively. This will cause the voltage difference between points A and B to change from a positive value to a negative value (from negative to positive). Furthermore, adding a constant resistor reduces the impact of the memristor's changes under irradiation on the overall synaptic circuit output, ensuring that the synaptic circuit's weight update function remains unaffected while maintaining high accuracy. out The change can be represented as: .

[0046] Therefore, the weight w of the synaptic circuit can be expressed as: .

[0047] Here, if we make R1 and R2 equal, we can easily derive the memristor states when the weights are positive, negative, and zero, that is: .

[0048] This allows for the representation of positive, negative, and zero weights using two memristors, while simultaneously incorporating two resistor values ​​and the memristor value to jointly represent the weight value. This reduces the impact of memristor value variations under irradiation on the synaptic circuit weights. It can be seen that this circuit exhibits better performance in reducing the requirements for precision components, overcoming the influence of the external environment, and improving the accuracy of synaptic weights. Furthermore, by adjusting the ratios of resistors R3, R4 and R5, R6 in the subtractor, and utilizing the virtual short-circuit and virtual open-circuit characteristics of the operational amplifier, V can be adjusted. out To the extent that is suitable for the next synapse or neuron.

[0049] Among them, resistors R3, R4, R5, and R6 satisfy the following equation: R3 / R4=R5 / R6=k.

[0050] Where: k represents the weight amplification factor.

[0051] like Figure 10 As shown, this demonstrates the radiation resistance of HfO before and after proton irradiation. x / TiO x The curves showing the changes in M1 / M2 memristor conductance and synaptic weights of the memristor synaptic circuit with pulses are presented. It can be seen that although the components in the radiation-resistant synaptic circuit also change under irradiation, the weights of the entire synaptic circuit are determined by the memristor and the constant resistance through the adjustment of the resistors in the circuit. The weight updates do not change significantly under irradiation, allowing the synapses in the network to update their weights normally, thus achieving the radiation resistance effect. Simulation results show that the NL of weight updates for the radiation-resistant memristor synaptic circuit before and after irradiation are 0.109 and 0.212, respectively, and the NL of weight updates for a single memristor synapse before and after irradiation are 0.191 and 0.317, respectively. (The last sentence appears to be incomplete and possibly refers to a different circuit.) x / TiO x The weight update NL of the memristor synapse was 0.15 and 0.22, respectively. The nonlinearity of the weight update of the improved synapse circuit before and after irradiation was reduced by 42% and 33% compared with the single memristor synapse, and by 27% and 3.6% compared with the four memristor synapse. The large nonlinearity of the weight update curve may lead to inaccurate weight update, which will have an important impact on the performance of the memristor neural network based on memristor synapse.

[0052] like Figure 11 As shown, this demonstrates the radiation resistance of Al:HfO before and after gamma irradiation. x / TiO x The curves showing the changes in M1 / M2 memristor conductance and synaptic weight as a function of pulses in a memristor synaptic circuit; it can be seen that due to the single Al:HfO x / TiO x Memristors maintain good linearity of conductance updates under gamma irradiation. This means that the memristors in the radiation-resistant synaptic circuit remain almost unchanged under irradiation. Furthermore, through the adjustment of resistors in the circuit, the weights of the entire synaptic circuit are jointly determined by the memristors and the constant resistors. During the second weight update, the weight update curve remains almost identical to that before irradiation. This allows the synapses in the network to update their weights normally, thus achieving the radiation resistance effect. Simulation results show that the NL of weight updates for the radiation-resistant memristor synaptic circuit before and after irradiation are 0.038 and 0.091, respectively. The NL of weight updates for a single memristor synapse before and after irradiation are 0.08 and 0.195, respectively. (The last sentence appears to be incomplete and possibly refers to a different circuit.) x / TiO xThe weight update NL of the memristor synapse was 0.09 and 0.19, respectively; the weight update nonlinearity of the improved synapse circuit before and after irradiation was reduced by 52% and 53% compared to a single memristor synapse, and by 57% and 52% compared to a four-memristor synapse, respectively, thanks to Al:HfO. x / TiO x Memristor synapses exhibit small nonlinear values ​​both before and after irradiation, showing a significant reduction in nonlinearity compared to single and quadruple memristor synapses. However, this is actually based on Al:HfO. x / TiO x The worst nonlinearity value of the memristor's synaptic weight update is only 0.195, indicating that even if the impact of device nonlinearity on synaptic weight update can be reduced by designing radiation-resistant circuits, a more effective approach is to optimize the radiation resistance of individual memristors by starting with the materials, fabrication, and structural design of the memristor itself, in order to achieve radiation resistance of the synapse.

[0053] like Figure 12 As shown, this demonstrates the radiation resistance of Mg:HfO before and after atmospheric neutron irradiation. x The curves showing the changes in M1 / M2 memristor conductance and synaptic weight as a function of pulses in a memristor synaptic circuit; it can be seen that due to the single Mg:HfO x The linearity of conductance updates of memristors before and after atmospheric neutron irradiation is not good. This results in significant nonlinearity in the conductance update curve of memristors in radiation-resistant synaptic circuits under irradiation. However, after adjusting the resistors in the circuit, the weights of the entire synaptic circuit are jointly determined by the memristors and the constant resistors. Although the weight update curve still has a large nonlinearity, it maintains a similar weight update curve as before irradiation and does not deteriorate more significantly under irradiation. This allows the synapses in the network to update their weights normally, thus achieving the radiation resistance effect. Simulation results show that the NL of weight updates for the radiation-resistant memristor synaptic circuit before and after irradiation are 0.137 and 0.231, respectively, and the NL of weight updates for a single memristor synapse before and after irradiation are 0.174 and 0.314, respectively. x The weight update NL of the memristor synapse were 0.191 and 0.245, respectively; the weight update nonlinearity of the improved synapse circuit before and after irradiation was reduced by 21% and 26% compared to a single memristor synapse, and by 27% and 5.6% compared to a four-memristor synapse, respectively, due to Mg:HfO x Memristors exhibit high nonlinearity both before and after irradiation, and are radiation resistant to Mg:HfO. x The nonlinearity of weight updates in memristor synapses increased by 0.1 under atmospheric neutron irradiation, which will have a significant impact on the performance of memristor neural networks.

[0054] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A radiation-resistant memristor synapse circuit, characterized in that, include: Weight control circuit and subtractor circuit; The weight control circuit includes memristors M1 and M2, resistors R1 and R2; wherein the output terminal of memristor M1 and resistor R1 are connected in series to form a first voltage divider branch, and the output terminal of memristor M2 and resistor R2 are connected in series to form a second voltage divider branch. The input terminals of memristor M1 in the first voltage divider branch and the input terminals of memristor M2 in the second voltage divider branch are connected in parallel to receive an external voltage V. in ; The output terminal of memristor M1 is also connected to the non-inverting input terminal of the subtractor circuit, and the output terminal of memristor M2 is also connected to the inverting input terminal of the subtractor circuit. The subtractor circuit adjusts and outputs the synaptic weighting voltage V by measuring the voltage difference between the output terminals of memristor M1 and memristor M2. out .

2. The radiation-resistant memristor synapse circuit according to claim 1, characterized in that, The subtractor circuit includes resistors R3, R4, R5, and R6, and an operational amplifier U; The non-inverting input terminal of the operational amplifier U is connected to the output terminal of the memristor M1 through resistor R3. One end of resistor R5 is connected to the output terminal of memristor M1, and the other end of resistor R5 is grounded. The inverting input of the operational amplifier U is connected to the output of the memristor M2 via resistor R4. One end of resistor R6 is connected to the output of the memristor M2, and the other end of resistor R6 is connected to the output of the operational amplifier U. The output of the operational amplifier U outputs a synaptic weighting voltage V. out .

3. The radiation-resistant memristor synapse circuit according to claim 1, characterized in that, The resistance values ​​of resistors R1 and R2 are equal; The memristors M1 and M2 are made of Al-doped HfO. x / TiO x Composite structure.

4. The radiation-resistant memristor synapse circuit according to claim 2, characterized in that, The resistors R3, R4, R5, and R6 satisfy the following equation: R3 / R4=R5 / R6=k; Where: k represents the weight amplification factor.

5. The radiation-resistant memristor synapse circuit according to claim 1, characterized in that, The synaptic weight voltage V out Represented as: ； in: express t The synaptic weight voltage output at any given time; express t The voltage at the output terminal of memristor M1 in the first voltage divider branch at any given moment; express t The voltage at the output terminal of memristor M2 in the second voltage divider branch at any given moment; Indicates the irradiated environment t Time-of-use memristor M 1. Dynamic resistance value; Indicates the irradiated environment t Time-of-use memristor M 2. Dynamic resistance value; express t The external voltage input at all times; Weight of synaptic circuits w for: ； By adjusting and The resistance relationship is used to achieve positive, negative, or zero weights.

6. The radiation-resistant memristor synapse circuit according to claim 5, characterized in that, The implementation weights being positive, negative, or zero include: By setting To realize the weight of synaptic circuits w It is positive; By setting To realize the weight of synaptic circuits w Zero; By setting To realize the weight of synaptic circuits w It is negative.

7. The radiation-resistant memristor synapse circuit according to claim 6, characterized in that, The nonlinear value of the weight w updated in the synaptic circuit. Represented as: ； in: Indicates the first n Weight values ​​under each pulse; Indicates the first n Ideal linear weight values ​​under each pulse; This represents the maximum weight value; This represents the minimum weight value.

8. The radiation-resistant memristor synapse circuit according to claim 7, characterized in that, The nonlinear value of the weight w updated in the synaptic circuit. Nonlinear values ​​under different irradiation environments The changes include: Nonlinear values ​​under proton irradiation From 0.109 to 0.212; Nonlinear values ​​under gamma irradiation From 0.038 to 0.091; Under neutron irradiation, nonlinear values It rose from 0.137 to 0.231.

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