Preparation method of through hole and semiconductor structure
By using anisotropic filling material to fill the groove and etching to form through holes, the problems of sidewall ripples and complex processes in high aspect ratio through holes in the prior art are solved, and the effect of smooth inner surface of through holes and simplified process is achieved.
Patent Information
- Application Number
- CN202510951771.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-10
- Publication Date
- 2025-10-31
AI Technical Summary
In existing technologies, when forming high aspect ratio through holes by alternating etching and passivation, periodic ripples will form on the sidewalls, affecting the smoothness of the inner surface of the through hole and complicating the process.
An anisotropic filling material is used to fill the groove to form a filling structure, and through holes are formed in the groove by etching. By utilizing the anisotropic properties of the filling material, the etching rate varies in different directions, forming through holes with a high aspect ratio.
The resulting through-hole has a smooth inner surface, the process is simple, it avoids the occurrence of periodic ripples, and it has a wide range of applications.
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Figure CN120878635A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of microelectronics, and in particular to a method for fabricating a through-hole and a semiconductor structure. Background Technology
[0002] Through Silicon Via (TSV) technology is a key technology in 3D integration and advanced packaging. It enables vertical interconnects between chips by etching deep holes in silicon wafers and filling them with conductive materials (such as copper). As semiconductor device sizes shrink and performance demands increase, traditional planar interconnects face problems such as wiring delays and increased power consumption. TSV technology provides solutions for applications such as high-performance computing, memory, and sensors by shortening interconnect lengths, increasing bandwidth, and reducing power consumption, becoming one of the important paths to continue Moore's Law.
[0003] However, in existing technologies, to fabricate high aspect ratio microstructures, such as microelectromechanical systems (MEMS) devices, TSVs, and optical components, alternating etching and passivation steps are typically employed. However, this method results in periodic ripples on the sidewalls of high aspect ratio vias, affecting the smoothness of the via's inner surface, and also complicates the process. Therefore, there is an urgent need for a method to create high aspect ratio vias that improves the smoothness of the via's inner surface while simplifying the fabrication process.
[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for preparing vias and a semiconductor structure to solve the problem that the sidewalls of vias with high aspect ratio formed by alternating etching and passivation in the prior art will form periodic ripples, affecting the smoothness of the inner surface of the via, and the process is relatively complicated.
[0006] To achieve the above and other related objectives, this application provides a method for preparing a through-hole, the method comprising:
[0007] Provide substrate;
[0008] Remove a portion of the substrate to form at least one groove on the upper surface of the substrate;
[0009] The groove is filled with an anisotropic filling material to form a filling structure;
[0010] The filling structure is etched to form the through hole in the filling structure within the groove.
[0011] In one embodiment, the aspect ratio of the through hole ranges from 5:1 to 100:1.
[0012] In one embodiment, the filler material includes at least one of polyimide, silicon dioxide, silicon nitride, and benzocyclobutene.
[0013] In one embodiment, before filling the groove with an anisotropic filling material, the method further includes:
[0014] An etching stop layer is formed at the bottom of the groove.
[0015] In one embodiment, after forming the through hole in the groove, the method further includes:
[0016] The through-hole is filled with a conductive material.
[0017] In one embodiment, the filling structure fills the groove and covers the substrate; after the through-hole is filled with the conductive material, the conductive material and the filling structure located on the surface of the substrate are removed by a grinding process.
[0018] In one embodiment, the method includes at least one of the following features:
[0019] The depth of the groove is 10 micrometers to 100 micrometers; and / or,
[0020] The width of the groove is 30 micrometers to 200 micrometers.
[0021] In one embodiment, the method includes at least one of the following features:
[0022] The depth of the through-hole is 10 micrometers to 100 micrometers; and / or,
[0023] The width of the through hole is 2 micrometers to 20 micrometers.
[0024] In one embodiment, the fabrication method further includes: thinning the substrate from the back side of the substrate until the via is exposed from the back side of the substrate.
[0025] Secondly, this application also provides a semiconductor structure, which is prepared by the via preparation method described in any one of the embodiments of this application.
[0026] As described above, the via fabrication method and semiconductor structure of this application have the following beneficial effects:
[0027] The via fabrication method and semiconductor structure of this application involve providing a substrate, removing a portion of the substrate, forming at least one groove on the upper surface of the substrate, filling the groove with an anisotropic filling material to form a filling structure, etching the filling structure, and forming a via within the filling structure in the groove. Because the filling material is anisotropic, some of its chemical and physical properties change with the etching direction, resulting in differences in etching in different directions. Therefore, during the etching process to form the via, the etching rate towards the via depth is greater than the etching rate towards the via width, thus enabling the formation of vias with high aspect ratios. Compared to existing via fabrication methods that use alternating etching and passivation, this application avoids periodic ripples caused by process alternation, resulting in smooth inner surfaces of the vias and a simpler process. Attached Figure Description
[0028] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.
[0029] Figure 1 This is a schematic flowchart of a method for preparing a through hole provided in one embodiment;
[0030] Figure 2 This is a schematic diagram of the structure obtained in step S102 of the through-hole preparation method provided in one embodiment;
[0031] Figure 3 This is a schematic diagram of the structure obtained in step S104 of the through-hole preparation method provided in one embodiment;
[0032] Figure 4 This is a schematic diagram of the structure obtained in step S106 of the through-hole preparation method provided in one embodiment;
[0033] Figure 5 This is a schematic diagram of the structure obtained in step S108 of the through-hole preparation method provided in one embodiment;
[0034] Figure 6 This is a schematic diagram of the structure of the conductive material provided in one embodiment;
[0035] Figure 7 This is a schematic diagram of the through hole provided in one embodiment;
[0036] Figure 8 This is a schematic diagram of the structure of the conductive material provided in another embodiment;
[0037] Figure 9This is a schematic diagram of the structure of the conductive material provided in another embodiment;
[0038] Figure 10 This is a schematic diagram of the structure of the first functional layer provided in one embodiment;
[0039] Figure 11 This is a schematic diagram of the substrate after thinning in one embodiment;
[0040] Figure 12 This is a schematic diagram of the structure of the second functional layer provided in one embodiment.
[0041] Component designation explanation
[0042] 10 Substrates
[0043] 20 grooves
[0044] 30 Filling Structure
[0045] 40 through hole
[0046] 50 Conductive materials
[0047] 601 First pad
[0048] 602 First Functional Layer
[0049] 603 First protective layer
[0050] 701 Second Pad
[0051] 702 Second Functional Layer
[0052] 703 Second Protective Layer
[0053] Steps S102~S108 Detailed Implementation
[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0055] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0056] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0059] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0061] As mentioned in the background section, Through Silicon Via (TSV) technology is a key technology in 3D integration and advanced packaging. It achieves vertical interconnects between chips by etching deep holes in silicon wafers and filling them with conductive materials (such as copper). With the shrinking size of semiconductor devices and the increasing performance requirements, traditional planar interconnects face problems such as wiring delay and increased power consumption. TSV technology provides solutions for applications such as high-performance computing, memory, and sensors by shortening interconnect length, increasing bandwidth, and reducing power consumption, becoming one of the important paths to continue Moore's Law.
[0062] However, in existing technologies, to fabricate microstructures with high aspect ratios, such as microelectromechanical systems (MEMS) devices, TSVs, and optical components, alternating etching and passivation steps are typically employed. During the passivation stage, C4F8 is decomposed to generate fluorinated polymers (such as CF2), which are deposited on the sidewalls and bottom to form passivation layers, protecting the sidewalls from lateral etching. During the etching stage, SF6 is decomposed to generate fluoride ions (F-). These vertically incident ions bombard the bottom silicon surface, removing material through a chemical reaction (Si + 4F- → SiF4↑). Simultaneously, some ions may laterally sputter the passivation layer on the sidewalls. The dynamic balance between passivation layer deposition and etching is difficult to fully control. If the passivation layer coverage on the sidewalls is uneven or the lateral component of ions is too high during the etching stage, the sidewalls will be locally etched in each cycle, forming periodic undulations. This results in periodic ripples on the sidewalls of the high aspect ratio vias, affecting the smoothness of the via's inner surface and complicating the process. Therefore, there is an urgent need to provide a method for creating high aspect ratio through holes that can improve the smoothness of the inner surface of the through hole and has a simple manufacturing process.
[0063] For the reasons mentioned above, please refer to Figure 1 This application provides a method for preparing a through hole, including steps S102-S108.
[0064] Step S102: Provide a substrate.
[0065] For example, please refer to Figure 2 The substrate 10 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 10 should not limit the scope of this disclosure.
[0066] Step S104: Remove part of the substrate and form at least one groove on the upper surface of the substrate.
[0067] For example, please refer to Figure 3A portion of the substrate 10 is removed, and at least one groove 20 is formed on the upper surface of the substrate 10. This process may include dry etching or wet etching. Dry etching may include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP); wet etching may include any one of isotropic etching or anisotropic etching. Furthermore, the number of grooves 20 is related to the positional distribution of vias in the final device, and the number of grooves 20 can be set according to actual needs; no specific limitation is imposed here.
[0068] Step S106: Fill the groove with an anisotropic filling material to form a filling structure.
[0069] For example, please refer to Figure 4 Anisotropic filling materials can be used to fill the grooves and cover the upper surface of the substrate 10. Then, wet etching, dry etching, chemical mechanical polishing, or planar etching can be used to planarize the filling material along the thickness direction to remove the filling material on the surface of the substrate 10 and form the filling structure 30.
[0070] As an example, the filling process for filling grooves can be determined based on the filling material. For example, the process of filling grooves with filling materials may include one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and Spin-on Dielectric (SOD).
[0071] Step S108: Etch the filling structure to form a through hole in the filling structure within the groove.
[0072] Please refer to the following: Figure 5 The via 40 penetrates the filling structure 30. As an example, the filling structure 30 can be etched using either a dry etching process or a wet etching process. The dry etching process can include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP); the wet etching process can include any one of isotropic etching or anisotropic etching.
[0073] As an example, multiple through holes 40 can be formed in a groove, and the number of through holes 40 is related to the distribution of through hole positions in the final formed device.
[0074] In the above embodiments, by providing a substrate, removing a portion of the substrate, forming at least one groove on the upper surface of the substrate, and then filling the groove with an anisotropic filling material to form a filling structure, the filling structure is etched to form a via within the filling structure in the groove. Since the filling material is anisotropic, some of its chemical and physical properties change with the etching direction, resulting in differences in etching in different directions. Therefore, during the etching of the filling structure to form a via, the etching rate towards the via depth is greater than the etching rate towards the via width, thereby forming a via with a high aspect ratio. Compared to existing via fabrication methods that use alternating etching and passivation, this application avoids periodic ripples caused by process alternation, resulting in a smooth inner surface of the via and a simpler process.
[0075] In some embodiments, the aspect ratio of the through hole ranges from 5:1 to 100:1.
[0076] As an example, the aspect ratio of a through hole can include 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, 50:1, 55:1, 60:1, 65:1, 70:1, 75:1, 80:1, 85:1, 90:1, 95:1, 100:1, etc.
[0077] In the above embodiments, the depth-to-width ratio of the through hole formed by this application has a wide range of applications. In other embodiments, the depth-to-width ratio of the through hole may also include 1:1, 2:1, 3:1, 4:1, etc. This application does not impose specific limitations on the depth-to-width ratio of the through hole.
[0078] In some embodiments, the filler material includes at least one of polyimide, silicon dioxide, silicon nitride, and benzocyclobutene.
[0079] As an example, the filler material may include any one of polyimide, silicon dioxide, silicon nitride, and styrene; or, the filler material may include any two of polyimide, silicon dioxide, silicon nitride, and styrene, and different filler materials may be stacked along the thickness direction of the filler structure; the filler material may include any three of polyimide, silicon dioxide, silicon nitride, and styrene, and different filler materials may be stacked along the thickness direction of the filler structure; the filler material may include a combination of polyimide, silicon dioxide, silicon nitride, and styrene, and the polyimide, silicon dioxide, silicon nitride, and styrene are stacked sequentially along the thickness direction of the filler structure.
[0080] In the above embodiments, polyimide, silicon dioxide, silicon nitride, and styrene-cyclobutene possess high insulation, low dielectric constant, and good process compatibility. By including polyimide, silicon dioxide, silicon nitride, and styrene-cyclobutene as the filling material, not only can high aspect ratio vias be formed, resulting in a smooth inner surface of the vias, but the dielectric properties of the semiconductor structure including the filling structure are not affected, ensuring normal device operation. Furthermore, since the filling material is an insulating material, no insulating layer needs to be deposited after etching the vias, reducing process complexity.
[0081] In some embodiments, the depth of the groove is 10 micrometers to 100 micrometers.
[0082] As an example, the depth of the groove is 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, etc.
[0083] In some embodiments, the width of the groove is 30 micrometers to 200 micrometers.
[0084] As an example, the width of the groove is 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, 140 micrometers, 150 micrometers, 160 micrometers, 170 micrometers, 180 micrometers, 190 micrometers, 200 micrometers, etc.
[0085] In some embodiments, the depth of the via is 10 micrometers to 100 micrometers.
[0086] As an example, the depth of the vias is 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, etc.
[0087] In some embodiments, the width of the via is 2 micrometers to 20 micrometers.
[0088] As an example, the width of the via is 2 micrometers, 4 micrometers, 6 micrometers, 8 micrometers, 10 micrometers, 12 micrometers, 14 micrometers, 16 micrometers, 18 micrometers, 20 micrometers, etc.
[0089] In some embodiments, before filling the groove with an anisotropic filling material, step S106 further includes the step of forming an etching stop layer at the bottom of the groove.
[0090] As an example, when the filler material is silicon dioxide, the material of the etch stop layer may include silicon nitride, silicon oxynitride, etc.; when the filler material is silicon nitride, the etch stop layer may include silicon dioxide, metal materials, etc.; when the filler material includes polyimide, styrene, etc., the material of the etch stop layer may include silicon dioxide, silicon nitride, etc.
[0091] In the above embodiments, by forming an etching stop layer at the bottom of the groove before filling the groove with an anisotropic filling material, the etching of the via can be stopped on the etching stop layer, thus avoiding over-etching and damage to the substrate.
[0092] In some embodiments, the filler material has a high etchability selectivity to the substrate.
[0093] In the above embodiments, by making the filling material and the substrate have a high etching selectivity, the etching of the via is stopped at the contact surface between the filling structure and the substrate, avoiding the use of an etch stop layer, thus simplifying the structure and fabrication process of the semiconductor device.
[0094] In some embodiments, after forming a through hole in the groove, step S108 further includes the step of filling the through hole with a conductive material.
[0095] For example, please refer to Figure 6 The conductive material 50 may include metals such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).
[0096] In some embodiments, please refer to Figures 7-9 The filling structure 30 fills the groove and covers the substrate 10; after filling the through hole 40 with conductive material 50, the conductive material 50 and the filling structure 30 located on the surface of the substrate 10 are removed by a grinding process.
[0097] In the above embodiments, by covering the substrate with the filling structure, the conductive material is prevented from directly contacting the substrate when filling the vias with conductive material, thus avoiding substrate contamination.
[0098] In some embodiments, please refer to Figure 10 After removing the conductive material 50 and filling structure on the substrate surface by a grinding process, the method further includes the step of forming a first functional layer 602 on the front side of the substrate 10.
[0099] As an example, the first functional layer 602 is connected to the via through the first pad 601, and the first functional layer 602 is also covered with a first protective layer 603.
[0100] In the above embodiments, after removing the conductive material and filling structure on the substrate surface, a front-side process can be performed on the front side of the substrate to form a first functional layer. The specific structure of the first functional layer can be set according to actual needs.
[0101] In some embodiments, please refer to Figure 11The method for preparing the via also includes the step of thinning the substrate 10 from the back side of the substrate until the via is exposed from the back side of the substrate 10.
[0102] For example, please refer to Figure 12 After exposing the vias on the back side of the substrate 10, the method further includes the step of forming a second functional layer 702 on the back side of the substrate.
[0103] As an example, the second functional layer 702 is connected to the via via through the second pad 701, and the second functional layer 702 is also covered by a second protective layer 703. The specific structure of the second functional layer 702 can be set according to actual needs.
[0104] In some embodiments, this application also provides a semiconductor structure, including: a substrate, a groove, a filling structure, and a through-hole; wherein the groove is located on the upper surface of the substrate; the filling structure fills the groove; wherein the filling material of the filling structure is anisotropic; and the through-hole penetrates the filling structure.
[0105] In some embodiments, the aspect ratio of the through hole ranges from 5:1 to 100:1.
[0106] In some embodiments, the filler material includes at least one of polyimide, silicon dioxide, silicon nitride, and benzocyclobutene.
[0107] In some embodiments, the semiconductor structure further includes an etch stop layer located at the bottom of the groove.
[0108] In some embodiments, the depth of the groove is 10 micrometers to 100 micrometers.
[0109] As an example, the depth of the groove is 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, etc.
[0110] In some embodiments, the width of the groove is 30 micrometers to 200 micrometers.
[0111] As an example, the width of the groove is 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, 140 micrometers, 150 micrometers, 160 micrometers, 170 micrometers, 180 micrometers, 190 micrometers, 200 micrometers, etc.
[0112] In some embodiments, the depth of the via is 10 micrometers to 100 micrometers.
[0113] As an example, the depth of the vias is 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, etc.
[0114] In some embodiments, the width of the via is 2 micrometers to 20 micrometers.
[0115] As an example, the width of the via is 2 micrometers, 4 micrometers, 6 micrometers, 8 micrometers, 10 micrometers, 12 micrometers, 14 micrometers, 16 micrometers, 18 micrometers, 20 micrometers, etc.
[0116] In summary, this application provides a substrate, removes a portion of the substrate, forms at least one groove on the upper surface of the substrate, then fills the groove with an anisotropic filling material to form a filled structure, and etches the filled structure to form a via within the groove. Because the filling material is anisotropic, some of its chemical and physical properties change with the etching direction, resulting in differences in etching in different directions. Therefore, during the etching process to form the via, the etching rate towards the via depth is greater than the etching rate towards the via width, thus enabling the formation of vias with high aspect ratios. Compared to existing via fabrication methods that use alternating etching and passivation, which avoid periodic ripples due to process alternation, the vias formed in this application have smooth inner surfaces and a simpler process. Therefore, this application effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.
[0117] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a through hole, characterized in that, The method includes: Provide substrate; Remove a portion of the substrate to form at least one groove on the upper surface of the substrate; The groove is filled with an anisotropic filling material to form a filling structure; The filling structure is etched to form the through hole in the filling structure within the groove.
2. The method for preparing a through hole according to claim 1, characterized in that, The aspect ratio of the through hole ranges from 5:1 to 100:
1.
3. The method for preparing a through hole according to claim 1, characterized in that, The filler material includes at least one of polyimide, silicon dioxide, silicon nitride, and benzocyclobutene.
4. The method for preparing a through hole according to claim 1, characterized in that, Before filling the groove with an anisotropic filling material, the method further includes: An etching stop layer is formed at the bottom of the groove.
5. The method for preparing a through hole according to claim 1, characterized in that, After forming the through hole in the groove, the method further includes: The through-hole is filled with a conductive material.
6. The method for preparing a through hole according to claim 5, characterized in that, The filling structure fills the groove and covers the substrate; after the through hole is filled with the conductive material, the conductive material and the filling structure located on the surface of the substrate are removed by a grinding process.
7. The method for preparing a through hole according to claim 1, characterized in that, The method includes at least one of the following features: The depth of the groove is 10 micrometers to 100 micrometers; and / or, The width of the groove is 30 micrometers to 200 micrometers.
8. The method for preparing a through hole according to claim 1, characterized in that, The method includes at least one of the following features: The depth of the through-hole is 10 micrometers to 100 micrometers; and / or, The width of the through hole is 2 micrometers to 20 micrometers.
9. The method for preparing a through hole according to claim 1, characterized in that, The preparation method further includes: thinning the substrate from the back side of the substrate until the through hole is exposed from the back side of the substrate.
10. A semiconductor structure, characterized in that, It is prepared by the method for preparing through holes as described in any one of claims 1-9.