Power failure delay power supply circuit
By introducing a detection module and MOSFET control into the electronic circuit system, rapid power-on and power-off of the backup power supply is achieved, solving the system instability problem caused by rapid power-on and power-off of the backup power supply, and ensuring the integrity of data storage and the normal operation of peripherals.
Patent Information
- Application Number
- CN202410491132.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-23
- Publication Date
- 2025-10-31
AI Technical Summary
In existing technologies, backup power supplies in electronic circuit systems can cause system instability when they are rapidly powered on and off. This is especially true when supercapacitors are used as backup power supplies, as they can cause problems with power-on, power-off, and repeated power-on/off cycles, leading to data loss and abnormal operation of peripheral devices.
A power-down delay power supply circuit is adopted, including a main power supply, a backup power supply, a control system, a detection module, multiple diodes and MOSFETs. The detection module detects the power-on and power-off status of the main power supply and controls the conduction and disconnection of the MOSFETs to realize the rapid power-on and power-off of the backup power supply, and completes data storage within the delay period.
It enables rapid power-on and power-off of backup power, ensuring stable system operation, avoiding data loss and peripheral device malfunctions, and is suitable for various application scenarios.
Smart Images
Figure CN120879897A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of electronic circuits, and in particular to a power-down delay power supply circuit. Background Technology
[0002] In electronic circuit systems, the control system typically includes a CPU, RAM memory, ROM memory, etc.
[0003] In many systems with power consumption around 10-20 watts, unexpected power outages can lead to the loss of data in the RAM. If the system can delay power loss, saving the RAM data to the ROM before safely shutting down, it can ensure that the system can operate normally on the next boot and that the data is not lost. Therefore, the system needs to provide a power-down delay solution.
[0004] In existing technologies, power-loss storage solutions typically use backup power sources, such as batteries or supercapacitors, to power the system. However, these solutions simply connect the backup power source in parallel to a branch circuit to supply power to the system, without considering problems caused by prolonged periods without power or repeated power cycling.
[0005] When a battery is used as a backup power source and is not used for a long time, the battery will be over-discharged due to prolonged discharge under load, which will eventually damage the battery.
[0006] When using supercapacitors as backup power, problems arise during power-on, power-off, and repeated power-on / off cycles. The following are some examples: Figure 1 As shown, during power-down, when the backup power supply voltage drops to the watchdog's detection voltage, the system resets. During the reset, the backup power supply, due to load reset, causes the supercapacitor voltage to rise again, allowing the system to boot and run. This cycle continues until the supercapacitor voltage is insufficient to power on the CPU. During power-up, the supercapacitor charges, which can also lead to insufficient current supply to the system, causing problems such as failure to boot. During rapid power-up and power-down, the minimum system always has power, but the peripheral power supplies also experience rapid power-up and power-down. If the CPU does not reset the peripherals during this time, it will cause peripheral malfunctions. Summary of the Invention
[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power-down delay power supply circuit that can realize the rapid power-on and power-off of the backup power supply, thereby ensuring the stable operation of the system.
[0008] To achieve the above and other related objectives, the present invention provides a power-down delay power supply circuit, comprising a main power supply, a backup power supply, a control system, a detection module, a first diode, a second diode, a third diode, a resistor, and a MOSFET; the backup power supply is a charging power supply; the control system includes a CPU, a RAM memory, and a ROM memory; both the RAM memory and the ROM memory are connected to the control system; the main power supply is connected to the control system via the first diode and the MOSFET connected in series; the main power supply is connected to the backup power supply via the resistor and the second diode connected in series, and the backup power supply is connected to the output terminal of the first diode via the third diode; the input terminal of the detection module is connected to the main power supply, the first output terminal is connected to the MOSFET, the second output terminal is connected to the control system, and the power supply terminal is connected to the backup power supply.
[0009] In one embodiment of the present invention, an external device is further included, which is connected to the main power supply and the control system.
[0010] In one embodiment of the present invention, a first DC-DC step-down circuit is further included. The first DC-DC step-down circuit is connected between the main power supply and the external device to provide a matching voltage for the external device.
[0011] In one embodiment of the present invention, a second DC-DC step-down circuit is further included, which is connected between the main power supply and the input terminal of the first diode.
[0012] In one embodiment of the present invention, when the main power supply is powered on, the input terminal of the detection module detects a high level, and the first output terminal controls the MOS transistor to be turned on, so that the main power supply supplies power to the control system through the first diode and the MOS transistor, and charges the backup power supply through the resistor and the second diode.
[0013] In one embodiment of the present invention, when the main power supply is powered off, the input terminal of the detection module detects a low level, the backup power supply supplies power to the control system through the third diode and the MOSFET, the first output terminal of the detection module controls the MOSFET to disconnect after a delay, and the second output terminal sends a power-off signal to the control system so that the CPU completes data storage within the delay period.
[0014] In one embodiment of the present invention, the detection module is connected to the control system via a fourth diode, the negative terminal of the fourth diode is connected to the second output terminal of the detection module, and the positive terminal is connected to the control system.
[0015] In one embodiment of the present invention, when the main power supply is rapidly powered on and off, if the input terminal of the detection module detects a low level, the first output terminal controls the MOS transistor to turn off after a delay period; the second output terminal sends a power-off signal to the control system so that the CPU completes data storage within the delay period; if the input terminal of the detection module detects a high level again, the first output terminal controls the MOS transistor to turn on.
[0016] In one embodiment of the present invention, the detection module employs a CPLD device.
[0017] In one embodiment of the present invention, the backup power supply is a supercapacitor.
[0018] As described above, the power-down delay power supply circuit of the present invention has the following beneficial effects:
[0019] (1) It can quickly power on and off the backup power supply, thereby ensuring the stable operation of the system;
[0020] (2) Solved the problems of power-on, power-off and repeated power-on / off when supercapacitors are used as backup power sources;
[0021] (3) It is applicable to a variety of application scenarios and is highly practical. Attached Figure Description
[0022] Figure 1 The diagram shows a schematic representation of a power-down delay power supply circuit using a supercapacitor in an embodiment of the prior art.
[0023] Figure 2 The diagram shows a schematic frame of the power-down delay power supply circuit of the present invention in one embodiment;
[0024] Figure 3 The diagram shown is a logical function diagram of the detection module of the present invention in one embodiment;
[0025] Figure 4 The diagram shown is a circuit schematic of the power-down delay power supply circuit of the present invention in one embodiment. Detailed Implementation
[0026] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0027] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of the invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.
[0028] The power-down delay power supply circuit of this invention uses a charging power supply as a backup power supply, enabling rapid power-on and power-off of the backup power supply. This solves the problems associated with power-on, power-off, and repeated power-on / off cycles when using the backup power supply, thereby ensuring stable system operation. Preferably, the backup power supply is a supercapacitor.
[0029] like Figure 2 As shown, in one embodiment, the power-down delay power supply circuit of the present invention includes a main power supply 1, a backup power supply 2, a control system 3, a detection module 4, a first diode 5, a second diode 6, a third diode 7, a resistor 8, and a MOSFET 9. Figure 2 The thick black line represents the power supply path, and the thin black line represents the signal control path.
[0030] The control system 3 includes a CPU, RAM, and ROM, and is used to implement data processing and storage functions. Both the RAM and ROM are connected to the control system 3. In this invention, the control system 3 provides the corresponding functions as a minimal system.
[0031] The main power supply 1 is connected to the control system 3 via the first diode 5 and the MOSFET 9 connected in series, thereby supplying power to the control system 3 when the main power supply 1 is powered on.
[0032] The main power supply 1 is connected to the backup power supply 2 via the resistor 8 and the second diode 6 connected in series. The backup power supply 2 is connected to the output terminal of the first diode 5 via the third diode 7, thereby realizing the charging and discharging of the backup power supply 2.
[0033] The detection module 4 has its input terminal IO2 connected to the main power supply 1, its first output terminal IO1 connected to the MOSFET 9, its second output terminal IO3 connected to the control system 3, and its power supply terminal connected to the backup power supply 2. It is used to detect the power-on / off status of the main power supply 1 and to directly or indirectly control the conduction and disconnection of the MOSFET 9. Specifically, the input terminal IO2 of the detection module 4 is used to detect whether the main power supply has lost power; the first output terminal IO1 is used to control the conduction and disconnection of the MOSFET; and the second output terminal IO3 is used to connect to the CPU IO to transmit a power-off signal. In one embodiment, the detection module 4 uses a CPLD device. It should be noted that the detection module 4 is always powered by the backup power supply 2.
[0034] In one embodiment of the present invention, the power-down delay power supply circuit further includes an external device 10, which is connected to the main power supply 1 and the control system 3, is powered by the main power supply 1, and communicates with the control system 3. To achieve voltage matching between the main power supply 1 and the external device 10, a first DC-DC step-down circuit 11 is provided between the main power supply 1 and the external device 10, thereby enabling the main power supply 1 to provide a matching voltage to the external device via the first DC-DC step-down circuit 11.
[0035] In addition, a second DC-DC step-down circuit 12 is provided between the main power supply 1 and the input terminal of the first diode 5, so that the main power supply 1 provides a matching voltage to the control system 3 via the second DC-DC step-down circuit 12.
[0036] Based on the above circuit structure, the working states of the power-down delay power supply circuit of the present invention under different scenarios are as follows:
[0037] When the main power supply is powered on, the input terminal IO2 of the detection module detects a high level, and the first output terminal IO1 controls the MOSFET to conduct, so that the main power supply supplies power to the control system through the first diode and the MOSFET, and charges the backup power supply through the resistor and the second diode. The value of the resistor determines the charging current. Simultaneously, the voltage drop across the main power supply through the first diode must be greater than the voltage drop across the backup power supply through the third diode. This ensures that the backup power supply only has a charging function in the current state.
[0038] When the main power supply fails, the input terminal IO2 of the detection module detects a low level. The backup power supply powers the control system through the third diode and the MOSFET. The first output terminal IO1 of the detection module controls the MOSFET to disconnect after a delay, and the second output terminal IO3 sends a power-down signal to the control system so that the CPU can complete data storage within the delay period. In this way, delayed power supply can be achieved based on the backup power supply when the main power supply fails, ensuring the effective storage of control system data and avoiding data loss due to unexpected power outages. In one embodiment, the detection module is connected to the control system through a fourth diode 13. The negative terminal of the fourth diode is connected to the second output terminal IO3 of the detection module, and the positive terminal is connected to the control system, thereby preventing backflow of CPU IO.
[0039] When the main power supply is rapidly powered on and off, if the input terminal IO2 of the detection module detects a low level, it indicates that the main power supply is powered off, and the backup power supply powers the control system. The first output terminal IO1 controls the MOSFET to turn off after a delay. The second output terminal IO3 sends a power-off signal to the control system so that the CPU can complete data storage within the delay period. The input terminal of the detection module is continuously monitored. If the input terminal detects a high level again, it indicates that the main power supply is powered on again, and the first output terminal IO1 controls the MOSFET to turn on, allowing the main power supply to power the control system; if the detection is still low, the MOSFET remains off.
[0040] The logic timing of the detection module is as follows: Figure 3 As shown in the figure, VCC_IN represents the main power supply, TON represents the power-on delay, TOFF represents the power-off delay, and TL represents the delay time for the next round of detection. As can be seen from the figure, the control system can be reset upon each power-on, thus ensuring the normal operation of the control system and external devices.
[0041] Figure 4 The diagram shows the specific circuit structure of the power-down delay power supply circuit of the present invention. For example... Figure 4As shown, when the main power supply is powered on, the input terminal IO2 of the detection module is at a high level, the second output terminal IO3 outputs a high level, and the first output terminal IO1 outputs a high level. VCC_IN supplies power to VCC_5V0, and the control system operates normally. When the main power supply is powered off, when the input terminal IO2 is at a low level, the second output terminal IO3 outputs a low level. The CPU detects the low level and determines to power off. At this time, the first output terminal IO1 remains at a high level for a few seconds, and then the low level causes the MOSFET to disconnect. During the power-off process, the supercapacitor supplies power to VCC_5V0, and the control system stores data before safely powering off. It should be noted that the input terminal IO2 is not checked before the MOSFET is disconnected, thus ensuring rapid power-on and normal reset.
[0042] in addition, Figure 4 Since capacitor C7 is relatively large, capacitor C8 needs to be added to the GS terminal of the MOSFET to delay the turn-on time of the switching transistor. This prevents the system from pulling VCC_CAP_5V0 low instantaneously upon startup, which could cause abnormal power supply to the detection chip. In this case, IO1 will output a low level, turning off the MOSFET.
[0043] In summary, the power-down delay power supply circuit of this invention enables rapid power-on and power-off of the backup power supply, thereby ensuring stable system operation; it solves the problems associated with power-on, power-off, and repeated power-on / off cycles when using supercapacitors as backup power; and it is applicable to various application scenarios, making it highly practical. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0044] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A power-down delay power supply circuit, characterized in that: It includes a main power supply, a backup power supply, a control system, a detection module, a first diode, a second diode, a third diode, resistors, and a MOSFET; the backup power supply is a charging power supply. The control system includes a CPU, a RAM memory, and a ROM memory; both the RAM memory and the ROM memory are connected to the control system. The main power supply is connected to the control system via the first diode and the MOSFET connected in series. The main power supply is connected to the backup power supply through the resistor and the second diode connected in series, and the backup power supply is connected to the output terminal of the first diode through the third diode; The input terminal of the detection module is connected to the main power supply, the first output terminal is connected to the MOS transistor, the second output terminal is connected to the control system, and the power supply terminal is connected to the backup power supply.
2. The power-down delay power supply circuit according to claim 1, characterized in that: It also includes external devices that are connected to the main power supply and the control system.
3. The power-down delay power supply circuit according to claim 2, characterized in that: It also includes a first DC-DC buck circuit, which is connected between the main power supply and the external device to provide a matching voltage for the external device.
4. The power-down delay power supply circuit according to claim 1, characterized in that: It also includes a second DC-DC step-down circuit, which is connected between the main power supply and the input terminal of the first diode.
5. The power-down delay power supply circuit according to claim 1, characterized in that: When the main power supply is powered on, the input terminal of the detection module detects a high level, and the first output terminal controls the MOSFET to turn on, so that the main power supply supplies power to the control system through the first diode and the MOSFET, and charges the backup power supply through the resistor and the second diode.
6. The power-down delay power supply circuit according to claim 1, characterized in that: When the main power supply is powered off, the input terminal of the detection module detects a low level. The backup power supply supplies power to the control system through the third diode and the MOSFET. After a delay, the first output terminal of the detection module controls the MOSFET to turn off, and the second output terminal sends a power-off signal to the control system so that the CPU can complete data storage within the delay period.
7. The power-down delay power supply circuit according to claim 6, characterized in that: The detection module is connected to the control system via a fourth diode. The negative terminal of the fourth diode is connected to the second output terminal of the detection module, and the positive terminal is connected to the control system.
8. The power-down delay power supply circuit according to claim 1, characterized in that: When the main power supply is rapidly powered on and off, if the input terminal of the detection module detects a low level, the first output terminal controls the MOSFET to turn off after a delay period; the second output terminal sends a power-off signal to the control system so that the CPU can complete data storage within the delay period; if the input terminal of the detection module detects a high level again, the first output terminal controls the MOSFET to turn on.
9. The power-down delay power supply circuit according to claim 1, characterized in that: The detection module uses a CPLD device.
10. The power-down delay power supply circuit according to claim 1, characterized in that: The backup power supply uses a supercapacitor.